From patchwork Mon Jun 22 07:59:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11617149 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F21D90 for ; Mon, 22 Jun 2020 07:59:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6FCF220857 for ; Mon, 22 Jun 2020 07:59:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="z7MEDIZW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726110AbgFVH7t (ORCPT ); Mon, 22 Jun 2020 03:59:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725981AbgFVH7r (ORCPT ); Mon, 22 Jun 2020 03:59:47 -0400 Received: from mail-oi1-x241.google.com (mail-oi1-x241.google.com [IPv6:2607:f8b0:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87619C061794 for ; Mon, 22 Jun 2020 00:59:47 -0700 (PDT) Received: by mail-oi1-x241.google.com with SMTP id t25so14817174oij.7 for ; Mon, 22 Jun 2020 00:59:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LJgqx0FElWYNHiKP6/azPu/efC7YRPz1t5jHiyjGX5I=; b=z7MEDIZWSm4dSLKud1tvjbVwKfWltkWrCH4cI0Tkv27wR37A8L2ku475Fi3XjSdQvj CeArAWZ4pkgSR63gpxUsc3v+ckNOEqxQvGSh1E8yLb1HfwlvU+W7IL0pBYfuefbu6Cmx 6rmcNEcfUBSwkBYwRTg1eEMYPTQPh6LNl+lzeu/YVxaOzOEnWKQ88XEvTlZR5fzRIJ6R duHpT4zSmYtxBQB3VFWCXIKgNqGGrOVWDDYUp0lLkX5ZW/INsyNXxylmxAITP4xyzMGj MfMujM7d9BFW957Np/8UfJQjdk0eabxbd8FTR4lPZ0U3n5cIv0OEEHbGImVH4P1Np+Kw ZrpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LJgqx0FElWYNHiKP6/azPu/efC7YRPz1t5jHiyjGX5I=; b=E9niO06k1E5EDevmCHOGuB6ByNMTgztmrR8Wp+nDebVEba0BMrEqvrRYfPqW49fSjq F7uueO9Z4rmgtypCq+dKGHS6GqjRyk7kdz4yN12sQZ3EUhYWgws46NE4Q863yM/90QmO HxZFjuamdfg+OttHaUKjF6A/CVKiD6fk9jsNTbN4qoZkYTgxTjkbN9JsWzLb5DvcEMgL QcauUROsfJy9fygAv93CKT5ES1RbcQ6EheVGNzM8xpP8j5HXi7cnO+7FFx7N9B1EQh0H vE057vPS6d2JD3qdbLH8X0cCdwcvDInQISI8bce6lWvRjn9ScT3I8HELQNsTVLAfVRii Um9w== X-Gm-Message-State: AOAM532cDt2rMfaKff0Lj/Vs6yZ+JNrqoA6dTp8ge+Npg0pRnhqy7zOz RiVz9RCWRrRT9H0y2TWEMDpK5Q== X-Google-Smtp-Source: ABdhPJwW08awvSrcBH/moxNLMZgjj2yqEijNnETVIOc23GGyh5ogpgmPd3z8sHprGv6P1VAq01Xuiw== X-Received: by 2002:aca:da44:: with SMTP id r65mr11144475oig.124.1592812786882; Mon, 22 Jun 2020 00:59:46 -0700 (PDT) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id f7sm3135396otl.60.2020.06.22.00.59.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2020 00:59:46 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Ohad Ben-Cohen , Baolin Wang , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v2 1/4] dt-bindings: hwlock: qcom: Migrate binding to YAML Date: Mon, 22 Jun 2020 00:59:53 -0700 Message-Id: <20200622075956.171058-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200622075956.171058-1-bjorn.andersson@linaro.org> References: <20200622075956.171058-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Migrate the Qualcomm TCSR mutex binding to YAML to allow validation. Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Reviewed-by: Rob Herring --- Changes since v1: - Actually remove the old binding doc .../bindings/hwlock/qcom-hwspinlock.txt | 39 -------------- .../bindings/hwlock/qcom-hwspinlock.yaml | 51 +++++++++++++++++++ 2 files changed, 51 insertions(+), 39 deletions(-) delete mode 100644 Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt create mode 100644 Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml diff --git a/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt deleted file mode 100644 index 4563f524556b..000000000000 --- a/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt +++ /dev/null @@ -1,39 +0,0 @@ -Qualcomm Hardware Mutex Block: - -The hardware block provides mutexes utilized between different processors on -the SoC as part of the communication protocol used by these processors. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,sfpb-mutex", - "qcom,tcsr-mutex" - -- syscon: - Usage: required - Value type: - Definition: one cell containing: - syscon phandle - offset of the hwmutex block within the syscon - stride of the hwmutex registers - -- #hwlock-cells: - Usage: required - Value type: - Definition: must be 1, the specified cell represent the lock id - (hwlock standard property, see hwlock.txt) - -Example: - - tcsr_mutex_block: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; - }; - - hwlock@fd484000 { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_block 0 0x80>; - - #hwlock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml new file mode 100644 index 000000000000..71e63b52edd5 --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwlock/qcom-hwspinlock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Hardware Mutex Block + +maintainers: + - Bjorn Andersson + +description: + The hardware block provides mutexes utilized between different processors on + the SoC as part of the communication protocol used by these processors. + +properties: + compatible: + enum: + - qcom,sfpb-mutex + - qcom,tcsr-mutex + + '#hwlock-cells': + const: 1 + + syscon: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + Should be a triple of phandle referencing the TCSR mutex syscon, offset + of first mutex within the syscon and stride between each mutex. + +required: + - compatible + - '#hwlock-cells' + - syscon + +additionalProperties: false + +examples: + - | + tcsr_mutex_block: syscon@fd484000 { + compatible = "syscon"; + reg = <0xfd484000 0x2000>; + }; + + hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x80>; + + #hwlock-cells = <1>; + }; +... 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id f7sm3135396otl.60.2020.06.22.00.59.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2020 00:59:47 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Ohad Ben-Cohen , Baolin Wang , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v2 2/4] dt-bindings: hwlock: qcom: Allow device on mmio bus Date: Mon, 22 Jun 2020 00:59:54 -0700 Message-Id: <20200622075956.171058-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200622075956.171058-1-bjorn.andersson@linaro.org> References: <20200622075956.171058-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In modern Qualcomm platforms the mutex region of the TCSR is forked off into its own block, all with a offset of 0 and stride of 4096, and in some of these platforms no other registers in this region is accessed from Linux. Update the binding to allow the hardware block to be described directly on the mmio bus, in addition to allowing the existing syscon based definition for backwards compatibility. Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Reviewed-by: Rob Herring --- Changes since v1: - None .../bindings/hwlock/qcom-hwspinlock.yaml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml index 71e63b52edd5..88f975837588 100644 --- a/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml +++ b/Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml @@ -19,6 +19,9 @@ properties: - qcom,sfpb-mutex - qcom,tcsr-mutex + reg: + maxItems: 1 + '#hwlock-cells': const: 1 @@ -31,7 +34,12 @@ properties: required: - compatible - '#hwlock-cells' - - syscon + +oneOf: + - required: + - reg + - required: + - syscon additionalProperties: false @@ -46,6 +54,12 @@ examples: compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_block 0 0x80>; + #hwlock-cells = <1>; + }; + - | + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01f40000 0x40000>; #hwlock-cells = <1>; }; ... From patchwork Mon Jun 22 07:59:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11617159 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B6C7792A for ; Mon, 22 Jun 2020 08:00:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A0C9220C09 for ; Mon, 22 Jun 2020 08:00:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="BNOYV4j6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726509AbgFVIAD (ORCPT ); Mon, 22 Jun 2020 04:00:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727010AbgFVH7v (ORCPT ); Mon, 22 Jun 2020 03:59:51 -0400 Received: from mail-oi1-x243.google.com (mail-oi1-x243.google.com [IPv6:2607:f8b0:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 904ECC061796 for ; Mon, 22 Jun 2020 00:59:50 -0700 (PDT) Received: by mail-oi1-x243.google.com with SMTP id 25so14798942oiy.13 for ; Mon, 22 Jun 2020 00:59:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wsD4JPbpu6P4JVf54PUOXffj8NM5iwWqNtOuxNrh1Ek=; b=BNOYV4j6OzxYc7GgjKpKV5iHhJDTcp7c44mazYdUT13aaDi4kX/kj0nSDBVIy20Kuv 2iWXqdC8MelZ6pT8J7IMyiTr761V9lDjt40hGEj2cUegqHluLTKhW9JO/foBnKb8WbU2 FPTMALkLdzsxrhvNkF75jEIkblhVdLIjoKKaSmvy8I+JxtUpLFNkM/wPUoR+TPwKdnme MFx5YdfH7JjV73EMfUZOh8BCsp3DazzPy3yLz5VRQ2duLgqhUuGVSDFz3I1ctv8fCfH2 M8WPY5rpRck6TXr/33Onpu5U2a2hN/c5h6xux7gLdrFN5AN/3yTOAozV3wy6bYlLkajy jIcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wsD4JPbpu6P4JVf54PUOXffj8NM5iwWqNtOuxNrh1Ek=; b=L/Ucp1R22w/FZICdjaojB9aLUGqL9iWPWi1VaeK4yC26sgSjcIXPyYNCbdRNPvCh5y EZNqwAABDGr8hFzGwATvUmK9QZyLKLwbl3aqqtDR6LJ7BNolMtHaeDFqsUPnHIblLwm9 IHtTc8RnMb086o7+aDoi399Pl2fwPmbLW5AOlUBKBQG3z5uR30qUSiH8hvNfvTacTSNI 8cE0Hfb89L+jbsX6KFsE+m060ygEczo/frJNIB+u8akwzx93x6RpFhhnXXaR93zb8CeY BHojJw5LeGILnQX7dit3abDpnq2N4jCazT2sYX90sSlPDeHLau2y+dnZL4w1OT21OtOM zWxQ== X-Gm-Message-State: AOAM532jARmg7xeqOpcij9b9rjqNan6tYSVbdztuiI65momBRIQWJRI7 yMwfgBlR9Xx7PpwqVw8eS0mttg== X-Google-Smtp-Source: ABdhPJzzr4SQgqtDcXOQA6jIMEtE2S+/98sTWL4tFRZgSSkA+8K8Ny8EKzh9/a1r9NRfHry3qVgZfQ== X-Received: by 2002:a05:6808:6ca:: with SMTP id m10mr11477202oih.27.1592812789939; Mon, 22 Jun 2020 00:59:49 -0700 (PDT) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id f7sm3135396otl.60.2020.06.22.00.59.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2020 00:59:49 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Ohad Ben-Cohen , Baolin Wang , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Subject: [PATCH v2 3/4] hwspinlock: qcom: Allow mmio usage in addition to syscon Date: Mon, 22 Jun 2020 00:59:55 -0700 Message-Id: <20200622075956.171058-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200622075956.171058-1-bjorn.andersson@linaro.org> References: <20200622075956.171058-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In modern Qualcomm platforms the mutex region of the TCSR is forked off into its own block, all with a offset of 0 and stride of 4096, and in some of these platforms no other registers in this region is accessed from Linux. So add support for directly memory mapping this register space, to avoid the need to represent this block using a syscon. Reviewed-by: Baolin Wang Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson --- Changes since v1: - Use devm_platform_ioremap_resource() drivers/hwspinlock/qcom_hwspinlock.c | 70 +++++++++++++++++++++------- 1 file changed, 54 insertions(+), 16 deletions(-) diff --git a/drivers/hwspinlock/qcom_hwspinlock.c b/drivers/hwspinlock/qcom_hwspinlock.c index f0da544b14d2..364710966665 100644 --- a/drivers/hwspinlock/qcom_hwspinlock.c +++ b/drivers/hwspinlock/qcom_hwspinlock.c @@ -70,41 +70,79 @@ static const struct of_device_id qcom_hwspinlock_of_match[] = { }; MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match); -static int qcom_hwspinlock_probe(struct platform_device *pdev) +static struct regmap *qcom_hwspinlock_probe_syscon(struct platform_device *pdev, + u32 *base, u32 *stride) { - struct hwspinlock_device *bank; struct device_node *syscon; - struct reg_field field; struct regmap *regmap; - size_t array_size; - u32 stride; - u32 base; int ret; - int i; syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0); - if (!syscon) { - dev_err(&pdev->dev, "no syscon property\n"); - return -ENODEV; - } + if (!syscon) + return ERR_PTR(-ENODEV); regmap = syscon_node_to_regmap(syscon); of_node_put(syscon); if (IS_ERR(regmap)) - return PTR_ERR(regmap); + return regmap; - ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, &base); + ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, base); if (ret < 0) { dev_err(&pdev->dev, "no offset in syscon\n"); - return -EINVAL; + return ERR_PTR(-EINVAL); } - ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, &stride); + ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, stride); if (ret < 0) { dev_err(&pdev->dev, "no stride syscon\n"); - return -EINVAL; + return ERR_PTR(-EINVAL); } + return regmap; +} + +static const struct regmap_config tcsr_mutex_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40000, + .fast_io = true, +}; + +static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev, + u32 *offset, u32 *stride) +{ + struct device *dev = &pdev->dev; + void __iomem *base; + + /* All modern platform has offset 0 and stride of 4k */ + *offset = 0; + *stride = 0x1000; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return ERR_CAST(base); + + return devm_regmap_init_mmio(dev, base, &tcsr_mutex_config); +} + +static int qcom_hwspinlock_probe(struct platform_device *pdev) +{ + struct hwspinlock_device *bank; + struct reg_field field; + struct regmap *regmap; + size_t array_size; + u32 stride; + u32 base; + int i; + + regmap = qcom_hwspinlock_probe_syscon(pdev, &base, &stride); + if (IS_ERR(regmap) && PTR_ERR(regmap) == -ENODEV) + regmap = qcom_hwspinlock_probe_mmio(pdev, &base, &stride); + + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + array_size = QCOM_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock); bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL); if (!bank) From patchwork Mon Jun 22 07:59:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11617153 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D916592A for ; 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id f7sm3135396otl.60.2020.06.22.00.59.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2020 00:59:50 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Ohad Ben-Cohen , Baolin Wang , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/4] arm64: dts: qcom: sm8250: Drop tcsr_mutex syscon Date: Mon, 22 Jun 2020 00:59:56 -0700 Message-Id: <20200622075956.171058-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200622075956.171058-1-bjorn.andersson@linaro.org> References: <20200622075956.171058-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that we don't need the intermediate syscon to represent the TCSR mutexes, update the dts to describe the TCSR mutex directly under /soc. The change also fixes the sort order of the nodes. Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam --- Changs since v1: - Adjusted sort order of the nodes arch/arm64/boot/dts/qcom/sm8250.dtsi | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7050adba7995..67a1b6f3301b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -144,12 +144,6 @@ scm: scm { }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -376,6 +370,12 @@ ufs_mem_phy_lanes: lanes@1d87400 { }; }; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -486,11 +486,6 @@ rpmhpd_opp_turbo_l1: opp10 { }; }; - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x0 0x01f40000 0x0 0x40000>; - }; - timer@17c20000 { #address-cells = <2>; #size-cells = <2>;