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Mon, 22 Jun 2020 23:43:44 -0800 Received: from MTKMBS02N2.mediatek.inc (172.21.101.101) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Jun 2020 00:44:11 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Jun 2020 15:44:07 +0800 Received: from localhost.localdomain (10.15.20.246) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 23 Jun 2020 15:44:06 +0800 From: Qiangming Xia To: , Wolfram Sang Subject: [PATCH] i2c: mediatek: Add to support continuous mode Date: Tue, 23 Jun 2020 15:42:46 +0800 Message-ID: <20200623074245.24513-1-qiangming.xia@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: 0FCA00D07C161A82247C3FE62C92D3EAE22AF5FA53B749BCD297468721A4E1652000:8 X-MTK: N X-Spam-Note: CRM114 invocation failed X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qiangming.xia" , devicetree@vger.kernel.org, srv_heupstream@mediatek.com, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Qii Wang , linux-i2c@vger.kernel.org, Yingjoe Chen , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: "qiangming.xia" Mediatek i2c controller support for continuous mode, it allow to transfer once multiple writing messages of equal length. A i2c slave sometimes need write a serial of non-continuous offset range in chip,e.g. camera sensor imx586,imx576. It need transfer 294 writing messages when initiate setting. It can use this mode to improve performance. Change-Id: If473d96d2b76e9d51f20741a9380db4fcad15dbd Signed-off-by: Qiangming Xia --- drivers/i2c/busses/i2c-mt65xx.c | 66 +++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index deef69e56906..108bca1a4042 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -97,6 +97,7 @@ enum mtk_trans_op { I2C_MASTER_WR = 1, I2C_MASTER_RD, I2C_MASTER_WRRD, + I2C_MASTER_CONTINUOUS_WR, }; enum I2C_REGS_OFFSET { @@ -846,6 +847,9 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, OFFSET_TRANSFER_LEN); } mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); + } else if (i2c->op == I2C_MASTER_CONTINUOUS_WR) { + mtk_i2c_writew(i2c, msgs->len / num, OFFSET_TRANSFER_LEN); + mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); } else { mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); @@ -896,6 +900,23 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); } + writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); + writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); + } else if (i2c->op == I2C_MASTER_CONTINUOUS_WR) { + writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); + writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON); + wpaddr = dma_map_single(i2c->dev, msgs->buf, + msgs->len, DMA_TO_DEVICE); + if (dma_mapping_error(i2c->dev, wpaddr)) { + kfree(msgs->buf); + return -ENOMEM; + } + + if (i2c->dev_comp->support_33bits) { + reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr); + writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); + } + writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); } else { @@ -979,6 +1000,11 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, msgs->len, DMA_FROM_DEVICE); i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true); + } else if (i2c->op == I2C_MASTER_CONTINUOUS_WR) { + dma_unmap_single(i2c->dev, wpaddr, + msgs->len, DMA_TO_DEVICE); + + kfree(msgs->buf); } else { dma_unmap_single(i2c->dev, wpaddr, msgs->len, DMA_TO_DEVICE); @@ -1009,6 +1035,9 @@ static int mtk_i2c_transfer(struct i2c_adapter *adap, { int ret; int left_num = num; + int i, j; + u8 *dma_multi_wr_buf; + struct i2c_msg multi_msg[1]; struct mtk_i2c *i2c = i2c_get_adapdata(adap); ret = mtk_i2c_clock_enable(i2c); @@ -1025,6 +1054,43 @@ static int mtk_i2c_transfer(struct i2c_adapter *adap, } } + if (num > 1 && !(msgs[0].flags & I2C_M_RD)) { + for (i = 0; i < num - 1; i++) { + if (!(msgs[i+1].flags & I2C_M_RD) && + (msgs[i].addr == msgs[i+1].addr) + && (msgs[i].len == msgs[i+1].len)) { + continue; + } else + break; + } + if (i == num - 1) { + i2c->op = I2C_MASTER_CONTINUOUS_WR; + j = 0; + dma_multi_wr_buf = kmalloc(msgs->len * num, GFP_KERNEL); + if (!dma_multi_wr_buf) { + ret = -ENOMEM; + goto err_exit; + } + multi_msg->addr = msgs->addr; + multi_msg->len = msgs->len * num; + multi_msg->buf = dma_multi_wr_buf; + multi_msg->flags = 0; + while (j < num) { + memcpy(dma_multi_wr_buf + msgs->len * j, + msgs->buf, msgs->len); + j++; + msgs++; + } + + i2c->ignore_restart_irq = false; + ret = mtk_i2c_do_transfer(i2c, multi_msg, num, 0); + if (ret < 0) + goto err_exit; + ret = num; + goto err_exit; + } + } + if (i2c->auto_restart && num >= 2 && i2c->speed_hz > I2C_MAX_FAST_MODE_FREQ) /* ignore the first restart irq after the master code, * otherwise the first transfer will be discarded.