From patchwork Fri Jun 26 20:59:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11628667 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7ABA6912 for ; Fri, 26 Jun 2020 21:02:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5CCA020720 for ; Fri, 26 Jun 2020 21:02:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5CCA020720 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:46398 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jovU8-0001qI-Iy for patchwork-qemu-devel@patchwork.kernel.org; Fri, 26 Jun 2020 17:02:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39226) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jovTY-0001N5-Nv; Fri, 26 Jun 2020 17:01:32 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:41804) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jovTW-0002uu-U1; Fri, 26 Jun 2020 17:01:32 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.09593284|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0130556-0.00467745-0.982267; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03294; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.Ht1zUrN_1593205286; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Ht1zUrN_1593205286) by smtp.aliyun-inc.com(10.147.42.241); Sat, 27 Jun 2020 05:01:26 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 1/6] target/riscv: move gen_nanbox_fpr to translate.c Date: Sat, 27 Jun 2020 04:59:12 +0800 Message-Id: <20200626205917.4545-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200626205917.4545-1-zhiwei_liu@c-sky.com> References: <20200626205917.4545-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/26 16:59:26 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, palmer@dabbelt.com, LIU Zhiwei , ianjiang.ict@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" As this function will be used by fcvt.d.s in trans_rvd.inc.c, make it a visible function for RVF and RVD. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvf.inc.c | 14 -------------- target/riscv/translate.c | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index 3bfd8881e7..0d5ce373cb 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -23,20 +23,6 @@ return false; \ } while (0) -/* - * RISC-V requires NaN-boxing of narrower width floating - * point values. This applies when a 32-bit value is - * assigned to a 64-bit FP register. Thus this does not - * apply when the RVD extension is not present. - */ -static void gen_nanbox_fpr(DisasContext *ctx, int regno) -{ - if (has_ext(ctx, RVD)) { - tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno], - MAKE_64BIT_MASK(32, 32)); - } -} - static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv t0 = tcg_temp_new(); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9632e79cf3..4b1534c9a6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -90,6 +90,20 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) return ctx->misa & ext; } +/* + * RISC-V requires NaN-boxing of narrower width floating + * point values. This applies when a 32-bit value is + * assigned to a 64-bit FP register. Thus this does not + * apply when the RVD extension is not present. + */ +static void gen_nanbox_fpr(DisasContext *ctx, int regno) +{ + if (has_ext(ctx, RVD)) { + tcg_gen_ori_i64(cpu_fpr[regno], cpu_fpr[regno], + MAKE_64BIT_MASK(32, 32)); + } +} + static void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); From patchwork Fri Jun 26 20:59:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11628669 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 607E0912 for ; Fri, 26 Jun 2020 21:04:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 422C72070A for ; Fri, 26 Jun 2020 21:04:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 422C72070A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:48690 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jovWJ-0002pX-Fo for patchwork-qemu-devel@patchwork.kernel.org; Fri, 26 Jun 2020 17:04:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39738) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jovVa-0002Md-83; Fri, 26 Jun 2020 17:03:38 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:47820) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jovVW-0003p7-Ct; Fri, 26 Jun 2020 17:03:37 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.123083-0.000330356-0.876587; FP=0|0|0|0|0|-1|-1|-1; HT=e01l07381; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.Ht2835v_1593205407; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Ht2835v_1593205407) by smtp.aliyun-inc.com(10.147.42.16); Sat, 27 Jun 2020 05:03:27 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 2/6] target/riscv: NaN-boxing compute, sign-injection and convert instructions. Date: Sat, 27 Jun 2020 04:59:13 +0800 Message-Id: <20200626205917.4545-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200626205917.4545-1-zhiwei_liu@c-sky.com> References: <20200626205917.4545-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/26 16:59:26 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, palmer@dabbelt.com, LIU Zhiwei , ianjiang.ict@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" An n-bit foating-point result is written to the n least-significant bits of the destination f register, with all 1s written to the uppermost FLEN - n bits to yield a legal NaN-boxed value Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvd.inc.c | 1 + target/riscv/insn_trans/trans_rvf.inc.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c index ea1044f13b..cd73a326f4 100644 --- a/target/riscv/insn_trans/trans_rvd.inc.c +++ b/target/riscv/insn_trans/trans_rvd.inc.c @@ -230,6 +230,7 @@ static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a) gen_set_rm(ctx, a->rm); gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index 0d5ce373cb..a3d74dd83d 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -61,6 +61,7 @@ static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a) gen_set_rm(ctx, a->rm); gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; } @@ -72,6 +73,7 @@ static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a) gen_set_rm(ctx, a->rm); gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; } @@ -83,6 +85,7 @@ static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a) gen_set_rm(ctx, a->rm); gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; } @@ -95,6 +98,7 @@ static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a) gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2], cpu_fpr[a->rs3]); mark_fs_dirty(ctx); + gen_nanbox_fpr(ctx, a->rd); return true; } @@ -106,6 +110,7 @@ static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a) gen_set_rm(ctx, a->rm); gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; } @@ -118,6 +123,7 @@ static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a) gen_set_rm(ctx, a->rm); gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; } @@ -130,6 +136,7 @@ static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a) gen_set_rm(ctx, a->rm); gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; } @@ -142,6 +149,7 @@ static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a) gen_set_rm(ctx, a->rm); gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; } @@ -153,6 +161,7 @@ static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a) gen_set_rm(ctx, a->rm); gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; } @@ -167,6 +176,7 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a) tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1], 0, 31); } + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; } @@ -183,6 +193,7 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a) tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31); tcg_temp_free_i64(t0); } + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; } @@ -199,6 +210,7 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a) tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); tcg_temp_free_i64(t0); } + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; } @@ -210,6 +222,7 @@ static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a) gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; } @@ -221,6 +234,7 @@ static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a) gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); return true; } @@ -331,6 +345,7 @@ static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a) gen_set_rm(ctx, a->rm); gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); tcg_temp_free(t0); @@ -348,6 +363,7 @@ static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a) gen_set_rm(ctx, a->rm); gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); tcg_temp_free(t0); @@ -369,6 +385,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) #else tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); #endif + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); tcg_temp_free(t0); @@ -413,6 +430,7 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a) gen_set_rm(ctx, a->rm); gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); tcg_temp_free(t0); @@ -429,6 +447,7 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a) gen_set_rm(ctx, a->rm); gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); + gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx); tcg_temp_free(t0); From patchwork Fri Jun 26 20:59:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11628671 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4E17114E3 for ; Fri, 26 Jun 2020 21:06:04 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2EE25206B7 for ; Fri, 26 Jun 2020 21:06:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2EE25206B7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:50956 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jovXv-0003x2-GH for patchwork-qemu-devel@patchwork.kernel.org; Fri, 26 Jun 2020 17:06:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40280) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jovXS-0003OO-2g; Fri, 26 Jun 2020 17:05:34 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:41396) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jovXQ-0004iU-BA; Fri, 26 Jun 2020 17:05:33 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.3410022|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.00804734-0.00154471-0.990408; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03306; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.Ht24-94_1593205527; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Ht24-94_1593205527) by smtp.aliyun-inc.com(10.147.42.22); Sat, 27 Jun 2020 05:05:28 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 3/6] target/riscv: Check for LEGAL NaN-boxing Date: Sat, 27 Jun 2020 04:59:14 +0800 Message-Id: <20200626205917.4545-4-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200626205917.4545-1-zhiwei_liu@c-sky.com> References: <20200626205917.4545-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/26 16:59:26 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, palmer@dabbelt.com, LIU Zhiwei , ianjiang.ict@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" A narrow n-bit operation, where n < FLEN, checks that input operands are correctly NaN-boxed, i.e., all upper FLEN - n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Signed-off-by: LIU Zhiwei --- target/riscv/translate.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4b1534c9a6..1c9b809d4a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -104,6 +104,35 @@ static void gen_nanbox_fpr(DisasContext *ctx, int regno) } } +/* + * A narrow n-bit operation, where n < FLEN, checks that input operands + * are correctly NaN-boxed, i.e., all upper FLEN - n bits are 1. + * If so, the n least-signicant bits of the input are used as the input value, + * otherwise the input value is treated as an n-bit canonical NaN. + * (riscv-spec-v2.2 Section 9.2). + */ +static void check_nanboxed(DisasContext *ctx, int num, ...) +{ + if (has_ext(ctx, RVD)) { + int i; + TCGv_i64 cond1 = tcg_temp_new_i64(); + TCGv_i64 t_nan = tcg_const_i64(0x7fc00000); + TCGv_i64 t_max = tcg_const_i64(MAKE_64BIT_MASK(32, 32)); + va_list valist; + va_start(valist, num); + + for (i = 0; i < num; i++) { + TCGv_i64 t = va_arg(valist, TCGv_i64); + tcg_gen_movcond_i64(TCG_COND_GEU, t, t, t_max, t, t_nan); + } + + va_end(valist); + tcg_temp_free_i64(cond1); + tcg_temp_free_i64(t_nan); + tcg_temp_free_i64(t_max); + } +} + static void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); From patchwork Fri Jun 26 20:59:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11628673 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A073514F6 for ; Fri, 26 Jun 2020 21:08:12 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 41E76208C7 for ; Fri, 26 Jun 2020 21:08:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 41E76208C7 Authentication-Results: mail.kernel.org; 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MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.Ht2CGB0_1593205648; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Ht2CGB0_1593205648) by smtp.aliyun-inc.com(10.147.44.129); Sat, 27 Jun 2020 05:07:28 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 4/6] target/riscv: check before allocating TCG temps Date: Sat, 27 Jun 2020 04:59:15 +0800 Message-Id: <20200626205917.4545-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200626205917.4545-1-zhiwei_liu@c-sky.com> References: <20200626205917.4545-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/26 16:59:26 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, palmer@dabbelt.com, LIU Zhiwei , ianjiang.ict@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvd.inc.c | 8 ++++---- target/riscv/insn_trans/trans_rvf.inc.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c index cd73a326f4..c0f4a0c789 100644 --- a/target/riscv/insn_trans/trans_rvd.inc.c +++ b/target/riscv/insn_trans/trans_rvd.inc.c @@ -20,10 +20,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) { - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); @@ -35,10 +35,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) static bool trans_fsd(DisasContext *ctx, arg_fsd *a) { - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index a3d74dd83d..04bc8e5cb5 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -25,10 +25,10 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) { - TCGv t0 = tcg_temp_new(); - gen_get_gpr(t0, a->rs1); REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); @@ -41,11 +41,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) static bool trans_fsw(DisasContext *ctx, arg_fsw *a) { + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); tcg_gen_addi_tl(t0, t0, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); From patchwork Fri Jun 26 20:59:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11628693 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13632161F for ; Fri, 26 Jun 2020 21:10:14 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D75FA20FC3 for ; Fri, 26 Jun 2020 21:10:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D75FA20FC3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:56820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jovbx-0006UT-4D for patchwork-qemu-devel@patchwork.kernel.org; Fri, 26 Jun 2020 17:10:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41310) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jovbO-0005is-0c; Fri, 26 Jun 2020 17:09:38 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:50956) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jovbL-0005wL-5N; Fri, 26 Jun 2020 17:09:37 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.00971263-0.00105046-0.989237; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03297; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.Ht2PVnK_1593205769; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Ht2PVnK_1593205769) by smtp.aliyun-inc.com(10.147.42.198); Sat, 27 Jun 2020 05:09:29 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 5/6] target/riscv: Flush not valid NaN-boxing input to canonical NaN Date: Sat, 27 Jun 2020 04:59:16 +0800 Message-Id: <20200626205917.4545-6-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200626205917.4545-1-zhiwei_liu@c-sky.com> References: <20200626205917.4545-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/26 16:59:26 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, palmer@dabbelt.com, LIU Zhiwei , ianjiang.ict@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.inc.c | 7 +- target/riscv/insn_trans/trans_rvf.inc.c | 272 ++++++++++++++++++++---- 2 files changed, 235 insertions(+), 44 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c index c0f4a0c789..16947ea6da 100644 --- a/target/riscv/insn_trans/trans_rvd.inc.c +++ b/target/riscv/insn_trans/trans_rvd.inc.c @@ -241,10 +241,15 @@ static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + TCGv_i64 t1 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + check_nanboxed(ctx, 1, t1); + gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, t1); mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); return true; } diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index 04bc8e5cb5..b0379b9d1f 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -58,11 +58,23 @@ static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + tcg_gen_mov_i64(t3, cpu_fpr[a->rs3]); + check_nanboxed(ctx, 3, t1, t2, t3); + gen_set_rm(ctx, a->rm); - gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, t1, t2, t3); gen_nanbox_fpr(ctx, a->rd); + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + tcg_temp_free_i64(t3); return true; } @@ -70,11 +82,23 @@ static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + tcg_gen_mov_i64(t3, cpu_fpr[a->rs3]); + check_nanboxed(ctx, 3, t1, t2, t3); + gen_set_rm(ctx, a->rm); - gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, t1, t2, t3); gen_nanbox_fpr(ctx, a->rd); + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + tcg_temp_free_i64(t3); return true; } @@ -82,11 +106,23 @@ static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + tcg_gen_mov_i64(t3, cpu_fpr[a->rs3]); + check_nanboxed(ctx, 3, t1, t2, t3); + gen_set_rm(ctx, a->rm); - gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, t1, t2, t3); gen_nanbox_fpr(ctx, a->rd); + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + tcg_temp_free_i64(t3); return true; } @@ -94,11 +130,23 @@ static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + tcg_gen_mov_i64(t3, cpu_fpr[a->rs3]); + check_nanboxed(ctx, 3, t1, t2, t3); + gen_set_rm(ctx, a->rm); - gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); - mark_fs_dirty(ctx); + gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, t1, t2, t3); gen_nanbox_fpr(ctx, a->rd); + + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + tcg_temp_free_i64(t3); return true; } @@ -107,11 +155,19 @@ static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + check_nanboxed(ctx, 2, t1, t2); + gen_set_rm(ctx, a->rm); - gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env, t1, t2); gen_nanbox_fpr(ctx, a->rd); + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); return true; } @@ -120,11 +176,19 @@ static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + check_nanboxed(ctx, 2, t1, t2); + gen_set_rm(ctx, a->rm); - gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env, t1, t2); gen_nanbox_fpr(ctx, a->rd); + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); return true; } @@ -133,11 +197,19 @@ static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + check_nanboxed(ctx, 2, t1, t2); + gen_set_rm(ctx, a->rm); - gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env, t1, t2); gen_nanbox_fpr(ctx, a->rd); + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); return true; } @@ -146,11 +218,19 @@ static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + check_nanboxed(ctx, 2, t1, t2); + gen_set_rm(ctx, a->rm); - gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env, t1, t2); gen_nanbox_fpr(ctx, a->rd); + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); return true; } @@ -159,10 +239,16 @@ static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + TCGv_i64 t1 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + check_nanboxed(ctx, 1, t1); + gen_set_rm(ctx, a->rm); - gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, t1); gen_nanbox_fpr(ctx, a->rd); + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); return true; } @@ -170,14 +256,23 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + check_nanboxed(ctx, 2, t1, t2); + if (a->rs1 == a->rs2) { /* FMOV */ - tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]); + tcg_gen_mov_i64(cpu_fpr[a->rd], t1); } else { /* FSGNJ */ - tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1], - 0, 31); + tcg_gen_deposit_i64(cpu_fpr[a->rd], t2, t1, 0, 31); } gen_nanbox_fpr(ctx, a->rd); + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); return true; } @@ -185,16 +280,26 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + check_nanboxed(ctx, 2, t1, t2); + if (a->rs1 == a->rs2) { /* FNEG */ - tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN); + tcg_gen_xori_i64(cpu_fpr[a->rd], t1, INT32_MIN); } else { TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_not_i64(t0, cpu_fpr[a->rs2]); - tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31); + tcg_gen_not_i64(t0, t2); + tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, t1, 0, 31); tcg_temp_free_i64(t0); } gen_nanbox_fpr(ctx, a->rd); + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); return true; } @@ -202,16 +307,26 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + check_nanboxed(ctx, 2, t1, t2); + if (a->rs1 == a->rs2) { /* FABS */ - tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN); + tcg_gen_andi_i64(cpu_fpr[a->rd], t1, ~INT32_MIN); } else { TCGv_i64 t0 = tcg_temp_new_i64(); - tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN); - tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); + tcg_gen_andi_i64(t0, t2, INT32_MIN); + tcg_gen_xor_i64(cpu_fpr[a->rd], t1, t0); tcg_temp_free_i64(t0); } gen_nanbox_fpr(ctx, a->rd); + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); return true; } @@ -220,10 +335,18 @@ static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2]); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + check_nanboxed(ctx, 2, t1, t2); + + gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, t1, t2); gen_nanbox_fpr(ctx, a->rd); + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); return true; } @@ -232,10 +355,18 @@ static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2]); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + check_nanboxed(ctx, 2, t1, t2); + + gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, t1, t2); gen_nanbox_fpr(ctx, a->rd); + mark_fs_dirty(ctx); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); return true; } @@ -245,11 +376,16 @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a) REQUIRE_EXT(ctx, RVF); TCGv t0 = tcg_temp_new(); + TCGv_i64 t1 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + check_nanboxed(ctx, 1, t1); + gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_w_s(t0, cpu_env, t1); gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); + tcg_temp_free(t0); + tcg_temp_free_i64(t1); return true; } @@ -259,11 +395,16 @@ static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a) REQUIRE_EXT(ctx, RVF); TCGv t0 = tcg_temp_new(); + TCGv_i64 t1 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + check_nanboxed(ctx, 1, t1); + gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_wu_s(t0, cpu_env, t1); gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); + tcg_temp_free(t0); + tcg_temp_free_i64(t1); return true; } @@ -291,10 +432,20 @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + TCGv t0 = tcg_temp_new(); - gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + check_nanboxed(ctx, 2, t1, t2); + + gen_helper_feq_s(t0, cpu_env, t1, t2); gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); return true; } @@ -302,10 +453,20 @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + TCGv t0 = tcg_temp_new(); - gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + check_nanboxed(ctx, 2, t1, t2); + + gen_helper_flt_s(t0, cpu_env, t1, t2); gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); return true; } @@ -313,10 +474,20 @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + TCGv t0 = tcg_temp_new(); - gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + tcg_gen_mov_i64(t2, cpu_fpr[a->rs2]); + check_nanboxed(ctx, 2, t1, t2); + + gen_helper_fle_s(t0, cpu_env, t1, t2); gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); return true; } @@ -326,12 +497,15 @@ static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a) REQUIRE_EXT(ctx, RVF); TCGv t0 = tcg_temp_new(); + TCGv_i64 t1 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + check_nanboxed(ctx, 1, t1); - gen_helper_fclass_s(t0, cpu_fpr[a->rs1]); - + gen_helper_fclass_s(t0, t1); gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); + tcg_temp_free(t0); + tcg_temp_free_i64(t1); return true; } @@ -400,10 +574,16 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) REQUIRE_EXT(ctx, RVF); TCGv t0 = tcg_temp_new(); + TCGv_i64 t1 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + check_nanboxed(ctx, 1, t1); + gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_l_s(t0, cpu_env, t1); gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + tcg_temp_free_i64(t1); return true; } @@ -413,10 +593,16 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a) REQUIRE_EXT(ctx, RVF); TCGv t0 = tcg_temp_new(); + TCGv_i64 t1 = tcg_temp_new_i64(); + tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); + check_nanboxed(ctx, 1, t1); + gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_lu_s(t0, cpu_env, t1); gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + tcg_temp_free_i64(t1); return true; } From patchwork Fri Jun 26 20:59:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11628719 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C4792161F for ; Fri, 26 Jun 2020 21:12:16 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A6C42208C7 for ; Fri, 26 Jun 2020 21:12:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A6C42208C7 Authentication-Results: mail.kernel.org; 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HT=e02c03301; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.Ht28Eh0_1593205890; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.Ht28Eh0_1593205890) by smtp.aliyun-inc.com(10.147.42.16); Sat, 27 Jun 2020 05:11:30 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 6/6] target/riscv: clean up fmv.w.x Date: Sat, 27 Jun 2020 04:59:17 +0800 Message-Id: <20200626205917.4545-7-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200626205917.4545-1-zhiwei_liu@c-sky.com> References: <20200626205917.4545-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/26 16:59:26 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, palmer@dabbelt.com, LIU Zhiwei , ianjiang.ict@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvf.inc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index b0379b9d1f..fabcd0eccf 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -554,11 +554,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); -#if defined(TARGET_RISCV64) - tcg_gen_mov_i64(cpu_fpr[a->rd], t0); -#else - tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); -#endif + tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0); gen_nanbox_fpr(ctx, a->rd); mark_fs_dirty(ctx);