From patchwork Mon Jun 29 13:07:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11630927 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C2ADF912 for ; Mon, 29 Jun 2020 13:09:54 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A328B23D37 for ; Mon, 29 Jun 2020 13:09:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A328B23D37 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:38422 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jptXl-00036Q-VU for patchwork-qemu-devel@patchwork.kernel.org; Mon, 29 Jun 2020 09:09:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50600) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jptVl-0008Gd-9e; Mon, 29 Jun 2020 09:07:49 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:48628) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jptVg-0003Y8-Nd; Mon, 29 Jun 2020 09:07:49 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.3082795|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.010747-0.000981833-0.988271; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03297; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=8; SR=0; TI=SMTPD_---.HucVN.U_1593436054; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.HucVN.U_1593436054) by smtp.aliyun-inc.com(10.147.44.145); Mon, 29 Jun 2020 21:07:35 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 1/2] tcg/tcg-op: Fix nonatomic_op load with MO_SIGN Date: Mon, 29 Jun 2020 21:07:30 +0800 Message-Id: <20200629130731.1080-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200629130731.1080-1-zhiwei_liu@c-sky.com> References: <20200629130731.1080-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/29 09:07:36 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" As an op follows load, MO_SIGN should not be cleared. Thus, we can call tcg_gen_atomic_*_i64 with a smaller Memop than MO_Q. Signed-off-by: LIU Zhiwei --- tcg/tcg-op.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index e60b74fb82..75b31048f5 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3189,7 +3189,7 @@ static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, memop = tcg_canonicalize_memop(memop, 0, 0); - tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_qemu_ld_i32(t1, addr, idx, memop); gen(t2, t1, val); tcg_gen_qemu_st_i32(t2, addr, idx, memop); @@ -3232,7 +3232,7 @@ static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, memop = tcg_canonicalize_memop(memop, 1, 0); - tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_qemu_ld_i64(t1, addr, idx, memop); gen(t2, t1, val); tcg_gen_qemu_st_i64(t2, addr, idx, memop); From patchwork Mon Jun 29 13:07:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11630929 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 29232138C for ; Mon, 29 Jun 2020 13:11:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0921723D4D for ; Mon, 29 Jun 2020 13:11:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0921723D4D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:40984 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jptZ7-0004JI-9e for patchwork-qemu-devel@patchwork.kernel.org; Mon, 29 Jun 2020 09:11:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50598) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jptVk-0008EH-0F; Mon, 29 Jun 2020 09:07:48 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:42935) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jptVf-0003Y9-Ts; Mon, 29 Jun 2020 09:07:47 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07438486|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0520955-0.00143157-0.946473; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03305; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=8; RT=8; SR=0; TI=SMTPD_---.HucVN.U_1593436054; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.HucVN.U_1593436054) by smtp.aliyun-inc.com(10.147.44.145); Mon, 29 Jun 2020 21:07:35 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 2/2] target/riscv: Do amo*.w insns operate with 32 bits Date: Mon, 29 Jun 2020 21:07:31 +0800 Message-Id: <20200629130731.1080-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200629130731.1080-1-zhiwei_liu@c-sky.com> References: <20200629130731.1080-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/29 09:07:36 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, palmer@dabbelt.com, LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" For amo*.w insns, we should only calculate on the 32 bits data either from the register or the memory. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rva.inc.c | 60 +++++++++++++++++++------ 1 file changed, 47 insertions(+), 13 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c index be8a9f06dd..6b3fc14436 100644 --- a/target/riscv/insn_trans/trans_rva.inc.c +++ b/target/riscv/insn_trans/trans_rva.inc.c @@ -81,19 +81,26 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) return true; } -static bool gen_amo(DisasContext *ctx, arg_atomic *a, - void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp), - MemOp mop) +static bool +gen_amo_w(DisasContext *ctx, arg_atomic *a, + void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp), + MemOp mop, bool sign) { TCGv src1 = tcg_temp_new(); TCGv src2 = tcg_temp_new(); gen_get_gpr(src1, a->rs1); gen_get_gpr(src2, a->rs2); + if (sign) { + tcg_gen_ext32s_tl(src2, src2); + } else { + tcg_gen_ext32u_tl(src2, src2); + } (*func)(src2, src1, src2, ctx->mem_idx, mop); - + tcg_gen_ext32s_tl(src2, src2); gen_set_gpr(a->rd, src2); + tcg_temp_free(src1); tcg_temp_free(src2); return true; @@ -114,59 +121,86 @@ static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a) static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL)); + return gen_amo_w(ctx, a, &tcg_gen_atomic_xchg_tl, + (MO_ALIGN | MO_TESL), true); } static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL)); + return gen_amo_w(ctx, a, &tcg_gen_atomic_fetch_add_tl, + (MO_ALIGN | MO_TESL), true); } static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL)); + return gen_amo_w(ctx, a, &tcg_gen_atomic_fetch_xor_tl, + (MO_ALIGN | MO_TESL), true); } static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL)); + return gen_amo_w(ctx, a, &tcg_gen_atomic_fetch_and_tl, + (MO_ALIGN | MO_TESL), true); } static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL)); + return gen_amo_w(ctx, a, &tcg_gen_atomic_fetch_or_tl, + (MO_ALIGN | MO_TESL), true); } static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL)); + return gen_amo_w(ctx, a, &tcg_gen_atomic_fetch_smin_tl, + (MO_ALIGN | MO_TESL), true); } static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL)); + return gen_amo_w(ctx, a, &tcg_gen_atomic_fetch_smax_tl, + (MO_ALIGN | MO_TESL), true); } static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL)); + return gen_amo_w(ctx, a, &tcg_gen_atomic_fetch_umin_tl, + (MO_ALIGN | MO_TEUL), false); } static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL)); + return gen_amo_w(ctx, a, &tcg_gen_atomic_fetch_umax_tl, + (MO_ALIGN | MO_TEUL), false); } #ifdef TARGET_RISCV64 +static bool gen_amo(DisasContext *ctx, arg_atomic *a, + void(*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp), + MemOp mop) +{ + TCGv src1 = tcg_temp_new(); + TCGv src2 = tcg_temp_new(); + + gen_get_gpr(src1, a->rs1); + gen_get_gpr(src2, a->rs2); + + (*func)(src2, src1, src2, ctx->mem_idx, mop); + + gen_set_gpr(a->rd, src2); + tcg_temp_free(src1); + tcg_temp_free(src2); + return true; +} + static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) { return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);