From patchwork Mon Jul 6 19:00:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 11646701 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D6DAF618 for ; Mon, 6 Jul 2020 19:00:34 +0000 (UTC) Received: by mail.kernel.org (Postfix) id D0757206CD; Mon, 6 Jul 2020 19:00:34 +0000 (UTC) Delivered-To: soc@kernel.org Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4F2C520675; Mon, 6 Jul 2020 19:00:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1594062034; bh=E5pI6IrxLk53qzMq2tNX5wp2ren9JrhZ6JcIu58KLWg=; h=From:List-Id:To:Cc:Subject:Date:From; b=KY5s3AFuzeyiAREnBBAa7U6USJy8z11r/gxJj1VWVhu9ObBUW8SJoxzHx1jQneVE2 QfcXyf3u4/ONaAQ8pvyGqti2+RqEchz2+NZIsVf4bzk7rsrspqjuWfbiPNr8ieBF52 VFvOkVNedTnT2TV0IOLj31oE/P58b8G74C/5JCdw= From: Dinh Nguyen List-Id: To: arm@kernel.org, soc@kernel.org Cc: dinguyen@kernel.org Subject: [GIT PULL] SoCFPGA DTS fixes for v5.8 Date: Mon, 6 Jul 2020 14:00:32 -0500 Message-Id: <20200706190032.24084-1-dinguyen@kernel.org> X-Mailer: git-send-email 2.17.1 Hi Arnd, Kevin, and Olof: Please pull in these SoCFPGA DTS fixes for v5.8. Thanks, Dinh The following changes since commit dcb7fd82c75ee2d6e6f9d8cc71c52519ed52e258: Linux 5.8-rc4 (2020-07-05 16:20:22 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git tags/socfpga_fixes_for_v5.8 for you to fetch changes up to 2b7c6a78edd2b012e22aabd788757ad977ac54a9: arm64: dts: spcfpga: Align GIC, NAND and UART nodenames with dtschema (2020-07-06 13:46:01 -0500) ---------------------------------------------------------------- arm/arm64: dts: socfpga: fixes for v5.8 - Add status = "okay" in QSPI - Increase QSPI size in reg property - Fix dtschema for SoCFPGA platforms ---------------------------------------------------------------- Dinh Nguyen (3): arm64: dts: agilex: add status to qspi dts node arm64: dts: stratix10: add status to qspi dts node arm64: dts: stratix10: increase QSPI reg address in nand dts file Krzysztof Kozlowski (2): ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema arm64: dts: spcfpga: Align GIC, NAND and UART nodenames with dtschema arch/arm/boot/dts/socfpga.dtsi | 2 +- arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 1 + arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts | 7 ++++--- arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 1 + 6 files changed, 12 insertions(+), 9 deletions(-)