From patchwork Mon Jul 6 23:47:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647163 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 82A771398 for ; Mon, 6 Jul 2020 23:50:16 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4936B20672 for ; Mon, 6 Jul 2020 23:50:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Ffz/kCnp" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4936B20672 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:44912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsasJ-0006Hw-9p for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:50:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaq4-0000oJ-9Q for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:47:56 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:35407) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaq1-0000oE-UJ for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:47:55 -0400 Received: by mail-pl1-x644.google.com with SMTP id x9so2304386plr.2 for ; Mon, 06 Jul 2020 16:47:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HeQ/nBO5HEDoYbhaICqOSmOqI/yFLMc1WW4g0/8VI/0=; b=Ffz/kCnpbGAPv/AORSp7tE9m7hp19SLQcCpXwnREuQn8K1D4RkIggwpJG4Uf2CHzhk XQ/j2av/ZYx6d5TslZUOKbUF0CJUGXDTH3b2UEshGbAvBdZ4ueXipkG95SY7LtLln2sf oWG6I8EGHhKflW10cwKgFZSrFat3USYxlxrDWLALjJCkl6ooJT0qjsv4gMJ+lL/+dSbt IZrxiRlULVfeiUMU2OQnx2qkixqijWtgKyRRPOvxVvrOaoIdyC3kC6u3XKbZ4tSNUvWX X2+rmCeRreEQXy3fPQgxCcI7zW29dvnkk5OviUCfYKa4IaWWsJ0vbsm3udlvTOuBpR1u KSjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HeQ/nBO5HEDoYbhaICqOSmOqI/yFLMc1WW4g0/8VI/0=; b=t8/tpJ0MiWS6KzhWOXL3N8+HtO6Nht4P2gy7pXixl5fQayy3kwNguv5956p4AcZhwo f7/LBZAZpiPfbhrySn7RYvbC3fgxXQZg4cvOVC4iBW5ywryG0DITchwC2uRCLudSlxDr 06WygKDitLgBe2BpNGrV2xyqhYvQaG8hoyFP4eyPXURrSklpBxEUJ4pol7CtpfCYOHrg LXcmnsc0dTlWkxgi6Sj/LWGHswfUUhgQ3eeRKYcLKFIp5WjnZ7qAnL9SQH+HzSJ1XGWZ kEnnD2HyY5D07XzpjLI6CBGeN+uCtNFnmHQehTf0jCWJ1DC0xnbF2rCb3CH7jwDimCJJ 8DyA== X-Gm-Message-State: AOAM533t1QIFf0E3iWR1mpcnvJrDba7Fc5pyE4ZgKZfGUu6BtOxRgR0y F99QcCiCejyj2NiJ2HdfmhIfol55 X-Google-Smtp-Source: ABdhPJy09tWbK+7CHqwFX0CWexmD2kTQ3l8mXK7HR262uIwPubU5Wa7z1BOsaniYgWo7N/I+lApYvw== X-Received: by 2002:a17:902:bc44:: with SMTP id t4mr43176361plz.290.1594079272086; Mon, 06 Jul 2020 16:47:52 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:47:51 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 01/21] softfloat: make NO_SIGNALING_NANS runtime property Date: Mon, 6 Jul 2020 16:47:17 -0700 Message-Id: <20200706234737.32378-2-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=jcmvbkbc@gmail.com; helo=mail-pl1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" target/xtensa, the only user of NO_SIGNALING_NANS macro has FPU implementations with and without the corresponding property. With NO_SIGNALING_NANS being a macro they cannot be a part of the same QEMU executable. Replace macro with new property in float_status to allow cores with different FPU implementations coexist. Cc: Peter Maydell Cc: "Alex Bennée" Signed-off-by: Max Filippov Reviewed-by: Philippe Mathieu-Daudé --- fpu/softfloat-specialize.inc.c | 228 ++++++++++++++++---------------- include/fpu/softfloat-helpers.h | 5 + include/fpu/softfloat-types.h | 1 + 3 files changed, 117 insertions(+), 117 deletions(-) diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c index 44f5b661f831..b26bc039b0b6 100644 --- a/fpu/softfloat-specialize.inc.c +++ b/fpu/softfloat-specialize.inc.c @@ -79,13 +79,6 @@ this code that are retained. * version 2 or later. See the COPYING file in the top-level directory. */ -/* Define for architectures which deviate from IEEE in not supporting - * signaling NaNs (so all NaNs are treated as quiet). - */ -#if defined(TARGET_XTENSA) -#define NO_SIGNALING_NANS 1 -#endif - /* Define how the architecture discriminates signaling NaNs. * This done with the most significant bit of the fraction. * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008 @@ -111,12 +104,12 @@ static inline bool snan_bit_is_one(float_status *status) static bool parts_is_snan_frac(uint64_t frac, float_status *status) { -#ifdef NO_SIGNALING_NANS - return false; -#else - bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); - return msb == snan_bit_is_one(status); -#endif + if (status->no_signaling_nans) { + return false; + } else { + bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); + return msb == snan_bit_is_one(status); + } } /*---------------------------------------------------------------------------- @@ -170,9 +163,10 @@ static FloatParts parts_default_nan(float_status *status) static FloatParts parts_silence_nan(FloatParts a, float_status *status) { -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#elif defined(TARGET_HPPA) + if (status->no_signaling_nans) { + g_assert_not_reached(); + } +#if defined(TARGET_HPPA) a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else @@ -247,16 +241,16 @@ typedef struct { bool float16_is_quiet_nan(float16 a_, float_status *status) { -#ifdef NO_SIGNALING_NANS - return float16_is_any_nan(a_); -#else - uint16_t a = float16_val(a_); - if (snan_bit_is_one(status)) { - return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); + if (status->no_signaling_nans) { + return float16_is_any_nan(a_); } else { - return ((a & ~0x8000) >= 0x7C80); + uint16_t a = float16_val(a_); + if (snan_bit_is_one(status)) { + return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); + } else { + return ((a & ~0x8000) >= 0x7C80); + } } -#endif } /*---------------------------------------------------------------------------- @@ -266,16 +260,16 @@ bool float16_is_quiet_nan(float16 a_, float_status *status) bool float16_is_signaling_nan(float16 a_, float_status *status) { -#ifdef NO_SIGNALING_NANS - return 0; -#else - uint16_t a = float16_val(a_); - if (snan_bit_is_one(status)) { - return ((a & ~0x8000) >= 0x7C80); + if (status->no_signaling_nans) { + return 0; } else { - return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); + uint16_t a = float16_val(a_); + if (snan_bit_is_one(status)) { + return ((a & ~0x8000) >= 0x7C80); + } else { + return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); + } } -#endif } /*---------------------------------------------------------------------------- @@ -285,16 +279,16 @@ bool float16_is_signaling_nan(float16 a_, float_status *status) bool float32_is_quiet_nan(float32 a_, float_status *status) { -#ifdef NO_SIGNALING_NANS - return float32_is_any_nan(a_); -#else - uint32_t a = float32_val(a_); - if (snan_bit_is_one(status)) { - return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); + if (status->no_signaling_nans) { + return float32_is_any_nan(a_); } else { - return ((uint32_t)(a << 1) >= 0xFF800000); + uint32_t a = float32_val(a_); + if (snan_bit_is_one(status)) { + return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); + } else { + return ((uint32_t)(a << 1) >= 0xFF800000); + } } -#endif } /*---------------------------------------------------------------------------- @@ -304,16 +298,16 @@ bool float32_is_quiet_nan(float32 a_, float_status *status) bool float32_is_signaling_nan(float32 a_, float_status *status) { -#ifdef NO_SIGNALING_NANS - return 0; -#else - uint32_t a = float32_val(a_); - if (snan_bit_is_one(status)) { - return ((uint32_t)(a << 1) >= 0xFF800000); + if (status->no_signaling_nans) { + return 0; } else { - return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); + uint32_t a = float32_val(a_); + if (snan_bit_is_one(status)) { + return ((uint32_t)(a << 1) >= 0xFF800000); + } else { + return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); + } } -#endif } /*---------------------------------------------------------------------------- @@ -639,17 +633,17 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) bool float64_is_quiet_nan(float64 a_, float_status *status) { -#ifdef NO_SIGNALING_NANS - return float64_is_any_nan(a_); -#else - uint64_t a = float64_val(a_); - if (snan_bit_is_one(status)) { - return (((a >> 51) & 0xFFF) == 0xFFE) - && (a & 0x0007FFFFFFFFFFFFULL); + if (status->no_signaling_nans) { + return float64_is_any_nan(a_); } else { - return ((a << 1) >= 0xFFF0000000000000ULL); + uint64_t a = float64_val(a_); + if (snan_bit_is_one(status)) { + return (((a >> 51) & 0xFFF) == 0xFFE) + && (a & 0x0007FFFFFFFFFFFFULL); + } else { + return ((a << 1) >= 0xFFF0000000000000ULL); + } } -#endif } /*---------------------------------------------------------------------------- @@ -659,17 +653,17 @@ bool float64_is_quiet_nan(float64 a_, float_status *status) bool float64_is_signaling_nan(float64 a_, float_status *status) { -#ifdef NO_SIGNALING_NANS - return 0; -#else - uint64_t a = float64_val(a_); - if (snan_bit_is_one(status)) { - return ((a << 1) >= 0xFFF0000000000000ULL); + if (status->no_signaling_nans) { + return 0; } else { - return (((a >> 51) & 0xFFF) == 0xFFE) - && (a & UINT64_C(0x0007FFFFFFFFFFFF)); + uint64_t a = float64_val(a_); + if (snan_bit_is_one(status)) { + return ((a << 1) >= 0xFFF0000000000000ULL); + } else { + return (((a >> 51) & 0xFFF) == 0xFFE) + && (a & UINT64_C(0x0007FFFFFFFFFFFF)); + } } -#endif } /*---------------------------------------------------------------------------- @@ -778,21 +772,21 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) int floatx80_is_quiet_nan(floatx80 a, float_status *status) { -#ifdef NO_SIGNALING_NANS - return floatx80_is_any_nan(a); -#else - if (snan_bit_is_one(status)) { - uint64_t aLow; - - aLow = a.low & ~0x4000000000000000ULL; - return ((a.high & 0x7FFF) == 0x7FFF) - && (aLow << 1) - && (a.low == aLow); + if (status->no_signaling_nans) { + return floatx80_is_any_nan(a); } else { - return ((a.high & 0x7FFF) == 0x7FFF) - && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1))); + if (snan_bit_is_one(status)) { + uint64_t aLow; + + aLow = a.low & ~0x4000000000000000ULL; + return ((a.high & 0x7FFF) == 0x7FFF) + && (aLow << 1) + && (a.low == aLow); + } else { + return ((a.high & 0x7FFF) == 0x7FFF) + && (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1))); + } } -#endif } /*---------------------------------------------------------------------------- @@ -803,21 +797,21 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *status) int floatx80_is_signaling_nan(floatx80 a, float_status *status) { -#ifdef NO_SIGNALING_NANS - return 0; -#else - if (snan_bit_is_one(status)) { - return ((a.high & 0x7FFF) == 0x7FFF) - && ((a.low << 1) >= 0x8000000000000000ULL); + if (status->no_signaling_nans) { + return 0; } else { - uint64_t aLow; + if (snan_bit_is_one(status)) { + return ((a.high & 0x7FFF) == 0x7FFF) + && ((a.low << 1) >= 0x8000000000000000ULL); + } else { + uint64_t aLow; - aLow = a.low & ~UINT64_C(0x4000000000000000); - return ((a.high & 0x7FFF) == 0x7FFF) - && (uint64_t)(aLow << 1) - && (a.low == aLow); + aLow = a.low & ~UINT64_C(0x4000000000000000); + return ((a.high & 0x7FFF) == 0x7FFF) + && (uint64_t)(aLow << 1) + && (a.low == aLow); + } } -#endif } /*---------------------------------------------------------------------------- @@ -941,17 +935,17 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) bool float128_is_quiet_nan(float128 a, float_status *status) { -#ifdef NO_SIGNALING_NANS - return float128_is_any_nan(a); -#else - if (snan_bit_is_one(status)) { - return (((a.high >> 47) & 0xFFFF) == 0xFFFE) - && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); + if (status->no_signaling_nans) { + return float128_is_any_nan(a); } else { - return ((a.high << 1) >= 0xFFFF000000000000ULL) - && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); + if (snan_bit_is_one(status)) { + return (((a.high >> 47) & 0xFFFF) == 0xFFFE) + && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); + } else { + return ((a.high << 1) >= 0xFFFF000000000000ULL) + && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); + } } -#endif } /*---------------------------------------------------------------------------- @@ -961,17 +955,17 @@ bool float128_is_quiet_nan(float128 a, float_status *status) bool float128_is_signaling_nan(float128 a, float_status *status) { -#ifdef NO_SIGNALING_NANS - return 0; -#else - if (snan_bit_is_one(status)) { - return ((a.high << 1) >= 0xFFFF000000000000ULL) - && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); + if (status->no_signaling_nans) { + return 0; } else { - return (((a.high >> 47) & 0xFFFF) == 0xFFFE) - && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF))); + if (snan_bit_is_one(status)) { + return ((a.high << 1) >= 0xFFFF000000000000ULL) + && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); + } else { + return (((a.high >> 47) & 0xFFFF) == 0xFFFE) + && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF))); + } } -#endif } /*---------------------------------------------------------------------------- @@ -981,16 +975,16 @@ bool float128_is_signaling_nan(float128 a, float_status *status) float128 float128_silence_nan(float128 a, float_status *status) { -#ifdef NO_SIGNALING_NANS - g_assert_not_reached(); -#else - if (snan_bit_is_one(status)) { - return float128_default_nan(status); + if (status->no_signaling_nans) { + g_assert_not_reached(); } else { - a.high |= UINT64_C(0x0000800000000000); - return a; + if (snan_bit_is_one(status)) { + return float128_default_nan(status); + } else { + a.high |= UINT64_C(0x0000800000000000); + return a; + } } -#endif } /*---------------------------------------------------------------------------- diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 735ed6b653ee..e842f83a1285 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -95,6 +95,11 @@ static inline void set_snan_bit_is_one(bool val, float_status *status) status->snan_bit_is_one = val; } +static inline void set_no_signaling_nans(bool val, float_status *status) +{ + status->no_signaling_nans = val; +} + static inline bool get_float_detect_tininess(float_status *status) { return status->tininess_before_rounding; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 7680193ebc1c..10bd208e559f 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -167,6 +167,7 @@ typedef struct float_status { bool default_nan_mode; /* not always used -- see snan_bit_is_one() in softfloat-specialize.h */ bool snan_bit_is_one; + bool no_signaling_nans; } float_status; #endif /* SOFTFLOAT_TYPES_H */ From patchwork Mon Jul 6 23:47:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647157 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D045D60D for ; Mon, 6 Jul 2020 23:48:42 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A6890206E9 for ; Mon, 6 Jul 2020 23:48:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PXil+WvO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A6890206E9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36654 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsaqn-0002TY-Sx for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:48:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35288) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaq4-0000oj-FJ for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:47:56 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:40392) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaq2-0000oI-PQ for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:47:56 -0400 Received: by mail-pf1-x430.google.com with SMTP id u5so17622745pfn.7 for ; Mon, 06 Jul 2020 16:47:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5fZcWsFgtINbL3J+mcEvZWKMQgiYWvYOG6ARA8oxr8g=; b=PXil+WvOeuL0lV3Id9Lll8hPOJEdOK8GZlVB8wtopDF45lS6cfrUuORooubQ6CpDCa 7KhAnqAV+NxK6Vm6AX/Wb4OKN2jyHeIr7Y5Ay/NCOgk8/qoVGE0n8WN3XA45lsmZGHmE dJzGvWpdvRsxUU4zIVBPcDh2KNpYslwv5HpXyQ9tUzMMSA+N44S2cGYMYAiak4goaIJC +iy1lKOdpBhRalZhimvFzcwUAw+vJvbpHdDUoT54/Ze4/+ryuoyRyFt/UmQEbi46RXov vTJZuWewOfle7eoDLIj/4FaHbGFnfGrEST+J6T4n5E77FzfIKqbJTGtC4HOd0Rp+XlBF isZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5fZcWsFgtINbL3J+mcEvZWKMQgiYWvYOG6ARA8oxr8g=; b=Q8+JUG7hA/71JK89cKOxhE6v3u2kETAVhQr04TGknMR33EJ13Oj/2cX0sL9nXyi5ry yZjtaGLJcLfBDSYhvO84lFr6rAAH6XS/52mbYeLh9eUUOyNQJH16Ix1pqxNO9z42jH3i 84eDqJuouWaAyR+g6VnHmFoWY1iG3LEKFvivxoQ3yZ5NnG0WjnRvzGFGqxclBYg9kD3o fPgSs1jlV03n7+ky7CN76Q7z1F2EAy4EuFzzcp5RVbx2Af8yFeMpa4iXEUq8AM6bAln6 vrCKrD3aXHIiCS1oApt5r2UF/+DOV93Ct+U2KAxGFieAMleRnVkpjUHrzWB7UpU7bhGS tI+Q== X-Gm-Message-State: AOAM531vzftRGLYTIrmRTEk9JHpo5rGzGmDXIS0OkeshRPonuioZ0xff SidhRoTRZhrlCwh8IBbWsqAYhILc X-Google-Smtp-Source: ABdhPJywhiwHXKrlETP8/g7miSNEbQFEeNnEYLdRLf/B8FUxWQVkbEwkzrv0DMC0kNXxm6NZsjKL7Q== X-Received: by 2002:a63:5a1a:: with SMTP id o26mr41747427pgb.420.1594079273222; Mon, 06 Jul 2020 16:47:53 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:47:52 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 02/21] softfloat: pass float_status pointer to pickNaN Date: Mon, 6 Jul 2020 16:47:18 -0700 Message-Id: <20200706234737.32378-3-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=jcmvbkbc@gmail.com; helo=mail-pf1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Pass float_status structure pointer to the pickNaN so that machine-specific settings are available to NaN selection code. Add use_first_nan property to float_status and use it in Xtensa-specific pickNaN. Cc: Peter Maydell Cc: "Alex Bennée" Signed-off-by: Max Filippov Reviewed-by: Alex Bennée --- fpu/softfloat-specialize.inc.c | 30 ++++++++++++++++++++++++------ fpu/softfloat.c | 2 +- include/fpu/softfloat-helpers.h | 5 +++++ include/fpu/softfloat-types.h | 1 + 4 files changed, 31 insertions(+), 7 deletions(-) diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c index b26bc039b0b6..e17327b405c5 100644 --- a/fpu/softfloat-specialize.inc.c +++ b/fpu/softfloat-specialize.inc.c @@ -368,7 +368,7 @@ static float32 commonNaNToFloat32(commonNaNT a, float_status *status) *----------------------------------------------------------------------------*/ static int pickNaN(FloatClass a_cls, FloatClass b_cls, - bool aIsLargerSignificand) + bool aIsLargerSignificand, float_status *status) { #if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take @@ -401,7 +401,7 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, } else { return 1; } -#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K) +#elif defined(TARGET_PPC) || defined(TARGET_M68K) /* PowerPC propagation rules: * 1. A if it sNaN or qNaN * 2. B if it sNaN or qNaN @@ -426,6 +426,24 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, } else { return 1; } +#elif defined(TARGET_XTENSA) + /* + * Xtensa has two NaN propagation modes. + * Which one is active is controlled by float_status::use_first_nan. + */ + if (status->use_first_nan) { + if (is_nan(a_cls)) { + return 0; + } else { + return 1; + } + } else { + if (is_nan(b_cls)) { + return 1; + } else { + return 0; + } + } #else /* This implements x87 NaN propagation rules: * SNaN + QNaN => return the QNaN @@ -613,7 +631,7 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) aIsLargerSignificand = (av < bv) ? 1 : 0; } - if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { if (is_snan(b_cls)) { return float32_silence_nan(b, status); } @@ -751,7 +769,7 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) aIsLargerSignificand = (av < bv) ? 1 : 0; } - if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { if (is_snan(b_cls)) { return float64_silence_nan(b, status); } @@ -915,7 +933,7 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) aIsLargerSignificand = (a.high < b.high) ? 1 : 0; } - if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { if (is_snan(b_cls)) { return floatx80_silence_nan(b, status); } @@ -1063,7 +1081,7 @@ static float128 propagateFloat128NaN(float128 a, float128 b, aIsLargerSignificand = (a.high < b.high) ? 1 : 0; } - if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { if (is_snan(b_cls)) { return float128_silence_nan(b, status); } diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 5e9746c2876f..a89056a1816e 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -881,7 +881,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) } else { if (pickNaN(a.cls, b.cls, a.frac > b.frac || - (a.frac == b.frac && a.sign < b.sign))) { + (a.frac == b.frac && a.sign < b.sign), s)) { a = b; } if (is_snan(a.cls)) { diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index e842f83a1285..2f0674fbddec 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -95,6 +95,11 @@ static inline void set_snan_bit_is_one(bool val, float_status *status) status->snan_bit_is_one = val; } +static inline void set_use_first_nan(bool val, float_status *status) +{ + status->use_first_nan = val; +} + static inline void set_no_signaling_nans(bool val, float_status *status) { status->no_signaling_nans = val; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 10bd208e559f..aaee6e4cdd23 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -167,6 +167,7 @@ typedef struct float_status { bool default_nan_mode; /* not always used -- see snan_bit_is_one() in softfloat-specialize.h */ bool snan_bit_is_one; + bool use_first_nan; bool no_signaling_nans; } float_status; From patchwork Mon Jul 6 23:47:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647159 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10DB160D for ; Mon, 6 Jul 2020 23:48:44 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DBE02206E9 for ; Mon, 6 Jul 2020 23:48:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="tNXhf0jF" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DBE02206E9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36714 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsaqp-0002Uv-65 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:48:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35290) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaq4-0000pK-W6 for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:47:57 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:39880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaq3-0000oS-Fn for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:47:56 -0400 Received: by mail-pg1-x544.google.com with SMTP id z5so19121449pgb.6 for ; Mon, 06 Jul 2020 16:47:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BGXGCD6zrewH9FPgdNPWGPrbye7T6uSjNY56yD55Vis=; b=tNXhf0jFshtSUnNa5Qem6m0ucSEilZjvfVj8C43G7wFXPhKd24gAsZ7LTzB+uoOqIw 0sUEkmGui+CTH2zuQSG9T2iOGSnOt7GCAx+XyrA3zUrTdhTF6CJKoKw3uQUFLjY1j9Ts Qf12GrxMJjPd/lfH+wq090fFxCoYLA+9alT6m5FAQ098jPqpDXOhgSdqiieRQ1pgVC3r Uyx89EuYp7G6lS/YR9uO8rDewrXT74e41PVWqMIGO7cqu0SiJsaNjCJQ8Anud6+KWr86 EHj0hRa+h3hcQiuY2iqNaTxFQdhh5BudBtRfM2qEPL+RsWphd3cKKxnJBY5pGAbqyvwW uD3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BGXGCD6zrewH9FPgdNPWGPrbye7T6uSjNY56yD55Vis=; b=itc+aOuturOwz0/Y7bW2XTP5l/iIkRtl56Cwq45WkPyRO3u9TVOM1u4yIqabifcpuf Aqmlp96rBkyQESvaQgpVJq8WvbIqB74lOj6QcW+R8SX4unIB4sBFNqU3GfazA5NOyKSN gwZeESx7S5MmyO/cpMiawxKU3NA5QMPXfleqgVuH2lwXfAC7jVyDwnS9n1Rx3rsSRB/i y00UarFO6huVtUzc6e2a7MR3hV6vWUkvpqFYKwTyXC/zMfsQjSBWMwnL6kErzX16onIj z0j+WxK+VkKB4i0wLgByC8sIaZTSHqjicoL/g+XuaBxjY3Z3RNkaJFJ4gu2EbHZdLrVK c6vg== X-Gm-Message-State: AOAM5338LBfCvkkN4lVr29P+0asJUYAull4q6laj6O6F50fRS0fmBqSn aLvTp0GvIQYkCQdNaqRdtRtNtWyn X-Google-Smtp-Source: ABdhPJxm/ToJ+zxnFXF6U8i1jVZ8pYiSZbgCL11LVkvSLC20JN+ny9ZakYQxI4rFdJdxxxQDQeFWgQ== X-Received: by 2002:a63:3f42:: with SMTP id m63mr43552259pga.310.1594079274122; Mon, 06 Jul 2020 16:47:54 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.47.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:47:53 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 03/21] softfloat: add xtensa specialization for pickNaNMulAdd Date: Mon, 6 Jul 2020 16:47:19 -0700 Message-Id: <20200706234737.32378-4-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=jcmvbkbc@gmail.com; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov , =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" pickNaNMulAdd logic on Xtensa is the same as pickNaN when applied to the expression (a * b) + c. So with two pickNaN variants there must be two pickNaNMulAdd variants. Cc: Peter Maydell Cc: "Alex Bennée" Signed-off-by: Max Filippov Acked-by: Alex Bennée --- fpu/softfloat-specialize.inc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c index e17327b405c5..6b07d50efad3 100644 --- a/fpu/softfloat-specialize.inc.c +++ b/fpu/softfloat-specialize.inc.c @@ -574,6 +574,24 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { return 1; } +#elif defined(TARGET_XTENSA) + if (status->use_first_nan) { + if (is_nan(a_cls)) { + return 0; + } else if (is_nan(b_cls)) { + return 1; + } else { + return 2; + } + } else { + if (is_nan(c_cls)) { + return 2; + } else if (is_nan(b_cls)) { + return 1; + } else { + return 0; + } + } #else /* A default implementation: prefer a to b to c. * This is unlikely to actually match any real implementation. From patchwork Mon Jul 6 23:47:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647161 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8199960D for ; Mon, 6 Jul 2020 23:48:46 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 58034206E9 for ; Mon, 6 Jul 2020 23:48:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="LQGKeTSa" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 58034206E9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:37032 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsaqr-0002ce-Hj for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:48:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35318) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaq6-0000rh-EF for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:47:58 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:38315) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaq4-0000or-RU for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:47:58 -0400 Received: by mail-pj1-x1032.google.com with SMTP id k5so8126097pjg.3 for ; Mon, 06 Jul 2020 16:47:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WZrxDgWWXXP9PmlZyyBGjdv9eqT/iSmUhBtmo9zxmiE=; b=LQGKeTSaur4jfDn2clIb3qHJzsVFcPr3tmYKuaLGwUlMeOHbldkOxomtVxkX2r/HRT hg8YhyRNczLF7mDQURX0cDKir0wB0xCFL8wwdRdk0WzIKrpg1mQQ4qGd+JSMThZinBau CriAiEGzX1nvR/Fzah0zL6+yldpHoVgJoHCUPfxwBDp6NoHBkTwAUTBB4DzIR6B0GFyS yaKz/QZLrS3wElxIxLFuP+ZVglz5gS02N1NLT/X1du5ObmBYeo8ipeLkkXt+dNASlSf7 a+gUGXXy+gvKGkrOxJ87tKWWTpewQEAOlkDXJEInAv2qc3D4K7wzxKGMThErWx/RH+6+ RIiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WZrxDgWWXXP9PmlZyyBGjdv9eqT/iSmUhBtmo9zxmiE=; b=koY8PTiTm9yiOARde+8smvL5Hqbz6Mh8zpIWFdn1I/0P3eQ6XGSXVkkXVvAOKoJryT xlWR22XBTyy3YYDrFQsU6GfBsorfFU4pFB7mGgp9VIxtQGpHOih0kj1mqXn6oPOWkRps BnUUR/v+dDLjGShbJ9B3TQUwH3MkH5WnXjB18Agdjg8g+9sHf7IXVwmG1fePlnzh26RX FMxI6dR6ANJd/Kl7ddGs2DJzqZT9XvTLDg8Ho5dWLuE41AhiCMyZZ2tbJLv1HUK5ouyq jeOI1XuY4aBpOc0Y+/W+xPViYJvPqUlWZJErMINRirm9L/6o1UsPQExFv3cPcSEBNOVU pJOg== X-Gm-Message-State: AOAM530unJsQlzxPozP587CbZS53iyVo4y1mwshsq/L4pWTWhtbsfE40 Xp81GUSSanQtPwpH6jHbCWxSX/fl X-Google-Smtp-Source: ABdhPJxmk7BTsnXEllQwPRIPePeS7svrlo9nl9CBUIKoROaqfWTq3ls2LA4q45JjQRUMNVWB5zGl6Q== X-Received: by 2002:a17:902:8d87:: with SMTP id v7mr42105297plo.73.1594079275062; Mon, 06 Jul 2020 16:47:55 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.47.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:47:54 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name Date: Mon, 6 Jul 2020 16:47:20 -0700 Message-Id: <20200706234737.32378-5-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=jcmvbkbc@gmail.com; helo=mail-pj1-x1032.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Register file name may not uniquely identify a register file in the set of configurations. E.g. floating point registers may have different size in different configurations. Use register file geometry as additional identifier. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 2 +- target/xtensa/helper.c | 4 +++- target/xtensa/translate.c | 35 +++++++++++++++++++++++++++-------- 3 files changed, 31 insertions(+), 10 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 0c96181212a5..0409aa6189cf 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -598,7 +598,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, void xtensa_collect_sr_names(const XtensaConfig *config); void xtensa_translate_init(void); -void **xtensa_get_regfile_by_name(const char *name); +void **xtensa_get_regfile_by_name(const char *name, int entries, int bits); void xtensa_breakpoint_handler(CPUState *cs); void xtensa_register_core(XtensaConfigList *node); void xtensa_sim_open_console(Chardev *chr); diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 7073381f03b2..05e2b7f70a1e 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -133,8 +133,10 @@ static void init_libisa(XtensaConfig *config) config->regfile = g_new(void **, regfiles); for (i = 0; i < regfiles; ++i) { const char *name = xtensa_regfile_name(config->isa, i); + int entries = xtensa_regfile_num_entries(config->isa, i); + int bits = xtensa_regfile_num_bits(config->isa, i); - config->regfile[i] = xtensa_get_regfile_by_name(name); + config->regfile[i] = xtensa_get_regfile_by_name(name, entries, bits); #ifdef DEBUG if (config->regfile[i] == NULL) { fprintf(stderr, "regfile '%s' not found for %s\n", diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 03d796d7a1ed..9838bf6b3ec5 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -227,24 +227,43 @@ void xtensa_translate_init(void) "exclusive_val"); } -void **xtensa_get_regfile_by_name(const char *name) +void **xtensa_get_regfile_by_name(const char *name, int entries, int bits) { + char *geometry_name; + void **res; + if (xtensa_regfile_table == NULL) { xtensa_regfile_table = g_hash_table_new(g_str_hash, g_str_equal); + /* + * AR is special. Xtensa translator uses it as a current register + * window, but configuration overlays represent it as a complete + * physical register file. + */ g_hash_table_insert(xtensa_regfile_table, - (void *)"AR", (void *)cpu_R); + (void *)"AR 16x32", (void *)cpu_R); g_hash_table_insert(xtensa_regfile_table, - (void *)"MR", (void *)cpu_MR); + (void *)"AR 32x32", (void *)cpu_R); g_hash_table_insert(xtensa_regfile_table, - (void *)"FR", (void *)cpu_FR); + (void *)"AR 64x32", (void *)cpu_R); + g_hash_table_insert(xtensa_regfile_table, - (void *)"BR", (void *)cpu_BR); + (void *)"MR 4x32", (void *)cpu_MR); + g_hash_table_insert(xtensa_regfile_table, - (void *)"BR4", (void *)cpu_BR4); + (void *)"FR 16x32", (void *)cpu_FR); + g_hash_table_insert(xtensa_regfile_table, - (void *)"BR8", (void *)cpu_BR8); + (void *)"BR 16x1", (void *)cpu_BR); + g_hash_table_insert(xtensa_regfile_table, + (void *)"BR4 4x4", (void *)cpu_BR4); + g_hash_table_insert(xtensa_regfile_table, + (void *)"BR8 2x8", (void *)cpu_BR8); } - return (void **)g_hash_table_lookup(xtensa_regfile_table, (void *)name); + + geometry_name = g_strdup_printf("%s %dx%d", name, entries, bits); + res = (void **)g_hash_table_lookup(xtensa_regfile_table, geometry_name); + g_free(geometry_name); + return res; } static inline bool option_enabled(DisasContext *dc, int opt) From patchwork Mon Jul 6 23:47:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647165 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 40E2014DD for ; Mon, 6 Jul 2020 23:50:17 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 17FE520672 for ; Mon, 6 Jul 2020 23:50:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pNkfUaNn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 17FE520672 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:45022 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsasK-0006KV-Aa for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:50:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaq7-0000tf-5z for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:47:59 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:43184) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaq5-0000pj-HG for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:47:58 -0400 Received: by mail-pg1-x542.google.com with SMTP id w2so18317553pgg.10 for ; Mon, 06 Jul 2020 16:47:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OxuARGdyDb7zyHOtMNspwtFCmEXAy7U1ZwwaIWB/blY=; b=pNkfUaNnMJrm59wBjCi5o++U/VanYUI7zIQAjxwrJFL1xOr2OvhKvXol0pWJT+c+9y sbT9aZHpVgmipXWOEQ4p5b8CL2a25R9/M1evJUQDRB+7632T0cS9NUuq7JeT6lFYbOnA SbO/hk5aJn5ABLKHHH0JAjvOZ4KuSk+NcT7cdIbIOqrIJQ4Ln95cFkrPB7fzvSCaoxeS xv6xnlw4cTVJ57oCuuZYbUTgwmXikr/r7t2i+EdneyLQiOpVhWQ2yIqIXCjwPSunT8Zu TZTfveAJUgvstyAAidgH358fqhjRLZ4aWNW0bfFKdoOutTQ7GTSNiK4OE8LQYQxYWo9I 8E5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OxuARGdyDb7zyHOtMNspwtFCmEXAy7U1ZwwaIWB/blY=; b=qc+PfP8VZplsYtFlpP+c7vTTXrvqndlVwc8ohEb9Sp5OdFtUJ9IOKph/HqG7muxowm cZ5P9Q3P3BYl0dwMjXhf5ozSLgdz79uAc0lXUXUexYtBZ8yJtkE1NQL5MZSerRmOXx97 REM3ePPw5VEhFphiNCbCWukdX0EmHblThxGbwyr3Bo7mOf3NpRulgGio2qOKKN1RLBXN CQFYL1FL9V0gvaNvEVCZxP4VT+YttAKZeYVuiQ1gaW0Idj2FUyneNCQRUfp8XWAYudOt e0rrW65MOA86peSKrGlLawK+V8acChlf31alkMy4+qO2ekC8kCJL1HJYaR5p4w0mnVWi pprw== X-Gm-Message-State: AOAM5316r6BM8Xm580Te22Py3E3w1sgRula4YfHbd4WPv2Dkt2fnAIZY ySwHj5HuhUwpOeuLuhQ8qd2HRRyV X-Google-Smtp-Source: ABdhPJxz6lD60sCPccd7AIY7obnCou1RKaeafDl74vlyuc8mTzfvI8836GFx1MCyHZ+Ml8G1UYL5kg== X-Received: by 2002:a63:5509:: with SMTP id j9mr41698729pgb.195.1594079276102; Mon, 06 Jul 2020 16:47:56 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.47.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:47:55 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 05/21] target/xtensa: support copying registers up to 64 bits wide Date: Mon, 6 Jul 2020 16:47:21 -0700 Message-Id: <20200706234737.32378-6-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=jcmvbkbc@gmail.com; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" FLIX dependency breaking code assumes that all registers are 32 bit wide. This may not always be correct. Extract actual register width from the associated register file and use it to create temporaries of correct width and generate correct data movement instructions. Signed-off-by: Max Filippov --- target/xtensa/cpu.h | 1 + target/xtensa/translate.c | 26 +++++++++++++++++++++----- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 0409aa6189cf..960f6573447f 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -359,6 +359,7 @@ typedef struct opcode_arg { uint32_t raw_imm; void *in; void *out; + uint32_t num_bits; } OpcodeArg; typedef struct DisasContext DisasContext; diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 9838bf6b3ec5..bc01a720719d 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -943,10 +943,10 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) for (opnd = vopnd = 0; opnd < opnds; ++opnd) { void **register_file = NULL; + xtensa_regfile rf; if (xtensa_operand_is_register(isa, opc, opnd)) { - xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd); - + rf = xtensa_operand_regfile(isa, opc, opnd); register_file = dc->config->regfile[rf]; if (rf == dc->config->a_regfile) { @@ -972,6 +972,9 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) if (register_file) { arg[vopnd].in = register_file[v]; arg[vopnd].out = register_file[v]; + arg[vopnd].num_bits = xtensa_regfile_num_bits(isa, rf); + } else { + arg[vopnd].num_bits = 32; } ++vopnd; } @@ -1111,8 +1114,15 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) for (i = j = 0; i < n_arg_copy; ++i) { if (i == 0 || arg_copy[i].resource != resource) { resource = arg_copy[i].resource; - temp = tcg_temp_local_new(); - tcg_gen_mov_i32(temp, arg_copy[i].arg->in); + if (arg_copy[i].arg->num_bits <= 32) { + temp = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(temp, arg_copy[i].arg->in); + } else if (arg_copy[i].arg->num_bits <= 64) { + temp = tcg_temp_local_new_i64(); + tcg_gen_mov_i64(temp, arg_copy[i].arg->in); + } else { + g_assert_not_reached(); + } arg_copy[i].temp = temp; if (i != j) { @@ -1143,7 +1153,13 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) } for (i = 0; i < n_arg_copy; ++i) { - tcg_temp_free(arg_copy[i].temp); + if (arg_copy[i].arg->num_bits <= 32) { + tcg_temp_free_i32(arg_copy[i].temp); + } else if (arg_copy[i].arg->num_bits <= 64) { + tcg_temp_free_i64(arg_copy[i].temp); + } else { + g_assert_not_reached(); + } } if (dc->base.is_jmp == DISAS_NEXT) { From patchwork Mon Jul 6 23:47:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647173 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DFED21398 for ; Mon, 6 Jul 2020 23:51:57 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B53AB20672 for ; Mon, 6 Jul 2020 23:51:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UJvPxKc4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B53AB20672 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:53322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsatw-0001GA-UG for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:51:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35340) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaq8-0000vr-0e for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:00 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:38623) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaq6-0000rm-C5 for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:47:59 -0400 Received: by mail-pg1-x542.google.com with SMTP id e8so19131647pgc.5 for ; Mon, 06 Jul 2020 16:47:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BuTRUcVfw0Tz3LwW4i2KF4kpD7J/2e1ErR7YqSKxXz4=; b=UJvPxKc4HvTa/ERexNxETRAM7bhUdVw7x4/OGxph9CWguFA5dnBkZIl9UjRxhgyokv uhrYHKrv2/Q8zeop8+k1XNNd2NJZXBhBpVNz3ZoydQW2MXUtVGsFTMYt+Vqfuoy2xfFe oJnrx2+8TY6PEoLyexdOkjmh7sYGYBzAhuZSK/sbjXS+SPfzhaVKH+eBcNTNZ2AEBHMP nLSSiCMDpoPagD2cMig2Aq8HS10lNkjMTx8tnPnpLNHUeSwmN2qV5a5zdTZFeJ1mozzW wymLdqYllsKu663H5lYdTwyi97mW0Q9M4WTf6z5bsXovG+YCNWTXjGGElXf1Ga4DyTi3 oJeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BuTRUcVfw0Tz3LwW4i2KF4kpD7J/2e1ErR7YqSKxXz4=; b=gV9cHGcX+CkzLO8PyasStXLr/YKOUGbTPWYW1EB+1i/gcllgv6l17Vw/pRhO8d+g0+ dbqXHJXUxZoP6ym5H3ozX9FTKEH0CLJLC3/vyJxwzjhOtDDlaXRJERNHsNv4VT76/3Ex uEdLAtotHqiD9S7FiBGvG9+sth1gJzxo8xmeH9ICV+i49YgXgt9cRsmajRU4SL38MmTP SVv59JTa+a0M2zlJk2HTxW0nqGm9Ap2YyUawiTiTXwzj/Gjm2GQXyA86Mj3fEhdBC3NV BqHYUNQIZHSwC125feFCnge6VixTMYR7RmMGxQrSFJ359n/Uu8wQy/zpqp/HVOszkUx9 5lcQ== X-Gm-Message-State: AOAM531BGtGRobJmArNXgbwHdhFlL+k+vgwBXmlGdROGFI9Wed3CWAOa shePa9HLdxcGI715KMbx56Ic5sW7 X-Google-Smtp-Source: ABdhPJz5d6X5UBRxRxpGkdlI/ycr/NATbXeKiwV/9fCVtVXsHLAFdJ4tHfLamlz9R65+C+MlnRN/NA== X-Received: by 2002:a63:125f:: with SMTP id 31mr44009037pgs.239.1594079276925; Mon, 06 Jul 2020 16:47:56 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:47:56 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 06/21] target/xtensa: rename FPU2000 translators and helpers Date: Mon, 6 Jul 2020 16:47:22 -0700 Message-Id: <20200706234737.32378-7-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=jcmvbkbc@gmail.com; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Add _s suffix to all FPU2000 opcode translators and helpers that also have double-precision variant to unify naming and allow adding DFPU implementations. Add _fpu2k_ to the name of wur_fcr helper to make space for the DFPU wur_fcr helper. Signed-off-by: Max Filippov Reviewed-by: Richard Henderson --- target/xtensa/fpu_helper.c | 10 +++++----- target/xtensa/helper.h | 10 +++++----- target/xtensa/translate.c | 20 ++++++++++---------- 3 files changed, 20 insertions(+), 20 deletions(-) diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index 87487293f9a1..57a284924045 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -33,7 +33,7 @@ #include "exec/exec-all.h" #include "fpu/softfloat.h" -void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v) +void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) { static const int rounding_mode[] = { float_round_nearest_even, @@ -82,7 +82,7 @@ float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) &env->fp_status); } -uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale) +uint32_t HELPER(ftoi_s)(float32 v, uint32_t rounding_mode, uint32_t scale) { float_status fp_status = {0}; @@ -90,7 +90,7 @@ uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale) return float32_to_int32(float32_scalbn(v, scale, &fp_status), &fp_status); } -uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) +uint32_t HELPER(ftoui_s)(float32 v, uint32_t rounding_mode, uint32_t scale) { float_status fp_status = {0}; float32 res; @@ -106,13 +106,13 @@ uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) } } -float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale) +float32 HELPER(itof_s)(CPUXtensaState *env, uint32_t v, uint32_t scale) { return float32_scalbn(int32_to_float32(v, &env->fp_status), (int32_t)scale, &env->fp_status); } -float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale) +float32 HELPER(uitof_s)(CPUXtensaState *env, uint32_t v, uint32_t scale) { return float32_scalbn(uint32_to_float32(v, &env->fp_status), (int32_t)scale, &env->fp_status); diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index 8532de0b35f5..a692254fe10a 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -46,7 +46,7 @@ DEF_HELPER_3(wsr_dbreaka, void, env, i32, i32) DEF_HELPER_3(wsr_dbreakc, void, env, i32, i32) #endif -DEF_HELPER_2(wur_fcr, void, env, i32) +DEF_HELPER_2(wur_fpu2k_fcr, void, env, i32) DEF_HELPER_FLAGS_1(abs_s, TCG_CALL_NO_RWG_SE, f32, f32) DEF_HELPER_FLAGS_1(neg_s, TCG_CALL_NO_RWG_SE, f32, f32) DEF_HELPER_3(add_s, f32, env, f32, f32) @@ -54,10 +54,10 @@ DEF_HELPER_3(sub_s, f32, env, f32, f32) DEF_HELPER_3(mul_s, f32, env, f32, f32) DEF_HELPER_4(madd_s, f32, env, f32, f32, f32) DEF_HELPER_4(msub_s, f32, env, f32, f32, f32) -DEF_HELPER_FLAGS_3(ftoi, TCG_CALL_NO_RWG_SE, i32, f32, i32, i32) -DEF_HELPER_FLAGS_3(ftoui, TCG_CALL_NO_RWG_SE, i32, f32, i32, i32) -DEF_HELPER_3(itof, f32, env, i32, i32) -DEF_HELPER_3(uitof, f32, env, i32, i32) +DEF_HELPER_FLAGS_3(ftoi_s, TCG_CALL_NO_RWG_SE, i32, f32, i32, i32) +DEF_HELPER_FLAGS_3(ftoui_s, TCG_CALL_NO_RWG_SE, i32, f32, i32, i32) +DEF_HELPER_3(itof_s, f32, env, i32, i32) +DEF_HELPER_3(uitof_s, f32, env, i32, i32) DEF_HELPER_4(un_s, void, env, i32, f32, f32) DEF_HELPER_4(oeq_s, void, env, i32, f32, f32) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index bc01a720719d..0deaeef6b5fa 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -2813,10 +2813,10 @@ static void translate_wur(DisasContext *dc, const OpcodeArg arg[], tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in); } -static void translate_wur_fcr(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - gen_helper_wur_fcr(cpu_env, arg[0].in); + gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in); } static void translate_wur_fsr(DisasContext *dc, const OpcodeArg arg[], @@ -5583,7 +5583,7 @@ static const XtensaOpcodeOps core_ops[] = { .par = (const uint32_t[]){EXPSTATE}, }, { .name = "wur.fcr", - .translate = translate_wur_fcr, + .translate = translate_wur_fpu2k_fcr, .par = (const uint32_t[]){FCR}, .coprocessor = 0x1, }, { @@ -6373,9 +6373,9 @@ static void translate_float_s(DisasContext *dc, const OpcodeArg arg[], TCGv_i32 scale = tcg_const_i32(-arg[2].imm); if (par[0]) { - gen_helper_uitof(arg[0].out, cpu_env, arg[1].in, scale); + gen_helper_uitof_s(arg[0].out, cpu_env, arg[1].in, scale); } else { - gen_helper_itof(arg[0].out, cpu_env, arg[1].in, scale); + gen_helper_itof_s(arg[0].out, cpu_env, arg[1].in, scale); } tcg_temp_free(scale); } @@ -6387,11 +6387,11 @@ static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[], TCGv_i32 scale = tcg_const_i32(arg[2].imm); if (par[1]) { - gen_helper_ftoui(arg[0].out, arg[1].in, - rounding_mode, scale); + gen_helper_ftoui_s(arg[0].out, arg[1].in, + rounding_mode, scale); } else { - gen_helper_ftoi(arg[0].out, arg[1].in, - rounding_mode, scale); + gen_helper_ftoi_s(arg[0].out, arg[1].in, + rounding_mode, scale); } tcg_temp_free(rounding_mode); tcg_temp_free(scale); From patchwork Mon Jul 6 23:47:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647167 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 399EF60D for ; Mon, 6 Jul 2020 23:50:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1078220672 for ; Mon, 6 Jul 2020 23:50:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="srm4Oetv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1078220672 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:45048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsasL-0006LB-9e for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:50:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35354) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaq8-0000xt-T3 for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:00 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:46817) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaq7-0000st-Af for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:00 -0400 Received: by mail-pf1-x444.google.com with SMTP id i14so1136274pfu.13 for ; Mon, 06 Jul 2020 16:47:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oeaiwHJekTGuu/i90XgUZWAnMUSgKNijCQLv8/PbPh8=; b=srm4Oetvx42IW6H6Qgm6+tl8TBD5VUNsjYTL5BI9R3kjOOklHC4DfJUj1heKT7Kt8E 311veSX7UUnDBxfzI826LxKjiWXUJhiN1hXKbWY1yItwhxj/duuLCNryJKRiS+yQinGM 3mTHCJOqCoBLbqh4z6rxIFwxiOMoIiduBC5LXmARN25UU+h4iRVMpZ7EaVHpGLMC6RjW 7cyd6Ig8AYeVmGJTUv+7gGTA0n45+98wDTCaGl8eeEhaxZGfES9I+snfZnim3J2ODr/j XaqbOkhs7dlDmnKHwLDG7NF1vvD+ScOPmhonT4HcqObatHB0NrEWTu9xyou+0dIdo+0c SMFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oeaiwHJekTGuu/i90XgUZWAnMUSgKNijCQLv8/PbPh8=; b=KPhc8VrMdTFHqoRvKZBfDX9qFDuIIw9BqIpnmjpQcxd8xuzb1osPOsSC5TtRoz7xJF DMkeanJ3TTOIfhcNFp8dl9llBbrDsJD5W/mVyCPiyeIWCOShxVYX/O2cgYJzow9JFtIU PBWNtzU8Qt8FZZYHTyLmg9g531lTZMQLUiJpkB3YrvuQ/6qcnpEjwpd7axnMAqXwLEyt KTinGZSOo++JrDx4yJBgmldoG3mKg3ijG8z/WhYM9Fpj9MFzzGrAsCoRkGH0KvFPtYDj GpP2FFWWtlgVTu6qYVwir5+F+BTkQR0TjJwKSaPKgHkwXPHeZrzD1/pMLipHwgB0S1/d UCfQ== X-Gm-Message-State: AOAM531rfaK70As/fcjdc8N+CD973daPgMiu4vak1EWjiCkpbLS6lHzT 9PcLznN2U7o3xzeZRTJRpSgmJ8lR X-Google-Smtp-Source: ABdhPJx00D792c47tDVHl+2FGhvoZglmon8/jHK+afwsSxo3NVurQsxDFLZyF+g68Hh3hc1qZ4njBg== X-Received: by 2002:a63:cb05:: with SMTP id p5mr17107893pgg.120.1594079277841; Mon, 06 Jul 2020 16:47:57 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.47.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:47:57 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 07/21] target/xtensa: move FSR/FCR register accessors Date: Mon, 6 Jul 2020 16:47:23 -0700 Message-Id: <20200706234737.32378-8-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=jcmvbkbc@gmail.com; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Move FSR/FCR register accessors from core opcodes to FPU2000 opcodes as they are FPU2000-specific. Signed-off-by: Max Filippov Reviewed-by: Richard Henderson --- target/xtensa/translate.c | 64 +++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 0deaeef6b5fa..f859cd3f0818 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -2813,18 +2813,6 @@ static void translate_wur(DisasContext *dc, const OpcodeArg arg[], tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in); } -static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) -{ - gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in); -} - -static void translate_wur_fsr(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) -{ - tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80); -} - static void translate_xor(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -4665,16 +4653,6 @@ static const XtensaOpcodeOps core_ops[] = { .name = "rur.expstate", .translate = translate_rur, .par = (const uint32_t[]){EXPSTATE}, - }, { - .name = "rur.fcr", - .translate = translate_rur, - .par = (const uint32_t[]){FCR}, - .coprocessor = 0x1, - }, { - .name = "rur.fsr", - .translate = translate_rur, - .par = (const uint32_t[]){FSR}, - .coprocessor = 0x1, }, { .name = "rur.threadptr", .translate = translate_rur, @@ -5581,16 +5559,6 @@ static const XtensaOpcodeOps core_ops[] = { .name = "wur.expstate", .translate = translate_wur, .par = (const uint32_t[]){EXPSTATE}, - }, { - .name = "wur.fcr", - .translate = translate_wur_fpu2k_fcr, - .par = (const uint32_t[]){FCR}, - .coprocessor = 0x1, - }, { - .name = "wur.fsr", - .translate = translate_wur_fsr, - .par = (const uint32_t[]){FSR}, - .coprocessor = 0x1, }, { .name = "wur.threadptr", .translate = translate_wur, @@ -6510,6 +6478,18 @@ static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[], tcg_gen_mov_i32(arg[0].out, arg[1].in); } +static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in); +} + +static void translate_wur_fpu2k_fsr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80); +} + static const XtensaOpcodeOps fpu2000_ops[] = { { .name = "abs.s", @@ -6632,6 +6612,16 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .translate = translate_ftoi_s, .par = (const uint32_t[]){float_round_nearest_even, false}, .coprocessor = 0x1, + }, { + .name = "rur.fcr", + .translate = translate_rur, + .par = (const uint32_t[]){FCR}, + .coprocessor = 0x1, + }, { + .name = "rur.fsr", + .translate = translate_rur, + .par = (const uint32_t[]){FSR}, + .coprocessor = 0x1, }, { .name = "ssi", .translate = translate_ldsti, @@ -6699,6 +6689,16 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "wfr", .translate = translate_wfr_s, .coprocessor = 0x1, + }, { + .name = "wur.fcr", + .translate = translate_wur_fpu2k_fcr, + .par = (const uint32_t[]){FCR}, + .coprocessor = 0x1, + }, { + .name = "wur.fsr", + .translate = translate_wur_fpu2k_fsr, + .par = (const uint32_t[]){FSR}, + .coprocessor = 0x1, }, }; From patchwork Mon Jul 6 23:47:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647181 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B5A4760D for ; Mon, 6 Jul 2020 23:53:48 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8C264206F6 for ; Mon, 6 Jul 2020 23:53:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rP3PH5pn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8C264206F6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:60568 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsavj-0004av-SM for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:53:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35362) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaq9-00010e-SO for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:01 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:36204) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaq8-0000tw-4Q for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:01 -0400 Received: by mail-pg1-x542.google.com with SMTP id p3so19120209pgh.3 for ; Mon, 06 Jul 2020 16:47:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w4M2hm6SX88vAmypNF1BsgknJj1VWHgn1OPZgKWy19o=; b=rP3PH5pn3cHoWiTiVWYVO+/ONDyUnV5NjDkJ0vWu5zjzfsvMdOJ8NvQZwxQg1XzZb4 1iTcy/pPEIHKrfeswMOU5zNZOdL/lH+TIu1QiEZjRQ+pWxaH+CSVwlEEp5lGbzZWNMdP faP08pJIB8O3FHQNdRRTF/h+Y0eqoLRJ1m0SKw/pzueMjyTNfOVc+dc6ykbJPtt8sQEh WJ6qlO4Bt+0ix8dOLuTE+s0hCGwnwB8a3pPZH1uIyqRRZRkcAq7hu69aelrx5DMgTEcd mLtfjLfId0zVi2gVvPxifXuXDQdCl95a0BkW0MFIlVT+l/p0xk0RbrqvnWcI9BjohjZT 9Bdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w4M2hm6SX88vAmypNF1BsgknJj1VWHgn1OPZgKWy19o=; b=ZUcTHSt3o1ptSVp4YCa5mu0Rml3rxgQ3rUDj+xF0Dx+sXREUP8oO0+5d3r4iw6ok9r b1kgYjW9KpQJR/w7DvW4yaOlVTZ9a5mBeSQ2osCXcasTfhQvo+1X5PhelkjjSp7ky5cC nM0AkG6gWg9f4dh0ammzZJ4FiFWn0WAGytBAVr4cpTxYbe3poFjRpAuw6VDoVN/yvZiX gHftMWJytVDIwbeVKi0Ly8V3ckvht4vVLIPzZ9MSyZPyV79iZj4KeRk6M6fRcggnv3lV iGov5wqaVu1sRcCiddbJdsJ1vYqW4bv2XCye2qXZ4xWx8AfvXMsC86YZLzxcVYbs+qDm sg4w== X-Gm-Message-State: AOAM530qwzwhAuxq/GBB39dH/HOvF/Nlm9TTuJD1hdSweqNUOnIFNajb /QzkXSiGgdrhOYME0sgiyqbHul0y X-Google-Smtp-Source: ABdhPJyF6GSH7/awMhty4aPXkrw9O9RlPN9Dl3tYQM4KCv1/JUkzQ46fVcLdG8Fy135BmHoPOq9F+g== X-Received: by 2002:a63:20d:: with SMTP id 13mr42640123pgc.166.1594079278773; Mon, 06 Jul 2020 16:47:58 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.47.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:47:58 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 08/21] target/xtensa: don't access BR regfile directly Date: Mon, 6 Jul 2020 16:47:24 -0700 Message-Id: <20200706234737.32378-9-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=jcmvbkbc@gmail.com; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" BR registers used in FPU comparison opcodes are available as opcode arguments for translators. Use them. This simplifies comparison helpers interface and makes them usable in FLIX bundles. Signed-off-by: Max Filippov Reviewed-by: Richard Henderson --- target/xtensa/fpu_helper.c | 42 +++++++++++++++++--------------------- target/xtensa/helper.h | 14 ++++++------- target/xtensa/translate.c | 20 ++++++++++++++---- 3 files changed, 42 insertions(+), 34 deletions(-) diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index 57a284924045..fae6836d3223 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -118,49 +118,45 @@ float32 HELPER(uitof_s)(CPUXtensaState *env, uint32_t v, uint32_t scale) (int32_t)scale, &env->fp_status); } -static inline void set_br(CPUXtensaState *env, bool v, uint32_t br) +uint32_t HELPER(un_s)(CPUXtensaState *env, float32 a, float32 b) { - if (v) { - env->sregs[BR] |= br; - } else { - env->sregs[BR] &= ~br; - } -} - -void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) -{ - set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br); + return float32_unordered_quiet(a, b, &env->fp_status); } -void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +uint32_t HELPER(oeq_s)(CPUXtensaState *env, float32 a, float32 b) { - set_br(env, float32_eq_quiet(a, b, &env->fp_status), br); + return float32_eq_quiet(a, b, &env->fp_status); } -void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +uint32_t HELPER(ueq_s)(CPUXtensaState *env, float32 a, float32 b) { FloatRelation v = float32_compare_quiet(a, b, &env->fp_status); - set_br(env, v == float_relation_equal || v == float_relation_unordered, br); + + return v == float_relation_equal || + v == float_relation_unordered; } -void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +uint32_t HELPER(olt_s)(CPUXtensaState *env, float32 a, float32 b) { - set_br(env, float32_lt_quiet(a, b, &env->fp_status), br); + return float32_lt_quiet(a, b, &env->fp_status); } -void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +uint32_t HELPER(ult_s)(CPUXtensaState *env, float32 a, float32 b) { FloatRelation v = float32_compare_quiet(a, b, &env->fp_status); - set_br(env, v == float_relation_less || v == float_relation_unordered, br); + + return v == float_relation_less || + v == float_relation_unordered; } -void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +uint32_t HELPER(ole_s)(CPUXtensaState *env, float32 a, float32 b) { - set_br(env, float32_le_quiet(a, b, &env->fp_status), br); + return float32_le_quiet(a, b, &env->fp_status); } -void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +uint32_t HELPER(ule_s)(CPUXtensaState *env, float32 a, float32 b) { FloatRelation v = float32_compare_quiet(a, b, &env->fp_status); - set_br(env, v != float_relation_greater, br); + + return v != float_relation_greater; } diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index a692254fe10a..bbada1c0b864 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -59,13 +59,13 @@ DEF_HELPER_FLAGS_3(ftoui_s, TCG_CALL_NO_RWG_SE, i32, f32, i32, i32) DEF_HELPER_3(itof_s, f32, env, i32, i32) DEF_HELPER_3(uitof_s, f32, env, i32, i32) -DEF_HELPER_4(un_s, void, env, i32, f32, f32) -DEF_HELPER_4(oeq_s, void, env, i32, f32, f32) -DEF_HELPER_4(ueq_s, void, env, i32, f32, f32) -DEF_HELPER_4(olt_s, void, env, i32, f32, f32) -DEF_HELPER_4(ult_s, void, env, i32, f32, f32) -DEF_HELPER_4(ole_s, void, env, i32, f32, f32) -DEF_HELPER_4(ule_s, void, env, i32, f32, f32) +DEF_HELPER_3(un_s, i32, env, f32, f32) +DEF_HELPER_3(oeq_s, i32, env, f32, f32) +DEF_HELPER_3(ueq_s, i32, env, f32, f32) +DEF_HELPER_3(olt_s, i32, env, f32, f32) +DEF_HELPER_3(ult_s, i32, env, f32, f32) +DEF_HELPER_3(ole_s, i32, env, f32, f32) +DEF_HELPER_3(ule_s, i32, env, f32, f32) DEF_HELPER_2(rer, i32, env, i32) DEF_HELPER_3(wer, void, env, i32, i32) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index f859cd3f0818..85bd63dffc9f 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -6319,7 +6319,7 @@ enum { static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - static void (* const helper[])(TCGv_env env, TCGv_i32 bit, + static void (* const helper[])(TCGv_i32 res, TCGv_env env, TCGv_i32 s, TCGv_i32 t) = { [COMPARE_UN] = gen_helper_un_s, [COMPARE_OEQ] = gen_helper_oeq_s, @@ -6329,10 +6329,22 @@ static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[], [COMPARE_OLE] = gen_helper_ole_s, [COMPARE_ULE] = gen_helper_ule_s, }; - TCGv_i32 bit = tcg_const_i32(1 << arg[0].imm); + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 res = tcg_temp_new_i32(); + TCGv_i32 set_br = tcg_temp_new_i32(); + TCGv_i32 clr_br = tcg_temp_new_i32(); - helper[par[0]](cpu_env, bit, arg[1].in, arg[2].in); - tcg_temp_free(bit); + tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm); + tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm)); + + helper[par[0]](res, cpu_env, arg[1].in, arg[2].in); + tcg_gen_movcond_i32(TCG_COND_NE, + arg[0].out, res, zero, + set_br, clr_br); + tcg_temp_free(zero); + tcg_temp_free(res); + tcg_temp_free(set_br); + tcg_temp_free(clr_br); } static void translate_float_s(DisasContext *dc, const OpcodeArg arg[], From patchwork Mon Jul 6 23:47:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647169 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7EC9D60D for ; Mon, 6 Jul 2020 23:50:30 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3304F206E9 for ; Mon, 6 Jul 2020 23:50:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MNzCVVwC" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3304F206E9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:45746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsasX-0006be-DG for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:50:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaqD-0001BY-Lx for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:05 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:51034) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaqA-0000vi-33 for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:05 -0400 Received: by mail-pj1-x1043.google.com with SMTP id k71so13962917pje.0 for ; Mon, 06 Jul 2020 16:48:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jygA66HJUudgdktoH8LBPEhgWsxA1ZK1b+i4DCvQfZw=; b=MNzCVVwCGubxgsKfx5qZZc10DdZl+y11mkc27A1hu1XMmtDYhxqJMRTPjW3WOUbgVc 4d3jlnyNKhnoWb5GBuX5opc9F0ZhgaoyGJbcKAJZ21yziPYYowwRUNOGG6tqKO66DC9v L0PXCiOi7RY86fd2AcELH3N01dkCPYj5YUAZjb1hoM5bcRpIP6CcYcBz+budvB+bommG NgjrZ5YXpdfqM8P6jJwUxf9iSMXTQN/346aF/HRkjbF9BSiJ5zOpnMhFOPOt/WrQJNYM 7CXxMlehIOyc471RFoZy20Vrg4nar2KY5MSF0nuguhaY+Wc1LM0ojqufZ8MbMAY7cVkk /ixg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jygA66HJUudgdktoH8LBPEhgWsxA1ZK1b+i4DCvQfZw=; b=pB9b5HtLR0t/FXSvbmSkYb5CA1+WyImTYdo1hje8szgBPIyKpxDO50dDz4+JL+P6r6 1BTfhMQdIBXTNYYZZulXiyN/jsx2RmmiC1r7ZzDlJvBEp3Q8U21+Vh3IbCuzE4ZJaK/I BoTLtC/inXqw7hgm1nabmZdpH1uoVsgj7/nFCNtQyumEX77AyOt2jNQlovdtIW8TbN5X NNzutexUiuaFwxoYUQgMsY1X7q+3UGHpsi7txMVelNVUPeZykMJyKzsqQDY1MGpqjCzE d+aSSpE0ORJzR82DS6uW/imUsfaveStLyD0APUmh1HgQ9osdW8Fu6d8HFMlR/OV9SD6i jImQ== X-Gm-Message-State: AOAM530Ek//lLWQyoVcbWgD8jfy19J26MOQmcl5cl+UQN2Zo3IY+Xrv2 y0B+1VlhV2pj4RNFr8jF7ZgsC0jV X-Google-Smtp-Source: ABdhPJwmHyAUYAkeFqv+t+s+W5RTVxVPP1w4p/6XaaoV8XDfOvwOjUY7omoRkzYPvsJJkxzj36YHLw== X-Received: by 2002:a17:902:8f96:: with SMTP id z22mr6585067plo.189.1594079279715; Mon, 06 Jul 2020 16:47:59 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.47.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:47:59 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 09/21] target/xtensa: add DFP option, registers and opcodes Date: Mon, 6 Jul 2020 16:47:25 -0700 Message-Id: <20200706234737.32378-10-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=jcmvbkbc@gmail.com; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" DFPU may be configured with 32-bit or with 64-bit registers. Xtensa ISA does not specify how single-precision values are stored in 64-bit registers. Existing implementations store them in the low half of the registers. Add value extraction and write back to single-precision opcodes. Add new double precision opcodes. Add 64-bit register file. Add 64-bit values dumping to the xtensa_cpu_dump_state. Signed-off-by: Max Filippov --- target/xtensa/cpu.c | 4 + target/xtensa/cpu.h | 4 + target/xtensa/fpu_helper.c | 252 +++++++- target/xtensa/helper.h | 29 +- target/xtensa/overlay_tool.h | 6 + target/xtensa/translate.c | 1088 ++++++++++++++++++++++++++++++++-- 6 files changed, 1338 insertions(+), 45 deletions(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 82c2ee0679f8..5abf3b6f994b 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -31,6 +31,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" +#include "fpu/softfloat.h" #include "qemu/module.h" #include "migration/vmstate.h" @@ -104,6 +105,9 @@ static void xtensa_cpu_reset(DeviceState *dev) reset_mmu(env); s->halted = env->runstall; #endif + if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DFP_COPROCESSOR)) { + set_no_signaling_nans(true, &env->fp_status); + } } static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 960f6573447f..76f596922ae6 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -52,6 +52,7 @@ enum { XTENSA_OPTION_COPROCESSOR, XTENSA_OPTION_BOOLEAN, XTENSA_OPTION_FP_COPROCESSOR, + XTENSA_OPTION_DFP_COPROCESSOR, XTENSA_OPTION_MP_SYNCHRO, XTENSA_OPTION_CONDITIONAL_STORE, XTENSA_OPTION_ATOMCTL, @@ -420,6 +421,7 @@ typedef struct XtensaOpcodeTranslators { extern const XtensaOpcodeTranslators xtensa_core_opcodes; extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes; +extern const XtensaOpcodeTranslators xtensa_fpu_opcodes; struct XtensaConfig { const char *name; @@ -482,6 +484,8 @@ struct XtensaConfig { unsigned n_mpu_fg_segments; unsigned n_mpu_bg_segments; const xtensa_mpu_entry *mpu_bg; + + bool use_first_nan; }; typedef struct XtensaConfigList { diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index fae6836d3223..514b888b3d9a 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -33,6 +33,30 @@ #include "exec/exec-all.h" #include "fpu/softfloat.h" +enum { + XTENSA_FP_I = 0x1, + XTENSA_FP_U = 0x2, + XTENSA_FP_O = 0x4, + XTENSA_FP_Z = 0x8, + XTENSA_FP_V = 0x10, +}; + +enum { + XTENSA_FCR_FLAGS_SHIFT = 2, + XTENSA_FSR_FLAGS_SHIFT = 7, +}; + +static const struct { + uint32_t xtensa_fp_flag; + int softfloat_fp_flag; +} xtensa_fp_flag_map[] = { + { XTENSA_FP_I, float_flag_inexact, }, + { XTENSA_FP_U, float_flag_underflow, }, + { XTENSA_FP_O, float_flag_overflow, }, + { XTENSA_FP_Z, float_flag_divbyzero, }, + { XTENSA_FP_V, float_flag_invalid, }, +}; + void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) { static const int rounding_mode[] = { @@ -46,64 +70,215 @@ void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); } +void HELPER(wur_fpu_fcr)(CPUXtensaState *env, uint32_t v) +{ + static const int rounding_mode[] = { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down, + }; + + if (v & 0xfffff000) { + qemu_log_mask(LOG_GUEST_ERROR, + "MBZ field of FCR is written non-zero: %08x\n", v); + } + env->uregs[FCR] = v & 0x0000007f; + set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); +} + +void HELPER(wur_fpu_fsr)(CPUXtensaState *env, uint32_t v) +{ + uint32_t flags = v >> XTENSA_FSR_FLAGS_SHIFT; + int fef = 0; + unsigned i; + + if (v & 0xfffff000) { + qemu_log_mask(LOG_GUEST_ERROR, + "MBZ field of FSR is written non-zero: %08x\n", v); + } + env->uregs[FSR] = v & 0x00000f80; + for (i = 0; i < ARRAY_SIZE(xtensa_fp_flag_map); ++i) { + if (flags & xtensa_fp_flag_map[i].xtensa_fp_flag) { + fef |= xtensa_fp_flag_map[i].softfloat_fp_flag; + } + } + set_float_exception_flags(fef, &env->fp_status); +} + +uint32_t HELPER(rur_fpu_fsr)(CPUXtensaState *env) +{ + uint32_t flags = 0; + int fef = get_float_exception_flags(&env->fp_status); + unsigned i; + + for (i = 0; i < ARRAY_SIZE(xtensa_fp_flag_map); ++i) { + if (fef & xtensa_fp_flag_map[i].softfloat_fp_flag) { + flags |= xtensa_fp_flag_map[i].xtensa_fp_flag; + } + } + env->uregs[FSR] = flags << XTENSA_FSR_FLAGS_SHIFT; + return flags << XTENSA_FSR_FLAGS_SHIFT; +} + +float64 HELPER(abs_d)(float64 v) +{ + return float64_abs(v); +} + float32 HELPER(abs_s)(float32 v) { return float32_abs(v); } +float64 HELPER(neg_d)(float64 v) +{ + return float64_chs(v); +} + float32 HELPER(neg_s)(float32 v) { return float32_chs(v); } +float64 HELPER(add_d)(CPUXtensaState *env, float64 a, float64 b) +{ + set_use_first_nan(true, &env->fp_status); + return float64_add(a, b, &env->fp_status); +} + float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b) { + set_use_first_nan(env->config->use_first_nan, &env->fp_status); return float32_add(a, b, &env->fp_status); } +float64 HELPER(sub_d)(CPUXtensaState *env, float64 a, float64 b) +{ + set_use_first_nan(true, &env->fp_status); + return float64_sub(a, b, &env->fp_status); +} + float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b) { + set_use_first_nan(env->config->use_first_nan, &env->fp_status); return float32_sub(a, b, &env->fp_status); } +float64 HELPER(mul_d)(CPUXtensaState *env, float64 a, float64 b) +{ + set_use_first_nan(true, &env->fp_status); + return float64_mul(a, b, &env->fp_status); +} + float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b) { + set_use_first_nan(env->config->use_first_nan, &env->fp_status); return float32_mul(a, b, &env->fp_status); } +float64 HELPER(madd_d)(CPUXtensaState *env, float64 a, float64 b, float64 c) +{ + set_use_first_nan(env->config->use_first_nan, &env->fp_status); + return float64_muladd(b, c, a, 0, &env->fp_status); +} + float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) { + set_use_first_nan(env->config->use_first_nan, &env->fp_status); return float32_muladd(b, c, a, 0, &env->fp_status); } +float64 HELPER(msub_d)(CPUXtensaState *env, float64 a, float64 b, float64 c) +{ + set_use_first_nan(env->config->use_first_nan, &env->fp_status); + return float64_muladd(b, c, a, float_muladd_negate_product, + &env->fp_status); +} + float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) { + set_use_first_nan(env->config->use_first_nan, &env->fp_status); return float32_muladd(b, c, a, float_muladd_negate_product, &env->fp_status); } -uint32_t HELPER(ftoi_s)(float32 v, uint32_t rounding_mode, uint32_t scale) +uint32_t HELPER(ftoi_d)(CPUXtensaState *env, float64 v, + uint32_t rounding_mode, uint32_t scale) +{ + float_status fp_status = env->fp_status; + uint32_t res; + + set_float_rounding_mode(rounding_mode, &fp_status); + res = float64_to_int32(float64_scalbn(v, scale, &fp_status), &fp_status); + set_float_exception_flags(get_float_exception_flags(&fp_status), + &env->fp_status); + return res; +} + +uint32_t HELPER(ftoi_s)(CPUXtensaState *env, float32 v, + uint32_t rounding_mode, uint32_t scale) { - float_status fp_status = {0}; + float_status fp_status = env->fp_status; + uint32_t res; set_float_rounding_mode(rounding_mode, &fp_status); - return float32_to_int32(float32_scalbn(v, scale, &fp_status), &fp_status); + res = float32_to_int32(float32_scalbn(v, scale, &fp_status), &fp_status); + set_float_exception_flags(get_float_exception_flags(&fp_status), + &env->fp_status); + return res; } -uint32_t HELPER(ftoui_s)(float32 v, uint32_t rounding_mode, uint32_t scale) +uint32_t HELPER(ftoui_d)(CPUXtensaState *env, float64 v, + uint32_t rounding_mode, uint32_t scale) { - float_status fp_status = {0}; + float_status fp_status = env->fp_status; + float64 res; + uint32_t rv; + + set_float_rounding_mode(rounding_mode, &fp_status); + + res = float64_scalbn(v, scale, &fp_status); + + if (float64_is_neg(v) && !float64_is_any_nan(v)) { + set_float_exception_flags(float_flag_invalid, &fp_status); + rv = float64_to_int32(res, &fp_status); + } else { + rv = float64_to_uint32(res, &fp_status); + } + set_float_exception_flags(get_float_exception_flags(&fp_status), + &env->fp_status); + return rv; +} + +uint32_t HELPER(ftoui_s)(CPUXtensaState *env, float32 v, + uint32_t rounding_mode, uint32_t scale) +{ + float_status fp_status = env->fp_status; float32 res; + uint32_t rv; set_float_rounding_mode(rounding_mode, &fp_status); res = float32_scalbn(v, scale, &fp_status); if (float32_is_neg(v) && !float32_is_any_nan(v)) { - return float32_to_int32(res, &fp_status); + rv = float32_to_int32(res, &fp_status); + if (rv) { + set_float_exception_flags(float_flag_invalid, &fp_status); + } } else { - return float32_to_uint32(res, &fp_status); + rv = float32_to_uint32(res, &fp_status); } + set_float_exception_flags(get_float_exception_flags(&fp_status), + &env->fp_status); + return rv; +} + +float64 HELPER(itof_d)(CPUXtensaState *env, uint32_t v, uint32_t scale) +{ + return float64_scalbn(int32_to_float64(v, &env->fp_status), + (int32_t)scale, &env->fp_status); } float32 HELPER(itof_s)(CPUXtensaState *env, uint32_t v, uint32_t scale) @@ -112,22 +287,56 @@ float32 HELPER(itof_s)(CPUXtensaState *env, uint32_t v, uint32_t scale) (int32_t)scale, &env->fp_status); } +float64 HELPER(uitof_d)(CPUXtensaState *env, uint32_t v, uint32_t scale) +{ + return float64_scalbn(uint32_to_float64(v, &env->fp_status), + (int32_t)scale, &env->fp_status); +} + float32 HELPER(uitof_s)(CPUXtensaState *env, uint32_t v, uint32_t scale) { return float32_scalbn(uint32_to_float32(v, &env->fp_status), (int32_t)scale, &env->fp_status); } +float64 HELPER(cvtd_s)(CPUXtensaState *env, float32 v) +{ + return float32_to_float64(v, &env->fp_status); +} + +float32 HELPER(cvts_d)(CPUXtensaState *env, float64 v) +{ + return float64_to_float32(v, &env->fp_status); +} + +uint32_t HELPER(un_d)(CPUXtensaState *env, float64 a, float64 b) +{ + return float64_unordered_quiet(a, b, &env->fp_status); +} + uint32_t HELPER(un_s)(CPUXtensaState *env, float32 a, float32 b) { return float32_unordered_quiet(a, b, &env->fp_status); } +uint32_t HELPER(oeq_d)(CPUXtensaState *env, float64 a, float64 b) +{ + return float64_eq_quiet(a, b, &env->fp_status); +} + uint32_t HELPER(oeq_s)(CPUXtensaState *env, float32 a, float32 b) { return float32_eq_quiet(a, b, &env->fp_status); } +uint32_t HELPER(ueq_d)(CPUXtensaState *env, float64 a, float64 b) +{ + FloatRelation v = float64_compare_quiet(a, b, &env->fp_status); + + return v == float_relation_equal || + v == float_relation_unordered; +} + uint32_t HELPER(ueq_s)(CPUXtensaState *env, float32 a, float32 b) { FloatRelation v = float32_compare_quiet(a, b, &env->fp_status); @@ -136,9 +345,22 @@ uint32_t HELPER(ueq_s)(CPUXtensaState *env, float32 a, float32 b) v == float_relation_unordered; } +uint32_t HELPER(olt_d)(CPUXtensaState *env, float64 a, float64 b) +{ + return float64_lt(a, b, &env->fp_status); +} + uint32_t HELPER(olt_s)(CPUXtensaState *env, float32 a, float32 b) { - return float32_lt_quiet(a, b, &env->fp_status); + return float32_lt(a, b, &env->fp_status); +} + +uint32_t HELPER(ult_d)(CPUXtensaState *env, float64 a, float64 b) +{ + FloatRelation v = float64_compare_quiet(a, b, &env->fp_status); + + return v == float_relation_less || + v == float_relation_unordered; } uint32_t HELPER(ult_s)(CPUXtensaState *env, float32 a, float32 b) @@ -149,9 +371,21 @@ uint32_t HELPER(ult_s)(CPUXtensaState *env, float32 a, float32 b) v == float_relation_unordered; } +uint32_t HELPER(ole_d)(CPUXtensaState *env, float64 a, float64 b) +{ + return float64_le(a, b, &env->fp_status); +} + uint32_t HELPER(ole_s)(CPUXtensaState *env, float32 a, float32 b) { - return float32_le_quiet(a, b, &env->fp_status); + return float32_le(a, b, &env->fp_status); +} + +uint32_t HELPER(ule_d)(CPUXtensaState *env, float64 a, float64 b) +{ + FloatRelation v = float64_compare_quiet(a, b, &env->fp_status); + + return v != float_relation_greater; } uint32_t HELPER(ule_s)(CPUXtensaState *env, float32 a, float32 b) diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index bbada1c0b864..a328af47cd31 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -54,10 +54,11 @@ DEF_HELPER_3(sub_s, f32, env, f32, f32) DEF_HELPER_3(mul_s, f32, env, f32, f32) DEF_HELPER_4(madd_s, f32, env, f32, f32, f32) DEF_HELPER_4(msub_s, f32, env, f32, f32, f32) -DEF_HELPER_FLAGS_3(ftoi_s, TCG_CALL_NO_RWG_SE, i32, f32, i32, i32) -DEF_HELPER_FLAGS_3(ftoui_s, TCG_CALL_NO_RWG_SE, i32, f32, i32, i32) +DEF_HELPER_4(ftoi_s, i32, env, f32, i32, i32) +DEF_HELPER_4(ftoui_s, i32, env, f32, i32, i32) DEF_HELPER_3(itof_s, f32, env, i32, i32) DEF_HELPER_3(uitof_s, f32, env, i32, i32) +DEF_HELPER_2(cvtd_s, f64, env, f32) DEF_HELPER_3(un_s, i32, env, f32, f32) DEF_HELPER_3(oeq_s, i32, env, f32, f32) @@ -67,5 +68,29 @@ DEF_HELPER_3(ult_s, i32, env, f32, f32) DEF_HELPER_3(ole_s, i32, env, f32, f32) DEF_HELPER_3(ule_s, i32, env, f32, f32) +DEF_HELPER_2(wur_fpu_fcr, void, env, i32) +DEF_HELPER_1(rur_fpu_fsr, i32, env) +DEF_HELPER_2(wur_fpu_fsr, void, env, i32) +DEF_HELPER_FLAGS_1(abs_d, TCG_CALL_NO_RWG_SE, f64, f64) +DEF_HELPER_FLAGS_1(neg_d, TCG_CALL_NO_RWG_SE, f64, f64) +DEF_HELPER_3(add_d, f64, env, f64, f64) +DEF_HELPER_3(sub_d, f64, env, f64, f64) +DEF_HELPER_3(mul_d, f64, env, f64, f64) +DEF_HELPER_4(madd_d, f64, env, f64, f64, f64) +DEF_HELPER_4(msub_d, f64, env, f64, f64, f64) +DEF_HELPER_4(ftoi_d, i32, env, f64, i32, i32) +DEF_HELPER_4(ftoui_d, i32, env, f64, i32, i32) +DEF_HELPER_3(itof_d, f64, env, i32, i32) +DEF_HELPER_3(uitof_d, f64, env, i32, i32) +DEF_HELPER_2(cvts_d, f32, env, f64) + +DEF_HELPER_3(un_d, i32, env, f64, f64) +DEF_HELPER_3(oeq_d, i32, env, f64, f64) +DEF_HELPER_3(ueq_d, i32, env, f64, f64) +DEF_HELPER_3(olt_d, i32, env, f64, f64) +DEF_HELPER_3(ult_d, i32, env, f64, f64) +DEF_HELPER_3(ole_d, i32, env, f64, f64) +DEF_HELPER_3(ule_d, i32, env, f64, f64) + DEF_HELPER_2(rer, i32, env, i32) DEF_HELPER_3(wer, void, env, i32, i32) diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index eb9f08af0bf6..a41f336d0843 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -39,6 +39,10 @@ #define XCHAL_HAVE_DEPBITS 0 #endif +#ifndef XCHAL_HAVE_DFP +#define XCHAL_HAVE_DFP 0 +#endif + #ifndef XCHAL_HAVE_DIV32 #define XCHAL_HAVE_DIV32 0 #endif @@ -99,6 +103,7 @@ XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \ XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \ XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \ + XCHAL_OPTION(XCHAL_HAVE_DFP, XTENSA_OPTION_DFP_COPROCESSOR) | \ XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \ XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \ XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \ @@ -515,6 +520,7 @@ .ndepc = (XCHAL_XEA_VERSION >= 2), \ .inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \ .max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \ + .use_first_nan = !XCHAL_HAVE_DFP, \ EXCEPTIONS_SECTION, \ INTERRUPTS_SECTION, \ TLB_SECTION, \ diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 85bd63dffc9f..ab83e259917a 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -79,6 +79,7 @@ struct DisasContext { static TCGv_i32 cpu_pc; static TCGv_i32 cpu_R[16]; static TCGv_i32 cpu_FR[16]; +static TCGv_i64 cpu_FRD[16]; static TCGv_i32 cpu_MR[4]; static TCGv_i32 cpu_BR[16]; static TCGv_i32 cpu_BR4[4]; @@ -169,6 +170,13 @@ void xtensa_translate_init(void) fregnames[i]); } + for (i = 0; i < 16; i++) { + cpu_FRD[i] = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUXtensaState, + fregs[i].f64), + fregnames[i]); + } + for (i = 0; i < 4; i++) { cpu_MR[i] = tcg_global_mem_new_i32(cpu_env, offsetof(CPUXtensaState, @@ -251,6 +259,8 @@ void **xtensa_get_regfile_by_name(const char *name, int entries, int bits) g_hash_table_insert(xtensa_regfile_table, (void *)"FR 16x32", (void *)cpu_FR); + g_hash_table_insert(xtensa_regfile_table, + (void *)"FR 16x64", (void *)cpu_FRD); g_hash_table_insert(xtensa_regfile_table, (void *)"BR 16x1", (void *)cpu_BR); @@ -1398,12 +1408,24 @@ void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "\n"); for (i = 0; i < 16; ++i) { - qemu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i, + qemu_fprintf(f, "F%02d=%08x (%-+15.8e)%c", i, float32_val(env->fregs[i].f32[FP_F32_LOW]), *(float *)(env->fregs[i].f32 + FP_F32_LOW), (i % 2) == 1 ? '\n' : ' '); } } + + if ((flags & CPU_DUMP_FPU) && + xtensa_option_enabled(env->config, XTENSA_OPTION_DFP_COPROCESSOR)) { + qemu_fprintf(f, "\n"); + + for (i = 0; i < 16; ++i) { + qemu_fprintf(f, "F%02d=%016"PRIx64" (%-+24.16le)%c", i, + float64_val(env->fregs[i].f64), + *(double *)(&env->fregs[i].f64), + (i % 2) == 1 ? '\n' : ' '); + } + } } void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, @@ -6293,17 +6315,154 @@ const XtensaOpcodeTranslators xtensa_core_opcodes = { }; +static inline void get_f32_o1_i3(const OpcodeArg *arg, OpcodeArg *arg32, + int o0, int i0, int i1, int i2) +{ + if ((i0 >= 0 && arg[i0].num_bits == 64) || + (o0 >= 0 && arg[o0].num_bits == 64)) { + if (o0 >= 0) { + arg32[o0].out = tcg_temp_new_i32(); + } + if (i0 >= 0) { + arg32[i0].in = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(arg32[i0].in, arg[i0].in); + } + if (i1 >= 0) { + arg32[i1].in = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(arg32[i1].in, arg[i1].in); + } + if (i2 >= 0) { + arg32[i2].in = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(arg32[i2].in, arg[i2].in); + } + } else { + if (o0 >= 0) { + arg32[o0].out = arg[o0].out; + } + if (i0 >= 0) { + arg32[i0].in = arg[i0].in; + } + if (i1 >= 0) { + arg32[i1].in = arg[i1].in; + } + if (i2 >= 0) { + arg32[i2].in = arg[i2].in; + } + } +} + +static inline void put_f32_o1_i3(const OpcodeArg *arg, const OpcodeArg *arg32, + int o0, int i0, int i1, int i2) +{ + if ((i0 >= 0 && arg[i0].num_bits == 64) || + (o0 >= 0 && arg[o0].num_bits == 64)) { + if (o0 >= 0) { + tcg_gen_extu_i32_i64(arg[o0].out, arg32[o0].out); + tcg_temp_free_i32(arg32[o0].out); + } + if (i0 >= 0) { + tcg_temp_free_i32(arg32[i0].in); + } + if (i1 >= 0) { + tcg_temp_free_i32(arg32[i1].in); + } + if (i2 >= 0) { + tcg_temp_free_i32(arg32[i2].in); + } + } +} + +static inline void get_f32_o1_i2(const OpcodeArg *arg, OpcodeArg *arg32, + int o0, int i0, int i1) +{ + get_f32_o1_i3(arg, arg32, o0, i0, i1, -1); +} + +static inline void put_f32_o1_i2(const OpcodeArg *arg, const OpcodeArg *arg32, + int o0, int i0, int i1) +{ + put_f32_o1_i3(arg, arg32, o0, i0, i1, -1); +} + +static inline void get_f32_o1_i1(const OpcodeArg *arg, OpcodeArg *arg32, + int o0, int i0) +{ + get_f32_o1_i2(arg, arg32, o0, i0, -1); +} + +static inline void put_f32_o1_i1(const OpcodeArg *arg, const OpcodeArg *arg32, + int o0, int i0) +{ + put_f32_o1_i2(arg, arg32, o0, i0, -1); +} + +static inline void get_f32_o1(const OpcodeArg *arg, OpcodeArg *arg32, + int o0) +{ + get_f32_o1_i1(arg, arg32, o0, -1); +} + +static inline void put_f32_o1(const OpcodeArg *arg, const OpcodeArg *arg32, + int o0) +{ + put_f32_o1_i1(arg, arg32, o0, -1); +} + +static inline void get_f32_i2(const OpcodeArg *arg, OpcodeArg *arg32, + int i0, int i1) +{ + get_f32_o1_i2(arg, arg32, -1, i0, i1); +} + +static inline void put_f32_i2(const OpcodeArg *arg, const OpcodeArg *arg32, + int i0, int i1) +{ + put_f32_o1_i2(arg, arg32, -1, i0, i1); +} + +static inline void get_f32_i1(const OpcodeArg *arg, OpcodeArg *arg32, + int i0) +{ + get_f32_i2(arg, arg32, i0, -1); +} + +static inline void put_f32_i1(const OpcodeArg *arg, const OpcodeArg *arg32, + int i0) +{ + put_f32_i2(arg, arg32, i0, -1); +} + + +static void translate_abs_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_abs_d(arg[0].out, arg[1].in); +} + static void translate_abs_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_abs_s(arg[0].out, arg[1].in); + OpcodeArg arg32[2]; + + get_f32_o1_i1(arg, arg32, 0, 1); + gen_helper_abs_s(arg32[0].out, arg32[1].in); + put_f32_o1_i1(arg, arg32, 0, 1); } -static void translate_add_s(DisasContext *dc, const OpcodeArg arg[], +static void translate_add_d(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_add_s(arg[0].out, cpu_env, - arg[1].in, arg[2].in); + gen_helper_add_d(arg[0].out, cpu_env, arg[1].in, arg[2].in); +} + +static void translate_add_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + OpcodeArg arg32[3]; + + get_f32_o1_i2(arg, arg32, 0, 1, 2); + gen_helper_add_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in); + put_f32_o1_i2(arg, arg32, 0, 1, 2); } enum { @@ -6316,6 +6475,37 @@ enum { COMPARE_ULE, }; +static void translate_compare_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + static void (* const helper[])(TCGv_i32 res, TCGv_env env, + TCGv_i64 s, TCGv_i64 t) = { + [COMPARE_UN] = gen_helper_un_d, + [COMPARE_OEQ] = gen_helper_oeq_d, + [COMPARE_UEQ] = gen_helper_ueq_d, + [COMPARE_OLT] = gen_helper_olt_d, + [COMPARE_ULT] = gen_helper_ult_d, + [COMPARE_OLE] = gen_helper_ole_d, + [COMPARE_ULE] = gen_helper_ule_d, + }; + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 res = tcg_temp_new_i32(); + TCGv_i32 set_br = tcg_temp_new_i32(); + TCGv_i32 clr_br = tcg_temp_new_i32(); + + tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm); + tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm)); + + helper[par[0]](res, cpu_env, arg[1].in, arg[2].in); + tcg_gen_movcond_i32(TCG_COND_NE, + arg[0].out, res, zero, + set_br, clr_br); + tcg_temp_free(zero); + tcg_temp_free(res); + tcg_temp_free(set_br); + tcg_temp_free(clr_br); +} + static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -6329,6 +6519,7 @@ static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[], [COMPARE_OLE] = gen_helper_ole_s, [COMPARE_ULE] = gen_helper_ule_s, }; + OpcodeArg arg32[3]; TCGv_i32 zero = tcg_const_i32(0); TCGv_i32 res = tcg_temp_new_i32(); TCGv_i32 set_br = tcg_temp_new_i32(); @@ -6337,26 +6528,101 @@ static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[], tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm); tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm)); - helper[par[0]](res, cpu_env, arg[1].in, arg[2].in); + get_f32_i2(arg, arg32, 1, 2); + helper[par[0]](res, cpu_env, arg32[1].in, arg32[2].in); tcg_gen_movcond_i32(TCG_COND_NE, arg[0].out, res, zero, set_br, clr_br); + put_f32_i2(arg, arg32, 1, 2); tcg_temp_free(zero); tcg_temp_free(res); tcg_temp_free(set_br); tcg_temp_free(clr_br); } +static void translate_const_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + static const uint64_t v[] = { + UINT64_C(0x0000000000000000), + UINT64_C(0x3ff0000000000000), + UINT64_C(0x4000000000000000), + UINT64_C(0x3fe0000000000000), + }; + + tcg_gen_movi_i64(arg[0].out, v[arg[1].imm % ARRAY_SIZE(v)]); + if (arg[1].imm >= ARRAY_SIZE(v)) { + qemu_log_mask(LOG_GUEST_ERROR, + "const.d f%d, #%d, immediate value is reserved\n", + arg[0].imm, arg[1].imm); + } +} + +static void translate_const_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + static const uint32_t v[] = { + 0x00000000, + 0x3f800000, + 0x40000000, + 0x3f000000, + }; + + if (arg[0].num_bits == 32) { + tcg_gen_movi_i32(arg[0].out, v[arg[1].imm % ARRAY_SIZE(v)]); + } else { + tcg_gen_movi_i64(arg[0].out, v[arg[1].imm % ARRAY_SIZE(v)]); + } + if (arg[1].imm >= ARRAY_SIZE(v)) { + qemu_log_mask(LOG_GUEST_ERROR, + "const.s f%d, #%d, immediate value is reserved\n", + arg[0].imm, arg[1].imm); + } +} + +static void translate_float_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 scale = tcg_const_i32(-arg[2].imm); + + if (par[0]) { + gen_helper_uitof_d(arg[0].out, cpu_env, arg[1].in, scale); + } else { + gen_helper_itof_d(arg[0].out, cpu_env, arg[1].in, scale); + } + tcg_temp_free(scale); +} + static void translate_float_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 scale = tcg_const_i32(-arg[2].imm); + OpcodeArg arg32[1]; + get_f32_o1(arg, arg32, 0); if (par[0]) { - gen_helper_uitof_s(arg[0].out, cpu_env, arg[1].in, scale); + gen_helper_uitof_s(arg32[0].out, cpu_env, arg[1].in, scale); + } else { + gen_helper_itof_s(arg32[0].out, cpu_env, arg[1].in, scale); + } + put_f32_o1(arg, arg32, 0); + tcg_temp_free(scale); +} + +static void translate_ftoi_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 rounding_mode = tcg_const_i32(par[0]); + TCGv_i32 scale = tcg_const_i32(arg[2].imm); + + if (par[1]) { + gen_helper_ftoui_d(arg[0].out, cpu_env, arg[1].in, + rounding_mode, scale); } else { - gen_helper_itof_s(arg[0].out, cpu_env, arg[1].in, scale); + gen_helper_ftoi_d(arg[0].out, cpu_env, arg[1].in, + rounding_mode, scale); } + tcg_temp_free(rounding_mode); tcg_temp_free(scale); } @@ -6365,14 +6631,17 @@ static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[], { TCGv_i32 rounding_mode = tcg_const_i32(par[0]); TCGv_i32 scale = tcg_const_i32(arg[2].imm); + OpcodeArg arg32[2]; + get_f32_i1(arg, arg32, 1); if (par[1]) { - gen_helper_ftoui_s(arg[0].out, arg[1].in, + gen_helper_ftoui_s(arg[0].out, cpu_env, arg32[1].in, rounding_mode, scale); } else { - gen_helper_ftoi_s(arg[0].out, arg[1].in, + gen_helper_ftoi_s(arg[0].out, cpu_env, arg32[1].in, rounding_mode, scale); } + put_f32_i1(arg, arg32, 1); tcg_temp_free(rounding_mode); tcg_temp_free(scale); } @@ -6413,81 +6682,200 @@ static void translate_ldstx(DisasContext *dc, const OpcodeArg arg[], tcg_temp_free(addr); } -static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[], +static void translate_madd_d(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_madd_s(arg[0].out, cpu_env, + gen_helper_madd_d(arg[0].out, cpu_env, arg[0].in, arg[1].in, arg[2].in); } +static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + OpcodeArg arg32[3]; + + get_f32_o1_i3(arg, arg32, 0, 0, 1, 2); + gen_helper_madd_s(arg32[0].out, cpu_env, + arg32[0].in, arg32[1].in, arg32[2].in); + put_f32_o1_i3(arg, arg32, 0, 0, 1, 2); +} + +static void translate_mov_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_mov_i64(arg[0].out, arg[1].in); +} + static void translate_mov_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(arg[0].out, arg[1].in); + if (arg[0].num_bits == 32) { + tcg_gen_mov_i32(arg[0].out, arg[1].in); + } else { + tcg_gen_mov_i64(arg[0].out, arg[1].in); + } +} + +static void translate_movcond_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 arg2 = tcg_temp_new_i64(); + + tcg_gen_ext_i32_i64(arg2, arg[2].in); + tcg_gen_movcond_i64(par[0], arg[0].out, + arg2, zero, + arg[1].in, arg[0].in); + tcg_temp_free_i64(zero); + tcg_temp_free_i64(arg2); } static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 zero = tcg_const_i32(0); + if (arg[0].num_bits == 32) { + TCGv_i32 zero = tcg_const_i32(0); - tcg_gen_movcond_i32(par[0], arg[0].out, - arg[2].in, zero, + tcg_gen_movcond_i32(par[0], arg[0].out, + arg[2].in, zero, + arg[1].in, arg[0].in); + tcg_temp_free(zero); + } else { + translate_movcond_d(dc, arg, par); + } +} + +static void translate_movp_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i64 zero = tcg_const_i64(0); + TCGv_i32 tmp1 = tcg_temp_new_i32(); + TCGv_i64 tmp2 = tcg_temp_new_i64(); + + tcg_gen_andi_i32(tmp1, arg[2].in, 1 << arg[2].imm); + tcg_gen_extu_i32_i64(tmp2, tmp1); + tcg_gen_movcond_i64(par[0], + arg[0].out, tmp2, zero, arg[1].in, arg[0].in); - tcg_temp_free(zero); + tcg_temp_free_i64(zero); + tcg_temp_free_i32(tmp1); + tcg_temp_free_i64(tmp2); } static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 zero = tcg_const_i32(0); - TCGv_i32 tmp = tcg_temp_new_i32(); + if (arg[0].num_bits == 32) { + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm); - tcg_gen_movcond_i32(par[0], - arg[0].out, tmp, zero, - arg[1].in, arg[0].in); - tcg_temp_free(tmp); - tcg_temp_free(zero); + tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm); + tcg_gen_movcond_i32(par[0], + arg[0].out, tmp, zero, + arg[1].in, arg[0].in); + tcg_temp_free(tmp); + tcg_temp_free(zero); + } else { + translate_movp_d(dc, arg, par); + } +} + +static void translate_mul_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_mul_d(arg[0].out, cpu_env, arg[1].in, arg[2].in); } static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_mul_s(arg[0].out, cpu_env, - arg[1].in, arg[2].in); + OpcodeArg arg32[3]; + + get_f32_o1_i2(arg, arg32, 0, 1, 2); + gen_helper_mul_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in); + put_f32_o1_i2(arg, arg32, 0, 1, 2); } -static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[], +static void translate_msub_d(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_msub_s(arg[0].out, cpu_env, + gen_helper_msub_d(arg[0].out, cpu_env, arg[0].in, arg[1].in, arg[2].in); } +static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + OpcodeArg arg32[3]; + + get_f32_o1_i3(arg, arg32, 0, 0, 1, 2); + gen_helper_msub_s(arg32[0].out, cpu_env, + arg32[0].in, arg32[1].in, arg32[2].in); + put_f32_o1_i3(arg, arg32, 0, 0, 1, 2); +} + +static void translate_neg_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_neg_d(arg[0].out, arg[1].in); +} + static void translate_neg_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_neg_s(arg[0].out, arg[1].in); + OpcodeArg arg32[2]; + + get_f32_o1_i1(arg, arg32, 0, 1); + gen_helper_neg_s(arg32[0].out, arg32[1].in); + put_f32_o1_i1(arg, arg32, 0, 1); +} + +static void translate_rfr_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_extrh_i64_i32(arg[0].out, arg[1].in); } static void translate_rfr_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(arg[0].out, arg[1].in); + if (arg[1].num_bits == 32) { + tcg_gen_mov_i32(arg[0].out, arg[1].in); + } else { + tcg_gen_extrl_i64_i32(arg[0].out, arg[1].in); + } +} + +static void translate_sub_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_sub_d(arg[0].out, cpu_env, arg[1].in, arg[2].in); } static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_sub_s(arg[0].out, cpu_env, - arg[1].in, arg[2].in); + OpcodeArg arg32[3]; + + get_f32_o1_i2(arg, arg32, 0, 1, 2); + gen_helper_sub_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in); + put_f32_o1_i2(arg, arg32, 0, 1, 2); +} + +static void translate_wfr_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_concat_i32_i64(arg[0].out, arg[2].in, arg[1].in); } static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(arg[0].out, arg[1].in); + if (arg[0].num_bits == 32) { + tcg_gen_mov_i32(arg[0].out, arg[1].in); + } else { + tcg_gen_ext_i32_i64(arg[0].out, arg[1].in); + } } static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[], @@ -6718,3 +7106,635 @@ const XtensaOpcodeTranslators xtensa_fpu2000_opcodes = { .num_opcodes = ARRAY_SIZE(fpu2000_ops), .opcode = fpu2000_ops, }; + + +static void translate_cvtd_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 v = tcg_temp_new_i32(); + + tcg_gen_extrl_i64_i32(v, arg[1].in); + gen_helper_cvtd_s(arg[0].out, cpu_env, v); + tcg_temp_free_i32(v); +} + +static void translate_cvts_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 v = tcg_temp_new_i32(); + + gen_helper_cvts_d(v, cpu_env, arg[1].in); + tcg_gen_extu_i32_i64(arg[0].out, v); + tcg_temp_free_i32(v); +} + +static void translate_ldsti_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 addr; + + if (par[1]) { + addr = tcg_temp_new_i32(); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); + } else { + addr = arg[1].in; + } + gen_load_store_alignment(dc, 3, addr, false); + if (par[0]) { + tcg_gen_qemu_st64(arg[0].in, addr, dc->cring); + } else { + tcg_gen_qemu_ld64(arg[0].out, addr, dc->cring); + } + if (par[2]) { + if (par[1]) { + tcg_gen_mov_i32(arg[1].out, addr); + } else { + tcg_gen_addi_i32(arg[1].out, arg[1].in, arg[2].imm); + } + } + if (par[1]) { + tcg_temp_free(addr); + } +} + +static void translate_ldsti_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 addr; + OpcodeArg arg32[1]; + + if (par[1]) { + addr = tcg_temp_new_i32(); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); + } else { + addr = arg[1].in; + } + gen_load_store_alignment(dc, 2, addr, false); + if (par[0]) { + get_f32_i1(arg, arg32, 0); + tcg_gen_qemu_st32(arg32[0].in, addr, dc->cring); + put_f32_i1(arg, arg32, 0); + } else { + get_f32_o1(arg, arg32, 0); + tcg_gen_qemu_ld32u(arg32[0].out, addr, dc->cring); + put_f32_o1(arg, arg32, 0); + } + if (par[2]) { + if (par[1]) { + tcg_gen_mov_i32(arg[1].out, addr); + } else { + tcg_gen_addi_i32(arg[1].out, arg[1].in, arg[2].imm); + } + } + if (par[1]) { + tcg_temp_free(addr); + } +} + +static void translate_ldstx_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 addr; + + if (par[1]) { + addr = tcg_temp_new_i32(); + tcg_gen_add_i32(addr, arg[1].in, arg[2].in); + } else { + addr = arg[1].in; + } + gen_load_store_alignment(dc, 3, addr, false); + if (par[0]) { + tcg_gen_qemu_st64(arg[0].in, addr, dc->cring); + } else { + tcg_gen_qemu_ld64(arg[0].out, addr, dc->cring); + } + if (par[2]) { + if (par[1]) { + tcg_gen_mov_i32(arg[1].out, addr); + } else { + tcg_gen_add_i32(arg[1].out, arg[1].in, arg[2].in); + } + } + if (par[1]) { + tcg_temp_free(addr); + } +} + +static void translate_ldstx_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 addr; + OpcodeArg arg32[1]; + + if (par[1]) { + addr = tcg_temp_new_i32(); + tcg_gen_add_i32(addr, arg[1].in, arg[2].in); + } else { + addr = arg[1].in; + } + gen_load_store_alignment(dc, 2, addr, false); + if (par[0]) { + get_f32_i1(arg, arg32, 0); + tcg_gen_qemu_st32(arg32[0].in, addr, dc->cring); + put_f32_i1(arg, arg32, 0); + } else { + get_f32_o1(arg, arg32, 0); + tcg_gen_qemu_ld32u(arg32[0].out, addr, dc->cring); + put_f32_o1(arg, arg32, 0); + } + if (par[2]) { + if (par[1]) { + tcg_gen_mov_i32(arg[1].out, addr); + } else { + tcg_gen_add_i32(arg[1].out, arg[1].in, arg[2].in); + } + } + if (par[1]) { + tcg_temp_free(addr); + } +} + +static void translate_wur_fpu_fcr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_wur_fpu_fcr(cpu_env, arg[0].in); +} + +static void translate_rur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_rur_fpu_fsr(arg[0].out, cpu_env); +} + +static void translate_wur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_wur_fpu_fsr(cpu_env, arg[0].in); +} + +static const XtensaOpcodeOps fpu_ops[] = { + { + .name = "abs.d", + .translate = translate_abs_d, + .coprocessor = 0x1, + }, { + .name = "abs.s", + .translate = translate_abs_s, + .coprocessor = 0x1, + }, { + .name = "add.d", + .translate = translate_add_d, + .coprocessor = 0x1, + }, { + .name = "add.s", + .translate = translate_add_s, + .coprocessor = 0x1, + }, { + .name = "ceil.d", + .translate = translate_ftoi_d, + .par = (const uint32_t[]){float_round_up, false}, + .coprocessor = 0x1, + }, { + .name = "ceil.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_up, false}, + .coprocessor = 0x1, + }, { + .name = "const.d", + .translate = translate_const_d, + .coprocessor = 0x1, + }, { + .name = "const.s", + .translate = translate_const_s, + .coprocessor = 0x1, + }, { + .name = "cvtd.s", + .translate = translate_cvtd_s, + .coprocessor = 0x1, + }, { + .name = "cvts.d", + .translate = translate_cvts_d, + .coprocessor = 0x1, + }, { + .name = "float.d", + .translate = translate_float_d, + .par = (const uint32_t[]){false}, + .coprocessor = 0x1, + }, { + .name = "float.s", + .translate = translate_float_s, + .par = (const uint32_t[]){false}, + .coprocessor = 0x1, + }, { + .name = "floor.d", + .translate = translate_ftoi_d, + .par = (const uint32_t[]){float_round_down, false}, + .coprocessor = 0x1, + }, { + .name = "floor.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_down, false}, + .coprocessor = 0x1, + }, { + .name = "ldi", + .translate = translate_ldsti_d, + .par = (const uint32_t[]){false, true, false}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "ldip", + .translate = translate_ldsti_d, + .par = (const uint32_t[]){false, false, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "ldiu", + .translate = translate_ldsti_d, + .par = (const uint32_t[]){false, true, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "ldx", + .translate = translate_ldstx_d, + .par = (const uint32_t[]){false, true, false}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "ldxp", + .translate = translate_ldstx_d, + .par = (const uint32_t[]){false, false, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "ldxu", + .translate = translate_ldstx_d, + .par = (const uint32_t[]){false, true, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "lsi", + .translate = translate_ldsti_s, + .par = (const uint32_t[]){false, true, false}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "lsip", + .translate = translate_ldsti_s, + .par = (const uint32_t[]){false, false, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "lsiu", + .translate = translate_ldsti_s, + .par = (const uint32_t[]){false, true, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "lsx", + .translate = translate_ldstx_s, + .par = (const uint32_t[]){false, true, false}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "lsxp", + .translate = translate_ldstx_s, + .par = (const uint32_t[]){false, false, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "lsxu", + .translate = translate_ldstx_s, + .par = (const uint32_t[]){false, true, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "madd.d", + .translate = translate_madd_d, + .coprocessor = 0x1, + }, { + .name = "madd.s", + .translate = translate_madd_s, + .coprocessor = 0x1, + }, { + .name = "mov.d", + .translate = translate_mov_d, + .coprocessor = 0x1, + }, { + .name = "mov.s", + .translate = translate_mov_s, + .coprocessor = 0x1, + }, { + .name = "moveqz.d", + .translate = translate_movcond_d, + .par = (const uint32_t[]){TCG_COND_EQ}, + .coprocessor = 0x1, + }, { + .name = "moveqz.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_EQ}, + .coprocessor = 0x1, + }, { + .name = "movf.d", + .translate = translate_movp_d, + .par = (const uint32_t[]){TCG_COND_EQ}, + .coprocessor = 0x1, + }, { + .name = "movf.s", + .translate = translate_movp_s, + .par = (const uint32_t[]){TCG_COND_EQ}, + .coprocessor = 0x1, + }, { + .name = "movgez.d", + .translate = translate_movcond_d, + .par = (const uint32_t[]){TCG_COND_GE}, + .coprocessor = 0x1, + }, { + .name = "movgez.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_GE}, + .coprocessor = 0x1, + }, { + .name = "movltz.d", + .translate = translate_movcond_d, + .par = (const uint32_t[]){TCG_COND_LT}, + .coprocessor = 0x1, + }, { + .name = "movltz.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_LT}, + .coprocessor = 0x1, + }, { + .name = "movnez.d", + .translate = translate_movcond_d, + .par = (const uint32_t[]){TCG_COND_NE}, + .coprocessor = 0x1, + }, { + .name = "movnez.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_NE}, + .coprocessor = 0x1, + }, { + .name = "movt.d", + .translate = translate_movp_d, + .par = (const uint32_t[]){TCG_COND_NE}, + .coprocessor = 0x1, + }, { + .name = "movt.s", + .translate = translate_movp_s, + .par = (const uint32_t[]){TCG_COND_NE}, + .coprocessor = 0x1, + }, { + .name = "msub.d", + .translate = translate_msub_d, + .coprocessor = 0x1, + }, { + .name = "msub.s", + .translate = translate_msub_s, + .coprocessor = 0x1, + }, { + .name = "mul.d", + .translate = translate_mul_d, + .coprocessor = 0x1, + }, { + .name = "mul.s", + .translate = translate_mul_s, + .coprocessor = 0x1, + }, { + .name = "neg.d", + .translate = translate_neg_d, + .coprocessor = 0x1, + }, { + .name = "neg.s", + .translate = translate_neg_s, + .coprocessor = 0x1, + }, { + .name = "oeq.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_OEQ}, + .coprocessor = 0x1, + }, { + .name = "oeq.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_OEQ}, + .coprocessor = 0x1, + }, { + .name = "ole.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_OLE}, + .coprocessor = 0x1, + }, { + .name = "ole.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_OLE}, + .coprocessor = 0x1, + }, { + .name = "olt.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_OLT}, + .coprocessor = 0x1, + }, { + .name = "olt.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_OLT}, + .coprocessor = 0x1, + }, { + .name = "rfr", + .translate = translate_rfr_s, + .coprocessor = 0x1, + }, { + .name = "rfrd", + .translate = translate_rfr_d, + .coprocessor = 0x1, + }, { + .name = "round.d", + .translate = translate_ftoi_d, + .par = (const uint32_t[]){float_round_nearest_even, false}, + .coprocessor = 0x1, + }, { + .name = "round.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_nearest_even, false}, + .coprocessor = 0x1, + }, { + .name = "rur.fcr", + .translate = translate_rur, + .par = (const uint32_t[]){FCR}, + .coprocessor = 0x1, + }, { + .name = "rur.fsr", + .translate = translate_rur_fpu_fsr, + .coprocessor = 0x1, + }, { + .name = "sdi", + .translate = translate_ldsti_d, + .par = (const uint32_t[]){true, true, false}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "sdip", + .translate = translate_ldsti_d, + .par = (const uint32_t[]){true, false, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "sdiu", + .translate = translate_ldsti_d, + .par = (const uint32_t[]){true, true, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "sdx", + .translate = translate_ldstx_d, + .par = (const uint32_t[]){true, true, false}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "sdxp", + .translate = translate_ldstx_d, + .par = (const uint32_t[]){true, false, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "sdxu", + .translate = translate_ldstx_d, + .par = (const uint32_t[]){true, true, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "ssi", + .translate = translate_ldsti_s, + .par = (const uint32_t[]){true, true, false}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "ssip", + .translate = translate_ldsti_s, + .par = (const uint32_t[]){true, false, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "ssiu", + .translate = translate_ldsti_s, + .par = (const uint32_t[]){true, true, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "ssx", + .translate = translate_ldstx_s, + .par = (const uint32_t[]){true, true, false}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "ssxp", + .translate = translate_ldstx_s, + .par = (const uint32_t[]){true, false, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "ssxu", + .translate = translate_ldstx_s, + .par = (const uint32_t[]){true, true, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "sub.d", + .translate = translate_sub_d, + .coprocessor = 0x1, + }, { + .name = "sub.s", + .translate = translate_sub_s, + .coprocessor = 0x1, + }, { + .name = "trunc.d", + .translate = translate_ftoi_d, + .par = (const uint32_t[]){float_round_to_zero, false}, + .coprocessor = 0x1, + }, { + .name = "trunc.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_to_zero, false}, + .coprocessor = 0x1, + }, { + .name = "ueq.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_UEQ}, + .coprocessor = 0x1, + }, { + .name = "ueq.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_UEQ}, + .coprocessor = 0x1, + }, { + .name = "ufloat.d", + .translate = translate_float_d, + .par = (const uint32_t[]){true}, + .coprocessor = 0x1, + }, { + .name = "ufloat.s", + .translate = translate_float_s, + .par = (const uint32_t[]){true}, + .coprocessor = 0x1, + }, { + .name = "ule.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_ULE}, + .coprocessor = 0x1, + }, { + .name = "ule.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_ULE}, + .coprocessor = 0x1, + }, { + .name = "ult.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_ULT}, + .coprocessor = 0x1, + }, { + .name = "ult.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_ULT}, + .coprocessor = 0x1, + }, { + .name = "un.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_UN}, + .coprocessor = 0x1, + }, { + .name = "un.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_UN}, + .coprocessor = 0x1, + }, { + .name = "utrunc.d", + .translate = translate_ftoi_d, + .par = (const uint32_t[]){float_round_to_zero, true}, + .coprocessor = 0x1, + }, { + .name = "utrunc.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_to_zero, true}, + .coprocessor = 0x1, + }, { + .name = "wfr", + .translate = translate_wfr_s, + .coprocessor = 0x1, + }, { + .name = "wfrd", + .translate = translate_wfr_d, + .coprocessor = 0x1, + }, { + .name = "wur.fcr", + .translate = translate_wur_fpu_fcr, + .par = (const uint32_t[]){FCR}, + .coprocessor = 0x1, + }, { + .name = "wur.fsr", + .translate = translate_wur_fpu_fsr, + .coprocessor = 0x1, + }, +}; + +const XtensaOpcodeTranslators xtensa_fpu_opcodes = { + .num_opcodes = ARRAY_SIZE(fpu_ops), + .opcode = fpu_ops, +}; From patchwork Mon Jul 6 23:47:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647175 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8296260D for ; Mon, 6 Jul 2020 23:51:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5915620672 for ; Mon, 6 Jul 2020 23:51:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bcjOY7mf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5915620672 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:53298 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsaty-0001Fc-Fs for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:51:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35380) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaqB-00015m-MR for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:03 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:34814) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaq9-0000vg-Sx for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:03 -0400 Received: by mail-pf1-x444.google.com with SMTP id u185so15583498pfu.1 for ; Mon, 06 Jul 2020 16:48:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eUiNODQ/7a2hmywnzx9VN+sLDGZQNqSwzW1+Xp1VjYg=; b=bcjOY7mfMWjziri4RE/Tmc/o7/eH/xBiA3t93b2Tnb9cuPMdCw0KtgJLeCllYc3uHZ ZB4IhWiTWkfnWbX7J5/78OukFqub+Si/5NELSBhaNU2DF36YQFeDXNgjWrN2Gb9JxWB3 PCDTMcqz/Oi6czeiCj7ngxU1bdXK25am+zWA0zHEupqx/0TGXM1jNeShOQ8/ESGeXWGm slF4OyPu37ck0V3tniL6aWiha3InPPSecZVerIhU3MzBHQ6JvnSIHyjFASzu6PLpHjJw wC31QiPyNohroDy4pOFewSTA4qDTqADtXA2m4MTRJxntGaMI55NX9uw9zlxZ3ZAE5FBi LpUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eUiNODQ/7a2hmywnzx9VN+sLDGZQNqSwzW1+Xp1VjYg=; b=VS+xjZ/hYdx4vxwgHsF1H9dZ1bEwZ5pwlWnCk7HEqi9bj6aNhgx9f1KWVMnlGJ/GCq oYU9WdIRZXGl7rEBnwBwBAS14T3/HOuIhaGZ25oK4HBJ/GAnnZ5VISuMTRtBUkxI0rGc 2uQUbL2AXiEdynor1BQAyJFYwJ/bGQ32evxgWUcoYWYoJb0cq5h1hAggklPAaC72PaTG 0zY0ctoLk52pYG+4/3T8m56wMyQ+OHMU/yxsZGX46DcgtJHN8p6uw9So5Yrf+mJklUAT FbI/8qJXoKYVeTKSGKc1j/AsynmkYTxzgHZr8KrOtr+uvs3ggQNMGafJJBR/37yyj+aW a9jA== X-Gm-Message-State: AOAM532tRENgdwI0tVOLW/B16geAW7sU4mqa0tIXrINs3AumJ19UP21l rBMFEVoPDBmTSOXEeC3aWR0Ih8l0 X-Google-Smtp-Source: ABdhPJxRgzVcQMiGKj05hWVRaqlMTkhgh8P4CuO6nPMoUx74mySkWQD8JbpORNPqxeeHAzHNNhkGHg== X-Received: by 2002:a63:745:: with SMTP id 66mr43769626pgh.316.1594079280470; Mon, 06 Jul 2020 16:48:00 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.47.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:48:00 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 10/21] target/xtensa: implement FPU division and square root Date: Mon, 6 Jul 2020 16:47:26 -0700 Message-Id: <20200706234737.32378-11-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=jcmvbkbc@gmail.com; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This does not implement all opcodes related to div/sqrt as specified in the xtensa ISA, partly because the official specification is not complete and partly because precise implementation is unnecessarily complex. Instead instructions specific to the div/sqrt sequences are implemented differently, most of them as nops, but the results of div/sqrt sequences is preserved. Signed-off-by: Max Filippov --- target/xtensa/fpu_helper.c | 24 +++++++++ target/xtensa/helper.h | 4 ++ target/xtensa/translate.c | 104 +++++++++++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+) diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index 514b888b3d9a..f03a6b000460 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -203,6 +203,30 @@ float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) &env->fp_status); } +float64 HELPER(mkdadj_d)(CPUXtensaState *env, float64 a, float64 b) +{ + set_use_first_nan(true, &env->fp_status); + return float64_div(b, a, &env->fp_status); +} + +float32 HELPER(mkdadj_s)(CPUXtensaState *env, float32 a, float32 b) +{ + set_use_first_nan(env->config->use_first_nan, &env->fp_status); + return float32_div(b, a, &env->fp_status); +} + +float64 HELPER(mksadj_d)(CPUXtensaState *env, float64 v) +{ + set_use_first_nan(true, &env->fp_status); + return float64_sqrt(v, &env->fp_status); +} + +float32 HELPER(mksadj_s)(CPUXtensaState *env, float32 v) +{ + set_use_first_nan(env->config->use_first_nan, &env->fp_status); + return float32_sqrt(v, &env->fp_status); +} + uint32_t HELPER(ftoi_d)(CPUXtensaState *env, float64 v, uint32_t rounding_mode, uint32_t scale) { diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index a328af47cd31..d38432bab2a0 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -54,6 +54,8 @@ DEF_HELPER_3(sub_s, f32, env, f32, f32) DEF_HELPER_3(mul_s, f32, env, f32, f32) DEF_HELPER_4(madd_s, f32, env, f32, f32, f32) DEF_HELPER_4(msub_s, f32, env, f32, f32, f32) +DEF_HELPER_3(mkdadj_s, f32, env, f32, f32) +DEF_HELPER_2(mksadj_s, f32, env, f32) DEF_HELPER_4(ftoi_s, i32, env, f32, i32, i32) DEF_HELPER_4(ftoui_s, i32, env, f32, i32, i32) DEF_HELPER_3(itof_s, f32, env, i32, i32) @@ -78,6 +80,8 @@ DEF_HELPER_3(sub_d, f64, env, f64, f64) DEF_HELPER_3(mul_d, f64, env, f64, f64) DEF_HELPER_4(madd_d, f64, env, f64, f64, f64) DEF_HELPER_4(msub_d, f64, env, f64, f64, f64) +DEF_HELPER_3(mkdadj_d, f64, env, f64, f64) +DEF_HELPER_2(mksadj_d, f64, env, f64) DEF_HELPER_4(ftoi_d, i32, env, f64, i32, i32) DEF_HELPER_4(ftoui_d, i32, env, f64, i32, i32) DEF_HELPER_3(itof_d, f64, env, i32, i32) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index ab83e259917a..ea8bac29831f 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -7254,6 +7254,38 @@ static void translate_ldstx_s(DisasContext *dc, const OpcodeArg arg[], } } +static void translate_mkdadj_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_mkdadj_d(arg[0].out, cpu_env, arg[0].in, arg[1].in); +} + +static void translate_mkdadj_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + OpcodeArg arg32[2]; + + get_f32_o1_i2(arg, arg32, 0, 0, 1); + gen_helper_mkdadj_s(arg32[0].out, cpu_env, arg32[0].in, arg32[1].in); + put_f32_o1_i2(arg, arg32, 0, 0, 1); +} + +static void translate_mksadj_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_mksadj_d(arg[0].out, cpu_env, arg[1].in); +} + +static void translate_mksadj_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + OpcodeArg arg32[2]; + + get_f32_o1_i1(arg, arg32, 0, 1); + gen_helper_mksadj_s(arg32[0].out, cpu_env, arg32[1].in); + put_f32_o1_i1(arg, arg32, 0, 1); +} + static void translate_wur_fpu_fcr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -7289,6 +7321,22 @@ static const XtensaOpcodeOps fpu_ops[] = { .name = "add.s", .translate = translate_add_s, .coprocessor = 0x1, + }, { + .name = "addexp.d", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "addexp.s", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "addexpm.d", + .translate = translate_mov_s, + .coprocessor = 0x1, + }, { + .name = "addexpm.s", + .translate = translate_mov_s, + .coprocessor = 0x1, }, { .name = "ceil.d", .translate = translate_ftoi_d, @@ -7315,6 +7363,22 @@ static const XtensaOpcodeOps fpu_ops[] = { .name = "cvts.d", .translate = translate_cvts_d, .coprocessor = 0x1, + }, { + .name = "div0.d", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "div0.s", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "divn.d", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "divn.s", + .translate = translate_nop, + .coprocessor = 0x1, }, { .name = "float.d", .translate = translate_float_d, @@ -7415,6 +7479,30 @@ static const XtensaOpcodeOps fpu_ops[] = { .name = "madd.s", .translate = translate_madd_s, .coprocessor = 0x1, + }, { + .name = "maddn.d", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "maddn.s", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "mkdadj.d", + .translate = translate_mkdadj_d, + .coprocessor = 0x1, + }, { + .name = "mkdadj.s", + .translate = translate_mkdadj_s, + .coprocessor = 0x1, + }, { + .name = "mksadj.d", + .translate = translate_mksadj_d, + .coprocessor = 0x1, + }, { + .name = "mksadj.s", + .translate = translate_mksadj_s, + .coprocessor = 0x1, }, { .name = "mov.d", .translate = translate_mov_d, @@ -7507,6 +7595,14 @@ static const XtensaOpcodeOps fpu_ops[] = { .name = "neg.s", .translate = translate_neg_s, .coprocessor = 0x1, + }, { + .name = "nexp01.d", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "nexp01.s", + .translate = translate_nop, + .coprocessor = 0x1, }, { .name = "oeq.d", .translate = translate_compare_d, @@ -7600,6 +7696,14 @@ static const XtensaOpcodeOps fpu_ops[] = { .par = (const uint32_t[]){true, true, true}, .op_flags = XTENSA_OP_STORE, .coprocessor = 0x1, + }, { + .name = "sqrt0.d", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "sqrt0.s", + .translate = translate_nop, + .coprocessor = 0x1, }, { .name = "ssi", .translate = translate_ldsti_s, From patchwork Mon Jul 6 23:47:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647185 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 481C61398 for ; Mon, 6 Jul 2020 23:55:11 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1EA1D207BB for ; Mon, 6 Jul 2020 23:55:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mGBB5ADW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1EA1D207BB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36582 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsax4-0006QP-E6 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:55:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaqC-00019A-Te for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:04 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:34877) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaqA-0000w6-Pp for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:04 -0400 Received: by mail-pj1-x102d.google.com with SMTP id f16so7309692pjt.0 for ; Mon, 06 Jul 2020 16:48:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ON8TlGBWP6j9tnyoD1Ob1PnTUOjdjsUaKfXxF5xWLoo=; b=mGBB5ADWjkw1K2wH++Ya1kMjmO9oW/mtQSBcKxb3Fb1lUBDOkiqN+4qdV2EEEfwSSg 1or8AO/uz0Lrzght15bNNC/6Udn+9vBA4rFsbfkpWFoBYZAoqUKIIDvzDRzPFQJWDKWi VI64Py4Tvey+Ts9frcfe/3JFnV0OZqLnnAKXnYyJ9AEIyzb3B2LuK0aMPssOZCtAp4Wr uQA1GdFi6b27Lfg1XR1fLHvp3SZRyXazITkXvXEU7cyFJl0onyINYaKjneyVTUyb59RW TCNej0SBmdY0i2BZqJeWclLsvvcHrwLycQi8zS/H8S9OiYnwfyD6E+ucu9Iff6gidcmT 3Rdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ON8TlGBWP6j9tnyoD1Ob1PnTUOjdjsUaKfXxF5xWLoo=; b=AxOWzZL/RBwKEJ9wsHS3hHOYu7jIkkTd42em2wMYQ5eyN7Y+YDLOi4vQ4NCm8mJe7W CRViIiTyJIPN3ZkTFM5PLEqz6dMy8m29VWjqKG5ujisnDPzuc0rvWm1Oe/jaoKi5Cu9R bX99wD9ditfgj/eAYUhMAOX19jnxFTHjHz+XxF+VmEh83cJhLz1EcX4aaoMt7TgDjEHM 7oF3ZYBnir0tXC+a374Eme7LwSlsEf/MWT7TFuKFyq/AgDmKYsWjBkaGnv8+u4te2jg8 oeL06Bbxhn03lfPbPLAlE4f3byBpyTpWEqehDnqHYEGNgKg2curMWU8SSCJIV9u/c62I cCnw== X-Gm-Message-State: AOAM530DKf6RI6EWBvINx38V+hDUFSI52EnEVsoLFHfchKluNVFoEZMA zHd+W3n7DAElAAJMtdx2HiCmUt9Y X-Google-Smtp-Source: ABdhPJyYoIBJaMcxfQ+mXAWmbtd1k2e+oH6ovoluwJqZRotaCH8DZR3TUkFUBDdjr4mzciNpq1Y/hQ== X-Received: by 2002:a17:90a:240a:: with SMTP id h10mr1532565pje.225.1594079281418; Mon, 06 Jul 2020 16:48:01 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.48.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:48:00 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 11/21] tests/tcg/xtensa: fix test execution on ISS Date: Mon, 6 Jul 2020 16:47:27 -0700 Message-Id: <20200706234737.32378-12-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=jcmvbkbc@gmail.com; helo=mail-pj1-x102d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Space for test results may be allocated in IRAM which is only word-accessible. Use full 32-bit words to access test results. Signed-off-by: Max Filippov --- tests/tcg/xtensa/macros.inc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/tcg/xtensa/macros.inc b/tests/tcg/xtensa/macros.inc index aa8f95bce879..f88937c7bf82 100644 --- a/tests/tcg/xtensa/macros.inc +++ b/tests/tcg/xtensa/macros.inc @@ -3,7 +3,7 @@ .macro test_suite name .data status: .word result -result: .space 256 +result: .space 1024 .text .global main .align 4 @@ -25,9 +25,9 @@ main: movi a3, 0 beqz a2, 2f 1: - l8ui a1, a0, 0 + l32i a1, a0, 0 or a3, a3, a1 - addi a0, a0, 1 + addi a0, a0, 4 addi a2, a2, -1 bnez a2, 1b 2: @@ -65,7 +65,7 @@ test_\name: reset_ps movi a2, status l32i a3, a2, 0 - addi a3, a3, 1 + addi a3, a3, 4 s32i a3, a2, 0 .endm @@ -78,7 +78,7 @@ test_\name: movi a2, status l32i a2, a2, 0 movi a3, 1 - s8i a3, a2, 0 + s32i a3, a2, 0 #ifdef DEBUG print failed #endif From patchwork Mon Jul 6 23:47:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647177 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F2F521398 for ; Mon, 6 Jul 2020 23:52:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B987220672 for ; Mon, 6 Jul 2020 23:52:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AQ3+anqL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B987220672 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:53458 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsau0-0001JX-TF for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:52:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaqE-0001DT-55 for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:06 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:43185) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaqB-0000yE-SE for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:05 -0400 Received: by mail-pg1-x542.google.com with SMTP id w2so18317669pgg.10 for ; Mon, 06 Jul 2020 16:48:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4jIV5omheeV0T3drxGexigxyJptxU+Y8G8xeDL3SRR8=; b=AQ3+anqLua6w9uuTptYIv9BWTW66dZ4d8yIN52NdR511htreAz/Q51QeLaS+rFFW7d dpTuTLEBh6ysQpQ5wtsUFJLpKTK+vO2VEdUSU99V6ZZFb0G8/0R6N2Dx6g9GDtt2ccMb 6Y1qA4ldY0SQd55xH6uEgTBN5+JShqL+udc7ExlLoODkH+w+lDtmmpXVcYmi5+K5ebRr H/aIVunFaKigrrywN8LHNXJ/ujuEumi8uzJpiT8fHehpjUALVr2Bqy5IYjGYIIM+0RJZ wvczhr85IXYcVS4nWA+Prg61cPX5WuH9EE1G7BDxZGZ44EhhURKXm9bQ+/vLScDcMFYP Xu/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4jIV5omheeV0T3drxGexigxyJptxU+Y8G8xeDL3SRR8=; b=Q70pEpSm2V53pF2x2NSdOi6WBF2ZUagjiQPFgNO4b5iA1LVidmIt36BxQxo85y81Uq S/RQIOZzauCBcIPUyYnvRHPgyN67b61CvCIMJh3yAtcBX+9WobenX5OmtqNfD+D3tW5T +pFKDBby6NzaZtLtWfA/r/ga+1Bql4cSGsfAe/5EN9+lEOUtw25goiZs1mqrHvPkJNtC 8IQI5kd90HhGWms3VxLOD9dTxIK+K2+SBYJvJl/LY+VYuK1V7/DVljS2pnWIUe8Ees4q 6twOJcUNYKZmQyTh62JSDD/lw3iS0AKODB/Y5UDzixjBYgwB9+oHq3DPFHGAf8YXk5EM K8Ug== X-Gm-Message-State: AOAM531qm7NJj37hgIhVOzeGLp7MIoyw7hfSpXMFoilWdAXAVrGjh0uZ OVuMmWSb0LijD4Z38uCK/XxUcGns X-Google-Smtp-Source: ABdhPJzRKWVU4biTAQe3bQbckRg+1aZxBofiVzIkz9meC4SWb4HVi4UqblXPkL2BPOv5m8FjTw2TNA== X-Received: by 2002:aa7:8e0c:: with SMTP id c12mr5141111pfr.38.1594079282325; Mon, 06 Jul 2020 16:48:02 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.48.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:48:01 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU Date: Mon, 6 Jul 2020 16:47:28 -0700 Message-Id: <20200706234737.32378-13-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=jcmvbkbc@gmail.com; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" DFPU arithmetic opcodes update FSR flags. Add FSR parameters and expected FSR register values for the arithmetic tests. Signed-off-by: Max Filippov --- tests/tcg/xtensa/fpu.h | 142 ++++++++++++++++++++++++ tests/tcg/xtensa/test_fp0_arith.S | 178 ++++++++++++++---------------- 2 files changed, 223 insertions(+), 97 deletions(-) create mode 100644 tests/tcg/xtensa/fpu.h diff --git a/tests/tcg/xtensa/fpu.h b/tests/tcg/xtensa/fpu.h new file mode 100644 index 000000000000..42e321747304 --- /dev/null +++ b/tests/tcg/xtensa/fpu.h @@ -0,0 +1,142 @@ +#if XCHAL_HAVE_DFP || XCHAL_HAVE_FP_DIV +#define DFPU 1 +#else +#define DFPU 0 +#endif + +#define FCR_RM_NEAREST 0 +#define FCR_RM_TRUNC 1 +#define FCR_RM_CEIL 2 +#define FCR_RM_FLOOR 3 + +#define FSR__ 0x00000000 +#define FSR_I 0x00000080 +#define FSR_U 0x00000100 +#define FSR_O 0x00000200 +#define FSR_Z 0x00000400 +#define FSR_V 0x00000800 + +#define FSR_UI (FSR_U | FSR_I) +#define FSR_OI (FSR_O | FSR_I) + +#define F32_0 0x00000000 +#define F32_0_5 0x3f000000 +#define F32_1 0x3f800000 +#define F32_MAX 0x7f7fffff +#define F32_PINF 0x7f800000 +#define F32_NINF 0xff800000 + +#define F32_DNAN 0x7fc00000 +#define F32_SNAN(v) (0x7f800000 | (v)) +#define F32_QNAN(v) (0x7fc00000 | (v)) + +#define F32_MINUS 0x80000000 + +#define F64_0 0x0000000000000000 +#define F64_MIN_NORM 0x0010000000000000 +#define F64_1 0x3ff0000000000000 +#define F64_MAX_2 0x7fe0000000000000 +#define F64_MAX 0x7fefffffffffffff +#define F64_PINF 0x7ff0000000000000 +#define F64_NINF 0xfff0000000000000 + +#define F64_DNAN 0x7ff8000000000000 +#define F64_SNAN(v) (0x7ff0000000000000 | (v)) +#define F64_QNAN(v) (0x7ff8000000000000 | (v)) + +#define F64_MINUS 0x8000000000000000 + +.macro test_op1_rm op, fr0, fr1, v0, r, sr + movi a2, 0 + wur a2, fsr + movfp \fr0, \v0 + \op \fr1, \fr0 + check_res \fr1, \r, \sr +.endm + +.macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r, sr + movi a2, 0 + wur a2, fsr + movfp \fr0, \v0 + movfp \fr1, \v1 + \op \fr2, \fr0, \fr1 + check_res \fr2, \r, \sr +.endm + +.macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r, sr + movi a2, 0 + wur a2, fsr + movfp \fr0, \v0 + movfp \fr1, \v1 + movfp \fr2, \v2 + \op \fr0, \fr1, \fr2 + check_res \fr3, \r, \sr +.endm + +.macro test_op1_ex op, fr0, fr1, v0, rm, r, sr + movi a2, \rm + wur a2, fcr + test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr + movi a2, (\rm) | 0x7c + wur a2, fcr + test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr +.endm + +.macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r, sr + movi a2, \rm + wur a2, fcr + test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r, \sr + movi a2, (\rm) | 0x7c + wur a2, fcr + test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r, \sr +.endm + +.macro test_op3_ex op, fr0, fr1, fr2, fr3, v0, v1, v2, rm, r, sr + movi a2, \rm + wur a2, fcr + test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r, \sr + movi a2, (\rm) | 0x7c + wur a2, fcr + test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r, \sr +.endm + +.macro test_op1 op, fr0, fr1, v0, r0, r1, r2, r3, sr0, sr1, sr2, sr3 + test_op1_ex \op, \fr0, \fr1, \v0, 0, \r0, \sr0 + test_op1_ex \op, \fr0, \fr1, \v0, 1, \r1, \sr1 + test_op1_ex \op, \fr0, \fr1, \v0, 2, \r2, \sr2 + test_op1_ex \op, \fr0, \fr1, \v0, 3, \r3, \sr3 +.endm + +.macro test_op2 op, fr0, fr1, fr2, v0, v1, r0, r1, r2, r3, sr0, sr1, sr2, sr3 + test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 0, \r0, \sr0 + test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 1, \r1, \sr1 + test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 2, \r2, \sr2 + test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 3, \r3, \sr3 +.endm + +.macro test_op3 op, fr0, fr1, fr2, fr3, v0, v1, v2, r0, r1, r2, r3, sr0, sr1, sr2, sr3 + test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 0, \r0, \sr0 + test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 1, \r1, \sr1 + test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 2, \r2, \sr2 + test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 3, \r3, \sr3 +.endm + +.macro test_op2_cpe op + set_vector kernel, 2f + movi a2, 0 + wsr a2, cpenable +1: + \op f2, f0, f1 + test_fail +2: + rsr a2, excvaddr + movi a3, 1b + assert eq, a2, a3 + rsr a2, exccause + movi a3, 32 + assert eq, a2, a3 + + set_vector kernel, 0 + movi a2, 1 + wsr a2, cpenable +.endm diff --git a/tests/tcg/xtensa/test_fp0_arith.S b/tests/tcg/xtensa/test_fp0_arith.S index 253d033a3398..df870eb7a013 100644 --- a/tests/tcg/xtensa/test_fp0_arith.S +++ b/tests/tcg/xtensa/test_fp0_arith.S @@ -1,4 +1,5 @@ #include "macros.inc" +#include "fpu.h" test_suite fp0_arith @@ -9,84 +10,18 @@ test_suite fp0_arith wfr \fr, a2 .endm -.macro check_res fr, r +.macro check_res fr, r, sr rfr a2, \fr dump a2 movi a3, \r assert eq, a2, a3 rur a2, fsr - assert eqi, a2, 0 -.endm - -.macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r - movi a2, 0 - wur a2, fsr - movfp \fr0, \v0 - movfp \fr1, \v1 - \op \fr2, \fr0, \fr1 - check_res \fr2, \r -.endm - -.macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r - movi a2, 0 - wur a2, fsr - movfp \fr0, \v0 - movfp \fr1, \v1 - movfp \fr2, \v2 - \op \fr0, \fr1, \fr2 - check_res \fr3, \r -.endm - -.macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r - movi a2, \rm - wur a2, fcr - test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r - movi a2, (\rm) | 0x7c - wur a2, fcr - test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r -.endm - -.macro test_op3_ex op, fr0, fr1, fr2, fr3, v0, v1, v2, rm, r - movi a2, \rm - wur a2, fcr - test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r - movi a2, (\rm) | 0x7c - wur a2, fcr - test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r -.endm - -.macro test_op2 op, fr0, fr1, fr2, v0, v1, r0, r1, r2, r3 - test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 0, \r0 - test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 1, \r1 - test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 2, \r2 - test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 3, \r3 -.endm - -.macro test_op3 op, fr0, fr1, fr2, fr3, v0, v1, v2, r0, r1, r2, r3 - test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 0, \r0 - test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 1, \r1 - test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 2, \r2 - test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 3, \r3 -.endm - -.macro test_op2_cpe op - set_vector kernel, 2f - movi a2, 0 - wsr a2, cpenable -1: - \op f2, f0, f1 - test_fail -2: - rsr a2, excvaddr - movi a3, 1b +#if DFPU + movi a3, \sr assert eq, a2, a3 - rsr a2, exccause - movi a3, 32 - assert eq, a2, a3 - - set_vector kernel, 0 - movi a2, 1 - wsr a2, cpenable +#else + assert eqi, a2, 0 +#endif .endm test add_s @@ -94,78 +29,127 @@ test add_s wsr a2, cpenable test_op2 add.s, f0, f1, f2, 0x3fc00000, 0x34400000, \ - 0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001 + 0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001, \ + FSR_I, FSR_I, FSR_I, FSR_I test_op2 add.s, f3, f4, f5, 0x3fc00000, 0x34a00000, \ - 0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002 + 0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002, \ + FSR_I, FSR_I, FSR_I, FSR_I /* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */ test_op2 add.s, f6, f7, f8, 0x7f7fffff, 0x7f7fffff, \ - 0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff + 0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff, \ + FSR_OI, FSR_OI, FSR_OI, FSR_OI test_end test add_s_inf /* 1 + +inf = +inf */ test_op2 add.s, f6, f7, f8, 0x3fc00000, 0x7f800000, \ - 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 + 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000, \ + FSR__, FSR__, FSR__, FSR__ /* +inf + -inf = default NaN */ test_op2 add.s, f0, f1, f2, 0x7f800000, 0xff800000, \ - 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 + 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000, \ + FSR_V, FSR_V, FSR_V, FSR_V test_end -test add_s_nan - /* 1 + NaN = NaN */ +#if DFPU +test add_s_nan_dfpu + /* 1 + QNaN = QNaN */ test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \ - 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001 + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \ + FSR__, FSR__, FSR__, FSR__ + /* 1 + SNaN = QNaN */ test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \ - 0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001 + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \ + FSR_V, FSR_V, FSR_V, FSR_V - /* NaN1 + NaN2 = NaN1 */ + /* SNaN1 + SNaN2 = QNaN2 */ + test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \ + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, \ + FSR_V, FSR_V, FSR_V, FSR_V + test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \ + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \ + FSR_V, FSR_V, FSR_V, FSR_V + /* QNaN1 + SNaN2 = QNaN2 */ + test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \ + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, \ + FSR_V, FSR_V, FSR_V, FSR_V + /* SNaN1 + QNaN2 = QNaN2 */ + test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \ + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end +#else +test add_s_nan_fpu2k + /* 1 + QNaN = QNaN */ + test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \ + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \ + FSR__, FSR__, FSR__, FSR__ + /* 1 + SNaN = SNaN */ + test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \ + 0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001, \ + FSR__, FSR__, FSR__, FSR__ + /* SNaN1 + SNaN2 = SNaN1 */ test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \ - 0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001 + 0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001, \ + FSR__, FSR__, FSR__, FSR__ test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \ - 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff + 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, \ + FSR__, FSR__, FSR__, FSR__ + /* QNaN1 + SNaN2 = QNaN1 */ test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \ - 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001 + 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \ + FSR__, FSR__, FSR__, FSR__ + /* SNaN1 + QNaN2 = SNaN1 */ test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \ - 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff + 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, \ + FSR__, FSR__, FSR__, FSR__ test_end +#endif test sub_s test_op2 sub.s, f0, f1, f0, 0x3f800001, 0x33800000, \ - 0x3f800000, 0x3f800000, 0x3f800001, 0x3f800000 + 0x3f800000, 0x3f800000, 0x3f800001, 0x3f800000, \ + FSR_I, FSR_I, FSR_I, FSR_I test_op2 sub.s, f0, f1, f1, 0x3f800002, 0x33800000, \ - 0x3f800002, 0x3f800001, 0x3f800002, 0x3f800001 + 0x3f800002, 0x3f800001, 0x3f800002, 0x3f800001, \ + FSR_I, FSR_I, FSR_I, FSR_I /* norm - norm = denorm */ test_op2 sub.s, f6, f7, f8, 0x00800001, 0x00800000, \ - 0x00000001, 0x00000001, 0x00000001, 0x00000001 + 0x00000001, 0x00000001, 0x00000001, 0x00000001, \ + FSR__, FSR__, FSR__, FSR__ test_end test mul_s test_op2 mul.s, f0, f1, f2, 0x3f800001, 0x3f800001, \ - 0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002 - + 0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002, \ + FSR_I, FSR_I, FSR_I, FSR_I /* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */ test_op2 mul.s, f6, f7, f8, 0x7f000000, 0x7f000000, \ - 0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff + 0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff, \ + FSR_OI, FSR_OI, FSR_OI, FSR_OI /* min norm * min norm = 0/denorm */ test_op2 mul.s, f6, f7, f8, 0x00800001, 0x00800000, \ - 0x00000000, 0x00000000, 0x00000001, 0x00000000 - + 0x00000000, 0x00000000, 0x00000001, 0x00000000, \ + FSR_UI, FSR_UI, FSR_UI, FSR_UI /* inf * 0 = default NaN */ test_op2 mul.s, f6, f7, f8, 0x7f800000, 0x00000000, \ - 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 + 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000, \ + FSR_V, FSR_V, FSR_V, FSR_V test_end test madd_s test_op3 madd.s, f0, f1, f2, f0, 0, 0x3f800001, 0x3f800001, \ - 0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002 + 0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002, \ + FSR_I, FSR_I, FSR_I, FSR_I test_end test msub_s test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \ - 0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001 + 0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001, \ + FSR_I, FSR_I, FSR_I, FSR_I test_end #endif From patchwork Mon Jul 6 23:47:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647179 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5422B60D for ; Mon, 6 Jul 2020 23:52:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DB5BE20672 for ; Mon, 6 Jul 2020 23:52:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CxJb/kAn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DB5BE20672 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:54492 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsauL-0001jX-Qx for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:52:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaqE-0001Dj-8E for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:06 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:37142) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaqC-0000yb-FK for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:05 -0400 Received: by mail-pl1-x641.google.com with SMTP id p1so6697581pls.4 for ; Mon, 06 Jul 2020 16:48:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qM4gdxNsTzx8cNz2D0TAu5KAdZ5SZ1c5qf/Vo1HXIQw=; b=CxJb/kAnrhzffjGO49N3XwhsWkBpu+j+BEc5+nFfmFlYY2qtDCz+249O3s9TvFwPon JE0LMRjjeTl4CV7Ugx+tiUmzzFody6eiEeugbn3wH9e3meOeLT1BHz/DWVCk+mwz8bzx lqj2HrEIE2DSsR1WtKeLM7QIOsWd6dbv9mhhy8hjU50j+VkvExZ1Zploh5ZseBmLi87d v72zpKQcMJ6drDBF00Iq7wWeSX5g019DexoO2WUslidJhRd4qxFPcs7iJomUhslN0yti qJuY2NO32e5s9ZkesVF/Juy2ysVeLXwW4Tpe+gSclB5Co5hskkVavpu9XoN02o3QeLsl tJ6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qM4gdxNsTzx8cNz2D0TAu5KAdZ5SZ1c5qf/Vo1HXIQw=; b=jx36nB+xuAWaRubWs1NExAHy6ccoJ1ouEr9oga9tRVVlV+f0flWPhWNDgaMEyGT+jn in5gna+DUv+EPi4HB/8tTBGQO3zKBQvbgyZ0WEqW8tM9tps8kDJDXGdqR9ms4/dmkXRQ Z+7Zjz2uXs89qayb1QgvKq+hvcRQeTyjaETo2PFfVgmQLaGFMmM3AhzeRpi/312t6nCI YERwhWvydosuw91HTPt+KmK0BTS9KKXHy+311mLACzPPiCGyZ9PAhUsQCCz0PGiAXytP WZFFL6UDWGa/4nqrBadZ1+jQijVA9vcLQ1SKGPWd7DbrGuWyvhl25bTj7IsfzA8IRXJU sWtg== X-Gm-Message-State: AOAM533VAzXMpAkshLiqqv7mP8WL2pfTR+lYcAne/BwRXRHWq+/v6VuM pr6KSFqm8US6hqqUuUj/sdFBpJnn X-Google-Smtp-Source: ABdhPJxEBiifpcuxAt+BEVkw/9gbZVl4AaVu9trxI62IrnjrT6jDG5ApdA/F1Ya74S9TmBOfyWEYPQ== X-Received: by 2002:a17:90a:7483:: with SMTP id p3mr1528784pjk.64.1594079283039; Mon, 06 Jul 2020 16:48:03 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:48:02 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 13/21] tests/tcg/xtensa: expand madd tests Date: Mon, 6 Jul 2020 16:47:29 -0700 Message-Id: <20200706234737.32378-14-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=jcmvbkbc@gmail.com; helo=mail-pl1-x641.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Test that madd doesn't do rounding after multiplication. Test NaN propagation rules for FPU2000 and DFPU madd opcode. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_fp0_arith.S | 88 +++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/tests/tcg/xtensa/test_fp0_arith.S b/tests/tcg/xtensa/test_fp0_arith.S index df870eb7a013..727db187a5cc 100644 --- a/tests/tcg/xtensa/test_fp0_arith.S +++ b/tests/tcg/xtensa/test_fp0_arith.S @@ -146,6 +146,94 @@ test madd_s FSR_I, FSR_I, FSR_I, FSR_I test_end +test madd_s_precision + test_op3 madd.s, f0, f1, f2, f0, 0xbf800002, 0x3f800001, 0x3f800001, \ + 0x28800000, 0x28800000, 0x28800000, 0x28800000, \ + FSR__, FSR__, FSR__, FSR__ +test_end + +#if DFPU +test madd_s_nan_dfpu + /* DFPU madd/msub NaN1, NaN2, NaN3 priority: NaN1, NaN3, NaN2 */ + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_1, \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_1, \ + F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_1, F32_QNAN(3), \ + F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \ + FSR__, FSR__, FSR__, FSR__ + + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_1, \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_QNAN(3), \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_QNAN(3), \ + F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \ + FSR__, FSR__, FSR__, FSR__ + + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_QNAN(3), \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + + /* inf * 0 = default NaN */ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_PINF, F32_0, \ + F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \ + FSR_V, FSR_V, FSR_V, FSR_V + + /* madd/msub SNaN turns to QNaN and sets Invalid flag */ + test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_1, F32_1, \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_SNAN(2), F32_1, \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end +#else +test madd_s_nan_fpu2k + /* FPU2000 madd/msub NaN1, NaN2, NaN3 priority: NaN2, NaN3, NaN1 */ + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_1, \ + F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_1, \ + F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_1, F32_QNAN(3), \ + F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \ + FSR__, FSR__, FSR__, FSR__ + + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_1, \ + F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_QNAN(3), \ + F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_QNAN(3), \ + F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \ + FSR__, FSR__, FSR__, FSR__ + + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_QNAN(3), \ + F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \ + FSR__, FSR__, FSR__, FSR__ + + /* inf * 0 = default NaN */ + test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_PINF, F32_0, \ + F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \ + FSR__, FSR__, FSR__, FSR__ + + /* madd/msub SNaN is preserved */ + test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_1, F32_1, \ + F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_SNAN(2), F32_1, \ + F32_SNAN(2), F32_SNAN(2), F32_SNAN(2), F32_SNAN(2), \ + FSR__, FSR__, FSR__, FSR__ +test_end +#endif + test msub_s test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \ 0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001, \ From patchwork Mon Jul 6 23:47:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647183 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2C7451398 for ; Mon, 6 Jul 2020 23:53:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E713620672 for ; Mon, 6 Jul 2020 23:53:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rmm91JOg" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E713620672 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:33082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsavu-0004xJ-8K for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:53:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35480) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaqG-0001Ir-6t for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:08 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:45191) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaqD-0000zf-KP for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:07 -0400 Received: by mail-pg1-x541.google.com with SMTP id l63so19099433pge.12 for ; Mon, 06 Jul 2020 16:48:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=643YbMqUe3cU9Y3BkZ4lZoPyP5SXzuFH+wHJ5r5v8mE=; b=rmm91JOgnidHWjgOeLN764ab2i8W/pWbBZbrv9howTNsAlsE3KYirgutdqfisKMGSO pw3zNAV7CSA92kOAxUttbU05zgY113rW73vivaUY5fW4ReUZZ3mMeEQvHI0iyoyj/eh8 cU30BH+4ti/wvj9aZOSzvlf4ry+KHDd264gkEVivTNqsX3SnSyJCS25f4SE7wydQadoY 5TbZXhhdi/nt5nwf8cf6Bupjy49zzSwslHLqa3RMauUrERLukw9DxPwoMnSEzihaxJUd IYjasdreFaqwTSCn3GArP65XXmxoWV/I4spEuW1CQntJv1P6sF8TTTL19QZC3mQixQZw wvmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=643YbMqUe3cU9Y3BkZ4lZoPyP5SXzuFH+wHJ5r5v8mE=; b=A9uNNG0rJXFZzko24abfCUFlRd4sfxUJJnZ+6B+hZCVQX2lPrWSh4qihtiVN3hqQoI m0oq4nmbE1UEFY0g4BCL3YVQlMl6YtJleuOkY38D9IGvOQ35WVwUi3HTkfv16joj2c3C pvlZK6aVhqwShygA6jbfKm02YxoELv2CSQQhF/B1d6aD8B04a9y4x3E5hx0gZt00TV87 IPu20fzTTzraekOF+9/ft0Fv+tUZlH3PcLljzJPbZXpS6x5dTOASMmkAT8gL7o7pm70i QQl0FsEWgtKv+1VukNG2Ck6f9Hbd6/i7Bg+RfcRB/49zcIQNfPht7Q4H/8F3Lo2sOWt2 T0lA== X-Gm-Message-State: AOAM5327/kSmzHGs+apgwKNblwFPwQVyQnDRBjvjxzj1K8IUW69f0WfG cXzbWD7k6x5uqR5TXcu9Oh1G7sTp X-Google-Smtp-Source: ABdhPJzDmgczfPxrqSKo3WO2nBv69eBclnHK81ZSJyNaKyK14j92GhD/5vhnhNe1VGpApi4RC6U00w== X-Received: by 2002:a63:7f5d:: with SMTP id p29mr42021282pgn.259.1594079283825; Mon, 06 Jul 2020 16:48:03 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.48.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:48:03 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 14/21] tests/tcg/xtensa: update test_fp0_conv for DFPU Date: Mon, 6 Jul 2020 16:47:30 -0700 Message-Id: <20200706234737.32378-15-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=jcmvbkbc@gmail.com; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" DFPU conversion opcodes update FSR flags. Add FSR parameters and expected FSR register values for the conversion tests. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_fp0_conv.S | 299 ++++++++++++++++--------------- 1 file changed, 155 insertions(+), 144 deletions(-) diff --git a/tests/tcg/xtensa/test_fp0_conv.S b/tests/tcg/xtensa/test_fp0_conv.S index 147e3d5062df..cfee6e51790c 100644 --- a/tests/tcg/xtensa/test_fp0_conv.S +++ b/tests/tcg/xtensa/test_fp0_conv.S @@ -1,4 +1,5 @@ #include "macros.inc" +#include "fpu.h" test_suite fp0_conv @@ -9,7 +10,7 @@ test_suite fp0_conv wfr \fr, a2 .endm -.macro test_ftoi_ex op, r0, fr0, v, c, r +.macro test_ftoi_ex op, r0, fr0, v, c, r, sr movi a2, 0 wur a2, fsr movfp \fr0, \v @@ -18,20 +19,25 @@ test_suite fp0_conv movi a3, \r assert eq, \r0, a3 rur a2, fsr +#if DFPU + movi a3, \sr + assert eq, a2, a3 +#else assert eqi, a2, 0 +#endif .endm -.macro test_ftoi op, r0, fr0, v, c, r +.macro test_ftoi op, r0, fr0, v, c, r, sr movi a2, 0 wur a2, fcr - test_ftoi_ex \op, \r0, \fr0, \v, \c, \r + test_ftoi_ex \op, \r0, \fr0, \v, \c, \r, \sr movi a2, 0x7c wur a2, fcr - test_ftoi_ex \op, \r0, \fr0, \v, \c, \r + test_ftoi_ex \op, \r0, \fr0, \v, \c, \r, \sr .endm -.macro test_itof_ex op, fr0, ar0, v, c, r +.macro test_itof_ex op, fr0, ar0, v, c, r, sr movi a2, 0 wur a2, fsr movi \ar0, \v @@ -42,23 +48,28 @@ test_suite fp0_conv movi a3, \r assert eq, a2, a3 rur a2, fsr +#if DFPU + movi a3, \sr + assert eq, a2, a3 +#else assert eqi, a2, 0 +#endif .endm -.macro test_itof_rm op, fr0, ar0, v, c, rm, r +.macro test_itof_rm op, fr0, ar0, v, c, rm, r, sr movi a2, \rm wur a2, fcr - test_itof_ex \op, \fr0, \ar0, \v, \c, \r + test_itof_ex \op, \fr0, \ar0, \v, \c, \r, \sr movi a2, (\rm) | 0x7c wur a2, fcr - test_itof_ex \op, \fr0, \ar0, \v, \c, \r + test_itof_ex \op, \fr0, \ar0, \v, \c, \r, \sr .endm -.macro test_itof op, fr0, ar0, v, c, r0, r1, r2, r3 - test_itof_rm \op, \fr0, \ar0, \v, \c, 0, \r0 - test_itof_rm \op, \fr0, \ar0, \v, \c, 1, \r1 - test_itof_rm \op, \fr0, \ar0, \v, \c, 2, \r2 - test_itof_rm \op, \fr0, \ar0, \v, \c, 3, \r3 +.macro test_itof op, fr0, ar0, v, c, r0, r1, r2, r3, sr + test_itof_rm \op, \fr0, \ar0, \v, \c, 0, \r0, \sr + test_itof_rm \op, \fr0, \ar0, \v, \c, 1, \r1, \sr + test_itof_rm \op, \fr0, \ar0, \v, \c, 2, \r2, \sr + test_itof_rm \op, \fr0, \ar0, \v, \c, 3, \r3, \sr .endm test round_s @@ -66,237 +77,237 @@ test round_s wsr a2, cpenable /* NaN */ - test_ftoi round.s, a2, f0, 0xffc00001, 0, 0x7fffffff - test_ftoi round.s, a2, f0, 0xff800001, 0, 0x7fffffff + test_ftoi round.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V + test_ftoi round.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V /* -inf */ - test_ftoi round.s, a2, f0, 0xff800000, 0, 0x80000000 + test_ftoi round.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V /* negative overflow */ - test_ftoi round.s, a2, f0, 0xceffffff, 1, 0x80000000 - test_ftoi round.s, a2, f0, 0xcf000000, 0, 0x80000000 - test_ftoi round.s, a2, f0, 0xceffffff, 0, 0x80000080 + test_ftoi round.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V + test_ftoi round.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__ + test_ftoi round.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__ /* negative */ - test_ftoi round.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */ - test_ftoi round.s, a2, f0, 0xbfc00000, 0, -2 /* -1.5 */ - test_ftoi round.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */ - test_ftoi round.s, a2, f0, 0xbf800000, 0, -1 /* -1 */ - test_ftoi round.s, a2, f0, 0xbf400000, 0, -1 /* -0.75 */ - test_ftoi round.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */ + test_ftoi round.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */ + test_ftoi round.s, a2, f0, 0xbfc00000, 0, -2, FSR_I /* -1.5 */ + test_ftoi round.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */ + test_ftoi round.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */ + test_ftoi round.s, a2, f0, 0xbf400000, 0, -1, FSR_I /* -0.75 */ + test_ftoi round.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */ /* positive */ - test_ftoi round.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */ - test_ftoi round.s, a2, f0, 0x3f400000, 0, 1 /* 0.75 */ - test_ftoi round.s, a2, f0, 0x3f800000, 0, 1 /* 1 */ - test_ftoi round.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */ - test_ftoi round.s, a2, f0, 0x3fc00000, 0, 2 /* 1.5 */ - test_ftoi round.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */ + test_ftoi round.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */ + test_ftoi round.s, a2, f0, 0x3f400000, 0, 1, FSR_I /* 0.75 */ + test_ftoi round.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */ + test_ftoi round.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */ + test_ftoi round.s, a2, f0, 0x3fc00000, 0, 2, FSR_I /* 1.5 */ + test_ftoi round.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */ /* positive overflow */ - test_ftoi round.s, a2, f0, 0x4effffff, 0, 0x7fffff80 - test_ftoi round.s, a2, f0, 0x4f000000, 0, 0x7fffffff - test_ftoi round.s, a2, f0, 0x4effffff, 1, 0x7fffffff + test_ftoi round.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__ + test_ftoi round.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V + test_ftoi round.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V /* +inf */ - test_ftoi round.s, a2, f0, 0x7f800000, 0, 0x7fffffff + test_ftoi round.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V /* NaN */ - test_ftoi round.s, a2, f0, 0x7f800001, 0, 0x7fffffff - test_ftoi round.s, a2, f0, 0x7fc00000, 0, 0x7fffffff + test_ftoi round.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V + test_ftoi round.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V test_end test trunc_s /* NaN */ - test_ftoi trunc.s, a2, f0, 0xffc00001, 0, 0x7fffffff - test_ftoi trunc.s, a2, f0, 0xff800001, 0, 0x7fffffff + test_ftoi trunc.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V + test_ftoi trunc.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V /* -inf */ - test_ftoi trunc.s, a2, f0, 0xff800000, 0, 0x80000000 + test_ftoi trunc.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V /* negative overflow */ - test_ftoi trunc.s, a2, f0, 0xceffffff, 1, 0x80000000 - test_ftoi trunc.s, a2, f0, 0xcf000000, 0, 0x80000000 - test_ftoi trunc.s, a2, f0, 0xceffffff, 0, 0x80000080 + test_ftoi trunc.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V + test_ftoi trunc.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__ + test_ftoi trunc.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__ /* negative */ - test_ftoi trunc.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */ - test_ftoi trunc.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */ - test_ftoi trunc.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */ - test_ftoi trunc.s, a2, f0, 0xbf800000, 0, -1 /* -1 */ - test_ftoi trunc.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */ - test_ftoi trunc.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */ + test_ftoi trunc.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */ + test_ftoi trunc.s, a2, f0, 0xbfc00000, 0, -1, FSR_I /* -1.5 */ + test_ftoi trunc.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */ + test_ftoi trunc.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */ + test_ftoi trunc.s, a2, f0, 0xbf400000, 0, 0, FSR_I /* -0.75 */ + test_ftoi trunc.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */ /* positive */ - test_ftoi trunc.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */ - test_ftoi trunc.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */ - test_ftoi trunc.s, a2, f0, 0x3f800000, 0, 1 /* 1 */ - test_ftoi trunc.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */ - test_ftoi trunc.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */ - test_ftoi trunc.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */ + test_ftoi trunc.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */ + test_ftoi trunc.s, a2, f0, 0x3f400000, 0, 0, FSR_I /* 0.75 */ + test_ftoi trunc.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */ + test_ftoi trunc.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */ + test_ftoi trunc.s, a2, f0, 0x3fc00000, 0, 1, FSR_I /* 1.5 */ + test_ftoi trunc.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */ /* positive overflow */ - test_ftoi trunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80 - test_ftoi trunc.s, a2, f0, 0x4f000000, 0, 0x7fffffff - test_ftoi trunc.s, a2, f0, 0x4effffff, 1, 0x7fffffff + test_ftoi trunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__ + test_ftoi trunc.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V + test_ftoi trunc.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V /* +inf */ - test_ftoi trunc.s, a2, f0, 0x7f800000, 0, 0x7fffffff + test_ftoi trunc.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V /* NaN */ - test_ftoi trunc.s, a2, f0, 0x7f800001, 0, 0x7fffffff - test_ftoi trunc.s, a2, f0, 0x7fc00000, 0, 0x7fffffff + test_ftoi trunc.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V + test_ftoi trunc.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V test_end test floor_s /* NaN */ - test_ftoi floor.s, a2, f0, 0xffc00001, 0, 0x7fffffff - test_ftoi floor.s, a2, f0, 0xff800001, 0, 0x7fffffff + test_ftoi floor.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V + test_ftoi floor.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V /* -inf */ - test_ftoi floor.s, a2, f0, 0xff800000, 0, 0x80000000 + test_ftoi floor.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V /* negative overflow */ - test_ftoi floor.s, a2, f0, 0xceffffff, 1, 0x80000000 - test_ftoi floor.s, a2, f0, 0xcf000000, 0, 0x80000000 - test_ftoi floor.s, a2, f0, 0xceffffff, 0, 0x80000080 + test_ftoi floor.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V + test_ftoi floor.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__ + test_ftoi floor.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__ /* negative */ - test_ftoi floor.s, a2, f0, 0xbfa00000, 1, -3 /* -1.25 * 2 */ - test_ftoi floor.s, a2, f0, 0xbfc00000, 0, -2 /* -1.5 */ - test_ftoi floor.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */ - test_ftoi floor.s, a2, f0, 0xbf800000, 0, -1 /* -1 */ - test_ftoi floor.s, a2, f0, 0xbf400000, 0, -1 /* -0.75 */ - test_ftoi floor.s, a2, f0, 0xbf000000, 0, -1 /* -0.5 */ + test_ftoi floor.s, a2, f0, 0xbfa00000, 1, -3, FSR_I /* -1.25 * 2 */ + test_ftoi floor.s, a2, f0, 0xbfc00000, 0, -2, FSR_I /* -1.5 */ + test_ftoi floor.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */ + test_ftoi floor.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */ + test_ftoi floor.s, a2, f0, 0xbf400000, 0, -1, FSR_I /* -0.75 */ + test_ftoi floor.s, a2, f0, 0xbf000000, 0, -1, FSR_I /* -0.5 */ /* positive */ - test_ftoi floor.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */ - test_ftoi floor.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */ - test_ftoi floor.s, a2, f0, 0x3f800000, 0, 1 /* 1 */ - test_ftoi floor.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */ - test_ftoi floor.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */ - test_ftoi floor.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */ + test_ftoi floor.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */ + test_ftoi floor.s, a2, f0, 0x3f400000, 0, 0, FSR_I /* 0.75 */ + test_ftoi floor.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */ + test_ftoi floor.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */ + test_ftoi floor.s, a2, f0, 0x3fc00000, 0, 1, FSR_I /* 1.5 */ + test_ftoi floor.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */ /* positive overflow */ - test_ftoi floor.s, a2, f0, 0x4effffff, 0, 0x7fffff80 - test_ftoi floor.s, a2, f0, 0x4f000000, 0, 0x7fffffff - test_ftoi floor.s, a2, f0, 0x4effffff, 1, 0x7fffffff + test_ftoi floor.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__ + test_ftoi floor.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V + test_ftoi floor.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V /* +inf */ - test_ftoi floor.s, a2, f0, 0x7f800000, 0, 0x7fffffff + test_ftoi floor.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V /* NaN */ - test_ftoi floor.s, a2, f0, 0x7f800001, 0, 0x7fffffff - test_ftoi floor.s, a2, f0, 0x7fc00000, 0, 0x7fffffff + test_ftoi floor.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V + test_ftoi floor.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V test_end test ceil_s /* NaN */ - test_ftoi ceil.s, a2, f0, 0xffc00001, 0, 0x7fffffff - test_ftoi ceil.s, a2, f0, 0xff800001, 0, 0x7fffffff + test_ftoi ceil.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V + test_ftoi ceil.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V /* -inf */ - test_ftoi ceil.s, a2, f0, 0xff800000, 0, 0x80000000 + test_ftoi ceil.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V /* negative overflow */ - test_ftoi ceil.s, a2, f0, 0xceffffff, 1, 0x80000000 - test_ftoi ceil.s, a2, f0, 0xcf000000, 0, 0x80000000 - test_ftoi ceil.s, a2, f0, 0xceffffff, 0, 0x80000080 + test_ftoi ceil.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V + test_ftoi ceil.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__ + test_ftoi ceil.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__ /* negative */ - test_ftoi ceil.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */ - test_ftoi ceil.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */ - test_ftoi ceil.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */ - test_ftoi ceil.s, a2, f0, 0xbf800000, 0, -1 /* -1 */ - test_ftoi ceil.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */ - test_ftoi ceil.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */ + test_ftoi ceil.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */ + test_ftoi ceil.s, a2, f0, 0xbfc00000, 0, -1, FSR_I /* -1.5 */ + test_ftoi ceil.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */ + test_ftoi ceil.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */ + test_ftoi ceil.s, a2, f0, 0xbf400000, 0, 0, FSR_I /* -0.75 */ + test_ftoi ceil.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */ /* positive */ - test_ftoi ceil.s, a2, f0, 0x3f000000, 0, 1 /* 0.5 */ - test_ftoi ceil.s, a2, f0, 0x3f400000, 0, 1 /* 0.75 */ - test_ftoi ceil.s, a2, f0, 0x3f800000, 0, 1 /* 1 */ - test_ftoi ceil.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */ - test_ftoi ceil.s, a2, f0, 0x3fc00000, 0, 2 /* 1.5 */ - test_ftoi ceil.s, a2, f0, 0x3fa00000, 1, 3 /* 1.25 * 2 */ + test_ftoi ceil.s, a2, f0, 0x3f000000, 0, 1, FSR_I /* 0.5 */ + test_ftoi ceil.s, a2, f0, 0x3f400000, 0, 1, FSR_I /* 0.75 */ + test_ftoi ceil.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */ + test_ftoi ceil.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */ + test_ftoi ceil.s, a2, f0, 0x3fc00000, 0, 2, FSR_I /* 1.5 */ + test_ftoi ceil.s, a2, f0, 0x3fa00000, 1, 3, FSR_I /* 1.25 * 2 */ /* positive overflow */ - test_ftoi ceil.s, a2, f0, 0x4effffff, 0, 0x7fffff80 - test_ftoi ceil.s, a2, f0, 0x4f000000, 0, 0x7fffffff - test_ftoi ceil.s, a2, f0, 0x4effffff, 1, 0x7fffffff + test_ftoi ceil.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__ + test_ftoi ceil.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V + test_ftoi ceil.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V /* +inf */ - test_ftoi ceil.s, a2, f0, 0x7f800000, 0, 0x7fffffff + test_ftoi ceil.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V /* NaN */ - test_ftoi ceil.s, a2, f0, 0x7f800001, 0, 0x7fffffff - test_ftoi ceil.s, a2, f0, 0x7fc00000, 0, 0x7fffffff + test_ftoi ceil.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V + test_ftoi ceil.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V test_end test utrunc_s /* NaN */ - test_ftoi utrunc.s, a2, f0, 0xffc00001, 0, 0xffffffff - test_ftoi utrunc.s, a2, f0, 0xff800001, 0, 0xffffffff + test_ftoi utrunc.s, a2, f0, 0xffc00001, 0, 0xffffffff, FSR_V + test_ftoi utrunc.s, a2, f0, 0xff800001, 0, 0xffffffff, FSR_V /* -inf */ - test_ftoi utrunc.s, a2, f0, 0xff800000, 0, 0x80000000 + test_ftoi utrunc.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V /* negative overflow */ - test_ftoi utrunc.s, a2, f0, 0xceffffff, 1, 0x80000000 - test_ftoi utrunc.s, a2, f0, 0xcf000000, 0, 0x80000000 - test_ftoi utrunc.s, a2, f0, 0xceffffff, 0, 0x80000080 + test_ftoi utrunc.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V + test_ftoi utrunc.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR_V + test_ftoi utrunc.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR_V /* negative */ - test_ftoi utrunc.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */ - test_ftoi utrunc.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */ - test_ftoi utrunc.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */ - test_ftoi utrunc.s, a2, f0, 0xbf800000, 0, -1 /* -1 */ - test_ftoi utrunc.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */ - test_ftoi utrunc.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */ + test_ftoi utrunc.s, a2, f0, 0xbfa00000, 1, -2, FSR_V /* -1.25 * 2 */ + test_ftoi utrunc.s, a2, f0, 0xbfc00000, 0, -1, FSR_V /* -1.5 */ + test_ftoi utrunc.s, a2, f0, 0xbf800000, 1, -2, FSR_V /* -1 * 2 */ + test_ftoi utrunc.s, a2, f0, 0xbf800000, 0, -1, FSR_V /* -1 */ + test_ftoi utrunc.s, a2, f0, 0xbf400000, 0, 0, FSR_I /* -0.75 */ + test_ftoi utrunc.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */ /* positive */ - test_ftoi utrunc.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */ - test_ftoi utrunc.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */ - test_ftoi utrunc.s, a2, f0, 0x3f800000, 0, 1 /* 1 */ - test_ftoi utrunc.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */ - test_ftoi utrunc.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */ - test_ftoi utrunc.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */ + test_ftoi utrunc.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */ + test_ftoi utrunc.s, a2, f0, 0x3f400000, 0, 0, FSR_I /* 0.75 */ + test_ftoi utrunc.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */ + test_ftoi utrunc.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */ + test_ftoi utrunc.s, a2, f0, 0x3fc00000, 0, 1, FSR_I /* 1.5 */ + test_ftoi utrunc.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */ /* positive overflow */ - test_ftoi utrunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80 - test_ftoi utrunc.s, a2, f0, 0x4f000000, 0, 0x80000000 - test_ftoi utrunc.s, a2, f0, 0x4effffff, 1, 0xffffff00 - test_ftoi utrunc.s, a2, f0, 0x4f800000, 1, 0xffffffff + test_ftoi utrunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__ + test_ftoi utrunc.s, a2, f0, 0x4f000000, 0, 0x80000000, FSR__ + test_ftoi utrunc.s, a2, f0, 0x4effffff, 1, 0xffffff00, FSR__ + test_ftoi utrunc.s, a2, f0, 0x4f800000, 1, 0xffffffff, FSR_V /* +inf */ - test_ftoi utrunc.s, a2, f0, 0x7f800000, 0, 0xffffffff + test_ftoi utrunc.s, a2, f0, 0x7f800000, 0, 0xffffffff, FSR_V /* NaN */ - test_ftoi utrunc.s, a2, f0, 0x7f800001, 0, 0xffffffff - test_ftoi utrunc.s, a2, f0, 0x7fc00000, 0, 0xffffffff + test_ftoi utrunc.s, a2, f0, 0x7f800001, 0, 0xffffffff, FSR_V + test_ftoi utrunc.s, a2, f0, 0x7fc00000, 0, 0xffffffff, FSR_V test_end test float_s test_itof float.s, f0, a2, -1, 0, \ - 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000 - test_itof float.s, f0, a2, 0, 0, 0, 0, 0, 0 + 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000, FSR__ + test_itof float.s, f0, a2, 0, 0, 0, 0, 0, 0, FSR__ test_itof float.s, f0, a2, 1, 1, \ - 0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000 + 0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000, FSR__ test_itof float.s, f0, a2, 1, 0, \ - 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, FSR__ test_itof float.s, f0, a2, 0x7fffffff, 0, \ - 0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff + 0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff, FSR_I test_end test ufloat_s - test_itof ufloat.s, f0, a2, 0, 0, 0, 0, 0, 0 + test_itof ufloat.s, f0, a2, 0, 0, 0, 0, 0, 0, FSR__ test_itof ufloat.s, f0, a2, 1, 1, \ - 0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000 + 0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000, FSR__ test_itof ufloat.s, f0, a2, 1, 0, \ - 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, FSR__ test_itof ufloat.s, f0, a2, 0x7fffffff, 0, \ - 0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff + 0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff, FSR_I test_itof ufloat.s, f0, a2, 0xffffffff, 0, \ - 0x4f800000, 0x4f7fffff, 0x4f800000, 0x4f7fffff + 0x4f800000, 0x4f7fffff, 0x4f800000, 0x4f7fffff, FSR_I test_end #endif From patchwork Mon Jul 6 23:47:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647191 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C028560D for ; Mon, 6 Jul 2020 23:57:00 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 95FB620823 for ; Mon, 6 Jul 2020 23:57:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BEgFLrY3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 95FB620823 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:42352 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsayp-0000Tc-Tb for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:56:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaqF-0001HI-Ks for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:07 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:40816) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaqE-0000zl-09 for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:07 -0400 Received: by mail-pf1-x444.google.com with SMTP id u5so17622901pfn.7 for ; Mon, 06 Jul 2020 16:48:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rzz0QASvhiLiMcKKjELZE5GUtAHuQdcLXEQeVo4joCE=; b=BEgFLrY3wm08RA17oYCj3bRguFb0o/yNSczD9QeWnveH7p+D7GBWnyP+RiVT5hOKpK Pni5OUyBPhzrbwcXSvDr034x415XCcioII0MQjjyyiMDakRbe6VCxVbSviUStE1ndKec 6DOkhMEgmvP85IPOfQzMlEEicj/7cZKaYo34ypynXQD9gx5xIcoA8pQIQrckHYhr7Mjp uDA8kB+UZnpAccRSyVJMIxUmdUoFo0e/ef2QfAiqTY88f9BLtue7l46L7shS2Tc8IWDe k0Ksb0ImbvKYSlRia+APCVcRJPXHFIKkOome2NB4IVEZpo7D+x6wZS8sFED3CKosdSAH fWhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rzz0QASvhiLiMcKKjELZE5GUtAHuQdcLXEQeVo4joCE=; b=Eb3uWBfomy84pTqJGVSptPJAFrJJ8AxGghbJGTfTCb/O0PS9GJBQkZIdTzej3ab1cP m8zOiEZrJSsVd5D1hFXTN1s7/63fvgvwg/XCEkvmvRl5gHRTt4iUyDh810kHsKD6FcSi c7iT2FEKm6xuxFVdJxKNwrZ5w5umDgpQ1QnbAORuKbR97YFL4L/JeLrni3N5Dq6vg3qc u4uXOgc39AgmeQkXbRS4WBfGdeiUH2kJBPBUT+EanCNqwaP9FelmORS958UD6BlAdhiu zIQw3S1hAOBN9Owj0ttd2Ynw6Bm5uTV8eVB0KJfPXRXXVZNPXncAb1nFv8t65VCbsQpr JolA== X-Gm-Message-State: AOAM531/gy0aL2/iFYJfAkLNAxxufVyhBQ3Z0tkO8jw8UibM9uaaBcag +X0D38F9V2khpVEGLY9fZYnAA7Oq X-Google-Smtp-Source: ABdhPJw7Ti0GTzQ40eqpCytFzhAc9TuI4kKs1nQI22i/JV4J4TkBSJqoekzYUZ3O8WEx2XqEBMB/jg== X-Received: by 2002:a62:ab15:: with SMTP id p21mr46366245pff.146.1594079284568; Mon, 06 Jul 2020 16:48:04 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.48.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:48:04 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 15/21] tests/tcg/xtensa: update test_fp1 for DFPU Date: Mon, 6 Jul 2020 16:47:31 -0700 Message-Id: <20200706234737.32378-16-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=jcmvbkbc@gmail.com; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" DFPU sets Invalid flag in FSR when at least one argument of FP comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole. Add checks for FSR and expected FSR values. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_fp1.S | 62 ++++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 28 deletions(-) diff --git a/tests/tcg/xtensa/test_fp1.S b/tests/tcg/xtensa/test_fp1.S index 6e182e5964bd..77336a3fcf2c 100644 --- a/tests/tcg/xtensa/test_fp1.S +++ b/tests/tcg/xtensa/test_fp1.S @@ -1,4 +1,5 @@ #include "macros.inc" +#include "fpu.h" test_suite fp1 @@ -9,7 +10,7 @@ test_suite fp1 wfr \fr, a2 .endm -.macro test_ord_ex op, br, fr0, fr1, v0, v1, r +.macro test_ord_ex op, br, fr0, fr1, v0, v1, r, sr movi a2, 0 wur a2, fsr movfp \fr0, \v0 @@ -20,65 +21,70 @@ test_suite fp1 movt a2, a3, \br assert eqi, a2, \r rur a2, fsr +#if DFPU + movi a3, \sr + assert eq, a2, a3 +#else assert eqi, a2, 0 +#endif .endm -.macro test_ord op, br, fr0, fr1, v0, v1, r +.macro test_ord op, br, fr0, fr1, v0, v1, r, sr movi a2, 0 wur a2, fcr - test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r + test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr movi a2, 0x7c wur a2, fcr - test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r + test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr .endm -.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI - test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa - test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab - test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba - test_ord \op b3, f6, f7, 0x3f800000, 0x7f800000, \aPI - test_ord \op b4, f8, f9, 0x7f800000, 0x3f800000, \PIa - test_ord \op b5, f10, f11, 0x3f800000, 0xffc00001, \aN - test_ord \op b6, f12, f13, 0x3f800000, 0xff800001, \aN - test_ord \op b7, f14, f15, 0x3f800000, 0x7f800001, \aN - test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN - test_ord \op b9, f2, f3, 0xffc00001, 0x3f800000, \Na - test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na - test_ord \op b11, f6, f7, 0x7f800001, 0x3f800000, \Na - test_ord \op b12, f8, f9, 0x7fc00000, 0x3f800000, \Na - test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II - test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN - test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI +.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI, qnan_sr + test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa, FSR__ /* ord == ord */ + test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab, FSR__ /* ord < ord */ + test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba, FSR__ /* ord > ord */ + test_ord \op b3, f6, f7, 0x3f800000, 0x7f800000, \aPI, FSR__ /* ord +INF */ + test_ord \op b4, f8, f9, 0x7f800000, 0x3f800000, \PIa, FSR__ /* +INF ord */ + test_ord \op b5, f10, f11, 0x3f800000, 0xffc00001, \aN, \qnan_sr /* ord -QNaN */ + test_ord \op b6, f12, f13, 0x3f800000, 0xff800001, \aN, FSR_V /* ord -SNaN */ + test_ord \op b7, f14, f15, 0x3f800000, 0x7f800001, \aN, FSR_V /* ord +SNaN */ + test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN, \qnan_sr /* ord +QNaN */ + test_ord \op b9, f2, f3, 0xffc00001, 0x3f800000, \Na, \qnan_sr /* -QNaN ord */ + test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na, FSR_V /* -SNaN ord */ + test_ord \op b11, f6, f7, 0x7f800001, 0x3f800000, \Na, FSR_V /* +SNaN ord */ + test_ord \op b12, f8, f9, 0x7fc00000, 0x3f800000, \Na, \qnan_sr /* +QNaN ord */ + test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II, FSR__ /* +INF +INF */ + test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN, \qnan_sr /* +INF +QNaN */ + test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI, \qnan_sr /* +QNaN +INF */ .endm test un_s movi a2, 1 wsr a2, cpenable - test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1 + test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, FSR__ test_end test oeq_s - test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0 + test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, FSR__ test_end test ueq_s - test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1 + test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, FSR__ test_end test olt_s - test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0 + test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, FSR_V test_end test ult_s - test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1 + test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1, FSR__ test_end test ole_s - test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0 + test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, FSR_V test_end test ule_s - test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1 + test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, FSR__ test_end .macro test_cond op, fr0, fr1, cr, v0, v1, r From patchwork Mon Jul 6 23:47:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647187 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AEE541398 for ; Mon, 6 Jul 2020 23:55:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 857DB207C4 for ; Mon, 6 Jul 2020 23:55:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bw+MC68E" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 857DB207C4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:37384 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsaxG-0006oM-R5 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:55:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35484) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaqG-0001JQ-FA for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:08 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:36846) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaqE-00011A-Sc for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:08 -0400 Received: by mail-pf1-x443.google.com with SMTP id 207so17433787pfu.3 for ; Mon, 06 Jul 2020 16:48:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R+lITptw5fn9ER442LKhdifOCNEK9wzAb+CMXJ6Z8J0=; b=bw+MC68E/oyzn+hOQ6j2EtWp9H7OF2kl/o9S+N0CqCxzk12rGm4AYqKNxPjyX6rXWM HQxI/PDQ5xMvAl0nAr707ToLRHX+VGROV0l2Yt9TGwktJ7NunZJ4kGZ/4nRR5h92fWjN m9zP6m+pl7hDKtWJ1xCpwtt8YhCU4kmOpW93RuIii7Y/zpnqnhy6CtINgoem2OMAVbC+ xvA66Wy6uct6NGH4n5qB9h6nts0eVZgl4kffF6uJreQe+ujy4vUNiPntN1Qs2pnz/+Z6 zrCwegNJ+kN8IxSUIvlh+xm6UGOLX60Oitx3laHs76GT0u4+kO9RMtUeF/QR7hHoyuEQ kJ4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R+lITptw5fn9ER442LKhdifOCNEK9wzAb+CMXJ6Z8J0=; b=aFH7ubi5J23aRotu5L8adF2b0X9lAmf6HWHg9FCyR6pVezNekp0p9/l6IwqhkCnwDy Kqj/Y/9031lzYljSsWSoy4Jq0e1zfzJBRT3107PWOS3QcHh2K0OnwV8kwRLZHbUDNVio 8RQjGwyh/yiD0H9pS402+JpAXv10jLzfF2aSQRE0BhGM9SIsgDouzlI3kQst7QL7GOxv eNxh3OTpuJ+5+w5x2ol+CYL7cXO7Wf26A5u13DGhtG2mda7oPvzz+AZmnxoyQy906fa8 g0ZUx9IFL6iozu3Ni2I5o2GNO2J72JOfBR/o/Cf1iEfcWjzjhoD/1KUB0HPF3D/M/Zd2 vBBA== X-Gm-Message-State: AOAM530kPXZj4/jg9kWusUdj+5AkPbGtE1cXqF+6GYJiqMaBsYnf0Kks FVueW5mFkLCN4aitSaHkX65HibHa X-Google-Smtp-Source: ABdhPJxh+Nt4P5HaDczifSCnNRMb/wQpETBy2t6lexxcYYVbS2PbswD/oFTl8qfNEaesk3ZjX+5f5g== X-Received: by 2002:a62:3587:: with SMTP id c129mr6840515pfa.212.1594079285500; Mon, 06 Jul 2020 16:48:05 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:48:04 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 16/21] tests/tcg/xtensa: update test_lsc for DFPU Date: Mon, 6 Jul 2020 16:47:32 -0700 Message-Id: <20200706234737.32378-17-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=jcmvbkbc@gmail.com; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" DFPU doesn't have pre-increment FP load/store opcodes, it has post-increment opcodes instead. Test increment opcodes present in the current config. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_lsc.S | 47 +++++++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 13 deletions(-) diff --git a/tests/tcg/xtensa/test_lsc.S b/tests/tcg/xtensa/test_lsc.S index 0578bf19e72e..9d59c1815a9e 100644 --- a/tests/tcg/xtensa/test_lsc.S +++ b/tests/tcg/xtensa/test_lsc.S @@ -1,4 +1,5 @@ #include "macros.inc" +#include "fpu.h" test_suite lsc @@ -9,9 +10,14 @@ test lsi wsr a2, cpenable movi a2, 1f - lsi f0, a2, 0 lsi f1, a2, 4 +#if DFPU + lsi f2, a2, 8 + lsip f0, a2, 8 +#else + lsi f0, a2, 0 lsiu f2, a2, 8 +#endif movi a3, 1f + 8 assert eq, a2, a3 rfr a2, f0 @@ -34,13 +40,18 @@ test ssi movi a2, 1f movi a3, 0x40800000 wfr f3, a3 - ssi f3, a2, 0 movi a3, 0x40a00000 wfr f4, a3 - ssi f4, a2, 4 movi a3, 0x40c00000 wfr f5, a3 + ssi f4, a2, 4 +#if DFPU + ssi f5, a2, 8 + ssip f3, a2, 8 +#else + ssi f3, a2, 0 ssiu f5, a2, 8 +#endif movi a3, 1f + 8 assert eq, a2, a3 l32i a4, a2, -8 @@ -62,11 +73,16 @@ test_end test lsx movi a2, 1f movi a3, 0 + movi a4, 4 + movi a5, 8 + lsx f7, a2, a4 +#if DFPU + lsx f8, a2, a5 + lsxp f6, a2, a5 +#else lsx f6, a2, a3 - movi a3, 4 - lsx f7, a2, a3 - movi a3, 8 - lsxu f8, a2, a3 + lsxu f8, a2, a5 +#endif movi a3, 1f + 8 assert eq, a2, a3 rfr a2, f6 @@ -87,18 +103,23 @@ test_end test ssx movi a2, 1f - movi a3, 0 movi a4, 0x41200000 wfr f9, a4 - ssx f9, a2, a3 - movi a3, 4 movi a4, 0x41300000 wfr f10, a4 - ssx f10, a2, a3 - movi a3, 8 movi a4, 0x41400000 wfr f11, a4 - ssxu f11, a2, a3 + movi a3, 0 + movi a4, 4 + movi a5, 8 + ssx f10, a2, a4 +#if DFPU + ssx f11, a2, a5 + ssxp f9, a2, a5 +#else + ssx f9, a2, a3 + ssxu f11, a2, a5 +#endif movi a3, 1f + 8 assert eq, a2, a3 l32i a4, a2, -8 From patchwork Mon Jul 6 23:47:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647189 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 543DB60D for ; Mon, 6 Jul 2020 23:56:36 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2A44420823 for ; Mon, 6 Jul 2020 23:56:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NCr6wx2+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2A44420823 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:41540 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsayR-0008U0-8c for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:56:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35502) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaqH-0001MM-EX for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:09 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:40961) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaqF-00011K-Ow for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:09 -0400 Received: by mail-pf1-x42d.google.com with SMTP id q17so17609618pfu.8 for ; Mon, 06 Jul 2020 16:48:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wa+AHpqfEWhhgAfAEPD77aSGzH6coLYk43PBINkaick=; b=NCr6wx2+R5cntPEhAq0STlGg8ebdf4qqtR6oD8e+wXTeSun91ayztURJkUNGRhkylv kNJmPV5zBOn6vuNV/kcFjOBPL1jZNhdOXKqEe1teB/4WZlASagxgPeSjb8iZMf/qX44M ScwLdfXaTSxuKWho40ttvFV6yMhaaMM8EvCniWgdMeDl5+eFXvTSoKLzVnBaRjXNCPIl wVsPeyjRjcVU7XpTg6ZfX7gYNxeeU7cnF0+68Obbx0fkW20v/uand31AjYQICWPjIn6N utxAuTwsJeNOVgcTP5Vf0XmCP0CwjdFU2wRFjg62avY7QLcY3iFP/x8WJNdwHACEfxKO 3+jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wa+AHpqfEWhhgAfAEPD77aSGzH6coLYk43PBINkaick=; b=leQLr8tGxeEyeyW6JuYMpqlb38aa2VEDXT94BLvBLHiPmcr350QEEZyRNvgSTTEbWf co3feF6u8lrEKLB7+Lv/0pmRDKGqOdl/2YTm1BJlDWLTSF8sIZxhGdIsFbmmYCQgcUz5 begxVXWlVNy/EkRitL/7uHofPXf5n7WJTygAhBSQOIU7vgRUQiOl/2ZVQKz/hgT81qiY aveITL53OhXtdVXHBUReYbVu1yG6Bb8ww+oIpmuPPZlEM4nC/D9WBlRLPEgKV3pJh/fS /wVpWXzLNx870Y3SgcjfgllJefTDHYY/dettBHL0QLhdza6rb52nutjCyPsikKA1pnKt 0V/w== X-Gm-Message-State: AOAM533IZ4XLWmZIcKiIO4F07NBpinEkIVitii5Y+zo0NlZMw6XSDf0/ IAdyDMg2nNuqeZVRyjrL10/z0LWA X-Google-Smtp-Source: ABdhPJxTMbbENNZyx3VK3rgUpe6cEh+AYBXAZt1YPM3RYFBjfLyffxBu1i9ImD/tfa3LLIeUpwnXwg== X-Received: by 2002:aa7:9638:: with SMTP id r24mr4130757pfg.297.1594079286312; Mon, 06 Jul 2020 16:48:06 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.48.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:48:05 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 17/21] tests/tcg/xtensa: add fp0 div and sqrt tests Date: Mon, 6 Jul 2020 16:47:33 -0700 Message-Id: <20200706234737.32378-18-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=jcmvbkbc@gmail.com; helo=mail-pf1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Test exact division/sqrt DFPU sequences. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_fp0_div.S | 82 ++++++++++++++++++++++++++++++++ tests/tcg/xtensa/test_fp0_sqrt.S | 76 +++++++++++++++++++++++++++++ 2 files changed, 158 insertions(+) create mode 100644 tests/tcg/xtensa/test_fp0_div.S create mode 100644 tests/tcg/xtensa/test_fp0_sqrt.S diff --git a/tests/tcg/xtensa/test_fp0_div.S b/tests/tcg/xtensa/test_fp0_div.S new file mode 100644 index 000000000000..c3e7ad7bb5b3 --- /dev/null +++ b/tests/tcg/xtensa/test_fp0_div.S @@ -0,0 +1,82 @@ +#include "macros.inc" +#include "fpu.h" + +test_suite fp0_div + +#if XCHAL_HAVE_FP_DIV + +.macro divs_seq q, a, b, r, y, y0, an, bn, e, ex + div0.s \y0, \b + nexp01.s \bn, \b + const.s \e, 1 + maddn.s \e, \bn, \y0 + mov.s \y, \y0 + mov.s \ex, \b + nexp01.s \an, \a + maddn.s \y, \e, \y0 + const.s \e, 1 + const.s \q, 0 + neg.s \r, \an + maddn.s \e, \bn, \y + maddn.s \q, \r, \y0 + mkdadj.s \ex, \a + maddn.s \y, \e, \y + maddn.s \r, \bn, \q + const.s \e, 1 + maddn.s \e, \bn, \y + maddn.s \q, \r, \y + neg.s \r, \an + maddn.s \y, \e, \y + maddn.s \r, \bn, \q + addexpm.s \q, \ex + addexp.s \y, \ex + divn.s \q, \r, \y +.endm + +.macro div_s fr0, fr1, fr2 + divs_seq \fr0, \fr1, \fr2, f9, f10, f11, f12, f13, f14, f15 +.endm + +.macro movfp fr, v + movi a2, \v + wfr \fr, a2 +.endm + +.macro check_res fr, r, sr + rfr a2, \fr + dump a2 + movi a3, \r + assert eq, a2, a3 + rur a2, fsr + movi a3, \sr + assert eq, a2, a3 +.endm + +test div_s + movi a2, 1 + wsr a2, cpenable + + test_op2 div_s, f0, f1, f2, 0x40000000, 0x40400000, \ + 0x3f2aaaab, 0x3f2aaaaa, 0x3f2aaaab, 0x3f2aaaaa, \ + FSR_I, FSR_I, FSR_I, FSR_I + test_op2 div_s, f3, f4, f5, F32_1, F32_0, \ + F32_PINF, F32_PINF, F32_PINF, F32_PINF, \ + FSR_Z, FSR_Z, FSR_Z, FSR_Z + test_op2 div_s, f6, f7, f8, F32_0, F32_0, \ + F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \ + FSR_V, FSR_V, FSR_V, FSR_V + + /* MAX_FLOAT / 0.5 = +inf/MAX_FLOAT */ + test_op2 div_s, f0, f1, f2, F32_MAX, F32_0_5, \ + F32_PINF, F32_MAX, F32_PINF, F32_MAX, \ + FSR_OI, FSR_OI, FSR_OI, FSR_OI + + /* 0.5 / MAX_FLOAT = denorm */ + test_op2 div_s, f0, f1, f2, F32_0_5, F32_MAX, \ + 0x00100000, 0x00100000, 0x00100001, 0x00100000, \ + FSR_UI, FSR_UI, FSR_UI, FSR_UI +test_end + +#endif + +test_suite_end diff --git a/tests/tcg/xtensa/test_fp0_sqrt.S b/tests/tcg/xtensa/test_fp0_sqrt.S new file mode 100644 index 000000000000..585973dce6bc --- /dev/null +++ b/tests/tcg/xtensa/test_fp0_sqrt.S @@ -0,0 +1,76 @@ +#include "macros.inc" +#include "fpu.h" + +test_suite fp0_sqrt + +#if XCHAL_HAVE_FP_SQRT + +.macro sqrt_seq r, a, y, t1, hn, h2, t5, h + sqrt0.s \y, \a + const.s \t1, 0 + maddn.s \t1, \y, \y + nexp01.s \hn, \a + const.s \r, 3 + addexp.s \hn, \r + maddn.s \r, \t1, \hn + nexp01.s \t1, \a + neg.s \h2, \t1 + maddn.s \y, \r, \y + const.s \r, 0 + const.s \t5, 0 + const.s \h, 0 + maddn.s \r, \h2, \y + maddn.s \t5, \y, \hn + const.s \hn, 3 + maddn.s \h, \hn, \y + maddn.s \t1, \r, \r + maddn.s \hn, \t5, \y + neg.s \y, \h + maddn.s \r, \t1, \y + maddn.s \h, \hn, \h + mksadj.s \y, \a + nexp01.s \a, \a + maddn.s \a, \r, \r + neg.s \t1, \h + addexpm.s \r, \y + addexp.s \t1, \y + divn.s \r, \a, \t1 +.endm + +.macro sqrt_s fr0, fr1 + sqrt_seq \fr0, \fr1, f10, f11, f12, f13, f14, f15 +.endm + +.macro movfp fr, v + movi a2, \v + wfr \fr, a2 +.endm + +.macro check_res fr, r, sr + rfr a2, \fr + dump a2 + movi a3, \r + assert eq, a2, a3 + rur a2, fsr + movi a3, \sr + assert eq, a2, a3 +.endm + +test sqrt_s + movi a2, 1 + wsr a2, cpenable + + test_op1 sqrt_s, f0, f1, 0x40000000, \ + 0x3fb504f3, 0x3fb504f3, 0x3fb504f4, 0x3fb504f3, \ + FSR_I, FSR_I, FSR_I, FSR_I + test_op1 sqrt_s, f3, f4, F32_1, \ + F32_1, F32_1, F32_1, F32_1, \ + FSR__, FSR__, FSR__, FSR__ + test_op1 sqrt_s, f6, f7, F32_MINUS | F32_1, \ + F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end + +#endif + +test_suite_end From patchwork Mon Jul 6 23:47:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647213 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 54AB714DD for ; Mon, 6 Jul 2020 23:58:11 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2B6C72082F for ; Mon, 6 Jul 2020 23:58:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WB4Y+b1T" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2B6C72082F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:45762 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsazy-0002In-AA for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:58:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35506) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaqI-0001O4-2Q for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:10 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:43122) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaqG-00011T-Go for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:09 -0400 Received: by mail-pf1-x434.google.com with SMTP id u18so2313135pfk.10 for ; Mon, 06 Jul 2020 16:48:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dczlRWi7ZhKkrGTsLLmYfEd66aSo3puvzeQP9Y5BUgA=; b=WB4Y+b1TI0batxODqFZHNcz/F2QuEZaxomnGOkLPUkFIUM6eFO5KF3bIVYivdhs8rX w7v3Y0YDDzJ3tLoOp9ej5c1u8JQSOGrRhlIFje89pAeMYHJfM/3v6QLEKD/cyWMwzSvN gQUCwGM6hNAzx3l2rPe5HsgvCMx/OIT+mq1uJtAewQ9AlRHsBMXU7NfHHrO4TwDJeJ7u FQ2zN0NBVepbKHK6luEYcC+cFg0vsaTcc/MK+8xUVPSz2b1apMsOKXNRkCrsEItvWiCz UlNo0RToPOL3sPFiePGL/jN3aBjJG67F1TKIPeT9h0sUkWIT0H5KPWphdzEOkSEiVXX9 ljNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dczlRWi7ZhKkrGTsLLmYfEd66aSo3puvzeQP9Y5BUgA=; b=tAp0tTxgNiDpU5WfOIDptOfQCoheaVuQDdxKb2hg258Mt24RrrYcsJPbl1u8ffXnfC Uag0DvQdzDbOY/R1bbgg3WhvjJkHheLppZ8FuS1iu0d1/H92nqpC7a2No9OzmEQccTHB GQhrPPGuI+eqp2EoAKMqTzsOgmqyKQQV1NLtfPauJkJIYWQPGjWeLiO3xFwv1xFCKe9P X8TEmVI9rKvjaQNLrBQBIYWbZlh0/v2QR7gceUmujPmunaMNa9zfScMU+S9GLFR69oa+ 1GfnU1DPCMGK27NM0MNe0ZGReAOxlSLZxCv8kOgYWV0MC+5oU5ylLzH3Wcz2r8wqRYAJ NqRA== X-Gm-Message-State: AOAM530bsFXMtcHUY0r9wHaqtccCum/il+UJ6pRiFm8vnPq7va098Z2s GsBHpaCnOGYifrfSlulYWnIIeLeA X-Google-Smtp-Source: ABdhPJzbzcmcqIbivC0PzlfVjI8xjxJjc2OkW0IAOhdzriPEBG5rAYBeHWv4eT71PMYeqZ2jz4oUOQ== X-Received: by 2002:a63:141:: with SMTP id 62mr41164616pgb.366.1594079287147; Mon, 06 Jul 2020 16:48:07 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:48:06 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 18/21] tests/tcg/xtensa: test double precision load/store Date: Mon, 6 Jul 2020 16:47:34 -0700 Message-Id: <20200706234737.32378-19-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=jcmvbkbc@gmail.com; helo=mail-pf1-x434.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Add ldi[p]/sdi[p]/ldx[p]/sdx[p] opcode tests to test_lsc. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_lsc.S | 123 ++++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/tests/tcg/xtensa/test_lsc.S b/tests/tcg/xtensa/test_lsc.S index 9d59c1815a9e..348822bdd359 100644 --- a/tests/tcg/xtensa/test_lsc.S +++ b/tests/tcg/xtensa/test_lsc.S @@ -140,4 +140,127 @@ test_end #endif +#if XCHAL_HAVE_DFP + +#if XCHAL_HAVE_BE +#define F64_HIGH_OFF 0 +#else +#define F64_HIGH_OFF 4 +#endif + +.macro movdf fr, hi, lo + movi a2, \hi + movi a3, \lo + wfrd \fr, a2, a3 +.endm + +test ldi + movi a2, 1 + wsr a2, cpenable + + movi a2, 1f + ldi f1, a2, 8 + ldi f2, a2, 16 + ldip f0, a2, 16 + movi a3, 1f + 16 + assert eq, a2, a3 + rfrd a2, f0 + movi a3, 0x3ff00000 + assert eq, a2, a3 + rfrd a2, f1 + movi a3, 0x40000000 + assert eq, a2, a3 + rfrd a2, f2 + movi a3, 0x40080000 + assert eq, a2, a3 +.data + .align 8 +1: +.double 1, 2, 3 +.text +test_end + +test sdi + movdf f3, 0x40800000, 0 + movdf f4, 0x40a00000, 0 + movdf f5, 0x40c00000, 0 + movi a2, 1f + sdi f4, a2, 8 + sdi f5, a2, 16 + sdip f3, a2, 16 + movi a3, 1f + 16 + assert eq, a2, a3 + l32i a4, a2, -16 + F64_HIGH_OFF + movi a3, 0x40800000 + assert eq, a4, a3 + l32i a4, a2, -8 + F64_HIGH_OFF + movi a3, 0x40a00000 + assert eq, a4, a3 + l32i a4, a2, F64_HIGH_OFF + movi a3, 0x40c00000 + assert eq, a4, a3 +.data + .align 8 +1: +.double 0, 0, 0 +.text +test_end + +test ldx + movi a2, 1f + movi a3, 0 + movi a4, 8 + movi a5, 16 + ldx f7, a2, a4 + ldx f8, a2, a5 + ldxp f6, a2, a5 + movi a3, 1f + 16 + assert eq, a2, a3 + rfrd a2, f6 + movi a3, 0x401c0000 + assert eq, a2, a3 + rfrd a2, f7 + movi a3, 0x40200000 + assert eq, a2, a3 + rfrd a2, f8 + movi a3, 0x40220000 + assert eq, a2, a3 +.data + .align 8 +1: +.double 7, 8, 9 +.text +test_end + +test sdx + movdf f9, 0x41200000, 0 + movdf f10, 0x41300000, 0 + movdf f11, 0x41400000, 0 + movi a2, 1f + movi a3, 0 + movi a4, 8 + movi a5, 16 + sdx f10, a2, a4 + sdx f11, a2, a5 + sdxp f9, a2, a5 + movi a3, 1f + 16 + assert eq, a2, a3 + l32i a4, a2, -16 + F64_HIGH_OFF + movi a3, 0x41200000 + assert eq, a4, a3 + l32i a4, a2, -8 + F64_HIGH_OFF + movi a3, 0x41300000 + assert eq, a4, a3 + l32i a4, a2, F64_HIGH_OFF + movi a3, 0x41400000 + assert eq, a4, a3 +.data + .align 8 +1: +.double 0, 0, 0 +.text +test_end + +#endif + test_suite_end From patchwork Mon Jul 6 23:47:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647233 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9FC7660D for ; Mon, 6 Jul 2020 23:59:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7499620823 for ; Mon, 6 Jul 2020 23:59:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gzr+AR+E" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7499620823 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:48110 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsb0r-0003FF-OQ for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 19:59:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaqJ-0001Rr-E1 for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:11 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:42807) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaqH-00011f-Et for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:11 -0400 Received: by mail-pg1-x535.google.com with SMTP id m22so8750101pgv.9 for ; Mon, 06 Jul 2020 16:48:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aTzwKyPqSVqduvxSFfgbpZf3K6u+1T0HA/N6+Yn1e6o=; b=gzr+AR+EUZUd85OwEPKTSWt/JiNl7dLzrG/C7c8uEtdEmp71ImxKpwEv3yVYz8yi8w ImiKfePdPApDH5DqLns8ESTHhQKUNfM818k9Y7YA3AcxKU6ctKqB44dS70k0xyI3+Kts pC265IjC3UPl++hu1Dm2/YdDl68jcABTEBPLBvtl3tK6PbtKKVAsx/9f/v9lxi/X/msv Hfpy1u521WHi+LiALABLcBmrNdrd7f6EAgmVKrqoyOCl8/uv2zpkyDhu/iJsMKTKnsLd OJshYgof+IRFnmoYDDFLVixJk/qFCubWACH8F0J1Zpu5GtYAc5qZtEGx9Baxms/3KdZq /43A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aTzwKyPqSVqduvxSFfgbpZf3K6u+1T0HA/N6+Yn1e6o=; b=XiaX6ICsts2+VIx3gRUk546fRpABPLG8LQ7EaUOGIE5tZfRyg3TxZIu8w7N2dXVpVf zyUZ0+MGhNbq0iFMc3yVmWB7I3D904uOQ6eLVL9A1g/N84vod9Aznsgo1V45xjiHEgAI SzjgcV5HyUsoV2wsYtUX5qnvgNFDo7aeiN71JJLDuN9HKgZapVN2lACEzcVd5e7Thhn7 UJCBm133UXFDZfSbWgRb0efsbuFWekrGyL60KWF4V5yhJOI891lGUPv3AxGcezRfXDpd jmKcP9xVW6ZYlxhsOjxi+2yw+biOTOhXUC1YC6UEZ42HzcN9j+fV2Vji7S7ErNtnLDfx GRkg== X-Gm-Message-State: AOAM532Jain08vZWb5RX3C+wMfD1jdFQ8iLhrnJOR+QE1mmv4wq39Q69 ZEX8TT+zWMk77/Su1vhw6J0SEaTr X-Google-Smtp-Source: ABdhPJyiVWuzJqCG8mf9foKP8D0PcwkzvVXiMVX+KkIS3tCbJKT3X57QP4dlTKkls4CWhLN50EjjPQ== X-Received: by 2002:aa7:94b0:: with SMTP id a16mr21815311pfl.86.1594079287909; Mon, 06 Jul 2020 16:48:07 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.48.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:48:07 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 19/21] tests/tcg/xtensa: add DFP0 arith tests Date: Mon, 6 Jul 2020 16:47:35 -0700 Message-Id: <20200706234737.32378-20-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=jcmvbkbc@gmail.com; helo=mail-pg1-x535.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Add test for basic double precision opcode properties. Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_dfp0_arith.S | 153 +++++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) create mode 100644 tests/tcg/xtensa/test_dfp0_arith.S diff --git a/tests/tcg/xtensa/test_dfp0_arith.S b/tests/tcg/xtensa/test_dfp0_arith.S new file mode 100644 index 000000000000..f2c72f97938d --- /dev/null +++ b/tests/tcg/xtensa/test_dfp0_arith.S @@ -0,0 +1,153 @@ +#include "macros.inc" +#include "fpu.h" + +test_suite fp0_arith + +#if XCHAL_HAVE_DFP + +.macro movfp fr, v + movi a2, ((\v) >> 32) & 0xffffffff + movi a3, ((\v) & 0xffffffff) + wfrd \fr, a2, a3 +.endm + +.macro check_res fr, r, sr + rfrd a2, \fr + dump a2 + movi a3, ((\r) >> 32) & 0xffffffff + assert eq, a2, a3 + rfr a2, \fr + dump a2 + movi a3, ((\r) & 0xffffffff) + assert eq, a2, a3 + rur a2, fsr + movi a3, \sr + assert eq, a2, a3 +.endm + +test add_d + movi a2, 1 + wsr a2, cpenable + + /* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */ + test_op2 add.d, f6, f7, f8, F64_MAX, F64_MAX, \ + F64_PINF, F64_MAX, F64_PINF, F64_MAX, \ + FSR_OI, FSR_OI, FSR_OI, FSR_OI +test_end + +test add_d_inf + /* 1 + +inf = +inf */ + test_op2 add.d, f6, f7, f8, F64_1, F64_PINF, \ + F64_PINF, F64_PINF, F64_PINF, F64_PINF, \ + FSR__, FSR__, FSR__, FSR__ + + /* +inf + -inf = default NaN */ + test_op2 add.d, f0, f1, f2, F64_PINF, F64_NINF, \ + F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end + +test add_d_nan_dfpu + /* 1 + QNaN = QNaN */ + test_op2 add.d, f9, f10, f11, F64_1, F64_QNAN(1), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + /* 1 + SNaN = QNaN */ + test_op2 add.d, f12, f13, f14, F64_1, F64_SNAN(1), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + + /* SNaN1 + SNaN2 = QNaN2 */ + test_op2 add.d, f15, f0, f1, F64_SNAN(1), F64_SNAN(2), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + /* QNaN1 + SNaN2 = QNaN2 */ + test_op2 add.d, f5, f6, f7, F64_QNAN(1), F64_SNAN(2), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + /* SNaN1 + QNaN2 = QNaN2 */ + test_op2 add.d, f8, f9, f10, F64_SNAN(1), F64_QNAN(2), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end + +test sub_s + /* norm - norm = denorm */ + test_op2 sub.d, f6, f7, f8, F64_MIN_NORM | 1, F64_MIN_NORM, \ + 0x00000001, 0x00000001, 0x00000001, 0x00000001, \ + FSR__, FSR__, FSR__, FSR__ +test_end + +test mul_s + test_op2 mul.d, f0, f1, f2, F64_1 | 1, F64_1 | 1, \ + F64_1 | 2, F64_1 | 2, F64_1 | 3, F64_1 | 2, \ + FSR_I, FSR_I, FSR_I, FSR_I + /* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */ + test_op2 mul.d, f6, f7, f8, F64_MAX_2, F64_MAX_2, \ + F64_PINF, F64_MAX, F64_PINF, F64_MAX, \ + FSR_OI, FSR_OI, FSR_OI, FSR_OI + /* min norm * min norm = 0/denorm */ + test_op2 mul.d, f6, f7, f8, F64_MIN_NORM, F64_MIN_NORM, \ + F64_0, F64_0, 0x00000001, F64_0, \ + FSR_UI, FSR_UI, FSR_UI, FSR_UI + /* inf * 0 = default NaN */ + test_op2 mul.d, f6, f7, f8, F64_PINF, F64_0, \ + F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end + +test madd_d + test_op3 madd.d, f0, f1, f2, f0, F64_0, F64_1 | 1, F64_1 | 1, \ + F64_1 | 2, F64_1 | 2, F64_1 | 3, F64_1 | 2, \ + FSR_I, FSR_I, FSR_I, FSR_I +test_end + +test madd_d_precision + test_op3 madd.d, f0, f1, f2, f0, \ + F64_MINUS | F64_1 | 2, F64_1 | 1, F64_1 | 1, \ + 0x3970000000000000, 0x3970000000000000, 0x3970000000000000, 0x3970000000000000, \ + FSR__, FSR__, FSR__, FSR__ +test_end + +test madd_d_nan_dfpu + /* DFPU madd/msub NaN1, NaN2, NaN3 priority: NaN1, NaN3, NaN2 */ + test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_1, F64_1, \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_QNAN(2), F64_1, \ + F64_QNAN(2), F64_QNAN(2), F64_QNAN(2), F64_QNAN(2), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_1, F64_QNAN(3), \ + F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), \ + FSR__, FSR__, FSR__, FSR__ + + test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_QNAN(2), F64_1, \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_1, F64_QNAN(3), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_QNAN(2), F64_QNAN(3), \ + F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), \ + FSR__, FSR__, FSR__, FSR__ + test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_QNAN(2), F64_QNAN(3), \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR__, FSR__, FSR__, FSR__ + + /* inf * 0 = default NaN */ + test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_PINF, F64_0, \ + F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \ + FSR_V, FSR_V, FSR_V, FSR_V + + /* madd/msub SNaN turns to QNaN and sets Invalid flag */ + test_op3 madd.d, f0, f1, f2, f0, F64_SNAN(1), F64_1, F64_1, \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V + test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_SNAN(2), F64_1, \ + F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \ + FSR_V, FSR_V, FSR_V, FSR_V +test_end + +#endif + +test_suite_end From patchwork Mon Jul 6 23:47:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647235 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3FF3092A for ; Tue, 7 Jul 2020 00:00:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5767920672 for ; Tue, 7 Jul 2020 00:00:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cwkXXUMu" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5767920672 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:50226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsb2Y-0004AH-Hr for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 20:00:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaqS-0001ph-66 for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:20 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:37133) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaqM-00012A-Ou for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:19 -0400 Received: by mail-pl1-x635.google.com with SMTP id p1so6697734pls.4 for ; Mon, 06 Jul 2020 16:48:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iZaTs0MbCnuwUZgeP+g4M5x5893c5O6tux7K1nhfmc4=; b=cwkXXUMuYEPUgAOISwWiGeKVcy81F5CQiqTxcSKoGFdZ5I/WwULPDtMwJyWHl9xck3 Amst8k1+qP54iHCqSBjeDe6xUTacOOe1hZt9ZzUMehZNzQjszabN2kDv7UjJbHVtE/nc QRoaQgR7hg2P5kzyE4+pfzmqL2+EsOuKbN5ut9BR/loUmYyuXlJO/5AV/9YT600dxqYs BgkQO8mokbRmTfiVM3yi5xhoSDW6cnTfi4Nq2Iob8qhzA5RuR3Dvm9W0pJTMmcHxcpdM xw9/Q1SBEKUp7s6IrL22hFiNbZT00G/ZkOjhYhwlb1EbPougZYbz6iS7FZ/M9w5+GvMp n0yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iZaTs0MbCnuwUZgeP+g4M5x5893c5O6tux7K1nhfmc4=; b=Leh+uh+DSKLQ10MCkq5a+ljYs8iNSd33EniI0jhbdZ2NUlshX5+nTjG4H3JXo9Ce5L rLPb732u6rDiDjS/XsjkhSCr7S/U2HrysFdMVN3PT8YSpX0lkccV7e0JnYEU4as9BCdF sDiCCT1K6XuspSNJ3PGVEZOUEOmc/EQWBF50EqW/HodHKCA/orI4cczwAnA6/xQr3VMX tZ+4S3JwOgr004c/8qWjmkBRBKf/G/re2Dc7BVAYLMsOobY7aqixI6VWwJQv5NiUI97l 4vKt9l5xTgwG4VDKFga5JsiUJ1FnE1mskDW2oMcU82zEznDTQhW1Xh5Z5Wuwb9NguvKS egKQ== X-Gm-Message-State: AOAM533xQNnAgbIJF2e2OmPMOxeSH1WqTAo5B2+A0uw1Lu6uI7KxN4wJ 6AgN3KnvAIOzQimri9abxx3JuP1v X-Google-Smtp-Source: ABdhPJyKnNTvEX0TkYW4zG+IogSc3Y2vmbVsJx/5MRyTgaC061QlqvaPhZAzwLYc+n9YzZ7NO4qIwg== X-Received: by 2002:a17:902:8641:: with SMTP id y1mr13335409plt.336.1594079290628; Mon, 06 Jul 2020 16:48:10 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.48.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:48:09 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 20/21] target/xtensa: import DE_233L_FPU core Date: Mon, 6 Jul 2020 16:47:36 -0700 Message-Id: <20200706234737.32378-21-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=jcmvbkbc@gmail.com; helo=mail-pl1-x635.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" DE_233L_FPU is a variant of 233L core with double precision FPU. Signed-off-by: Max Filippov --- target/xtensa/Makefile.objs | 1 + target/xtensa/core-DE_233L_FPU.c | 31 + target/xtensa/core-DE_233L_FPU/core-isa.h | 727 + target/xtensa/core-DE_233L_FPU/core-matmap.h | 717 + .../xtensa/core-DE_233L_FPU/gdb-config.inc.c | 277 + .../core-DE_233L_FPU/xtensa-modules.inc.c | 20758 ++++++++++++++++ 6 files changed, 22511 insertions(+) create mode 100644 target/xtensa/core-DE_233L_FPU.c create mode 100644 target/xtensa/core-DE_233L_FPU/core-isa.h create mode 100644 target/xtensa/core-DE_233L_FPU/core-matmap.h create mode 100644 target/xtensa/core-DE_233L_FPU/gdb-config.inc.c create mode 100644 target/xtensa/core-DE_233L_FPU/xtensa-modules.inc.c diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs index c7e7fe606384..e0a3d5e103e6 100644 --- a/target/xtensa/Makefile.objs +++ b/target/xtensa/Makefile.objs @@ -1,3 +1,4 @@ +obj-y += core-DE_233L_FPU.o obj-y += core-dc232b.o obj-y += core-dc233c.o obj-y += core-de212.o diff --git a/target/xtensa/core-DE_233L_FPU.c b/target/xtensa/core-DE_233L_FPU.c new file mode 100644 index 000000000000..482434302f9b --- /dev/null +++ b/target/xtensa/core-DE_233L_FPU.c @@ -0,0 +1,31 @@ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/gdbstub.h" +#include "qemu-common.h" +#include "qemu/host-utils.h" + +#include "core-DE_233L_FPU/core-isa.h" +#include "core-DE_233L_FPU/core-matmap.h" +#include "overlay_tool.h" + +#define xtensa_modules xtensa_modules_DE_233L_FPU +#include "core-DE_233L_FPU/xtensa-modules.inc.c" + +static XtensaConfig DE_233L_FPU __attribute__((unused)) = { + .name = "DE_233L_FPU", + .gdb_regmap = { + .reg = { +#include "core-DE_233L_FPU/gdb-config.inc.c" + } + }, + .isa_internal = &xtensa_modules, + .clock_freq_khz = 40000, + .opcode_translators = (const XtensaOpcodeTranslators *[]){ + &xtensa_core_opcodes, + &xtensa_fpu_opcodes, + NULL, + }, + DEFAULT_SECTIONS +}; + +REGISTER_CORE(DE_233L_FPU) diff --git a/target/xtensa/core-DE_233L_FPU/core-isa.h b/target/xtensa/core-DE_233L_FPU/core-isa.h new file mode 100644 index 000000000000..f125619e8de5 --- /dev/null +++ b/target/xtensa/core-DE_233L_FPU/core-isa.h @@ -0,0 +1,727 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Copyright (c) 1999-2020 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_CORE_CONFIGURATION_H_ +#define XTENSA_CORE_CONFIGURATION_H_ + +//depot/dev/Homewood/Xtensa/SWConfig/hal/core-common.h.tph#24 - edit change 444323 (text+ko) + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 1 /* MAC16 package */ +#define XCHAL_HAVE_LX 1 /* LX core */ +#define XCHAL_HAVE_NX 0 /* NX core (starting RH) */ + +#define XCHAL_HAVE_SUPERGATHER 0 /* SuperGather */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */ +#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */ +#define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 1 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 1 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 1 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 1 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 1 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 1 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ + +#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ +#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ +#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ +#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ +#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ +#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ + +#define XCHAL_HAVE_FUSIONJ 0 /* FusionJ */ +#define XCHAL_HAVE_FUSIONJ6 0 /* FusionJ6 */ +#define XCHAL_HAVE_FUSIONJ_SP_VFPU 0 /* sp_vfpu option on FusionJ */ +#define XCHAL_HAVE_FUSIONJ_DP_VFPU 0 /* dp_vfpu option on FusionJ */ +#define XCHAL_FUSIONJ_SIMD32 0 /* simd32 for FusionJ */ + +#define XCHAL_HAVE_PDX 0 /* PDX-LX */ +#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ +#define XCHAL_HAVE_PDX4 0 /* PDX4-LX */ +#define XCHAL_HAVE_PDX8 0 /* PDX8-LX */ +#define XCHAL_HAVE_PDX16 0 /* PDX16-LX */ +#define XCHAL_HAVE_PDXNX 0 /* PDX-NX */ + +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BALL 0 +#define XCHAL_HAVE_BALLAP 0 +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_CONNX_B10 0 /* ConnX B10 pkg*/ +#define XCHAL_HAVE_CONNX_B20 0 /* ConnX B20 pkg*/ +#define XCHAL_HAVE_CONNX_B_SP_VFPU 0 /* Single-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_SPX_VFPU 0 /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_HPX_VFPU 0 /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_32B_MAC 0 /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_VITERBI 0 /* Viterbi option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_TURBO 0 /* Turbo option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_LDPC 0 /* LDPC option on ConnX B10 & B20 */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ +#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ +#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, Q6 or Q7 */ +#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ +#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6/Q6/Q7 */ +#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0 /* sp_vfpu_2xfma option on Vision Q7 */ +#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6/Q6 */ +#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0 /* hp_vfpu_2xfma option on Vision Q7 */ + +#define XCHAL_HAVE_VISIONC 0 /* Vision C */ + +#define XCHAL_HAVE_XNNE 0 /* XNNE */ + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ + +#define XCHAL_UNIFIED_LOADSTORE 0 + +#define XCHAL_SW_VERSION 1403000 /* sw version of this header */ +#define XCHAL_SW_VERSION_MAJOR 14000 /* major ver# of sw */ +#define XCHAL_SW_VERSION_MINOR 3 /* minor ver# of sw */ +#define XCHAL_SW_VERSION_MICRO 0 /* micro ver# of sw */ +#define XCHAL_SW_MINOR_VERSION 1403000 /* with zeroed micro */ +#define XCHAL_SW_MICRO_VERSION 1403000 + +#define XCHAL_CORE_ID "DE_233L_FPU" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x000872E0 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC1039286 /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x28C872E0 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX7.1.3" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2810 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION_MICRO 0 /* subdot ver# of targeted hw */ +#define XCHAL_HW_VERSION 281030 /* major*100+(major<2810 ? minor : minor*10+micro) */ +#define XCHAL_HW_REL_LX7 1 +#define XCHAL_HW_REL_LX7_1 1 +#define XCHAL_HW_REL_LX7_1_3 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2810 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MICRO 0 /* micro v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 281030 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2810 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MICRO 0 /* micro v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 281030 /* latest targeted hw */ + +/* Config is enabled for functional safety: */ +#define XCHAL_HAVE_FUNC_SAFETY 0 + +#define XCHAL_HAVE_APB 0 + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ +#define XCHAL_ICACHE_SIZE_LOG2 14 +#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE_LOG2 14 + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 cache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_CME_DOWNGRADES 0 +#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ +#define XCHAL_HAVE_ICACHE_DYN_ENABLE 0 /* Icache enabled via MEMCTL */ +#define XCHAL_HAVE_DCACHE_DYN_ENABLE 0 /* Dcache enabled via MEMCTL */ + +#define XCHAL_L1SCACHE_SIZE 0 +#define XCHAL_L1SCACHE_SIZE_LOG2 0 +#define XCHAL_L1SCACHE_WAYS 1 +#define XCHAL_L1SCACHE_WAYS_LOG2 0 +#define XCHAL_L1SCACHE_ACCESS_SIZE 0 +#define XCHAL_L1SCACHE_BANKS 1 + +#define XCHAL_HAVE_L2 0 /* NX L2 cache controller */ + +/* Number of cores in cluster */ +#if XCHAL_HAVE_L2 +#define XCHAL_NUM_CORES_IN_CLUSTER XCHAL_L2CC_NUM_CORES_LOG2 +#else +#define XCHAL_NUM_CORES_IN_CLUSTER 0 +#endif + +/* PRID_ID macros are for internal use only ... subject to removal */ +#define PRID_ID_SHIFT 0 +#define PRID_ID_BITS 4 +#define PRID_ID_MASK 0x0000000F + +/* This one is a form of caching, though not architecturally visible: */ +#define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ + +#define XCHAL_HAVE_AXI 0 /* AXI bus */ +#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ +#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 7 +#define XCHAL_DCACHE_SETWIDTH 7 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_ICACHE_WAYS_LOG2 2 +#define XCHAL_DCACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS_LOG2 2 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 +#define XCHAL_ICACHE_ECC_WIDTH 4 +#define XCHAL_DCACHE_ECC_WIDTH 1 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 4 +#define XCHAL_DCACHE_ACCESS_SIZE 8 + +#define XCHAL_DCACHE_BANKS 1 /* number of banks */ + +/* The number of Cache lines associated with a single cache tag */ +#define XCHAL_DCACHE_LINES_PER_TAG_LOG2 0 + +/* Number of encoded cache attr bits (see for decoded bits): */ +#define XCHAL_CA_BITS 4 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ +#define XCHAL_HAVE_IRAMCFG 0 /* IRAMxCFG register present */ +#define XCHAL_HAVE_DRAMCFG 0 /* DRAMxCFG register present */ + + +#define XCHAL_HAVE_IDMA 0 + + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels + (not including level zero) */ + + +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x001F80FF +#define XCHAL_INTLEVEL2_MASK 0x00000100 +#define XCHAL_INTLEVEL3_MASK 0x00200E00 +#define XCHAL_INTLEVEL4_MASK 0x00001000 +#define XCHAL_INTLEVEL5_MASK 0x00002000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00004000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 3 +#define XCHAL_INT10_LEVEL 3 +#define XCHAL_INT11_LEVEL 3 +#define XCHAL_INT12_LEVEL 4 +#define XCHAL_INT13_LEVEL 5 +#define XCHAL_INT14_LEVEL 7 +#define XCHAL_INT15_LEVEL 1 +#define XCHAL_INT16_LEVEL 1 +#define XCHAL_INT17_LEVEL 1 +#define XCHAL_INT18_LEVEL 1 +#define XCHAL_INT19_LEVEL 1 +#define XCHAL_INT20_LEVEL 1 +#define XCHAL_INT21_LEVEL 3 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 +#define XCHAL_INTTYPE_MASK_TIMER 0x00002440 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XCHAL_INTTYPE_MASK_DBG_REQUEST 0x00000000 +#define XCHAL_INTTYPE_MASK_BREAKIN 0x00000000 +#define XCHAL_INTTYPE_MASK_TRAX 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 +#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 +#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_STATUS 0x00000000 +#define XCHAL_INTTYPE_MASK_COR_ECC_ERR 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL2_NUM 8 +#define XCHAL_INTLEVEL4_NUM 12 +#define XCHAL_INTLEVEL5_NUM 13 +#define XCHAL_INTLEVEL7_NUM 14 +/* (There are many interrupts each at level(s) 1, 3.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ +#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ +#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ +#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */ +#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */ +#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */ +#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */ +#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */ +#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */ +#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ +#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ +#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */ +#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */ +#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */ + +#define XCHAL_HAVE_ISB 0 /* No ISB */ +#define XCHAL_ISB_VADDR 0 /* N/A */ +#define XCHAL_HAVE_ITB 0 /* No ITB */ +#define XCHAL_ITB_VADDR 0 /* N/A */ + +#define XCHAL_HAVE_KSL 0 /* Kernel Stack Limit */ +#define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */ +#define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (until T1050) + 2 == XEA2 (T1040 onwards) + 3 == XEA3 (LX8/NX/SX onwards) + 0 == XEAX (extern) or TX */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEA3 0 /* Exception Architecture 3 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS 0 /* imprecise exception option */ +#define XCHAL_EXCCAUSE_NUM 64 /* Number of exceptions */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x00002000 +#define XCHAL_RESET_VECBASE_OVERLAP 0 /* UNUSED */ + +#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 +#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x00001000 +#define XCHAL_RESET_VECTOR1_PADDR 0x00001000 +#define XCHAL_RESET_VECTOR_VADDR XCHAL_RESET_VECTOR0_VADDR +#define XCHAL_RESET_VECTOR_PADDR XCHAL_RESET_VECTOR0_PADDR +#define XCHAL_USER_VECOFS 0x00000340 +#define XCHAL_USER_VECTOR_VADDR 0x00002340 +#define XCHAL_USER_VECTOR_PADDR 0x00002340 +#define XCHAL_KERNEL_VECOFS 0x00000300 +#define XCHAL_KERNEL_VECTOR_VADDR 0x00002300 +#define XCHAL_KERNEL_VECTOR_PADDR 0x00002300 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x00002000 +#define XCHAL_WINDOW_VECTORS_PADDR 0x00002000 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240 +#define XCHAL_INTLEVEL6_VECOFS 0x00000280 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000002C0 +#define XCHAL_NMI_VECTOR_VADDR 0x000022C0 +#define XCHAL_NMI_VECTOR_PADDR 0x000022C0 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ + +/* If none of the above last 5 are set, it's a custom TLB configuration. */ +#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ +#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ + +#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ + +/*---------------------------------------------------------------------- + MPU + ----------------------------------------------------------------------*/ +#define XCHAL_HAVE_MPU 0 +#define XCHAL_MPU_ENTRIES 0 + +#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ +#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ +#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ + +#define XCHAL_MPU_ALIGN_BITS 0 +#define XCHAL_MPU_ALIGN 0 + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* XTENSA_CORE_CONFIGURATION_H_ */ + diff --git a/target/xtensa/core-DE_233L_FPU/core-matmap.h b/target/xtensa/core-DE_233L_FPU/core-matmap.h new file mode 100644 index 000000000000..cca51c7af1b5 --- /dev/null +++ b/target/xtensa/core-DE_233L_FPU/core-matmap.h @@ -0,0 +1,717 @@ +/* + * xtensa/config/core-matmap.h -- Memory access and translation mapping + * parameters (CHAL) of the Xtensa processor core configuration. + * + * If you are using Xtensa Tools, see (which includes + * this file) for more details. + * + * In the Xtensa processor products released to date, all parameters + * defined in this file are derivable (at least in theory) from + * information contained in the core-isa.h header file. + * In particular, the following core configuration parameters are relevant: + * XCHAL_HAVE_CACHEATTR + * XCHAL_HAVE_MIMIC_CACHEATTR + * XCHAL_HAVE_XLT_CACHEATTR + * XCHAL_HAVE_PTP_MMU + * XCHAL_ITLB_ARF_ENTRIES_LOG2 + * XCHAL_DTLB_ARF_ENTRIES_LOG2 + * XCHAL_DCACHE_IS_WRITEBACK + * XCHAL_ICACHE_SIZE (presence of I-cache) + * XCHAL_DCACHE_SIZE (presence of D-cache) + * XCHAL_HW_VERSION_MAJOR + * XCHAL_HW_VERSION_MINOR + */ + +/* Copyright (c) 1999-2020 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#ifndef XTENSA_CONFIG_CORE_MATMAP_H +#define XTENSA_CONFIG_CORE_MATMAP_H + + +/*---------------------------------------------------------------------- + CACHE (MEMORY ACCESS) ATTRIBUTES + ----------------------------------------------------------------------*/ + + + +/* Cache Attribute encodings -- lists of access modes for each cache attribute: */ +#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION +#define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION +#define XCHAL_SCA_LIST XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_WRITEBACK XCHAL_SEP \ + XTHAL_SAM_WRITEBACK XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_WRITETHRU XCHAL_SEP \ + XTHAL_SAM_WRITETHRU XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION + +#define XCHAL_CA_R (0xC0 | 0x40000000) +#define XCHAL_CA_RX (0xD0 | 0x40000000) +#define XCHAL_CA_RW (0xE0 | 0x40000000) +#define XCHAL_CA_RWX (0xF0 | 0x40000000) + +/* + * Specific encoded cache attribute values of general interest. + * If a specific cache mode is not available, the closest available + * one is returned instead (eg. writethru instead of writeback, + * bypass instead of writethru). + */ +#define XCHAL_CA_BYPASS 3 /* cache disabled (bypassed) mode */ +#define XCHAL_CA_WRITETHRU 11 /* cache enabled (write-through) mode */ +#define XCHAL_CA_WRITEBACK 7 /* cache enabled (write-back) mode */ +#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */ +#define XCHAL_CA_WRITEBACK_NOALLOC 7 /* cache enabled (write-back no-allocate) mode */ +#define XCHAL_CA_BYPASS_RX 1 /* cache disabled (bypassed) mode (no write) */ +#define XCHAL_CA_WRITETHRU_RX 9 /* cache enabled (write-through) mode (no write) */ +#define XCHAL_CA_WRITEBACK_RX 5 /* cache enabled (write-back) mode (no write) */ +#define XCHAL_CA_WRITEBACK_NOALLOC_RX 5 /* cache enabled (write-back no-allocate) mode (no write) */ +#define XCHAL_CA_BYPASS_RW 2 /* cache disabled (bypassed) mode (no exec) */ +#define XCHAL_CA_WRITETHRU_RW 10 /* cache enabled (write-through) mode (no exec) */ +#define XCHAL_CA_WRITEBACK_RW 6 /* cache enabled (write-back) mode (no exec) */ +#define XCHAL_CA_WRITEBACK_NOALLOC_RW 6 /* cache enabled (write-back no-allocate) mode (no exec) */ +#define XCHAL_CA_BYPASS_R 0 /* cache disabled (bypassed) mode (no exec, no write) */ +#define XCHAL_CA_WRITETHRU_R 8 /* cache enabled (write-through) mode (no exec, no write) */ +#define XCHAL_CA_WRITEBACK_R 4 /* cache enabled (write-back) mode (no exec, no write) */ +#define XCHAL_CA_WRITEBACK_NOALLOC_R 4 /* cache enabled (write-back no-allocate) mode (no exec, no write) */ +#define XCHAL_CA_ILLEGAL 12 /* no access allowed (all cause exceptions) mode */ + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* + * General notes on MMU parameters. + * + * Terminology: + * ASID = address-space ID (acts as an "extension" of virtual addresses) + * VPN = virtual page number + * PPN = physical page number + * CA = encoded cache attribute (access modes) + * TLB = translation look-aside buffer (term is stretched somewhat here) + * I = instruction (fetch accesses) + * D = data (load and store accesses) + * way = each TLB (ITLB and DTLB) consists of a number of "ways" + * that simultaneously match the virtual address of an access; + * a TLB successfully translates a virtual address if exactly + * one way matches the vaddr; if none match, it is a miss; + * if multiple match, one gets a "multihit" exception; + * each way can be independently configured in terms of number of + * entries, page sizes, which fields are writable or constant, etc. + * set = group of contiguous ways with exactly identical parameters + * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE + * from the page table and storing it in one of the auto-refill ways; + * if this PTE load also misses, a miss exception is posted for s/w. + * min-wired = a "min-wired" way can be used to map a single (minimum-sized) + * page arbitrarily under program control; it has a single entry, + * is non-auto-refill (some other way(s) must be auto-refill), + * all its fields (VPN, PPN, ASID, CA) are all writable, and it + * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current + * restriction is that this be the only page size it supports). + * + * TLB way entries are virtually indexed. + * TLB ways that support multiple page sizes: + * - must have all writable VPN and PPN fields; + * - can only use one page size at any given time (eg. setup at startup), + * selected by the respective ITLBCFG or DTLBCFG special register, + * whose bits n*4+3 .. n*4 index the list of page sizes for way n + * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); + * this list may be sparse for auto-refill ways because auto-refill + * ways have independent lists of supported page sizes sharing a + * common encoding with PTE entries; the encoding is the index into + * this list; unsupported sizes for a given way are zero in the list; + * selecting unsupported sizes results in undefine hardware behaviour; + * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). + */ + +#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ +#define XCHAL_MMU_ASID_KERNEL 1 /* ASID value indicating kernel (ring 0) address space */ +#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ +#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ +#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure (log2) */ +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure (log2) */ + + +/*** Instruction TLB: ***/ + +#define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */ +#define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */ +#define XCHAL_ITLB_SETS 7 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_ITLB_WAY0_SET 0 +#define XCHAL_ITLB_WAY1_SET 1 +#define XCHAL_ITLB_WAY2_SET 2 +#define XCHAL_ITLB_WAY3_SET 3 +#define XCHAL_ITLB_WAY4_SET 4 +#define XCHAL_ITLB_WAY5_SET 5 +#define XCHAL_ITLB_WAY6_SET 6 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_ITLB_ARF_SETS 4 /* number of auto-refill sets */ +#define XCHAL_ITLB_ARF_SET0 0 /* index of n'th auto-refill set */ +#define XCHAL_ITLB_ARF_SET1 1 /* index of n'th auto-refill set */ +#define XCHAL_ITLB_ARF_SET2 2 /* index of n'th auto-refill set */ +#define XCHAL_ITLB_ARF_SET3 3 /* index of n'th auto-refill set */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ + + +/* ITLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_ITLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ +#define XCHAL_ITLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */ +#define XCHAL_ITLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ + +/* ITLB way set 1 (group of ways 1 thru 1): */ +#define XCHAL_ITLB_SET1_WAY 1 /* index of first way in this way set */ +#define XCHAL_ITLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_ITLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ +#define XCHAL_ITLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */ +#define XCHAL_ITLB_SET1_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_ITLB_SET1_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_ITLB_SET1_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ +#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ +#define XCHAL_ITLB_SET1_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_ITLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_ITLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_ITLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ + +/* ITLB way set 2 (group of ways 2 thru 2): */ +#define XCHAL_ITLB_SET2_WAY 2 /* index of first way in this way set */ +#define XCHAL_ITLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_ITLB_SET2_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ +#define XCHAL_ITLB_SET2_ENTRIES 4 /* number of entries in this way (always a power of 2) */ +#define XCHAL_ITLB_SET2_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_ITLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_ITLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ +#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ +#define XCHAL_ITLB_SET2_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_ITLB_SET2_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_ITLB_SET2_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET2_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET2_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_ITLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ + +/* ITLB way set 3 (group of ways 3 thru 3): */ +#define XCHAL_ITLB_SET3_WAY 3 /* index of first way in this way set */ +#define XCHAL_ITLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_ITLB_SET3_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ +#define XCHAL_ITLB_SET3_ENTRIES 4 /* number of entries in this way (always a power of 2) */ +#define XCHAL_ITLB_SET3_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_ITLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_ITLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ +#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ +#define XCHAL_ITLB_SET3_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_ITLB_SET3_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_ITLB_SET3_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET3_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET3_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_ITLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ + +/* ITLB way set 4 (group of ways 4 thru 4): */ +#define XCHAL_ITLB_SET4_WAY 4 /* index of first way in this way set */ +#define XCHAL_ITLB_SET4_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_ITLB_SET4_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ +#define XCHAL_ITLB_SET4_ENTRIES 4 /* number of entries in this way (always a power of 2) */ +#define XCHAL_ITLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_ITLB_SET4_PAGESIZES 4 /* number of supported page sizes in this way */ +#define XCHAL_ITLB_SET4_PAGESZ_BITS 2 /* number of bits to encode the page size */ +#define XCHAL_ITLB_SET4_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */ +#define XCHAL_ITLB_SET4_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */ +#define XCHAL_ITLB_SET4_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_ITLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_ITLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_ITLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ + +/* ITLB way set 5 (group of ways 5 thru 5): */ +#define XCHAL_ITLB_SET5_WAY 5 /* index of first way in this way set */ +#define XCHAL_ITLB_SET5_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_ITLB_SET5_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ +#define XCHAL_ITLB_SET5_ENTRIES 4 /* number of entries in this way (always a power of 2) */ +#define XCHAL_ITLB_SET5_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_ITLB_SET5_PAGESIZES 2 /* number of supported page sizes in this way */ +#define XCHAL_ITLB_SET5_PAGESZ_BITS 1 /* number of bits to encode the page size */ +#define XCHAL_ITLB_SET5_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */ +#define XCHAL_ITLB_SET5_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */ +#define XCHAL_ITLB_SET5_PAGESZ_LOG2_LIST 27 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_ITLB_SET5_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_ITLB_SET5_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET5_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET5_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_ITLB_SET5_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET5_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET5_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET5_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Reset ASID values for each entry of ITLB way set 5 (because SET5_ASID_RESET is non-zero): */ +#define XCHAL_ITLB_SET5_E0_ASID_RESET 0x00 +#define XCHAL_ITLB_SET5_E1_ASID_RESET 0x00 +#define XCHAL_ITLB_SET5_E2_ASID_RESET 0x00 +#define XCHAL_ITLB_SET5_E3_ASID_RESET 0x00 +/* Reset VPN values for each entry of ITLB way set 5 (because SET5_VPN_RESET is non-zero): */ +#define XCHAL_ITLB_SET5_E0_VPN_RESET 0x00000000 +#define XCHAL_ITLB_SET5_E1_VPN_RESET 0x00000000 +#define XCHAL_ITLB_SET5_E2_VPN_RESET 0x00000000 +#define XCHAL_ITLB_SET5_E3_VPN_RESET 0x00000000 +/* Reset PPN values for each entry of ITLB way set 5 (because SET5_PPN_RESET is non-zero): */ +#define XCHAL_ITLB_SET5_E0_PPN_RESET 0x00000000 +#define XCHAL_ITLB_SET5_E1_PPN_RESET 0x00000000 +#define XCHAL_ITLB_SET5_E2_PPN_RESET 0x00000000 +#define XCHAL_ITLB_SET5_E3_PPN_RESET 0x00000000 + +/* ITLB way set 6 (group of ways 6 thru 6): */ +#define XCHAL_ITLB_SET6_WAY 6 /* index of first way in this way set */ +#define XCHAL_ITLB_SET6_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_ITLB_SET6_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_ITLB_SET6_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_ITLB_SET6_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_ITLB_SET6_PAGESIZES 2 /* number of supported page sizes in this way */ +#define XCHAL_ITLB_SET6_PAGESZ_BITS 1 /* number of bits to encode the page size */ +#define XCHAL_ITLB_SET6_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */ +#define XCHAL_ITLB_SET6_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_ITLB_SET6_PAGESZ_LOG2_LIST 29 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_ITLB_SET6_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_ITLB_SET6_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET6_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET6_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_ITLB_SET6_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET6_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET6_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET6_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Reset ASID values for each entry of ITLB way set 6 (because SET6_ASID_RESET is non-zero): */ +#define XCHAL_ITLB_SET6_E0_ASID_RESET 0x01 +#define XCHAL_ITLB_SET6_E1_ASID_RESET 0x01 +#define XCHAL_ITLB_SET6_E2_ASID_RESET 0x01 +#define XCHAL_ITLB_SET6_E3_ASID_RESET 0x01 +#define XCHAL_ITLB_SET6_E4_ASID_RESET 0x01 +#define XCHAL_ITLB_SET6_E5_ASID_RESET 0x01 +#define XCHAL_ITLB_SET6_E6_ASID_RESET 0x01 +#define XCHAL_ITLB_SET6_E7_ASID_RESET 0x01 +/* Reset VPN values for each entry of ITLB way set 6 (because SET6_VPN_RESET is non-zero): */ +#define XCHAL_ITLB_SET6_E0_VPN_RESET 0x00000000 +#define XCHAL_ITLB_SET6_E1_VPN_RESET 0x20000000 +#define XCHAL_ITLB_SET6_E2_VPN_RESET 0x40000000 +#define XCHAL_ITLB_SET6_E3_VPN_RESET 0x60000000 +#define XCHAL_ITLB_SET6_E4_VPN_RESET 0x80000000 +#define XCHAL_ITLB_SET6_E5_VPN_RESET 0xA0000000 +#define XCHAL_ITLB_SET6_E6_VPN_RESET 0xC0000000 +#define XCHAL_ITLB_SET6_E7_VPN_RESET 0xE0000000 +/* Reset PPN values for each entry of ITLB way set 6 (because SET6_PPN_RESET is non-zero): */ +#define XCHAL_ITLB_SET6_E0_PPN_RESET 0x00000000 +#define XCHAL_ITLB_SET6_E1_PPN_RESET 0x20000000 +#define XCHAL_ITLB_SET6_E2_PPN_RESET 0x40000000 +#define XCHAL_ITLB_SET6_E3_PPN_RESET 0x60000000 +#define XCHAL_ITLB_SET6_E4_PPN_RESET 0x80000000 +#define XCHAL_ITLB_SET6_E5_PPN_RESET 0xA0000000 +#define XCHAL_ITLB_SET6_E6_PPN_RESET 0xC0000000 +#define XCHAL_ITLB_SET6_E7_PPN_RESET 0xE0000000 +/* Reset CA values for each entry of ITLB way set 6 (because SET6_CA_RESET is non-zero): */ +#define XCHAL_ITLB_SET6_E0_CA_RESET 0x03 +#define XCHAL_ITLB_SET6_E1_CA_RESET 0x03 +#define XCHAL_ITLB_SET6_E2_CA_RESET 0x03 +#define XCHAL_ITLB_SET6_E3_CA_RESET 0x03 +#define XCHAL_ITLB_SET6_E4_CA_RESET 0x03 +#define XCHAL_ITLB_SET6_E5_CA_RESET 0x03 +#define XCHAL_ITLB_SET6_E6_CA_RESET 0x03 +#define XCHAL_ITLB_SET6_E7_CA_RESET 0x03 + + +/*** Data TLB: ***/ + +#define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */ +#define XCHAL_DTLB_WAYS 10 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */ +#define XCHAL_DTLB_SETS 10 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_DTLB_WAY0_SET 0 +#define XCHAL_DTLB_WAY1_SET 1 +#define XCHAL_DTLB_WAY2_SET 2 +#define XCHAL_DTLB_WAY3_SET 3 +#define XCHAL_DTLB_WAY4_SET 4 +#define XCHAL_DTLB_WAY5_SET 5 +#define XCHAL_DTLB_WAY6_SET 6 +#define XCHAL_DTLB_WAY7_SET 7 +#define XCHAL_DTLB_WAY8_SET 8 +#define XCHAL_DTLB_WAY9_SET 9 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_DTLB_ARF_SETS 4 /* number of auto-refill sets */ +#define XCHAL_DTLB_ARF_SET0 0 /* index of n'th auto-refill set */ +#define XCHAL_DTLB_ARF_SET1 1 /* index of n'th auto-refill set */ +#define XCHAL_DTLB_ARF_SET2 2 /* index of n'th auto-refill set */ +#define XCHAL_DTLB_ARF_SET3 3 /* index of n'th auto-refill set */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_DTLB_MINWIRED_SETS 3 /* number of "min-wired" sets */ +#define XCHAL_DTLB_MINWIRED_SET0 7 /* index of n'th "min-wired" set */ +#define XCHAL_DTLB_MINWIRED_SET1 8 /* index of n'th "min-wired" set */ +#define XCHAL_DTLB_MINWIRED_SET2 9 /* index of n'th "min-wired" set */ + + +/* DTLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ + +/* DTLB way set 1 (group of ways 1 thru 1): */ +#define XCHAL_DTLB_SET1_WAY 1 /* index of first way in this way set */ +#define XCHAL_DTLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET1_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET1_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET1_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET1_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ + +/* DTLB way set 2 (group of ways 2 thru 2): */ +#define XCHAL_DTLB_SET2_WAY 2 /* index of first way in this way set */ +#define XCHAL_DTLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET2_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET2_ENTRIES 4 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET2_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET2_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET2_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET2_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET2_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET2_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ + +/* DTLB way set 3 (group of ways 3 thru 3): */ +#define XCHAL_DTLB_SET3_WAY 3 /* index of first way in this way set */ +#define XCHAL_DTLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET3_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET3_ENTRIES 4 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET3_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET3_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET3_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET3_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET3_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET3_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ + +/* DTLB way set 4 (group of ways 4 thru 4): */ +#define XCHAL_DTLB_SET4_WAY 4 /* index of first way in this way set */ +#define XCHAL_DTLB_SET4_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET4_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET4_ENTRIES 4 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET4_PAGESIZES 4 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET4_PAGESZ_BITS 2 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET4_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ + +/* DTLB way set 5 (group of ways 5 thru 5): */ +#define XCHAL_DTLB_SET5_WAY 5 /* index of first way in this way set */ +#define XCHAL_DTLB_SET5_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET5_ENTRIES_LOG2 2 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET5_ENTRIES 4 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET5_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET5_PAGESIZES 2 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET5_PAGESZ_BITS 1 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET5_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET5_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET5_PAGESZ_LOG2_LIST 27 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET5_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET5_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET5_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET5_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET5_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET5_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET5_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET5_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Reset ASID values for each entry of DTLB way set 5 (because SET5_ASID_RESET is non-zero): */ +#define XCHAL_DTLB_SET5_E0_ASID_RESET 0x00 +#define XCHAL_DTLB_SET5_E1_ASID_RESET 0x00 +#define XCHAL_DTLB_SET5_E2_ASID_RESET 0x00 +#define XCHAL_DTLB_SET5_E3_ASID_RESET 0x00 +/* Reset VPN values for each entry of DTLB way set 5 (because SET5_VPN_RESET is non-zero): */ +#define XCHAL_DTLB_SET5_E0_VPN_RESET 0x00000000 +#define XCHAL_DTLB_SET5_E1_VPN_RESET 0x00000000 +#define XCHAL_DTLB_SET5_E2_VPN_RESET 0x00000000 +#define XCHAL_DTLB_SET5_E3_VPN_RESET 0x00000000 +/* Reset PPN values for each entry of DTLB way set 5 (because SET5_PPN_RESET is non-zero): */ +#define XCHAL_DTLB_SET5_E0_PPN_RESET 0x00000000 +#define XCHAL_DTLB_SET5_E1_PPN_RESET 0x00000000 +#define XCHAL_DTLB_SET5_E2_PPN_RESET 0x00000000 +#define XCHAL_DTLB_SET5_E3_PPN_RESET 0x00000000 + +/* DTLB way set 6 (group of ways 6 thru 6): */ +#define XCHAL_DTLB_SET6_WAY 6 /* index of first way in this way set */ +#define XCHAL_DTLB_SET6_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET6_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET6_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET6_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET6_PAGESIZES 2 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET6_PAGESZ_BITS 1 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET6_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET6_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET6_PAGESZ_LOG2_LIST 29 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET6_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET6_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET6_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET6_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET6_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET6_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET6_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET6_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Reset ASID values for each entry of DTLB way set 6 (because SET6_ASID_RESET is non-zero): */ +#define XCHAL_DTLB_SET6_E0_ASID_RESET 0x01 +#define XCHAL_DTLB_SET6_E1_ASID_RESET 0x01 +#define XCHAL_DTLB_SET6_E2_ASID_RESET 0x01 +#define XCHAL_DTLB_SET6_E3_ASID_RESET 0x01 +#define XCHAL_DTLB_SET6_E4_ASID_RESET 0x01 +#define XCHAL_DTLB_SET6_E5_ASID_RESET 0x01 +#define XCHAL_DTLB_SET6_E6_ASID_RESET 0x01 +#define XCHAL_DTLB_SET6_E7_ASID_RESET 0x01 +/* Reset VPN values for each entry of DTLB way set 6 (because SET6_VPN_RESET is non-zero): */ +#define XCHAL_DTLB_SET6_E0_VPN_RESET 0x00000000 +#define XCHAL_DTLB_SET6_E1_VPN_RESET 0x20000000 +#define XCHAL_DTLB_SET6_E2_VPN_RESET 0x40000000 +#define XCHAL_DTLB_SET6_E3_VPN_RESET 0x60000000 +#define XCHAL_DTLB_SET6_E4_VPN_RESET 0x80000000 +#define XCHAL_DTLB_SET6_E5_VPN_RESET 0xA0000000 +#define XCHAL_DTLB_SET6_E6_VPN_RESET 0xC0000000 +#define XCHAL_DTLB_SET6_E7_VPN_RESET 0xE0000000 +/* Reset PPN values for each entry of DTLB way set 6 (because SET6_PPN_RESET is non-zero): */ +#define XCHAL_DTLB_SET6_E0_PPN_RESET 0x00000000 +#define XCHAL_DTLB_SET6_E1_PPN_RESET 0x20000000 +#define XCHAL_DTLB_SET6_E2_PPN_RESET 0x40000000 +#define XCHAL_DTLB_SET6_E3_PPN_RESET 0x60000000 +#define XCHAL_DTLB_SET6_E4_PPN_RESET 0x80000000 +#define XCHAL_DTLB_SET6_E5_PPN_RESET 0xA0000000 +#define XCHAL_DTLB_SET6_E6_PPN_RESET 0xC0000000 +#define XCHAL_DTLB_SET6_E7_PPN_RESET 0xE0000000 +/* Reset CA values for each entry of DTLB way set 6 (because SET6_CA_RESET is non-zero): */ +#define XCHAL_DTLB_SET6_E0_CA_RESET 0x03 +#define XCHAL_DTLB_SET6_E1_CA_RESET 0x03 +#define XCHAL_DTLB_SET6_E2_CA_RESET 0x03 +#define XCHAL_DTLB_SET6_E3_CA_RESET 0x03 +#define XCHAL_DTLB_SET6_E4_CA_RESET 0x03 +#define XCHAL_DTLB_SET6_E5_CA_RESET 0x03 +#define XCHAL_DTLB_SET6_E6_CA_RESET 0x03 +#define XCHAL_DTLB_SET6_E7_CA_RESET 0x03 + +/* DTLB way set 7 (group of ways 7 thru 7): */ +#define XCHAL_DTLB_SET7_WAY 7 /* index of first way in this way set */ +#define XCHAL_DTLB_SET7_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET7_ENTRIES_LOG2 0 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET7_ENTRIES 1 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET7_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET7_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET7_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET7_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET7_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET7_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET7_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET7_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET7_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET7_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET7_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET7_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET7_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET7_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ + +/* DTLB way set 8 (group of ways 8 thru 8): */ +#define XCHAL_DTLB_SET8_WAY 8 /* index of first way in this way set */ +#define XCHAL_DTLB_SET8_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET8_ENTRIES_LOG2 0 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET8_ENTRIES 1 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET8_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET8_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET8_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET8_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET8_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET8_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET8_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET8_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET8_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET8_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET8_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET8_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET8_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET8_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ + +/* DTLB way set 9 (group of ways 9 thru 9): */ +#define XCHAL_DTLB_SET9_WAY 9 /* index of first way in this way set */ +#define XCHAL_DTLB_SET9_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET9_ENTRIES_LOG2 0 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET9_ENTRIES 1 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET9_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET9_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET9_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET9_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET9_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET9_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET9_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET9_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET9_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET9_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET9_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET9_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET9_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET9_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */ + + + + +#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ + diff --git a/target/xtensa/core-DE_233L_FPU/gdb-config.inc.c b/target/xtensa/core-DE_233L_FPU/gdb-config.inc.c new file mode 100644 index 000000000000..66fcb4894a7c --- /dev/null +++ b/target/xtensa/core-DE_233L_FPU/gdb-config.inc.c @@ -0,0 +1,277 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Copyright (c) 2003-2020 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0) + XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) + XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) + XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) + XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) + XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) + XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) + XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) + XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) + XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) + XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) + XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) + XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) + XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) + XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) + XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) + XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) + XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) + XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) + XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) + XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) + XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) + XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) + XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) + XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) + XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) + XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) + XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) + XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) + XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) + XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) + XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) + XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) + XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) + XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) + XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) + XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) + XTREG( 37,148, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) + XTREG( 38,152, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) + XTREG( 39,156,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0) + XTREG( 40,160,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0) + XTREG( 41,164,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) + XTREG( 42,168,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) + XTREG( 43,172,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) + XTREG( 44,176,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) + XTREG( 45,180,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0) + XTREG( 46,184, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0) + XTREG( 47,188,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0) + XTREG( 48,192,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0) + XTREG( 49,196,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0) + XTREG( 50,200,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0) + XTREG( 51,204,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0) + XTREG( 52,208,64, 8, 8,0x0030,0x0006, 0, 4,0x0401,f0, + "03:03:54:00","03:03:14:00",0,0,0,0) + XTREG( 53,216,64, 8, 8,0x0031,0x0006, 0, 4,0x0401,f1, + "03:13:54:00","03:13:14:00",0,0,0,0) + XTREG( 54,224,64, 8, 8,0x0032,0x0006, 0, 4,0x0401,f2, + "03:23:54:00","03:23:14:00",0,0,0,0) + XTREG( 55,232,64, 8, 8,0x0033,0x0006, 0, 4,0x0401,f3, + "03:33:54:00","03:33:14:00",0,0,0,0) + XTREG( 56,240,64, 8, 8,0x0034,0x0006, 0, 4,0x0401,f4, + "03:43:54:00","03:43:14:00",0,0,0,0) + XTREG( 57,248,64, 8, 8,0x0035,0x0006, 0, 4,0x0401,f5, + "03:53:54:00","03:53:14:00",0,0,0,0) + XTREG( 58,256,64, 8, 8,0x0036,0x0006, 0, 4,0x0401,f6, + "03:63:54:00","03:63:14:00",0,0,0,0) + XTREG( 59,264,64, 8, 8,0x0037,0x0006, 0, 4,0x0401,f7, + "03:73:54:00","03:73:14:00",0,0,0,0) + XTREG( 60,272,64, 8, 8,0x0038,0x0006, 0, 4,0x0401,f8, + "03:83:54:00","03:83:14:00",0,0,0,0) + XTREG( 61,280,64, 8, 8,0x0039,0x0006, 0, 4,0x0401,f9, + "03:93:54:00","03:93:14:00",0,0,0,0) + XTREG( 62,288,64, 8, 8,0x003a,0x0006, 0, 4,0x0401,f10, + "03:a3:54:00","03:a3:14:00",0,0,0,0) + XTREG( 63,296,64, 8, 8,0x003b,0x0006, 0, 4,0x0401,f11, + "03:b3:54:00","03:b3:14:00",0,0,0,0) + XTREG( 64,304,64, 8, 8,0x003c,0x0006, 0, 4,0x0401,f12, + "03:c3:54:00","03:c3:14:00",0,0,0,0) + XTREG( 65,312,64, 8, 8,0x003d,0x0006, 0, 4,0x0401,f13, + "03:d3:54:00","03:d3:14:00",0,0,0,0) + XTREG( 66,320,64, 8, 8,0x003e,0x0006, 0, 4,0x0401,f14, + "03:e3:54:00","03:e3:14:00",0,0,0,0) + XTREG( 67,328,64, 8, 8,0x003f,0x0006, 0, 4,0x0401,f15, + "03:f3:54:00","03:f3:14:00",0,0,0,0) + XTREG( 68,336,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr, 0,0,0,0,0,0) + XTREG( 69,340,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr, 0,0,0,0,0,0) + XTREG( 70,344,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0) + XTREG( 71,348,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) + XTREG( 72,352,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0) + XTREG( 73,356,25, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0) + XTREG( 74,360,25, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0) + XTREG( 75,364,16, 4, 4,0x025f,0x0007,-2, 2,0x1000,eraccess, 0,0,0,0,0,0) + XTREG( 76,368, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) + XTREG( 77,372, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) + XTREG( 78,376,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) + XTREG( 79,380,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) + XTREG( 80,384,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) + XTREG( 81,388,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) + XTREG( 82,392,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) + XTREG( 83,396,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) + XTREG( 84,400,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) + XTREG( 85,404,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) + XTREG( 86,408,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) + XTREG( 87,412,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) + XTREG( 88,416,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) + XTREG( 89,420,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) + XTREG( 90,424,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) + XTREG( 91,428,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0) + XTREG( 92,432,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) + XTREG( 93,436,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) + XTREG( 94,440,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) + XTREG( 95,444,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) + XTREG( 96,448,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) + XTREG( 97,452,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) + XTREG( 98,456,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0) + XTREG( 99,460,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) + XTREG(100,464,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) + XTREG(101,468,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) + XTREG(102,472,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) + XTREG(103,476,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) + XTREG(104,480,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) + XTREG(105,484,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0) + XTREG(106,488, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) + XTREG(107,492,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) + XTREG(108,496,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) + XTREG(109,500,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) + XTREG(110,504,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) + XTREG(111,508,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) + XTREG(112,512, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) + XTREG(113,516,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) + XTREG(114,520,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) + XTREG(115,524,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) + XTREG(116,528,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) + XTREG(117,532, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) + XTREG(118,536,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) + XTREG(119,540,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) + XTREG(120,544,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) + XTREG(121,548,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0) + XTREG(122,552,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0) + XTREG(123,556,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0) + XTREG(124,560,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0, 0,0,0,0,0,0) + XTREG(125,564,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1, 0,0,0,0,0,0) + XTREG(126,568,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2, 0,0,0,0,0,0) + XTREG(127,572,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3, 0,0,0,0,0,0) + XTREG(128,576,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4, 0,0,0,0,0,0) + XTREG(129,580,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5, 0,0,0,0,0,0) + XTREG(130,584,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6, 0,0,0,0,0,0) + XTREG(131,588,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7, 0,0,0,0,0,0) + XTREG(132,592,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8, 0,0,0,0,0,0) + XTREG(133,596,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9, 0,0,0,0,0,0) + XTREG(134,600,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10, 0,0,0,0,0,0) + XTREG(135,604,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11, 0,0,0,0,0,0) + XTREG(136,608,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12, 0,0,0,0,0,0) + XTREG(137,612,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13, 0,0,0,0,0,0) + XTREG(138,616,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14, 0,0,0,0,0,0) + XTREG(139,620,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15, 0,0,0,0,0,0) + XTREG(140,624, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, + 0,0,&xtensa_mask0,0,0,0) + XTREG(141,625, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, + 0,0,&xtensa_mask1,0,0,0) + XTREG(142,626, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, + 0,0,&xtensa_mask2,0,0,0) + XTREG(143,627, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, + 0,0,&xtensa_mask3,0,0,0) + XTREG(144,628, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, + 0,0,&xtensa_mask4,0,0,0) + XTREG(145,629, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, + 0,0,&xtensa_mask5,0,0,0) + XTREG(146,630, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, + 0,0,&xtensa_mask6,0,0,0) + XTREG(147,631, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, + 0,0,&xtensa_mask7,0,0,0) + XTREG(148,632, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, + 0,0,&xtensa_mask8,0,0,0) + XTREG(149,633, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, + 0,0,&xtensa_mask9,0,0,0) + XTREG(150,634, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, + 0,0,&xtensa_mask10,0,0,0) + XTREG(151,635, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, + 0,0,&xtensa_mask11,0,0,0) + XTREG(152,636, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, + 0,0,&xtensa_mask12,0,0,0) + XTREG(153,637, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, + 0,0,&xtensa_mask13,0,0,0) + XTREG(154,638, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, + 0,0,&xtensa_mask14,0,0,0) + XTREG(155,639, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, + 0,0,&xtensa_mask15,0,0,0) + XTREG(156,640, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel, + 0,0,&xtensa_mask16,0,0,0) + XTREG(157,644, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum, + 0,0,&xtensa_mask17,0,0,0) + XTREG(158,648, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe, + 0,0,&xtensa_mask18,0,0,0) + XTREG(159,652, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring, + 0,0,&xtensa_mask19,0,0,0) + XTREG(160,656, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm, + 0,0,&xtensa_mask20,0,0,0) + XTREG(161,660, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc, + 0,0,&xtensa_mask21,0,0,0) + XTREG(162,664, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb, + 0,0,&xtensa_mask22,0,0,0) + XTREG(163,668,40, 8, 4,0x200f,0x0006,-2, 6,0x1010,acc, + 0,0,&xtensa_mask23,0,0,0) + XTREG(164,676, 4, 4, 4,0x2014,0x0006,-2, 6,0x1010,dbnum, + 0,0,&xtensa_mask24,0,0,0) + XTREG(165,680, 8, 4, 4,0x2015,0x0006,-2, 6,0x1010,asid3, + 0,0,&xtensa_mask25,0,0,0) + XTREG(166,684, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid2, + 0,0,&xtensa_mask26,0,0,0) + XTREG(167,688, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid1, + 0,0,&xtensa_mask27,0,0,0) + XTREG(168,692, 1, 4, 4,0x2018,0x0006,-2, 6,0x1010,instpgszid6, + 0,0,&xtensa_mask28,0,0,0) + XTREG(169,696, 1, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid5, + 0,0,&xtensa_mask29,0,0,0) + XTREG(170,700, 2, 4, 4,0x201a,0x0006,-2, 6,0x1010,instpgszid4, + 0,0,&xtensa_mask30,0,0,0) + XTREG(171,704, 1, 4, 4,0x201b,0x0006,-2, 6,0x1010,datapgszid6, + 0,0,&xtensa_mask31,0,0,0) + XTREG(172,708, 1, 4, 4,0x201c,0x0006,-2, 6,0x1010,datapgszid5, + 0,0,&xtensa_mask32,0,0,0) + XTREG(173,712, 2, 4, 4,0x201d,0x0006,-2, 6,0x1010,datapgszid4, + 0,0,&xtensa_mask33,0,0,0) + XTREG(174,716,10, 4, 4,0x201e,0x0006,-2, 6,0x1010,ptbase, + 0,0,&xtensa_mask34,0,0,0) + XTREG(175,720, 2, 4, 4,0x201f,0x0006, 0, 5,0x1010,roundmode, + 0,0,&xtensa_mask35,0,0,0) + XTREG(176,724, 1, 4, 4,0x2020,0x0006, 0, 5,0x1010,invalidenable, + 0,0,&xtensa_mask36,0,0,0) + XTREG(177,728, 1, 4, 4,0x2021,0x0006, 0, 5,0x1010,divzeroenable, + 0,0,&xtensa_mask37,0,0,0) + XTREG(178,732, 1, 4, 4,0x2022,0x0006, 0, 5,0x1010,overflowenable, + 0,0,&xtensa_mask38,0,0,0) + XTREG(179,736, 1, 4, 4,0x2023,0x0006, 0, 5,0x1010,underflowenable, + 0,0,&xtensa_mask39,0,0,0) + XTREG(180,740, 1, 4, 4,0x2024,0x0006, 0, 5,0x1010,inexactenable, + 0,0,&xtensa_mask40,0,0,0) + XTREG(181,744, 1, 4, 4,0x2025,0x0006, 0, 5,0x1010,invalidflag, + 0,0,&xtensa_mask41,0,0,0) + XTREG(182,748, 1, 4, 4,0x2026,0x0006, 0, 5,0x1010,divzeroflag, + 0,0,&xtensa_mask42,0,0,0) + XTREG(183,752, 1, 4, 4,0x2027,0x0006, 0, 5,0x1010,overflowflag, + 0,0,&xtensa_mask43,0,0,0) + XTREG(184,756, 1, 4, 4,0x2028,0x0006, 0, 5,0x1010,underflowflag, + 0,0,&xtensa_mask44,0,0,0) + XTREG(185,760, 1, 4, 4,0x2029,0x0006, 0, 5,0x1010,inexactflag, + 0,0,&xtensa_mask45,0,0,0) + XTREG(186,764,20, 4, 4,0x202a,0x0006, 0, 5,0x1010,fpreserved20, + 0,0,&xtensa_mask46,0,0,0) + XTREG(187,768,20, 4, 4,0x202b,0x0006, 0, 5,0x1010,fpreserved20a, + 0,0,&xtensa_mask47,0,0,0) + XTREG(188,772, 5, 4, 4,0x202c,0x0006, 0, 5,0x1010,fpreserved5, + 0,0,&xtensa_mask48,0,0,0) + XTREG_END diff --git a/target/xtensa/core-DE_233L_FPU/xtensa-modules.inc.c b/target/xtensa/core-DE_233L_FPU/xtensa-modules.inc.c new file mode 100644 index 000000000000..129c02351416 --- /dev/null +++ b/target/xtensa/core-DE_233L_FPU/xtensa-modules.inc.c @@ -0,0 +1,20758 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2020 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "xtensa-isa.h" +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "BR", 4, 0 }, + { "ACCLO", 16, 0 }, + { "ACCHI", 17, 0 }, + { "M0", 32, 0 }, + { "M1", 33, 0 }, + { "M2", 34, 0 }, + { "M3", 35, 0 }, + { "PTEVADDR", 83, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "CONFIGID0", 176, 0 }, + { "CONFIGID1", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "CCOMPARE2", 242, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EPC7", 183, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EXCSAVE7", 215, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EPS7", 199, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "SAR", 3, 0 }, + { "PS", 230, 0 }, + { "MISC0", 244, 0 }, + { "MISC1", 245, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "RASID", 90, 0 }, + { "ITLBCFG", 91, 0 }, + { "DTLBCFG", 92, 0 }, + { "CPENABLE", 224, 0 }, + { "SCOMPARE1", 12, 0 }, + { "ATOMCTL", 99, 0 }, + { "ERACCESS", 95, 0 }, + { "THREADPTR", 231, 1 }, + { "FCR", 232, 1 }, + { "FSR", 233, 1 }, + { "EXPSTATE", 230, 1 } +}; + +#define NUM_SYSREGS 74 +#define MAX_SPECIAL_REG 245 +#define MAX_USER_REG 233 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 22, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EPC7", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EXCSAVE7", 32, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, + { "EPS5", 15, 0 }, + { "EPS6", 15, 0 }, + { "EPS7", 15, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "MISC0", 32, 0 }, + { "MISC1", 32, 0 }, + { "ACC", 40, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 22, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CCOMPARE2", 32, 0 }, + { "ASID3", 8, 0 }, + { "ASID2", 8, 0 }, + { "ASID1", 8, 0 }, + { "INSTPGSZID6", 1, 0 }, + { "INSTPGSZID5", 1, 0 }, + { "INSTPGSZID4", 2, 0 }, + { "DATAPGSZID6", 1, 0 }, + { "DATAPGSZID5", 1, 0 }, + { "DATAPGSZID4", 2, 0 }, + { "PTBASE", 10, 0 }, + { "CPENABLE", 8, 0 }, + { "SCOMPARE1", 32, 0 }, + { "ATOMCTL", 6, 0 }, + { "ERACCESS", 16, 0 }, + { "RoundMode", 2, 0 }, + { "InvalidEnable", 1, 0 }, + { "DivZeroEnable", 1, 0 }, + { "OverflowEnable", 1, 0 }, + { "UnderflowEnable", 1, 0 }, + { "InexactEnable", 1, 0 }, + { "InvalidFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "DivZeroFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "OverflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "UnderflowFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "InexactFlag", 1, XTENSA_STATE_IS_SHARED_OR }, + { "FPreserved20", 20, 0 }, + { "FPreserved20a", 20, 0 }, + { "FPreserved5", 5, 0 }, + { "FPreserved7", 7, 0 }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } +}; + +#define NUM_STATES 92 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_ICOUNT, + STATE_DDR, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EPC6, + STATE_EPC7, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EXCSAVE6, + STATE_EXCSAVE7, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EPS6, + STATE_EPS7, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSRING, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_SAR, + STATE_THREADPTR, + STATE_MISC0, + STATE_MISC1, + STATE_ACC, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CCOMPARE2, + STATE_ASID3, + STATE_ASID2, + STATE_ASID1, + STATE_INSTPGSZID6, + STATE_INSTPGSZID5, + STATE_INSTPGSZID4, + STATE_DATAPGSZID6, + STATE_DATAPGSZID5, + STATE_DATAPGSZID4, + STATE_PTBASE, + STATE_CPENABLE, + STATE_SCOMPARE1, + STATE_ATOMCTL, + STATE_ERACCESS, + STATE_RoundMode, + STATE_InvalidEnable, + STATE_DivZeroEnable, + STATE_OverflowEnable, + STATE_UnderflowEnable, + STATE_InexactEnable, + STATE_InvalidFlag, + STATE_DivZeroFlag, + STATE_OverflowFlag, + STATE_UnderflowFlag, + STATE_InexactFlag, + STATE_FPreserved20, + STATE_FPreserved20a, + STATE_FPreserved5, + STATE_FPreserved7, + STATE_EXPSTATE +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_w_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_r3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_imms8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_imms8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_disp_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_r_disp_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_r_3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_y_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_x_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 1; +} + +static unsigned +Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 2; +} + +static unsigned +Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 3; +} + +static unsigned +Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_s8, + FIELD_imms8, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_r_disp, + FIELD_r_3, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_r3, + FIELD_rbit2, + FIELD_rhi, + FIELD_t3, + FIELD_tbit2, + FIELD_tlo, + FIELD_w, + FIELD_y, + FIELD_x, + FIELD_t2, + FIELD_s2, + FIELD_r2, + FIELD_t4, + FIELD_s4, + FIELD_r4, + FIELD_t8, + FIELD_r8, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_bitindex, + FIELD_s3to1, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__mr0, + FIELD__mr1, + FIELD__mr2, + FIELD__mr3, + FIELD__bt16, + FIELD__bs16, + FIELD__br16, + FIELD__brall +}; + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + {"XT_LOADSTORE_UNIT", 1} +}; + +enum xtensa_funcUnit_id { + FUNCUNIT_XT_LOADSTORE_UNIT +}; + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_MR, + REGFILE_BR, + REGFILE_FR, + REGFILE_BR2, + REGFILE_BR4, + REGFILE_BR8, + REGFILE_BR16 +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 32 }, + { "MR", "m", REGFILE_MR, 32, 4 }, + { "BR", "b", REGFILE_BR, 1, 16 }, + { "FR", "f", REGFILE_FR, 64, 16 }, + { "BR2", "b", REGFILE_BR, 2, 8 }, + { "BR4", "b", REGFILE_BR, 4, 4 }, + { "BR8", "b", REGFILE_BR, 8, 2 }, + { "BR16", "b", REGFILE_BR, 16, 1 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "IMPWIRE", 32, 0, 0, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_IMPWIRE +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table RECIP_Data8 */ +static const unsigned CONST_TBL_RECIP_Data8_0[] = { + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf5 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf0 & 0xff, + 0xee & 0xff, + 0xed & 0xff, + 0xeb & 0xff, + 0xe9 & 0xff, + 0xe8 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xde & 0xff, + 0xdd & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd1 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb1 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xad & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa4 & 0xff, + 0xa3 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0 +}; + +/* constant table RSQRT_Data8 */ +static const unsigned CONST_TBL_RSQRT_Data8_0[] = { + 0xb4 & 0xff, + 0xb3 & 0xff, + 0xb2 & 0xff, + 0xb0 & 0xff, + 0xaf & 0xff, + 0xae & 0xff, + 0xac & 0xff, + 0xab & 0xff, + 0xaa & 0xff, + 0xa9 & 0xff, + 0xa8 & 0xff, + 0xa7 & 0xff, + 0xa6 & 0xff, + 0xa5 & 0xff, + 0xa3 & 0xff, + 0xa2 & 0xff, + 0xa1 & 0xff, + 0xa0 & 0xff, + 0x9f & 0xff, + 0x9e & 0xff, + 0x9e & 0xff, + 0x9d & 0xff, + 0x9c & 0xff, + 0x9b & 0xff, + 0x9a & 0xff, + 0x99 & 0xff, + 0x98 & 0xff, + 0x97 & 0xff, + 0x97 & 0xff, + 0x96 & 0xff, + 0x95 & 0xff, + 0x94 & 0xff, + 0x93 & 0xff, + 0x93 & 0xff, + 0x92 & 0xff, + 0x91 & 0xff, + 0x90 & 0xff, + 0x90 & 0xff, + 0x8f & 0xff, + 0x8e & 0xff, + 0x8e & 0xff, + 0x8d & 0xff, + 0x8c & 0xff, + 0x8c & 0xff, + 0x8b & 0xff, + 0x8a & 0xff, + 0x8a & 0xff, + 0x89 & 0xff, + 0x89 & 0xff, + 0x88 & 0xff, + 0x87 & 0xff, + 0x87 & 0xff, + 0x86 & 0xff, + 0x86 & 0xff, + 0x85 & 0xff, + 0x84 & 0xff, + 0x84 & 0xff, + 0x83 & 0xff, + 0x83 & 0xff, + 0x82 & 0xff, + 0x82 & 0xff, + 0x81 & 0xff, + 0x81 & 0xff, + 0x80 & 0xff, + 0xff & 0xff, + 0xfd & 0xff, + 0xfb & 0xff, + 0xf9 & 0xff, + 0xf7 & 0xff, + 0xf6 & 0xff, + 0xf4 & 0xff, + 0xf2 & 0xff, + 0xf1 & 0xff, + 0xef & 0xff, + 0xed & 0xff, + 0xec & 0xff, + 0xea & 0xff, + 0xe9 & 0xff, + 0xe7 & 0xff, + 0xe6 & 0xff, + 0xe4 & 0xff, + 0xe3 & 0xff, + 0xe1 & 0xff, + 0xe0 & 0xff, + 0xdf & 0xff, + 0xdd & 0xff, + 0xdc & 0xff, + 0xdb & 0xff, + 0xda & 0xff, + 0xd8 & 0xff, + 0xd7 & 0xff, + 0xd6 & 0xff, + 0xd5 & 0xff, + 0xd4 & 0xff, + 0xd3 & 0xff, + 0xd2 & 0xff, + 0xd0 & 0xff, + 0xcf & 0xff, + 0xce & 0xff, + 0xcd & 0xff, + 0xcc & 0xff, + 0xcb & 0xff, + 0xca & 0xff, + 0xc9 & 0xff, + 0xc8 & 0xff, + 0xc7 & 0xff, + 0xc6 & 0xff, + 0xc6 & 0xff, + 0xc5 & 0xff, + 0xc4 & 0xff, + 0xc3 & 0xff, + 0xc2 & 0xff, + 0xc1 & 0xff, + 0xc0 & 0xff, + 0xbf & 0xff, + 0xbf & 0xff, + 0xbe & 0xff, + 0xbd & 0xff, + 0xbc & 0xff, + 0xbb & 0xff, + 0xbb & 0xff, + 0xba & 0xff, + 0xb9 & 0xff, + 0xb8 & 0xff, + 0xb8 & 0xff, + 0xb7 & 0xff, + 0xb6 & 0xff, + 0xb5 & 0xff, + 0 +}; + +/* constant table RECIP_Data10_2 */ +static const unsigned CONST_TBL_RECIP_Data10_2_0[] = { + 0x3fc & 0x3ff, + 0x3f4 & 0x3ff, + 0x3ec & 0x3ff, + 0x3e5 & 0x3ff, + 0x3dd & 0x3ff, + 0x3d6 & 0x3ff, + 0x3cf & 0x3ff, + 0x3c7 & 0x3ff, + 0x3c0 & 0x3ff, + 0x3b9 & 0x3ff, + 0x3b2 & 0x3ff, + 0x3ac & 0x3ff, + 0x3a5 & 0x3ff, + 0x39e & 0x3ff, + 0x398 & 0x3ff, + 0x391 & 0x3ff, + 0x38b & 0x3ff, + 0x385 & 0x3ff, + 0x37f & 0x3ff, + 0x378 & 0x3ff, + 0x373 & 0x3ff, + 0x36c & 0x3ff, + 0x367 & 0x3ff, + 0x361 & 0x3ff, + 0x35c & 0x3ff, + 0x356 & 0x3ff, + 0x350 & 0x3ff, + 0x34b & 0x3ff, + 0x345 & 0x3ff, + 0x340 & 0x3ff, + 0x33b & 0x3ff, + 0x335 & 0x3ff, + 0x330 & 0x3ff, + 0x32c & 0x3ff, + 0x327 & 0x3ff, + 0x322 & 0x3ff, + 0x31c & 0x3ff, + 0x318 & 0x3ff, + 0x314 & 0x3ff, + 0x30e & 0x3ff, + 0x30a & 0x3ff, + 0x306 & 0x3ff, + 0x300 & 0x3ff, + 0x2fc & 0x3ff, + 0x2f8 & 0x3ff, + 0x2f4 & 0x3ff, + 0x2f0 & 0x3ff, + 0x2ea & 0x3ff, + 0x2e6 & 0x3ff, + 0x2e2 & 0x3ff, + 0x2de & 0x3ff, + 0x2da & 0x3ff, + 0x2d6 & 0x3ff, + 0x2d2 & 0x3ff, + 0x2ce & 0x3ff, + 0x2ca & 0x3ff, + 0x2c6 & 0x3ff, + 0x2c2 & 0x3ff, + 0x2be & 0x3ff, + 0x2ba & 0x3ff, + 0x2b8 & 0x3ff, + 0x2b4 & 0x3ff, + 0x2b0 & 0x3ff, + 0x2ac & 0x3ff, + 0x2a8 & 0x3ff, + 0x2a6 & 0x3ff, + 0x2a2 & 0x3ff, + 0x29e & 0x3ff, + 0x29c & 0x3ff, + 0x298 & 0x3ff, + 0x294 & 0x3ff, + 0x290 & 0x3ff, + 0x28e & 0x3ff, + 0x28a & 0x3ff, + 0x288 & 0x3ff, + 0x284 & 0x3ff, + 0x280 & 0x3ff, + 0x27e & 0x3ff, + 0x27a & 0x3ff, + 0x278 & 0x3ff, + 0x274 & 0x3ff, + 0x272 & 0x3ff, + 0x26e & 0x3ff, + 0x26c & 0x3ff, + 0x268 & 0x3ff, + 0x266 & 0x3ff, + 0x264 & 0x3ff, + 0x260 & 0x3ff, + 0x25e & 0x3ff, + 0x25a & 0x3ff, + 0x258 & 0x3ff, + 0x254 & 0x3ff, + 0x252 & 0x3ff, + 0x250 & 0x3ff, + 0x24c & 0x3ff, + 0x24a & 0x3ff, + 0x248 & 0x3ff, + 0x246 & 0x3ff, + 0x242 & 0x3ff, + 0x240 & 0x3ff, + 0x23e & 0x3ff, + 0x23c & 0x3ff, + 0x238 & 0x3ff, + 0x236 & 0x3ff, + 0x234 & 0x3ff, + 0x232 & 0x3ff, + 0x230 & 0x3ff, + 0x22c & 0x3ff, + 0x22a & 0x3ff, + 0x228 & 0x3ff, + 0x226 & 0x3ff, + 0x224 & 0x3ff, + 0x220 & 0x3ff, + 0x21e & 0x3ff, + 0x21c & 0x3ff, + 0x21a & 0x3ff, + 0x218 & 0x3ff, + 0x216 & 0x3ff, + 0x214 & 0x3ff, + 0x212 & 0x3ff, + 0x210 & 0x3ff, + 0x20e & 0x3ff, + 0x20c & 0x3ff, + 0x208 & 0x3ff, + 0x208 & 0x3ff, + 0x204 & 0x3ff, + 0x204 & 0x3ff, + 0x201 & 0x3ff, + 0 +}; + +/* constant table RSQRT_10b_256 */ +static const unsigned CONST_TBL_RSQRT_10b_256_0[] = { + 0x1a5 & 0x3ff, + 0x1a0 & 0x3ff, + 0x19a & 0x3ff, + 0x195 & 0x3ff, + 0x18f & 0x3ff, + 0x18a & 0x3ff, + 0x185 & 0x3ff, + 0x180 & 0x3ff, + 0x17a & 0x3ff, + 0x175 & 0x3ff, + 0x170 & 0x3ff, + 0x16b & 0x3ff, + 0x166 & 0x3ff, + 0x161 & 0x3ff, + 0x15d & 0x3ff, + 0x158 & 0x3ff, + 0x153 & 0x3ff, + 0x14e & 0x3ff, + 0x14a & 0x3ff, + 0x145 & 0x3ff, + 0x140 & 0x3ff, + 0x13c & 0x3ff, + 0x138 & 0x3ff, + 0x133 & 0x3ff, + 0x12f & 0x3ff, + 0x12a & 0x3ff, + 0x126 & 0x3ff, + 0x122 & 0x3ff, + 0x11e & 0x3ff, + 0x11a & 0x3ff, + 0x115 & 0x3ff, + 0x111 & 0x3ff, + 0x10d & 0x3ff, + 0x109 & 0x3ff, + 0x105 & 0x3ff, + 0x101 & 0x3ff, + 0xfd & 0x3ff, + 0xfa & 0x3ff, + 0xf6 & 0x3ff, + 0xf2 & 0x3ff, + 0xee & 0x3ff, + 0xea & 0x3ff, + 0xe7 & 0x3ff, + 0xe3 & 0x3ff, + 0xdf & 0x3ff, + 0xdc & 0x3ff, + 0xd8 & 0x3ff, + 0xd5 & 0x3ff, + 0xd1 & 0x3ff, + 0xce & 0x3ff, + 0xca & 0x3ff, + 0xc7 & 0x3ff, + 0xc3 & 0x3ff, + 0xc0 & 0x3ff, + 0xbd & 0x3ff, + 0xb9 & 0x3ff, + 0xb6 & 0x3ff, + 0xb3 & 0x3ff, + 0xb0 & 0x3ff, + 0xad & 0x3ff, + 0xa9 & 0x3ff, + 0xa6 & 0x3ff, + 0xa3 & 0x3ff, + 0xa0 & 0x3ff, + 0x9d & 0x3ff, + 0x9a & 0x3ff, + 0x97 & 0x3ff, + 0x94 & 0x3ff, + 0x91 & 0x3ff, + 0x8e & 0x3ff, + 0x8b & 0x3ff, + 0x88 & 0x3ff, + 0x85 & 0x3ff, + 0x82 & 0x3ff, + 0x7f & 0x3ff, + 0x7d & 0x3ff, + 0x7a & 0x3ff, + 0x77 & 0x3ff, + 0x74 & 0x3ff, + 0x71 & 0x3ff, + 0x6f & 0x3ff, + 0x6c & 0x3ff, + 0x69 & 0x3ff, + 0x67 & 0x3ff, + 0x64 & 0x3ff, + 0x61 & 0x3ff, + 0x5f & 0x3ff, + 0x5c & 0x3ff, + 0x5a & 0x3ff, + 0x57 & 0x3ff, + 0x54 & 0x3ff, + 0x52 & 0x3ff, + 0x4f & 0x3ff, + 0x4d & 0x3ff, + 0x4a & 0x3ff, + 0x48 & 0x3ff, + 0x45 & 0x3ff, + 0x43 & 0x3ff, + 0x41 & 0x3ff, + 0x3e & 0x3ff, + 0x3c & 0x3ff, + 0x3a & 0x3ff, + 0x37 & 0x3ff, + 0x35 & 0x3ff, + 0x33 & 0x3ff, + 0x30 & 0x3ff, + 0x2e & 0x3ff, + 0x2c & 0x3ff, + 0x29 & 0x3ff, + 0x27 & 0x3ff, + 0x25 & 0x3ff, + 0x23 & 0x3ff, + 0x20 & 0x3ff, + 0x1e & 0x3ff, + 0x1c & 0x3ff, + 0x1a & 0x3ff, + 0x18 & 0x3ff, + 0x16 & 0x3ff, + 0x14 & 0x3ff, + 0x11 & 0x3ff, + 0xf & 0x3ff, + 0xd & 0x3ff, + 0xb & 0x3ff, + 0x9 & 0x3ff, + 0x7 & 0x3ff, + 0x5 & 0x3ff, + 0x3 & 0x3ff, + 0x1 & 0x3ff, + 0x3fc & 0x3ff, + 0x3f4 & 0x3ff, + 0x3ec & 0x3ff, + 0x3e5 & 0x3ff, + 0x3dd & 0x3ff, + 0x3d5 & 0x3ff, + 0x3ce & 0x3ff, + 0x3c7 & 0x3ff, + 0x3bf & 0x3ff, + 0x3b8 & 0x3ff, + 0x3b1 & 0x3ff, + 0x3aa & 0x3ff, + 0x3a3 & 0x3ff, + 0x39c & 0x3ff, + 0x395 & 0x3ff, + 0x38e & 0x3ff, + 0x388 & 0x3ff, + 0x381 & 0x3ff, + 0x37a & 0x3ff, + 0x374 & 0x3ff, + 0x36d & 0x3ff, + 0x367 & 0x3ff, + 0x361 & 0x3ff, + 0x35a & 0x3ff, + 0x354 & 0x3ff, + 0x34e & 0x3ff, + 0x348 & 0x3ff, + 0x342 & 0x3ff, + 0x33c & 0x3ff, + 0x336 & 0x3ff, + 0x330 & 0x3ff, + 0x32b & 0x3ff, + 0x325 & 0x3ff, + 0x31f & 0x3ff, + 0x31a & 0x3ff, + 0x314 & 0x3ff, + 0x30f & 0x3ff, + 0x309 & 0x3ff, + 0x304 & 0x3ff, + 0x2fe & 0x3ff, + 0x2f9 & 0x3ff, + 0x2f4 & 0x3ff, + 0x2ee & 0x3ff, + 0x2e9 & 0x3ff, + 0x2e4 & 0x3ff, + 0x2df & 0x3ff, + 0x2da & 0x3ff, + 0x2d5 & 0x3ff, + 0x2d0 & 0x3ff, + 0x2cb & 0x3ff, + 0x2c6 & 0x3ff, + 0x2c1 & 0x3ff, + 0x2bd & 0x3ff, + 0x2b8 & 0x3ff, + 0x2b3 & 0x3ff, + 0x2ae & 0x3ff, + 0x2aa & 0x3ff, + 0x2a5 & 0x3ff, + 0x2a1 & 0x3ff, + 0x29c & 0x3ff, + 0x298 & 0x3ff, + 0x293 & 0x3ff, + 0x28f & 0x3ff, + 0x28a & 0x3ff, + 0x286 & 0x3ff, + 0x282 & 0x3ff, + 0x27d & 0x3ff, + 0x279 & 0x3ff, + 0x275 & 0x3ff, + 0x271 & 0x3ff, + 0x26d & 0x3ff, + 0x268 & 0x3ff, + 0x264 & 0x3ff, + 0x260 & 0x3ff, + 0x25c & 0x3ff, + 0x258 & 0x3ff, + 0x254 & 0x3ff, + 0x250 & 0x3ff, + 0x24c & 0x3ff, + 0x249 & 0x3ff, + 0x245 & 0x3ff, + 0x241 & 0x3ff, + 0x23d & 0x3ff, + 0x239 & 0x3ff, + 0x235 & 0x3ff, + 0x232 & 0x3ff, + 0x22e & 0x3ff, + 0x22a & 0x3ff, + 0x227 & 0x3ff, + 0x223 & 0x3ff, + 0x220 & 0x3ff, + 0x21c & 0x3ff, + 0x218 & 0x3ff, + 0x215 & 0x3ff, + 0x211 & 0x3ff, + 0x20e & 0x3ff, + 0x20a & 0x3ff, + 0x207 & 0x3ff, + 0x204 & 0x3ff, + 0x200 & 0x3ff, + 0x1fd & 0x3ff, + 0x1f9 & 0x3ff, + 0x1f6 & 0x3ff, + 0x1f3 & 0x3ff, + 0x1f0 & 0x3ff, + 0x1ec & 0x3ff, + 0x1e9 & 0x3ff, + 0x1e6 & 0x3ff, + 0x1e3 & 0x3ff, + 0x1df & 0x3ff, + 0x1dc & 0x3ff, + 0x1d9 & 0x3ff, + 0x1d6 & 0x3ff, + 0x1d3 & 0x3ff, + 0x1d0 & 0x3ff, + 0x1cd & 0x3ff, + 0x1ca & 0x3ff, + 0x1c7 & 0x3ff, + 0x1c4 & 0x3ff, + 0x1c1 & 0x3ff, + 0x1be & 0x3ff, + 0x1bb & 0x3ff, + 0x1b8 & 0x3ff, + 0x1b5 & 0x3ff, + 0x1b2 & 0x3ff, + 0x1af & 0x3ff, + 0x1ac & 0x3ff, + 0x1aa & 0x3ff, + 0 +}; + +/* constant table RECIP_10b_256 */ +static const unsigned CONST_TBL_RECIP_10b_256_0[] = { + 0x3fc & 0x3ff, + 0x3f4 & 0x3ff, + 0x3ec & 0x3ff, + 0x3e4 & 0x3ff, + 0x3dd & 0x3ff, + 0x3d5 & 0x3ff, + 0x3cd & 0x3ff, + 0x3c6 & 0x3ff, + 0x3be & 0x3ff, + 0x3b7 & 0x3ff, + 0x3af & 0x3ff, + 0x3a8 & 0x3ff, + 0x3a1 & 0x3ff, + 0x399 & 0x3ff, + 0x392 & 0x3ff, + 0x38b & 0x3ff, + 0x384 & 0x3ff, + 0x37d & 0x3ff, + 0x376 & 0x3ff, + 0x36f & 0x3ff, + 0x368 & 0x3ff, + 0x361 & 0x3ff, + 0x35b & 0x3ff, + 0x354 & 0x3ff, + 0x34d & 0x3ff, + 0x346 & 0x3ff, + 0x340 & 0x3ff, + 0x339 & 0x3ff, + 0x333 & 0x3ff, + 0x32c & 0x3ff, + 0x326 & 0x3ff, + 0x320 & 0x3ff, + 0x319 & 0x3ff, + 0x313 & 0x3ff, + 0x30d & 0x3ff, + 0x307 & 0x3ff, + 0x300 & 0x3ff, + 0x2fa & 0x3ff, + 0x2f4 & 0x3ff, + 0x2ee & 0x3ff, + 0x2e8 & 0x3ff, + 0x2e2 & 0x3ff, + 0x2dc & 0x3ff, + 0x2d7 & 0x3ff, + 0x2d1 & 0x3ff, + 0x2cb & 0x3ff, + 0x2c5 & 0x3ff, + 0x2bf & 0x3ff, + 0x2ba & 0x3ff, + 0x2b4 & 0x3ff, + 0x2af & 0x3ff, + 0x2a9 & 0x3ff, + 0x2a3 & 0x3ff, + 0x29e & 0x3ff, + 0x299 & 0x3ff, + 0x293 & 0x3ff, + 0x28e & 0x3ff, + 0x288 & 0x3ff, + 0x283 & 0x3ff, + 0x27e & 0x3ff, + 0x279 & 0x3ff, + 0x273 & 0x3ff, + 0x26e & 0x3ff, + 0x269 & 0x3ff, + 0x264 & 0x3ff, + 0x25f & 0x3ff, + 0x25a & 0x3ff, + 0x255 & 0x3ff, + 0x250 & 0x3ff, + 0x24b & 0x3ff, + 0x246 & 0x3ff, + 0x241 & 0x3ff, + 0x23c & 0x3ff, + 0x237 & 0x3ff, + 0x232 & 0x3ff, + 0x22e & 0x3ff, + 0x229 & 0x3ff, + 0x224 & 0x3ff, + 0x21f & 0x3ff, + 0x21b & 0x3ff, + 0x216 & 0x3ff, + 0x211 & 0x3ff, + 0x20d & 0x3ff, + 0x208 & 0x3ff, + 0x204 & 0x3ff, + 0x1ff & 0x3ff, + 0x1fb & 0x3ff, + 0x1f6 & 0x3ff, + 0x1f2 & 0x3ff, + 0x1ed & 0x3ff, + 0x1e9 & 0x3ff, + 0x1e5 & 0x3ff, + 0x1e0 & 0x3ff, + 0x1dc & 0x3ff, + 0x1d8 & 0x3ff, + 0x1d4 & 0x3ff, + 0x1cf & 0x3ff, + 0x1cb & 0x3ff, + 0x1c7 & 0x3ff, + 0x1c3 & 0x3ff, + 0x1bf & 0x3ff, + 0x1bb & 0x3ff, + 0x1b6 & 0x3ff, + 0x1b2 & 0x3ff, + 0x1ae & 0x3ff, + 0x1aa & 0x3ff, + 0x1a6 & 0x3ff, + 0x1a2 & 0x3ff, + 0x19e & 0x3ff, + 0x19a & 0x3ff, + 0x197 & 0x3ff, + 0x193 & 0x3ff, + 0x18f & 0x3ff, + 0x18b & 0x3ff, + 0x187 & 0x3ff, + 0x183 & 0x3ff, + 0x17f & 0x3ff, + 0x17c & 0x3ff, + 0x178 & 0x3ff, + 0x174 & 0x3ff, + 0x171 & 0x3ff, + 0x16d & 0x3ff, + 0x169 & 0x3ff, + 0x166 & 0x3ff, + 0x162 & 0x3ff, + 0x15e & 0x3ff, + 0x15b & 0x3ff, + 0x157 & 0x3ff, + 0x154 & 0x3ff, + 0x150 & 0x3ff, + 0x14d & 0x3ff, + 0x149 & 0x3ff, + 0x146 & 0x3ff, + 0x142 & 0x3ff, + 0x13f & 0x3ff, + 0x13b & 0x3ff, + 0x138 & 0x3ff, + 0x134 & 0x3ff, + 0x131 & 0x3ff, + 0x12e & 0x3ff, + 0x12a & 0x3ff, + 0x127 & 0x3ff, + 0x124 & 0x3ff, + 0x120 & 0x3ff, + 0x11d & 0x3ff, + 0x11a & 0x3ff, + 0x117 & 0x3ff, + 0x113 & 0x3ff, + 0x110 & 0x3ff, + 0x10d & 0x3ff, + 0x10a & 0x3ff, + 0x107 & 0x3ff, + 0x103 & 0x3ff, + 0x100 & 0x3ff, + 0xfd & 0x3ff, + 0xfa & 0x3ff, + 0xf7 & 0x3ff, + 0xf4 & 0x3ff, + 0xf1 & 0x3ff, + 0xee & 0x3ff, + 0xeb & 0x3ff, + 0xe8 & 0x3ff, + 0xe5 & 0x3ff, + 0xe2 & 0x3ff, + 0xdf & 0x3ff, + 0xdc & 0x3ff, + 0xd9 & 0x3ff, + 0xd6 & 0x3ff, + 0xd3 & 0x3ff, + 0xd0 & 0x3ff, + 0xcd & 0x3ff, + 0xca & 0x3ff, + 0xc8 & 0x3ff, + 0xc5 & 0x3ff, + 0xc2 & 0x3ff, + 0xbf & 0x3ff, + 0xbc & 0x3ff, + 0xb9 & 0x3ff, + 0xb7 & 0x3ff, + 0xb4 & 0x3ff, + 0xb1 & 0x3ff, + 0xae & 0x3ff, + 0xac & 0x3ff, + 0xa9 & 0x3ff, + 0xa6 & 0x3ff, + 0xa4 & 0x3ff, + 0xa1 & 0x3ff, + 0x9e & 0x3ff, + 0x9c & 0x3ff, + 0x99 & 0x3ff, + 0x96 & 0x3ff, + 0x94 & 0x3ff, + 0x91 & 0x3ff, + 0x8e & 0x3ff, + 0x8c & 0x3ff, + 0x89 & 0x3ff, + 0x87 & 0x3ff, + 0x84 & 0x3ff, + 0x82 & 0x3ff, + 0x7f & 0x3ff, + 0x7c & 0x3ff, + 0x7a & 0x3ff, + 0x77 & 0x3ff, + 0x75 & 0x3ff, + 0x73 & 0x3ff, + 0x70 & 0x3ff, + 0x6e & 0x3ff, + 0x6b & 0x3ff, + 0x69 & 0x3ff, + 0x66 & 0x3ff, + 0x64 & 0x3ff, + 0x61 & 0x3ff, + 0x5f & 0x3ff, + 0x5d & 0x3ff, + 0x5a & 0x3ff, + 0x58 & 0x3ff, + 0x56 & 0x3ff, + 0x53 & 0x3ff, + 0x51 & 0x3ff, + 0x4f & 0x3ff, + 0x4c & 0x3ff, + 0x4a & 0x3ff, + 0x48 & 0x3ff, + 0x45 & 0x3ff, + 0x43 & 0x3ff, + 0x41 & 0x3ff, + 0x3f & 0x3ff, + 0x3c & 0x3ff, + 0x3a & 0x3ff, + 0x38 & 0x3ff, + 0x36 & 0x3ff, + 0x33 & 0x3ff, + 0x31 & 0x3ff, + 0x2f & 0x3ff, + 0x2d & 0x3ff, + 0x2b & 0x3ff, + 0x29 & 0x3ff, + 0x26 & 0x3ff, + 0x24 & 0x3ff, + 0x22 & 0x3ff, + 0x20 & 0x3ff, + 0x1e & 0x3ff, + 0x1c & 0x3ff, + 0x1a & 0x3ff, + 0x18 & 0x3ff, + 0x15 & 0x3ff, + 0x13 & 0x3ff, + 0x11 & 0x3ff, + 0xf & 0x3ff, + 0xd & 0x3ff, + 0xb & 0x3ff, + 0x9 & 0x3ff, + 0x7 & 0x3ff, + 0x5 & 0x3ff, + 0x3 & 0x3ff, + 0x1 & 0x3ff, + 0 +}; + + +/* Instruction operands. */ + +static int +OperandSem_opnd_sem_MR_0_decode (uint32 *valp) +{ + *valp += 2; + return 0; +} + +static int +OperandSem_opnd_sem_MR_0_encode (uint32 *valp) +{ + int error; + error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); + *valp = *valp & 1; + return error; +} + +static int +OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_out_0; + unsigned soffsetx4_in_0; + soffsetx4_in_0 = *valp & 0x3ffff; + soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); + *valp = soffsetx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) +{ + unsigned soffsetx4_in_0; + unsigned soffsetx4_out_0; + soffsetx4_out_0 = *valp; + soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; + *valp = soffsetx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_decode (uint32 *valp) +{ + unsigned immr_out_0; + unsigned immr_in_0; + immr_in_0 = *valp & 0xf; + immr_out_0 = immr_in_0; + *valp = immr_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immr_encode (uint32 *valp) +{ + unsigned immr_in_0; + unsigned immr_out_0; + immr_out_0 = *valp; + immr_in_0 = (immr_out_0 & 0xf); + *valp = immr_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_out_0; + unsigned uimm12x8_in_0; + uimm12x8_in_0 = *valp & 0xfff; + uimm12x8_out_0 = uimm12x8_in_0 << 3; + *valp = uimm12x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) +{ + unsigned uimm12x8_in_0; + unsigned uimm12x8_out_0; + uimm12x8_out_0 = *valp; + uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); + *valp = uimm12x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_decode (uint32 *valp) +{ + unsigned simm4_out_0; + unsigned simm4_in_0; + simm4_in_0 = *valp & 0xf; + simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; + *valp = simm4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm4_encode (uint32 *valp) +{ + unsigned simm4_in_0; + unsigned simm4_out_0; + simm4_out_0 = *valp; + simm4_in_0 = (simm4_out_0 & 0xf); + *valp = simm4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_0_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_8_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_12_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_AR_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_AR_entry_encode (uint32 *valp) +{ + int error; + error = (*valp >= 32); + return error; +} + +static int +OperandSem_opnd_sem_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_out_0; + unsigned immrx4_in_0; + immrx4_in_0 = *valp & 0xf; + immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; + *valp = immrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immrx4_encode (uint32 *valp) +{ + unsigned immrx4_in_0; + unsigned immrx4_out_0; + immrx4_out_0 = *valp; + immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); + *valp = immrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_out_0; + unsigned lsi4x4_in_0; + lsi4x4_in_0 = *valp & 0xf; + lsi4x4_out_0 = lsi4x4_in_0 << 2; + *valp = lsi4x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) +{ + unsigned lsi4x4_in_0; + unsigned lsi4x4_out_0; + lsi4x4_out_0 = *valp; + lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); + *valp = lsi4x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_decode (uint32 *valp) +{ + unsigned simm7_out_0; + unsigned simm7_in_0; + simm7_in_0 = *valp & 0x7f; + simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; + *valp = simm7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm7_encode (uint32 *valp) +{ + unsigned simm7_in_0; + unsigned simm7_out_0; + simm7_out_0 = *valp; + simm7_in_0 = (simm7_out_0 & 0x7f); + *valp = simm7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_out_0; + unsigned uimm6_in_0; + uimm6_in_0 = *valp & 0x3f; + uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); + *valp = uimm6_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm6_encode (uint32 *valp) +{ + unsigned uimm6_in_0; + unsigned uimm6_out_0; + uimm6_out_0 = *valp; + uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; + *valp = uimm6_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_out_0; + unsigned ai4const_in_0; + ai4const_in_0 = *valp & 0xf; + ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; + *valp = ai4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ai4const_encode (uint32 *valp) +{ + unsigned ai4const_in_0; + unsigned ai4const_out_0; + ai4const_out_0 = *valp; + switch (ai4const_out_0) + { + case 0xffffffff: ai4const_in_0 = 0; break; + case 0x1: ai4const_in_0 = 0x1; break; + case 0x2: ai4const_in_0 = 0x2; break; + case 0x3: ai4const_in_0 = 0x3; break; + case 0x4: ai4const_in_0 = 0x4; break; + case 0x5: ai4const_in_0 = 0x5; break; + case 0x6: ai4const_in_0 = 0x6; break; + case 0x7: ai4const_in_0 = 0x7; break; + case 0x8: ai4const_in_0 = 0x8; break; + case 0x9: ai4const_in_0 = 0x9; break; + case 0xa: ai4const_in_0 = 0xa; break; + case 0xb: ai4const_in_0 = 0xb; break; + case 0xc: ai4const_in_0 = 0xc; break; + case 0xd: ai4const_in_0 = 0xd; break; + case 0xe: ai4const_in_0 = 0xe; break; + default: ai4const_in_0 = 0xf; break; + } + *valp = ai4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_decode (uint32 *valp) +{ + unsigned b4const_out_0; + unsigned b4const_in_0; + b4const_in_0 = *valp & 0xf; + b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; + *valp = b4const_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4const_encode (uint32 *valp) +{ + unsigned b4const_in_0; + unsigned b4const_out_0; + b4const_out_0 = *valp; + switch (b4const_out_0) + { + case 0xffffffff: b4const_in_0 = 0; break; + case 0x1: b4const_in_0 = 0x1; break; + case 0x2: b4const_in_0 = 0x2; break; + case 0x3: b4const_in_0 = 0x3; break; + case 0x4: b4const_in_0 = 0x4; break; + case 0x5: b4const_in_0 = 0x5; break; + case 0x6: b4const_in_0 = 0x6; break; + case 0x7: b4const_in_0 = 0x7; break; + case 0x8: b4const_in_0 = 0x8; break; + case 0xa: b4const_in_0 = 0x9; break; + case 0xc: b4const_in_0 = 0xa; break; + case 0x10: b4const_in_0 = 0xb; break; + case 0x20: b4const_in_0 = 0xc; break; + case 0x40: b4const_in_0 = 0xd; break; + case 0x80: b4const_in_0 = 0xe; break; + default: b4const_in_0 = 0xf; break; + } + *valp = b4const_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_out_0; + unsigned b4constu_in_0; + b4constu_in_0 = *valp & 0xf; + b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; + *valp = b4constu_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_b4constu_encode (uint32 *valp) +{ + unsigned b4constu_in_0; + unsigned b4constu_out_0; + b4constu_out_0 = *valp; + switch (b4constu_out_0) + { + case 0x8000: b4constu_in_0 = 0; break; + case 0x10000: b4constu_in_0 = 0x1; break; + case 0x2: b4constu_in_0 = 0x2; break; + case 0x3: b4constu_in_0 = 0x3; break; + case 0x4: b4constu_in_0 = 0x4; break; + case 0x5: b4constu_in_0 = 0x5; break; + case 0x6: b4constu_in_0 = 0x6; break; + case 0x7: b4constu_in_0 = 0x7; break; + case 0x8: b4constu_in_0 = 0x8; break; + case 0xa: b4constu_in_0 = 0x9; break; + case 0xc: b4constu_in_0 = 0xa; break; + case 0x10: b4constu_in_0 = 0xb; break; + case 0x20: b4constu_in_0 = 0xc; break; + case 0x40: b4constu_in_0 = 0xd; break; + case 0x80: b4constu_in_0 = 0xe; break; + default: b4constu_in_0 = 0xf; break; + } + *valp = b4constu_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_decode (uint32 *valp) +{ + unsigned immt_out_0; + unsigned immt_in_0; + immt_in_0 = *valp & 0xf; + immt_out_0 = immt_in_0; + *valp = immt_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_immt_encode (uint32 *valp) +{ + unsigned immt_in_0; + unsigned immt_out_0; + immt_out_0 = *valp; + immt_in_0 = immt_out_0 & 0xf; + *valp = immt_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimms8_decode (uint32 *valp) +{ + unsigned uimms8_out_0; + unsigned uimms8_in_0; + uimms8_in_0 = *valp & 0x7; + uimms8_out_0 = uimms8_in_0; + *valp = uimms8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimms8_encode (uint32 *valp) +{ + unsigned uimms8_in_0; + unsigned uimms8_out_0; + uimms8_out_0 = *valp; + uimms8_in_0 = uimms8_out_0 & 0x7; + *valp = uimms8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_out_0; + unsigned uimm8_in_0; + uimm8_in_0 = *valp & 0xff; + uimm8_out_0 = uimm8_in_0; + *valp = uimm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8_encode (uint32 *valp) +{ + unsigned uimm8_in_0; + unsigned uimm8_out_0; + uimm8_out_0 = *valp; + uimm8_in_0 = (uimm8_out_0 & 0xff); + *valp = uimm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_out_0; + unsigned uimm8x2_in_0; + uimm8x2_in_0 = *valp & 0xff; + uimm8x2_out_0 = uimm8x2_in_0 << 1; + *valp = uimm8x2_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) +{ + unsigned uimm8x2_in_0; + unsigned uimm8x2_out_0; + uimm8x2_out_0 = *valp; + uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); + *valp = uimm8x2_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_out_0; + unsigned uimm8x4_in_0; + uimm8x4_in_0 = *valp & 0xff; + uimm8x4_out_0 = uimm8x4_in_0 << 2; + *valp = uimm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) +{ + unsigned uimm8x4_in_0; + unsigned uimm8x4_out_0; + uimm8x4_out_0 = *valp; + uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); + *valp = uimm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_out_0; + unsigned uimm4x16_in_0; + uimm4x16_in_0 = *valp & 0xf; + uimm4x16_out_0 = uimm4x16_in_0 << 4; + *valp = uimm4x16_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) +{ + unsigned uimm4x16_in_0; + unsigned uimm4x16_out_0; + uimm4x16_out_0 = *valp; + uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); + *valp = uimm4x16_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) +{ + unsigned uimmrx4_out_0; + unsigned uimmrx4_in_0; + uimmrx4_in_0 = *valp & 0xf; + uimmrx4_out_0 = uimmrx4_in_0 << 2; + *valp = uimmrx4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) +{ + unsigned uimmrx4_in_0; + unsigned uimmrx4_out_0; + uimmrx4_out_0 = *valp; + uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); + *valp = uimmrx4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_decode (uint32 *valp) +{ + unsigned simm8_out_0; + unsigned simm8_in_0; + simm8_in_0 = *valp & 0xff; + simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; + *valp = simm8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8_encode (uint32 *valp) +{ + unsigned simm8_in_0; + unsigned simm8_out_0; + simm8_out_0 = *valp; + simm8_in_0 = (simm8_out_0 & 0xff); + *valp = simm8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_out_0; + unsigned simm8x256_in_0; + simm8x256_in_0 = *valp & 0xff; + simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; + *valp = simm8x256_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) +{ + unsigned simm8x256_in_0; + unsigned simm8x256_out_0; + simm8x256_out_0 = *valp; + simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); + *valp = simm8x256_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_out_0; + unsigned simm12b_in_0; + simm12b_in_0 = *valp & 0xfff; + simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; + *valp = simm12b_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_simm12b_encode (uint32 *valp) +{ + unsigned simm12b_in_0; + unsigned simm12b_out_0; + simm12b_out_0 = *valp; + simm12b_in_0 = (simm12b_out_0 & 0xfff); + *valp = simm12b_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_out_0; + unsigned msalp32_in_0; + msalp32_in_0 = *valp & 0x1f; + msalp32_out_0 = 0x20 - msalp32_in_0; + *valp = msalp32_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_msalp32_encode (uint32 *valp) +{ + unsigned msalp32_in_0; + unsigned msalp32_out_0; + msalp32_out_0 = *valp; + msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; + *valp = msalp32_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_out_0; + unsigned op2p1_in_0; + op2p1_in_0 = *valp & 0xf; + op2p1_out_0 = op2p1_in_0 + 0x1; + *valp = op2p1_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_op2p1_encode (uint32 *valp) +{ + unsigned op2p1_in_0; + unsigned op2p1_out_0; + op2p1_out_0 = *valp; + op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; + *valp = op2p1_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_decode (uint32 *valp) +{ + unsigned label8_out_0; + unsigned label8_in_0; + label8_in_0 = *valp & 0xff; + label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); + *valp = label8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label8_encode (uint32 *valp) +{ + unsigned label8_in_0; + unsigned label8_out_0; + label8_out_0 = *valp; + label8_in_0 = (label8_out_0 - 0x4) & 0xff; + *valp = label8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_out_0; + unsigned ulabel8_in_0; + ulabel8_in_0 = *valp & 0xff; + ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); + *valp = ulabel8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) +{ + unsigned ulabel8_in_0; + unsigned ulabel8_out_0; + ulabel8_out_0 = *valp; + ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; + *valp = ulabel8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_decode (uint32 *valp) +{ + unsigned label12_out_0; + unsigned label12_in_0; + label12_in_0 = *valp & 0xfff; + label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); + *valp = label12_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_label12_encode (uint32 *valp) +{ + unsigned label12_in_0; + unsigned label12_out_0; + label12_out_0 = *valp; + label12_in_0 = (label12_out_0 - 0x4) & 0xfff; + *valp = label12_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_decode (uint32 *valp) +{ + unsigned soffset_out_0; + unsigned soffset_in_0; + soffset_in_0 = *valp & 0x3ffff; + soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); + *valp = soffset_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_soffset_encode (uint32 *valp) +{ + unsigned soffset_in_0; + unsigned soffset_out_0; + soffset_out_0 = *valp; + soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; + *valp = soffset_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_out_0; + unsigned uimm16x4_in_0; + uimm16x4_in_0 = *valp & 0xffff; + uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; + *valp = uimm16x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) +{ + unsigned uimm16x4_in_0; + unsigned uimm16x4_out_0; + uimm16x4_out_0 = *valp; + uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; + *valp = uimm16x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_1_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_3_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_MR_5_encode (uint32 *valp) +{ + int error; + error = (*valp >= 4); + return error; +} + +static int +OperandSem_opnd_sem_imms_decode (uint32 *valp) +{ + unsigned imms_out_0; + unsigned imms_in_0; + imms_in_0 = *valp & 0xf; + imms_out_0 = imms_in_0; + *valp = imms_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imms_encode (uint32 *valp) +{ + unsigned imms_in_0; + unsigned imms_out_0; + imms_out_0 = *valp; + imms_in_0 = imms_out_0 & 0xf; + *valp = imms_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_BR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_BR2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +OperandSem_opnd_sem_BR2_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 1) != 0); + *valp = *valp >> 1; + return error; +} + +static int +OperandSem_opnd_sem_BR4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +OperandSem_opnd_sem_BR4_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 3) != 0); + *valp = *valp >> 2; + return error; +} + +static int +OperandSem_opnd_sem_BR8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +OperandSem_opnd_sem_BR8_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 7) != 0); + *valp = *valp >> 3; + return error; +} + +static int +OperandSem_opnd_sem_BR16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +OperandSem_opnd_sem_BR16_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16) || ((*valp & 15) != 0); + *valp = *valp >> 4; + return error; +} + +static int +OperandSem_opnd_sem_tp7_decode (uint32 *valp) +{ + unsigned tp7_out_0; + unsigned tp7_in_0; + tp7_in_0 = *valp & 0xf; + tp7_out_0 = tp7_in_0 + 0x7; + *valp = tp7_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_tp7_encode (uint32 *valp) +{ + unsigned tp7_in_0; + unsigned tp7_out_0; + tp7_out_0 = *valp; + tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; + *valp = tp7_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_out_0; + unsigned xt_wbr15_label_in_0; + xt_wbr15_label_in_0 = *valp & 0x7fff; + xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); + *valp = xt_wbr15_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_label_in_0; + unsigned xt_wbr15_label_out_0; + xt_wbr15_label_out_0 = *valp; + xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_out_0; + unsigned xt_wbr18_label_in_0; + xt_wbr18_label_in_0 = *valp & 0x3ffff; + xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14); + *valp = xt_wbr18_label_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_label_in_0; + unsigned xt_wbr18_label_out_0; + xt_wbr18_label_out_0 = *valp; + xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_label_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_FR_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +OperandSem_opnd_sem_FR_encode (uint32 *valp) +{ + int error; + error = (*valp >= 16); + return error; +} + +static int +OperandSem_opnd_sem_imm_t_decode (uint32 *valp) +{ + unsigned imm_t_out_0; + unsigned imm_t_in_0; + imm_t_in_0 = *valp & 0xf; + imm_t_out_0 = (0 << 4) | imm_t_in_0; + *valp = imm_t_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm_t_encode (uint32 *valp) +{ + unsigned imm_t_in_0; + unsigned imm_t_out_0; + imm_t_out_0 = *valp; + imm_t_in_0 = (imm_t_out_0 & 0xf); + *valp = imm_t_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm8x4_decode (uint32 *valp) +{ + unsigned imm8x4_out_0; + unsigned imm8x4_in_0; + imm8x4_in_0 = *valp & 0xff; + imm8x4_out_0 = (0 << 10) | (imm8x4_in_0 << 2) | 0; + *valp = imm8x4_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm8x4_encode (uint32 *valp) +{ + unsigned imm8x4_in_0; + unsigned imm8x4_out_0; + imm8x4_out_0 = *valp; + imm8x4_in_0 = ((imm8x4_out_0 >> 2) & 0xff); + *valp = imm8x4_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm8x8_decode (uint32 *valp) +{ + unsigned imm8x8_out_0; + unsigned imm8x8_in_0; + imm8x8_in_0 = *valp & 0xff; + imm8x8_out_0 = (0 << 11) | (imm8x8_in_0 << 3) | 0; + *valp = imm8x8_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_imm8x8_encode (uint32 *valp) +{ + unsigned imm8x8_in_0; + unsigned imm8x8_out_0; + imm8x8_out_0 = *valp; + imm8x8_in_0 = ((imm8x8_out_0 >> 3) & 0xff); + *valp = imm8x8_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_decode (uint32 *valp) +{ + unsigned bbi_out_0; + unsigned bbi_in_0; + bbi_in_0 = *valp & 0x1f; + bbi_out_0 = (0 << 5) | bbi_in_0; + *valp = bbi_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bbi_encode (uint32 *valp) +{ + unsigned bbi_in_0; + unsigned bbi_out_0; + bbi_out_0 = *valp; + bbi_in_0 = (bbi_out_0 & 0x1f); + *valp = bbi_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_decode (uint32 *valp) +{ + unsigned s_out_0; + unsigned s_in_0; + s_in_0 = *valp & 0xf; + s_out_0 = (0 << 4) | s_in_0; + *valp = s_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_s_encode (uint32 *valp) +{ + unsigned s_in_0; + unsigned s_out_0; + s_out_0 = *valp; + s_in_0 = (s_out_0 & 0xf); + *valp = s_in_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_decode (uint32 *valp) +{ + unsigned bitindex_out_0; + unsigned bitindex_in_0; + bitindex_in_0 = *valp & 0x1f; + bitindex_out_0 = (0 << 5) | bitindex_in_0; + *valp = bitindex_out_0; + return 0; +} + +static int +OperandSem_opnd_sem_bitindex_encode (uint32 *valp) +{ + unsigned bitindex_in_0; + unsigned bitindex_out_0; + bitindex_out_0 = *valp; + bitindex_in_0 = (bitindex_out_0 & 0x1f); + *valp = bitindex_in_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "immr", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immr_encode, OperandSem_opnd_sem_immr_decode, + 0, 0 }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, + 0, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, + 0, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, + 0, 0 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, + 0, 0 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, + 0, 0 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_8_encode, OperandSem_opnd_sem_AR_8_decode, + 0, 0 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_AR_12_encode, OperandSem_opnd_sem_AR_12_decode, + 0, 0 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_AR_entry_encode, OperandSem_opnd_sem_AR_entry_decode, + 0, 0 }, + { "immrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, + 0, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, + 0, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, + 0, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, + 0, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, + 0, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, + 0, 0 }, + { "immt", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, + 0, 0 }, + { "uimms8", FIELD_imms8, -1, 0, + 0, + OperandSem_opnd_sem_uimms8_encode, OperandSem_opnd_sem_uimms8_decode, + 0, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, + 0, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, + 0, 0 }, + { "uimmrx4", FIELD_r, -1, 0, + 0, + OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, + 0, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, + 0, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, + 0, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, + 0, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, + 0, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, + 0, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "mx", FIELD_x, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode, + 0, 0 }, + { "my", FIELD_y, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, + OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode, + 0, 0 }, + { "mw", FIELD_w, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode, + 0, 0 }, + { "mr0", FIELD__mr0, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode, + 0, 0 }, + { "mr1", FIELD__mr1, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode, + 0, 0 }, + { "mr2", FIELD__mr2, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode, + 0, 0 }, + { "mr3", FIELD__mr3, REGFILE_MR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode, + 0, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0 }, + { "imms1", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode, + 0, 0 }, + { "bt", FIELD_t, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "bs", FIELD_s, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "br", FIELD_r, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, + 0, 0 }, + { "bt2", FIELD_t2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "bs2", FIELD_s2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "br2", FIELD_r2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, + 0, 0 }, + { "bt4", FIELD_t4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "bs4", FIELD_s4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "br4", FIELD_r4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, + 0, 0 }, + { "bt8", FIELD_t8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "bs8", FIELD_s8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "br8", FIELD_r8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, + 0, 0 }, + { "bt16", FIELD__bt16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "bs16", FIELD__bs16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "br16", FIELD__br16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "brall", FIELD__brall, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, + 0, 0 }, + { "tp7", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "frr", FIELD_r, REGFILE_FR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode, + 0, 0 }, + { "frs", FIELD_s, REGFILE_FR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode, + 0, 0 }, + { "frt", FIELD_t, REGFILE_FR, 1, + XTENSA_OPERAND_IS_REGISTER, + OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode, + 0, 0 }, + { "imm_t", FIELD_t, -1, 0, + 0, + OperandSem_opnd_sem_imm_t_encode, OperandSem_opnd_sem_imm_t_decode, + 0, 0 }, + { "imm_s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_imm_t_encode, OperandSem_opnd_sem_imm_t_decode, + 0, 0 }, + { "imm8x4", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_imm8x4_encode, OperandSem_opnd_sem_imm8x4_decode, + 0, 0 }, + { "imm8x8", FIELD_imm8, -1, 0, + 0, + OperandSem_opnd_sem_imm8x8_encode, OperandSem_opnd_sem_imm8x8_decode, + 0, 0 }, + { "bbi", FIELD_bbi, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sae", FIELD_sae, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sas", FIELD_sas, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "sargt", FIELD_sargt, -1, 0, + 0, + OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, + 0, 0 }, + { "s", FIELD_s, -1, 0, + 0, + OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, + 0, 0 }, + { "bitindex", FIELD_bitindex, -1, 0, + 0, + OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode, + 0, 0 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "imms8", FIELD_imms8, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "r_disp", FIELD_r_disp, -1, 0, 0, 0, 0, 0, 0 }, + { "r_3", FIELD_r_3, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, + { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, + { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, + { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, + { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, + { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, + { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, + { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, + { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, + { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, + { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, + { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, + { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, + { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, + { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_immr, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_immt, + OPERAND_uimms8, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_uimmrx4, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_mx, + OPERAND_my, + OPERAND_mw, + OPERAND_mr0, + OPERAND_mr1, + OPERAND_mr2, + OPERAND_mr3, + OPERAND_imms, + OPERAND_imms1, + OPERAND_bt, + OPERAND_bs, + OPERAND_br, + OPERAND_bt2, + OPERAND_bs2, + OPERAND_br2, + OPERAND_bt4, + OPERAND_bs4, + OPERAND_br4, + OPERAND_bt8, + OPERAND_bs8, + OPERAND_br8, + OPERAND_bt16, + OPERAND_bs16, + OPERAND_br16, + OPERAND_brall, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_frr, + OPERAND_frs, + OPERAND_frt, + OPERAND_imm_t, + OPERAND_imm_s, + OPERAND_imm8x4, + OPERAND_imm8x8, + OPERAND_bbi, + OPERAND_sae, + OPERAND_sas, + OPERAND_sargt, + OPERAND_s, + OPERAND_bitindex, + OPERAND_t, + OPERAND_bbi4, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_s8, + OPERAND_imms8, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_r_disp, + OPERAND_r_3, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sal, + OPERAND_sas4, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_r3, + OPERAND_rbit2, + OPERAND_rhi, + OPERAND_t3, + OPERAND_tbit2, + OPERAND_tlo, + OPERAND_w, + OPERAND_y, + OPERAND_x, + OPERAND_t2, + OPERAND_s2, + OPERAND_r2, + OPERAND_t4, + OPERAND_s4, + OPERAND_r4, + OPERAND_t8, + OPERAND_r8, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_s3to1 +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_simcall_args[] = { + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimmrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPC7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCSAVE7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EPS7 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_MISC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_mul32_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { + { { STATE_ACC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_mx }, 'i' }, + { { OPERAND_my }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { + { { OPERAND_mw }, 'o' }, + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_mr3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_mr3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_mr3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { + { { STATE_ACC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPC7 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_EPS7 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_InOCDMode }, 'i' }, + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_bs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { + { { OPERAND_bs }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_brall }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_brall }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_brall }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CCOMPARE2 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { + { { OPERAND_ars }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdcw_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdcw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldcw_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldcw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'm' }, + { { STATE_EXCVADDR }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'i' }, + { { STATE_ASID2 }, 'i' }, + { { STATE_ASID1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'o' }, + { { STATE_ASID2 }, 'o' }, + { { STATE_ASID1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'm' }, + { { STATE_ASID2 }, 'm' }, + { { STATE_ASID1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID6 }, 'i' }, + { { STATE_INSTPGSZID5 }, 'i' }, + { { STATE_INSTPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID6 }, 'o' }, + { { STATE_INSTPGSZID5 }, 'o' }, + { { STATE_INSTPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID6 }, 'm' }, + { { STATE_INSTPGSZID5 }, 'm' }, + { { STATE_INSTPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID6 }, 'i' }, + { { STATE_DATAPGSZID5 }, 'i' }, + { { STATE_DATAPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID6 }, 'o' }, + { { STATE_DATAPGSZID5 }, 'o' }, + { { STATE_DATAPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID6 }, 'm' }, + { { STATE_DATAPGSZID5 }, 'm' }, + { { STATE_DATAPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_XTSYNC }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ERACCESS }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { + { { STATE_ERACCESS }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InvalidEnable }, 'i' }, + { { STATE_DivZeroEnable }, 'i' }, + { { STATE_OverflowEnable }, 'i' }, + { { STATE_UnderflowEnable }, 'i' }, + { { STATE_InexactEnable }, 'i' }, + { { STATE_FPreserved20 }, 'i' }, + { { STATE_FPreserved5 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_InvalidEnable }, 'o' }, + { { STATE_DivZeroEnable }, 'o' }, + { { STATE_OverflowEnable }, 'o' }, + { { STATE_UnderflowEnable }, 'o' }, + { { STATE_InexactEnable }, 'o' }, + { { STATE_FPreserved20 }, 'o' }, + { { STATE_FPreserved5 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_FPreserved20a }, 'i' }, + { { STATE_FPreserved7 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_FPreserved20a }, 'o' }, + { { STATE_FPreserved7 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { + { { OPERAND_bitindex }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSI_args[] = { + { { OPERAND_frt }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_imm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSIP_args[] = { + { { OPERAND_frt }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_imm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSX_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSX_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSXP_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_LSXP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSI_args[] = { + { { OPERAND_frt }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_imm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSIP_args[] = { + { { OPERAND_frt }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_imm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSX_args[] = { + { { OPERAND_frr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSX_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSXP_args[] = { + { { OPERAND_frr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_SSXP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_LDI_args[] = { + { { OPERAND_frt }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_imm8x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_LDI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_LDIP_args[] = { + { { OPERAND_frt }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_imm8x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_LDIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_LDX_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_LDX_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_LDXP_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_LDXP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SDI_args[] = { + { { OPERAND_frt }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_imm8x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_SDI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SDIP_args[] = { + { { OPERAND_frt }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_imm8x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_SDIP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SDX_args[] = { + { { OPERAND_frr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_SDX_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SDXP_args[] = { + { { OPERAND_frr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_SDXP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_ABS_D_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEG_D_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOV_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOV_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOV_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOV_D_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVEQZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVNEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVLTZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVGEZ_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVF_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MOVT_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFRD_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_RFRD_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFRD_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_WFRD_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ROUND_S_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_ROUND_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ROUND_D_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_ROUND_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CEIL_S_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_CEIL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CEIL_D_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_CEIL_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOOR_S_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOOR_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOOR_D_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOOR_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_D_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_TRUNC_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_D_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_UTRUNC_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_FLOAT_D_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_S_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_imm_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_UFLOAT_D_stateArgs[] = { + { { STATE_InexactFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTD_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTS_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_CVTS_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_D_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_UN_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_D_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULT_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_D_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_ULE_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_D_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_UEQ_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_D_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLT_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_D_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_OLE_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_D_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_OEQ_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADD_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_SUB_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MUL_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_D_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADD_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_D_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MSUB_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_SQRT0_D_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIV0_D_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_RECIP0_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_RSQRT0_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_D_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_MADDN_D_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_S_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_D_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_DIVN_D_stateArgs[] = { + { { STATE_OverflowFlag }, 'm' }, + { { STATE_UnderflowFlag }, 'm' }, + { { STATE_InexactFlag }, 'm' }, + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_imm_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_imm_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_CONST_D_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_NEXP01_D_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_D_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXP_D_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_S_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_D_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_ADDEXPM_D_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_D_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKDADJ_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_DivZeroFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_S_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_D_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_MKSADJ_D_stateArgs[] = { + { { STATE_InvalidFlag }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_simcall_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32nb_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_memctl_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_memctl_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_memctl_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid0_args, + 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_configid0_args, + 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_configid1_args, + 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc7_args, + 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc7_args, + 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc7_args, + 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave7_args, + 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave7_args, + 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave7_args, + 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps7_args, + 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps7_args, + 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps7_args, + 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc0_args, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc0_args, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc0_args, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_misc1_args, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_misc1_args, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_misc1_args, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_salt_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_mul32_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_aa_args, + 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_ad_args, + 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_da_args, + 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_dd_args, + 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_aa_args, + 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_ad_args, + 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_da_args, + 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16a_dd_args, + 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_da_args, + 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, + { 4, Iclass_xt_iclass_mac16al_dd_args, + 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_mac16_l_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m2_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_rsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wsr_m3_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_xsr_m3_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acclo_args, + 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acclo_args, + 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acclo_args, + 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_acchi_args, + 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_acchi_args, + 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_acchi_args, + 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_lddr32_p_args, + 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sddr32_p_args, + 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 2, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_bbool1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbranch_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bmove_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_RSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_WSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_XSR_BR_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare2_args, + 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare2_args, + 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare2_args, + 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_dcache_dyn_args, + 2, Iclass_xt_iclass_dcache_dyn_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_sdcw_args, + 2, Iclass_xt_iclass_sdcw_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ldcw_args, + 2, Iclass_xt_iclass_ldcw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ptevaddr_args, + 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ptevaddr_args, + 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ptevaddr_args, + 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_rasid_args, + 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_rasid_args, + 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_rasid_args, + 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_itlbcfg_args, + 5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_itlbcfg_args, + 6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_itlbcfg_args, + 6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, + 5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, + 6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, + 6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_ldpte */, + 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwitlba */, + 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwdtlba */, + 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_div_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eraccess_args, + 3, Iclass_xt_iclass_rsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eraccess_args, + 3, Iclass_xt_iclass_wsr_eraccess_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eraccess_args, + 3, Iclass_xt_iclass_xsr_eraccess_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rer_args, + 3, Iclass_xt_iclass_rer_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_wer_args, + 3, Iclass_xt_iclass_wer_stateArgs, 0, 0 }, + { 1, Iclass_rur_fcr_args, + 9, Iclass_rur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fcr_args, + 9, Iclass_wur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_rur_fsr_args, + 8, Iclass_rur_fsr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fsr_args, + 8, Iclass_wur_fsr_stateArgs, 0, 0 }, + { 1, Iclass_iclass_READ_IMPWIRE_args, + 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, + { 1, Iclass_iclass_SETB_EXPSTATE_args, + 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRB_EXPSTATE_args, + 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, + { 2, Iclass_iclass_WRMSK_EXPSTATE_args, + 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 2, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 2, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 3, Iclass_LSI_args, + 1, Iclass_LSI_stateArgs, 0, 0 }, + { 3, Iclass_LSIP_args, + 1, Iclass_LSIP_stateArgs, 0, 0 }, + { 3, Iclass_LSX_args, + 1, Iclass_LSX_stateArgs, 0, 0 }, + { 3, Iclass_LSXP_args, + 1, Iclass_LSXP_stateArgs, 0, 0 }, + { 3, Iclass_SSI_args, + 1, Iclass_SSI_stateArgs, 0, 0 }, + { 3, Iclass_SSIP_args, + 1, Iclass_SSIP_stateArgs, 0, 0 }, + { 3, Iclass_SSX_args, + 1, Iclass_SSX_stateArgs, 0, 0 }, + { 3, Iclass_SSXP_args, + 1, Iclass_SSXP_stateArgs, 0, 0 }, + { 3, Iclass_LDI_args, + 1, Iclass_LDI_stateArgs, 0, 0 }, + { 3, Iclass_LDIP_args, + 1, Iclass_LDIP_stateArgs, 0, 0 }, + { 3, Iclass_LDX_args, + 1, Iclass_LDX_stateArgs, 0, 0 }, + { 3, Iclass_LDXP_args, + 1, Iclass_LDXP_stateArgs, 0, 0 }, + { 3, Iclass_SDI_args, + 1, Iclass_SDI_stateArgs, 0, 0 }, + { 3, Iclass_SDIP_args, + 1, Iclass_SDIP_stateArgs, 0, 0 }, + { 3, Iclass_SDX_args, + 1, Iclass_SDX_stateArgs, 0, 0 }, + { 3, Iclass_SDXP_args, + 1, Iclass_SDXP_stateArgs, 0, 0 }, + { 2, Iclass_ABS_S_args, + 1, Iclass_ABS_S_stateArgs, 0, 0 }, + { 2, Iclass_NEG_S_args, + 1, Iclass_NEG_S_stateArgs, 0, 0 }, + { 2, Iclass_ABS_D_args, + 1, Iclass_ABS_D_stateArgs, 0, 0 }, + { 2, Iclass_NEG_D_args, + 1, Iclass_NEG_D_stateArgs, 0, 0 }, + { 2, Iclass_MOV_S_args, + 1, Iclass_MOV_S_stateArgs, 0, 0 }, + { 2, Iclass_MOV_D_args, + 1, Iclass_MOV_D_stateArgs, 0, 0 }, + { 3, Iclass_MOVEQZ_S_args, + 1, Iclass_MOVEQZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVNEZ_S_args, + 1, Iclass_MOVNEZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVLTZ_S_args, + 1, Iclass_MOVLTZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVGEZ_S_args, + 1, Iclass_MOVGEZ_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVF_S_args, + 1, Iclass_MOVF_S_stateArgs, 0, 0 }, + { 3, Iclass_MOVT_S_args, + 1, Iclass_MOVT_S_stateArgs, 0, 0 }, + { 2, Iclass_WFR_args, + 1, Iclass_WFR_stateArgs, 0, 0 }, + { 2, Iclass_RFR_args, + 1, Iclass_RFR_stateArgs, 0, 0 }, + { 2, Iclass_RFRD_args, + 1, Iclass_RFRD_stateArgs, 0, 0 }, + { 3, Iclass_WFRD_args, + 1, Iclass_WFRD_stateArgs, 0, 0 }, + { 3, Iclass_ROUND_S_args, + 3, Iclass_ROUND_S_stateArgs, 0, 0 }, + { 3, Iclass_ROUND_D_args, + 3, Iclass_ROUND_D_stateArgs, 0, 0 }, + { 3, Iclass_CEIL_S_args, + 3, Iclass_CEIL_S_stateArgs, 0, 0 }, + { 3, Iclass_CEIL_D_args, + 3, Iclass_CEIL_D_stateArgs, 0, 0 }, + { 3, Iclass_FLOOR_S_args, + 3, Iclass_FLOOR_S_stateArgs, 0, 0 }, + { 3, Iclass_FLOOR_D_args, + 3, Iclass_FLOOR_D_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC_S_args, + 3, Iclass_TRUNC_S_stateArgs, 0, 0 }, + { 3, Iclass_TRUNC_D_args, + 3, Iclass_TRUNC_D_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC_S_args, + 3, Iclass_UTRUNC_S_stateArgs, 0, 0 }, + { 3, Iclass_UTRUNC_D_args, + 3, Iclass_UTRUNC_D_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT_S_args, + 3, Iclass_FLOAT_S_stateArgs, 0, 0 }, + { 3, Iclass_FLOAT_D_args, + 2, Iclass_FLOAT_D_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT_S_args, + 3, Iclass_UFLOAT_S_stateArgs, 0, 0 }, + { 3, Iclass_UFLOAT_D_args, + 2, Iclass_UFLOAT_D_stateArgs, 0, 0 }, + { 2, Iclass_CVTD_S_args, + 2, Iclass_CVTD_S_stateArgs, 0, 0 }, + { 2, Iclass_CVTS_D_args, + 6, Iclass_CVTS_D_stateArgs, 0, 0 }, + { 3, Iclass_UN_S_args, + 2, Iclass_UN_S_stateArgs, 0, 0 }, + { 3, Iclass_UN_D_args, + 2, Iclass_UN_D_stateArgs, 0, 0 }, + { 3, Iclass_ULT_S_args, + 2, Iclass_ULT_S_stateArgs, 0, 0 }, + { 3, Iclass_ULT_D_args, + 2, Iclass_ULT_D_stateArgs, 0, 0 }, + { 3, Iclass_ULE_S_args, + 2, Iclass_ULE_S_stateArgs, 0, 0 }, + { 3, Iclass_ULE_D_args, + 2, Iclass_ULE_D_stateArgs, 0, 0 }, + { 3, Iclass_UEQ_S_args, + 2, Iclass_UEQ_S_stateArgs, 0, 0 }, + { 3, Iclass_UEQ_D_args, + 2, Iclass_UEQ_D_stateArgs, 0, 0 }, + { 3, Iclass_OLT_S_args, + 2, Iclass_OLT_S_stateArgs, 0, 0 }, + { 3, Iclass_OLT_D_args, + 2, Iclass_OLT_D_stateArgs, 0, 0 }, + { 3, Iclass_OLE_S_args, + 2, Iclass_OLE_S_stateArgs, 0, 0 }, + { 3, Iclass_OLE_D_args, + 2, Iclass_OLE_D_stateArgs, 0, 0 }, + { 3, Iclass_OEQ_S_args, + 2, Iclass_OEQ_S_stateArgs, 0, 0 }, + { 3, Iclass_OEQ_D_args, + 2, Iclass_OEQ_D_stateArgs, 0, 0 }, + { 3, Iclass_ADD_S_args, + 6, Iclass_ADD_S_stateArgs, 0, 0 }, + { 3, Iclass_ADD_D_args, + 6, Iclass_ADD_D_stateArgs, 0, 0 }, + { 3, Iclass_SUB_S_args, + 6, Iclass_SUB_S_stateArgs, 0, 0 }, + { 3, Iclass_SUB_D_args, + 6, Iclass_SUB_D_stateArgs, 0, 0 }, + { 3, Iclass_MUL_S_args, + 6, Iclass_MUL_S_stateArgs, 0, 0 }, + { 3, Iclass_MUL_D_args, + 6, Iclass_MUL_D_stateArgs, 0, 0 }, + { 3, Iclass_MADD_S_args, + 6, Iclass_MADD_S_stateArgs, 0, 0 }, + { 3, Iclass_MADD_D_args, + 6, Iclass_MADD_D_stateArgs, 0, 0 }, + { 3, Iclass_MSUB_S_args, + 6, Iclass_MSUB_S_stateArgs, 0, 0 }, + { 3, Iclass_MSUB_D_args, + 6, Iclass_MSUB_D_stateArgs, 0, 0 }, + { 2, Iclass_SQRT0_S_args, + 1, Iclass_SQRT0_S_stateArgs, 0, 0 }, + { 2, Iclass_SQRT0_D_args, + 1, Iclass_SQRT0_D_stateArgs, 0, 0 }, + { 2, Iclass_DIV0_S_args, + 1, Iclass_DIV0_S_stateArgs, 0, 0 }, + { 2, Iclass_DIV0_D_args, + 1, Iclass_DIV0_D_stateArgs, 0, 0 }, + { 2, Iclass_RECIP0_S_args, + 3, Iclass_RECIP0_S_stateArgs, 0, 0 }, + { 2, Iclass_RECIP0_D_args, + 3, Iclass_RECIP0_D_stateArgs, 0, 0 }, + { 2, Iclass_RSQRT0_S_args, + 3, Iclass_RSQRT0_S_stateArgs, 0, 0 }, + { 2, Iclass_RSQRT0_D_args, + 3, Iclass_RSQRT0_D_stateArgs, 0, 0 }, + { 3, Iclass_MADDN_S_args, + 1, Iclass_MADDN_S_stateArgs, 0, 0 }, + { 3, Iclass_MADDN_D_args, + 1, Iclass_MADDN_D_stateArgs, 0, 0 }, + { 3, Iclass_DIVN_S_args, + 5, Iclass_DIVN_S_stateArgs, 0, 0 }, + { 3, Iclass_DIVN_D_args, + 5, Iclass_DIVN_D_stateArgs, 0, 0 }, + { 2, Iclass_CONST_S_args, + 1, Iclass_CONST_S_stateArgs, 0, 0 }, + { 2, Iclass_CONST_D_args, + 1, Iclass_CONST_D_stateArgs, 0, 0 }, + { 2, Iclass_NEXP01_S_args, + 1, Iclass_NEXP01_S_stateArgs, 0, 0 }, + { 2, Iclass_NEXP01_D_args, + 1, Iclass_NEXP01_D_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXP_S_args, + 1, Iclass_ADDEXP_S_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXP_D_args, + 1, Iclass_ADDEXP_D_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXPM_S_args, + 1, Iclass_ADDEXPM_S_stateArgs, 0, 0 }, + { 2, Iclass_ADDEXPM_D_args, + 1, Iclass_ADDEXPM_D_stateArgs, 0, 0 }, + { 2, Iclass_MKDADJ_S_args, + 3, Iclass_MKDADJ_S_stateArgs, 0, 0 }, + { 2, Iclass_MKDADJ_D_args, + 3, Iclass_MKDADJ_D_stateArgs, 0, 0 }, + { 2, Iclass_MKSADJ_S_args, + 2, Iclass_MKSADJ_S_stateArgs, 0, 0 }, + { 2, Iclass_MKSADJ_D_args, + 2, Iclass_MKSADJ_D_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s32nb, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_memctl, + ICLASS_xt_iclass_wsr_memctl, + ICLASS_xt_iclass_xsr_memctl, + ICLASS_xt_iclass_rsr_configid0, + ICLASS_xt_iclass_wsr_configid0, + ICLASS_xt_iclass_rsr_configid1, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_epc6, + ICLASS_xt_iclass_wsr_epc6, + ICLASS_xt_iclass_xsr_epc6, + ICLASS_xt_iclass_rsr_excsave6, + ICLASS_xt_iclass_wsr_excsave6, + ICLASS_xt_iclass_xsr_excsave6, + ICLASS_xt_iclass_rsr_epc7, + ICLASS_xt_iclass_wsr_epc7, + ICLASS_xt_iclass_xsr_epc7, + ICLASS_xt_iclass_rsr_excsave7, + ICLASS_xt_iclass_wsr_excsave7, + ICLASS_xt_iclass_xsr_excsave7, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_eps6, + ICLASS_xt_iclass_wsr_eps6, + ICLASS_xt_iclass_xsr_eps6, + ICLASS_xt_iclass_rsr_eps7, + ICLASS_xt_iclass_wsr_eps7, + ICLASS_xt_iclass_xsr_eps7, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_misc0, + ICLASS_xt_iclass_wsr_misc0, + ICLASS_xt_iclass_xsr_misc0, + ICLASS_xt_iclass_rsr_misc1, + ICLASS_xt_iclass_wsr_misc1, + ICLASS_xt_iclass_xsr_misc1, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_iclass_salt, + ICLASS_xt_mul16, + ICLASS_xt_mul32, + ICLASS_xt_iclass_mac16_aa, + ICLASS_xt_iclass_mac16_ad, + ICLASS_xt_iclass_mac16_da, + ICLASS_xt_iclass_mac16_dd, + ICLASS_xt_iclass_mac16a_aa, + ICLASS_xt_iclass_mac16a_ad, + ICLASS_xt_iclass_mac16a_da, + ICLASS_xt_iclass_mac16a_dd, + ICLASS_xt_iclass_mac16al_da, + ICLASS_xt_iclass_mac16al_dd, + ICLASS_xt_iclass_mac16_l, + ICLASS_xt_iclass_rsr_m0, + ICLASS_xt_iclass_wsr_m0, + ICLASS_xt_iclass_xsr_m0, + ICLASS_xt_iclass_rsr_m1, + ICLASS_xt_iclass_wsr_m1, + ICLASS_xt_iclass_xsr_m1, + ICLASS_xt_iclass_rsr_m2, + ICLASS_xt_iclass_wsr_m2, + ICLASS_xt_iclass_xsr_m2, + ICLASS_xt_iclass_rsr_m3, + ICLASS_xt_iclass_wsr_m3, + ICLASS_xt_iclass_xsr_m3, + ICLASS_xt_iclass_rsr_acclo, + ICLASS_xt_iclass_wsr_acclo, + ICLASS_xt_iclass_xsr_acclo, + ICLASS_xt_iclass_rsr_acchi, + ICLASS_xt_iclass_wsr_acchi, + ICLASS_xt_iclass_xsr_acchi, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_lddr32_p, + ICLASS_xt_iclass_sddr32_p, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_bbool1, + ICLASS_xt_iclass_bbool4, + ICLASS_xt_iclass_bbool8, + ICLASS_xt_iclass_bbranch, + ICLASS_xt_iclass_bmove, + ICLASS_xt_iclass_RSR_BR, + ICLASS_xt_iclass_WSR_BR, + ICLASS_xt_iclass_XSR_BR, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_rsr_ccompare2, + ICLASS_xt_iclass_wsr_ccompare2, + ICLASS_xt_iclass_xsr_ccompare2, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_dcache, + ICLASS_xt_iclass_dcache_dyn, + ICLASS_xt_iclass_dcache_ind, + ICLASS_xt_iclass_dcache_inv, + ICLASS_xt_iclass_dpf, + ICLASS_xt_iclass_dcache_lock, + ICLASS_xt_iclass_sdct, + ICLASS_xt_iclass_ldct, + ICLASS_xt_iclass_sdcw, + ICLASS_xt_iclass_ldcw, + ICLASS_xt_iclass_wsr_ptevaddr, + ICLASS_xt_iclass_rsr_ptevaddr, + ICLASS_xt_iclass_xsr_ptevaddr, + ICLASS_xt_iclass_rsr_rasid, + ICLASS_xt_iclass_wsr_rasid, + ICLASS_xt_iclass_xsr_rasid, + ICLASS_xt_iclass_rsr_itlbcfg, + ICLASS_xt_iclass_wsr_itlbcfg, + ICLASS_xt_iclass_xsr_itlbcfg, + ICLASS_xt_iclass_rsr_dtlbcfg, + ICLASS_xt_iclass_wsr_dtlbcfg, + ICLASS_xt_iclass_xsr_dtlbcfg, + ICLASS_xt_iclass_idtlb, + ICLASS_xt_iclass_rdtlb, + ICLASS_xt_iclass_wdtlb, + ICLASS_xt_iclass_iitlb, + ICLASS_xt_iclass_ritlb, + ICLASS_xt_iclass_witlb, + ICLASS_xt_iclass_ldpte, + ICLASS_xt_iclass_hwwitlba, + ICLASS_xt_iclass_hwwdtlba, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_s32c1i, + ICLASS_xt_iclass_rsr_scompare1, + ICLASS_xt_iclass_wsr_scompare1, + ICLASS_xt_iclass_xsr_scompare1, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_div, + ICLASS_xt_iclass_rsr_eraccess, + ICLASS_xt_iclass_wsr_eraccess, + ICLASS_xt_iclass_xsr_eraccess, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_rur_fcr, + ICLASS_wur_fcr, + ICLASS_rur_fsr, + ICLASS_wur_fsr, + ICLASS_iclass_READ_IMPWIRE, + ICLASS_iclass_SETB_EXPSTATE, + ICLASS_iclass_CLRB_EXPSTATE, + ICLASS_iclass_WRMSK_EXPSTATE, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_LSI, + ICLASS_LSIP, + ICLASS_LSX, + ICLASS_LSXP, + ICLASS_SSI, + ICLASS_SSIP, + ICLASS_SSX, + ICLASS_SSXP, + ICLASS_LDI, + ICLASS_LDIP, + ICLASS_LDX, + ICLASS_LDXP, + ICLASS_SDI, + ICLASS_SDIP, + ICLASS_SDX, + ICLASS_SDXP, + ICLASS_ABS_S, + ICLASS_NEG_S, + ICLASS_ABS_D, + ICLASS_NEG_D, + ICLASS_MOV_S, + ICLASS_MOV_D, + ICLASS_MOVEQZ_S, + ICLASS_MOVNEZ_S, + ICLASS_MOVLTZ_S, + ICLASS_MOVGEZ_S, + ICLASS_MOVF_S, + ICLASS_MOVT_S, + ICLASS_WFR, + ICLASS_RFR, + ICLASS_RFRD, + ICLASS_WFRD, + ICLASS_ROUND_S, + ICLASS_ROUND_D, + ICLASS_CEIL_S, + ICLASS_CEIL_D, + ICLASS_FLOOR_S, + ICLASS_FLOOR_D, + ICLASS_TRUNC_S, + ICLASS_TRUNC_D, + ICLASS_UTRUNC_S, + ICLASS_UTRUNC_D, + ICLASS_FLOAT_S, + ICLASS_FLOAT_D, + ICLASS_UFLOAT_S, + ICLASS_UFLOAT_D, + ICLASS_CVTD_S, + ICLASS_CVTS_D, + ICLASS_UN_S, + ICLASS_UN_D, + ICLASS_ULT_S, + ICLASS_ULT_D, + ICLASS_ULE_S, + ICLASS_ULE_D, + ICLASS_UEQ_S, + ICLASS_UEQ_D, + ICLASS_OLT_S, + ICLASS_OLT_D, + ICLASS_OLE_S, + ICLASS_OLE_D, + ICLASS_OEQ_S, + ICLASS_OEQ_D, + ICLASS_ADD_S, + ICLASS_ADD_D, + ICLASS_SUB_S, + ICLASS_SUB_D, + ICLASS_MUL_S, + ICLASS_MUL_D, + ICLASS_MADD_S, + ICLASS_MADD_D, + ICLASS_MSUB_S, + ICLASS_MSUB_D, + ICLASS_SQRT0_S, + ICLASS_SQRT0_D, + ICLASS_DIV0_S, + ICLASS_DIV0_D, + ICLASS_RECIP0_S, + ICLASS_RECIP0_D, + ICLASS_RSQRT0_S, + ICLASS_RSQRT0_D, + ICLASS_MADDN_S, + ICLASS_MADDN_D, + ICLASS_DIVN_S, + ICLASS_DIVN_D, + ICLASS_CONST_S, + ICLASS_CONST_D, + ICLASS_NEXP01_S, + ICLASS_NEXP01_D, + ICLASS_ADDEXP_S, + ICLASS_ADDEXP_D, + ICLASS_ADDEXPM_S, + ICLASS_ADDEXPM_D, + ICLASS_MKDADJ_S, + ICLASS_MKDADJ_D, + ICLASS_MKSADJ_S, + ICLASS_MKSADJ_D +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590000; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36100; +} + +static void +Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136100; +} + +static void +Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616100; +} + +static void +Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b600; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b600; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b600; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d600; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d600; +} + +static void +Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b700; +} + +static void +Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b700; +} + +static void +Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b700; +} + +static void +Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d700; +} + +static void +Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d700; +} + +static void +Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d700; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c600; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c600; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c600; +} + +static void +Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c700; +} + +static void +Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c700; +} + +static void +Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c700; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f400; +} + +static void +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f400; +} + +static void +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f400; +} + +static void +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f500; +} + +static void +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f500; +} + +static void +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f500; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720000; +} + +static void +Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x620000; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820000; +} + +static void +Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770004; +} + +static void +Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x750004; +} + +static void +Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x760004; +} + +static void +Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x740004; +} + +static void +Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730004; +} + +static void +Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x710004; +} + +static void +Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x720004; +} + +static void +Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x700004; +} + +static void +Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370004; +} + +static void +Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350004; +} + +static void +Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360004; +} + +static void +Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340004; +} + +static void +Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x670004; +} + +static void +Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x650004; +} + +static void +Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x660004; +} + +static void +Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x640004; +} + +static void +Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270004; +} + +static void +Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x250004; +} + +static void +Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x260004; +} + +static void +Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240004; +} + +static void +Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0004; +} + +static void +Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x790004; +} + +static void +Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0004; +} + +static void +Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780004; +} + +static void +Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0004; +} + +static void +Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7d0004; +} + +static void +Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0004; +} + +static void +Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0004; +} + +static void +Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0004; +} + +static void +Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x390004; +} + +static void +Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a0004; +} + +static void +Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380004; +} + +static void +Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0004; +} + +static void +Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0004; +} + +static void +Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0004; +} + +static void +Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0004; +} + +static void +Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0004; +} + +static void +Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x690004; +} + +static void +Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0004; +} + +static void +Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680004; +} + +static void +Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0004; +} + +static void +Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0004; +} + +static void +Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0004; +} + +static void +Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0004; +} + +static void +Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0004; +} + +static void +Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x290004; +} + +static void +Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0004; +} + +static void +Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280004; +} + +static void +Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0004; +} + +static void +Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0004; +} + +static void +Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0004; +} + +static void +Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0004; +} + +static void +Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0004; +} + +static void +Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0004; +} + +static void +Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x590004; +} + +static void +Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490004; +} + +static void +Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0004; +} + +static void +Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0004; +} + +static void +Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580004; +} + +static void +Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480004; +} + +static void +Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0004; +} + +static void +Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb0004; +} + +static void +Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x190004; +} + +static void +Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90004; +} + +static void +Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0004; +} + +static void +Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0004; +} + +static void +Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180004; +} + +static void +Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80004; +} + +static void +Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900004; +} + +static void +Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800004; +} + +static void +Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132000; +} + +static void +Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612000; +} + +static void +Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32100; +} + +static void +Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132100; +} + +static void +Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612100; +} + +static void +Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32200; +} + +static void +Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132200; +} + +static void +Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612200; +} + +static void +Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32300; +} + +static void +Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132300; +} + +static void +Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x612300; +} + +static void +Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31000; +} + +static void +Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131000; +} + +static void +Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611000; +} + +static void +Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31100; +} + +static void +Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131100; +} + +static void +Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x611100; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e0; +} + +static void +Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f0; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76; +} + +static void +Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1076; +} + +static void +Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400; +} + +static void +Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610400; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f200; +} + +static void +Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f200; +} + +static void +Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f200; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf7082; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27082; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37082; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7082; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_sdcw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1b000; +} + +static void +Opcode_ldcw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1a000; +} + +static void +Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135300; +} + +static void +Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35300; +} + +static void +Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615300; +} + +static void +Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a00; +} + +static void +Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135a00; +} + +static void +Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615a00; +} + +static void +Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35b00; +} + +static void +Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135b00; +} + +static void +Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615b00; +} + +static void +Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35c00; +} + +static void +Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135c00; +} + +static void +Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615c00; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50c000; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x504000; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505000; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x503000; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x507000; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x506000; +} + +static void +Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1f000; +} + +static void +Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x501000; +} + +static void +Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x509000; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30c00; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610c00; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd20000; +} + +static void +Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc20000; +} + +static void +Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf20000; +} + +static void +Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe20000; +} + +static void +Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35f00; +} + +static void +Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135f00; +} + +static void +Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x615f00; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e80; +} + +static void +Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e800; +} + +static void +Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e90; +} + +static void +Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e900; +} + +static void +Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0000; +} + +static void +Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1000; +} + +static void +Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe1200; +} + +static void +Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe2000; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e60; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e600; +} + +static void +Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_lsip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8003; +} + +static void +Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_lsxp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4003; +} + +static void +Opcode_ssip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc003; +} + +static void +Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ssxp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ldi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1003; +} + +static void +Opcode_ldip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9003; +} + +static void +Opcode_ldx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280000; +} + +static void +Opcode_ldxp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380000; +} + +static void +Opcode_sdi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5003; +} + +static void +Opcode_sdip_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003; +} + +static void +Opcode_sdx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_sdxp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0010; +} + +static void +Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0060; +} + +static void +Opcode_abs_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff0010; +} + +static void +Opcode_neg_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff0060; +} + +static void +Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0000; +} + +static void +Opcode_mov_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff0000; +} + +static void +Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b0000; +} + +static void +Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b0000; +} + +static void +Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab0000; +} + +static void +Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb0000; +} + +static void +Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb0000; +} + +static void +Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb0000; +} + +static void +Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0050; +} + +static void +Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0040; +} + +static void +Opcode_rfrd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff0040; +} + +static void +Opcode_wfrd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8e0000; +} + +static void +Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a0000; +} + +static void +Opcode_round_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8f0000; +} + +static void +Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba0000; +} + +static void +Opcode_ceil_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbf0000; +} + +static void +Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa0000; +} + +static void +Opcode_floor_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaf0000; +} + +static void +Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a0000; +} + +static void +Opcode_trunc_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9f0000; +} + +static void +Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0000; +} + +static void +Opcode_utrunc_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xef0000; +} + +static void +Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca0000; +} + +static void +Opcode_float_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcf0000; +} + +static void +Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda0000; +} + +static void +Opcode_ufloat_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdf0000; +} + +static void +Opcode_cvtd_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0020; +} + +static void +Opcode_cvts_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff0020; +} + +static void +Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_un_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0000; +} + +static void +Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0000; +} + +static void +Opcode_ult_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e0000; +} + +static void +Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0000; +} + +static void +Opcode_ule_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7e0000; +} + +static void +Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0000; +} + +static void +Opcode_ueq_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0000; +} + +static void +Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0000; +} + +static void +Opcode_olt_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_ole_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e0000; +} + +static void +Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0000; +} + +static void +Opcode_oeq_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e0000; +} + +static void +Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_add_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0000; +} + +static void +Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_sub_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0000; +} + +static void +Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0000; +} + +static void +Opcode_mul_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f0000; +} + +static void +Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_madd_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f0000; +} + +static void +Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_msub_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5f0000; +} + +static void +Opcode_sqrt0_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0090; +} + +static void +Opcode_sqrt0_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff0090; +} + +static void +Opcode_div0_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0070; +} + +static void +Opcode_div0_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff0070; +} + +static void +Opcode_recip0_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0080; +} + +static void +Opcode_recip0_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff0080; +} + +static void +Opcode_rsqrt0_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa00a0; +} + +static void +Opcode_rsqrt0_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff00a0; +} + +static void +Opcode_maddn_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0000; +} + +static void +Opcode_maddn_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6f0000; +} + +static void +Opcode_divn_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7a0000; +} + +static void +Opcode_divn_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7f0000; +} + +static void +Opcode_const_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0030; +} + +static void +Opcode_const_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff0030; +} + +static void +Opcode_nexp01_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa00b0; +} + +static void +Opcode_nexp01_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff00b0; +} + +static void +Opcode_addexp_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa00e0; +} + +static void +Opcode_addexp_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff00e0; +} + +static void +Opcode_addexpm_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa00f0; +} + +static void +Opcode_addexpm_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff00f0; +} + +static void +Opcode_mkdadj_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa00d0; +} + +static void +Opcode_mkdadj_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff00d0; +} + +static void +Opcode_mksadj_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa00c0; +} + +static void +Opcode_mksadj_d_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xff00c0; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { + Opcode_s32nb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { + Opcode_rsr_memctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { + Opcode_wsr_memctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { + Opcode_xsr_memctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { + Opcode_rsr_configid0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { + Opcode_wsr_configid0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { + Opcode_rsr_configid1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { + Opcode_rsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { + Opcode_wsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { + Opcode_xsr_epc7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { + Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { + Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { + Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { + Opcode_rsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { + Opcode_wsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { + Opcode_xsr_eps7_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { + Opcode_rsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { + Opcode_wsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { + Opcode_xsr_misc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { + Opcode_rsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { + Opcode_wsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { + Opcode_xsr_misc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = { + Opcode_salt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = { + Opcode_saltu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { + Opcode_mull_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { + Opcode_mul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { + Opcode_mul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { + Opcode_mul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { + Opcode_mul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { + Opcode_umul_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { + Opcode_umul_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { + Opcode_umul_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { + Opcode_umul_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { + Opcode_mul_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { + Opcode_mul_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { + Opcode_mul_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { + Opcode_mul_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { + Opcode_mul_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { + Opcode_mul_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { + Opcode_mul_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { + Opcode_mul_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { + Opcode_mul_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { + Opcode_mul_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { + Opcode_mul_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { + Opcode_mul_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { + Opcode_mula_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { + Opcode_mula_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { + Opcode_mula_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { + Opcode_mula_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { + Opcode_muls_aa_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { + Opcode_muls_aa_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { + Opcode_muls_aa_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { + Opcode_muls_aa_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { + Opcode_mula_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { + Opcode_mula_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { + Opcode_mula_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { + Opcode_mula_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { + Opcode_muls_ad_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { + Opcode_muls_ad_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { + Opcode_muls_ad_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { + Opcode_muls_ad_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { + Opcode_mula_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { + Opcode_mula_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { + Opcode_mula_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { + Opcode_mula_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { + Opcode_muls_da_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { + Opcode_muls_da_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { + Opcode_muls_da_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { + Opcode_muls_da_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { + Opcode_mula_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { + Opcode_mula_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { + Opcode_mula_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { + Opcode_mula_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { + Opcode_muls_dd_hh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { + Opcode_muls_dd_hl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { + Opcode_muls_dd_lh_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { + Opcode_muls_dd_ll_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { + Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { + Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { + Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { + Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { + Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { + Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { + Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { + Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { + Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { + Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { + Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { + Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { + Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { + Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { + Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { + Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { + Opcode_lddec_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { + Opcode_ldinc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { + Opcode_rsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { + Opcode_wsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { + Opcode_xsr_m0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { + Opcode_rsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { + Opcode_wsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { + Opcode_xsr_m1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { + Opcode_rsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { + Opcode_wsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { + Opcode_xsr_m2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { + Opcode_rsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { + Opcode_wsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { + Opcode_xsr_m3_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { + Opcode_rsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { + Opcode_wsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { + Opcode_xsr_acclo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { + Opcode_rsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { + Opcode_wsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { + Opcode_xsr_acchi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { + Opcode_lddr32_p_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { + Opcode_sddr32_p_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { + Opcode_andb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { + Opcode_andbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { + Opcode_orb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { + Opcode_orbc_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { + Opcode_xorb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { + Opcode_all4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { + Opcode_any4_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { + Opcode_all8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { + Opcode_any8_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { + Opcode_bf_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { + Opcode_bt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { + Opcode_movf_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { + Opcode_movt_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { + Opcode_rsr_br_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { + Opcode_wsr_br_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { + Opcode_xsr_br_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { + Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { + Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { + Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { + Opcode_diwbui_p_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdcw_encode_fns[] = { + Opcode_sdcw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldcw_encode_fns[] = { + Opcode_ldcw_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { + Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { + Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { + Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { + Opcode_rsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { + Opcode_wsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { + Opcode_xsr_rasid_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { + Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { + Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { + Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { + Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { + Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { + Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { + Opcode_ldpte_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { + Opcode_hwwitlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { + Opcode_hwwdtlba_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { + Opcode_quos_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { + Opcode_quou_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { + Opcode_rems_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { + Opcode_remu_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = { + Opcode_rsr_eraccess_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = { + Opcode_wsr_eraccess_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = { + Opcode_xsr_eraccess_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = { + Opcode_rur_fcr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = { + Opcode_wur_fcr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = { + Opcode_rur_fsr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = { + Opcode_wur_fsr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { + Opcode_read_impwire_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { + Opcode_setb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { + Opcode_clrb_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { + Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = { + Opcode_lsi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lsip_encode_fns[] = { + Opcode_lsip_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = { + Opcode_lsx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lsxp_encode_fns[] = { + Opcode_lsxp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = { + Opcode_ssi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssip_encode_fns[] = { + Opcode_ssip_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = { + Opcode_ssx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ssxp_encode_fns[] = { + Opcode_ssxp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldi_encode_fns[] = { + Opcode_ldi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldip_encode_fns[] = { + Opcode_ldip_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldx_encode_fns[] = { + Opcode_ldx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldxp_encode_fns[] = { + Opcode_ldxp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdi_encode_fns[] = { + Opcode_sdi_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdip_encode_fns[] = { + Opcode_sdip_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdx_encode_fns[] = { + Opcode_sdx_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdxp_encode_fns[] = { + Opcode_sdxp_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = { + Opcode_abs_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = { + Opcode_neg_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs_d_encode_fns[] = { + Opcode_abs_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_neg_d_encode_fns[] = { + Opcode_neg_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = { + Opcode_mov_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_d_encode_fns[] = { + Opcode_mov_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = { + Opcode_moveqz_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = { + Opcode_movnez_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = { + Opcode_movltz_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = { + Opcode_movgez_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = { + Opcode_movf_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = { + Opcode_movt_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = { + Opcode_wfr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = { + Opcode_rfr_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfrd_encode_fns[] = { + Opcode_rfrd_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wfrd_encode_fns[] = { + Opcode_wfrd_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = { + Opcode_round_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_round_d_encode_fns[] = { + Opcode_round_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = { + Opcode_ceil_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ceil_d_encode_fns[] = { + Opcode_ceil_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = { + Opcode_floor_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_floor_d_encode_fns[] = { + Opcode_floor_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = { + Opcode_trunc_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trunc_d_encode_fns[] = { + Opcode_trunc_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = { + Opcode_utrunc_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_d_encode_fns[] = { + Opcode_utrunc_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = { + Opcode_float_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_float_d_encode_fns[] = { + Opcode_float_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = { + Opcode_ufloat_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_d_encode_fns[] = { + Opcode_ufloat_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvtd_s_encode_fns[] = { + Opcode_cvtd_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cvts_d_encode_fns[] = { + Opcode_cvts_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = { + Opcode_un_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_un_d_encode_fns[] = { + Opcode_un_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = { + Opcode_ult_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ult_d_encode_fns[] = { + Opcode_ult_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = { + Opcode_ule_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ule_d_encode_fns[] = { + Opcode_ule_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = { + Opcode_ueq_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ueq_d_encode_fns[] = { + Opcode_ueq_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = { + Opcode_olt_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_olt_d_encode_fns[] = { + Opcode_olt_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = { + Opcode_ole_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ole_d_encode_fns[] = { + Opcode_ole_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = { + Opcode_oeq_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_oeq_d_encode_fns[] = { + Opcode_oeq_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = { + Opcode_add_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_d_encode_fns[] = { + Opcode_add_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = { + Opcode_sub_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub_d_encode_fns[] = { + Opcode_sub_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = { + Opcode_mul_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul_d_encode_fns[] = { + Opcode_mul_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = { + Opcode_madd_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_madd_d_encode_fns[] = { + Opcode_madd_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = { + Opcode_msub_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_msub_d_encode_fns[] = { + Opcode_msub_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sqrt0_s_encode_fns[] = { + Opcode_sqrt0_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sqrt0_d_encode_fns[] = { + Opcode_sqrt0_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_div0_s_encode_fns[] = { + Opcode_div0_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_div0_d_encode_fns[] = { + Opcode_div0_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_recip0_s_encode_fns[] = { + Opcode_recip0_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_recip0_d_encode_fns[] = { + Opcode_recip0_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsqrt0_s_encode_fns[] = { + Opcode_rsqrt0_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsqrt0_d_encode_fns[] = { + Opcode_rsqrt0_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddn_s_encode_fns[] = { + Opcode_maddn_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_maddn_d_encode_fns[] = { + Opcode_maddn_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_divn_s_encode_fns[] = { + Opcode_divn_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_divn_d_encode_fns[] = { + Opcode_divn_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_s_encode_fns[] = { + Opcode_const_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_const_d_encode_fns[] = { + Opcode_const_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp01_s_encode_fns[] = { + Opcode_nexp01_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nexp01_d_encode_fns[] = { + Opcode_nexp01_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexp_s_encode_fns[] = { + Opcode_addexp_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexp_d_encode_fns[] = { + Opcode_addexp_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexpm_s_encode_fns[] = { + Opcode_addexpm_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addexpm_d_encode_fns[] = { + Opcode_addexpm_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mkdadj_s_encode_fns[] = { + Opcode_mkdadj_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mkdadj_d_encode_fns[] = { + Opcode_mkdadj_d_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mksadj_s_encode_fns[] = { + Opcode_mksadj_s_Slot_inst_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mksadj_d_encode_fns[] = { + Opcode_mksadj_d_Slot_inst_encode, 0, 0 +}; + + + + + +/* Opcode table. */ + +static xtensa_funcUnit_use Opcode_l32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32e_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_n_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l16si_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32r_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l8ui_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s16i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32nb_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s8i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_hh_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_hh_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_hl_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_hl_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_lh_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_lh_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_ll_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_da_ll_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_hh_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_hh_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_hl_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_hl_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_lh_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_lh_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_ll_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_mula_dd_ll_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lddec_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldinc_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sddr32_p_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_licw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sict_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sicw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldct_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdcw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldcw_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldpte_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_l32ai_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32ri_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_s32c1i_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lsi_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lsip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lsx_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_lsxp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ssi_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ssip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ssx_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ssxp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldi_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldx_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_ldxp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdi_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdip_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdx_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_funcUnit_use Opcode_sdxp_funcUnit_uses[] = { + { FUNCUNIT_XT_LOADSTORE_UNIT, 0 } +}; + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 1, Opcode_l32e_funcUnit_uses }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 1, Opcode_s32e_funcUnit_uses }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 1, Opcode_l32i_n_funcUnit_uses }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 1, Opcode_s32i_n_funcUnit_uses }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 1, Opcode_l16ui_funcUnit_uses }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 1, Opcode_l16si_funcUnit_uses }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 1, Opcode_l32i_funcUnit_uses }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 1, Opcode_l32r_funcUnit_uses }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 1, Opcode_l8ui_funcUnit_uses }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 1, Opcode_s16i_funcUnit_uses }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 1, Opcode_s32i_funcUnit_uses }, + { "s32nb", ICLASS_xt_iclass_s32nb, + 0, + Opcode_s32nb_encode_fns, 1, Opcode_s32nb_funcUnit_uses }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 1, Opcode_s8i_funcUnit_uses }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, + 0, + Opcode_rsr_memctl_encode_fns, 0, 0 }, + { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, + 0, + Opcode_wsr_memctl_encode_fns, 0, 0 }, + { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, + 0, + Opcode_xsr_memctl_encode_fns, 0, 0 }, + { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, + 0, + Opcode_rsr_configid0_encode_fns, 0, 0 }, + { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, + 0, + Opcode_wsr_configid0_encode_fns, 0, 0 }, + { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, + 0, + Opcode_rsr_configid1_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, + 0, + Opcode_rsr_epc7_encode_fns, 0, 0 }, + { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, + 0, + Opcode_wsr_epc7_encode_fns, 0, 0 }, + { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, + 0, + Opcode_xsr_epc7_encode_fns, 0, 0 }, + { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, + 0, + Opcode_rsr_excsave7_encode_fns, 0, 0 }, + { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, + 0, + Opcode_wsr_excsave7_encode_fns, 0, 0 }, + { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, + 0, + Opcode_xsr_excsave7_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, + 0, + Opcode_rsr_eps7_encode_fns, 0, 0 }, + { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, + 0, + Opcode_wsr_eps7_encode_fns, 0, 0 }, + { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, + 0, + Opcode_xsr_eps7_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, + 0, + Opcode_rsr_misc0_encode_fns, 0, 0 }, + { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, + 0, + Opcode_wsr_misc0_encode_fns, 0, 0 }, + { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, + 0, + Opcode_xsr_misc0_encode_fns, 0, 0 }, + { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, + 0, + Opcode_rsr_misc1_encode_fns, 0, 0 }, + { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, + 0, + Opcode_wsr_misc1_encode_fns, 0, 0 }, + { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, + 0, + Opcode_xsr_misc1_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "salt", ICLASS_xt_iclass_salt, + 0, + Opcode_salt_encode_fns, 0, 0 }, + { "saltu", ICLASS_xt_iclass_salt, + 0, + Opcode_saltu_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mull", ICLASS_xt_mul32, + 0, + Opcode_mull_encode_fns, 0, 0 }, + { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hh_encode_fns, 0, 0 }, + { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_hl_encode_fns, 0, 0 }, + { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_lh_encode_fns, 0, 0 }, + { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_mul_aa_ll_encode_fns, 0, 0 }, + { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hh_encode_fns, 0, 0 }, + { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_hl_encode_fns, 0, 0 }, + { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_lh_encode_fns, 0, 0 }, + { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, + 0, + Opcode_umul_aa_ll_encode_fns, 0, 0 }, + { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hh_encode_fns, 0, 0 }, + { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_hl_encode_fns, 0, 0 }, + { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_lh_encode_fns, 0, 0 }, + { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, + 0, + Opcode_mul_ad_ll_encode_fns, 0, 0 }, + { "mul.da.hh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hh_encode_fns, 0, 0 }, + { "mul.da.hl", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_hl_encode_fns, 0, 0 }, + { "mul.da.lh", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_lh_encode_fns, 0, 0 }, + { "mul.da.ll", ICLASS_xt_iclass_mac16_da, + 0, + Opcode_mul_da_ll_encode_fns, 0, 0 }, + { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hh_encode_fns, 0, 0 }, + { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_hl_encode_fns, 0, 0 }, + { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_lh_encode_fns, 0, 0 }, + { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, + 0, + Opcode_mul_dd_ll_encode_fns, 0, 0 }, + { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hh_encode_fns, 0, 0 }, + { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_hl_encode_fns, 0, 0 }, + { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_lh_encode_fns, 0, 0 }, + { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_mula_aa_ll_encode_fns, 0, 0 }, + { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hh_encode_fns, 0, 0 }, + { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_hl_encode_fns, 0, 0 }, + { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_lh_encode_fns, 0, 0 }, + { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, + 0, + Opcode_muls_aa_ll_encode_fns, 0, 0 }, + { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hh_encode_fns, 0, 0 }, + { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_hl_encode_fns, 0, 0 }, + { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_lh_encode_fns, 0, 0 }, + { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_mula_ad_ll_encode_fns, 0, 0 }, + { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hh_encode_fns, 0, 0 }, + { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_hl_encode_fns, 0, 0 }, + { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_lh_encode_fns, 0, 0 }, + { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, + 0, + Opcode_muls_ad_ll_encode_fns, 0, 0 }, + { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hh_encode_fns, 0, 0 }, + { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_hl_encode_fns, 0, 0 }, + { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_lh_encode_fns, 0, 0 }, + { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_mula_da_ll_encode_fns, 0, 0 }, + { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hh_encode_fns, 0, 0 }, + { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_hl_encode_fns, 0, 0 }, + { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_lh_encode_fns, 0, 0 }, + { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, + 0, + Opcode_muls_da_ll_encode_fns, 0, 0 }, + { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hh_encode_fns, 0, 0 }, + { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_hl_encode_fns, 0, 0 }, + { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_lh_encode_fns, 0, 0 }, + { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_mula_dd_ll_encode_fns, 0, 0 }, + { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hh_encode_fns, 0, 0 }, + { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_hl_encode_fns, 0, 0 }, + { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_lh_encode_fns, 0, 0 }, + { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, + 0, + Opcode_muls_dd_ll_encode_fns, 0, 0 }, + { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_lddec_encode_fns, 1, Opcode_mula_da_hh_lddec_funcUnit_uses }, + { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hh_ldinc_encode_fns, 1, Opcode_mula_da_hh_ldinc_funcUnit_uses }, + { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_lddec_encode_fns, 1, Opcode_mula_da_hl_lddec_funcUnit_uses }, + { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_hl_ldinc_encode_fns, 1, Opcode_mula_da_hl_ldinc_funcUnit_uses }, + { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_lddec_encode_fns, 1, Opcode_mula_da_lh_lddec_funcUnit_uses }, + { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_lh_ldinc_encode_fns, 1, Opcode_mula_da_lh_ldinc_funcUnit_uses }, + { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_lddec_encode_fns, 1, Opcode_mula_da_ll_lddec_funcUnit_uses }, + { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, + 0, + Opcode_mula_da_ll_ldinc_encode_fns, 1, Opcode_mula_da_ll_ldinc_funcUnit_uses }, + { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_lddec_encode_fns, 1, Opcode_mula_dd_hh_lddec_funcUnit_uses }, + { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hh_ldinc_encode_fns, 1, Opcode_mula_dd_hh_ldinc_funcUnit_uses }, + { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_lddec_encode_fns, 1, Opcode_mula_dd_hl_lddec_funcUnit_uses }, + { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_hl_ldinc_encode_fns, 1, Opcode_mula_dd_hl_ldinc_funcUnit_uses }, + { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_lddec_encode_fns, 1, Opcode_mula_dd_lh_lddec_funcUnit_uses }, + { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_lh_ldinc_encode_fns, 1, Opcode_mula_dd_lh_ldinc_funcUnit_uses }, + { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_lddec_encode_fns, 1, Opcode_mula_dd_ll_lddec_funcUnit_uses }, + { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, + 0, + Opcode_mula_dd_ll_ldinc_encode_fns, 1, Opcode_mula_dd_ll_ldinc_funcUnit_uses }, + { "lddec", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_lddec_encode_fns, 1, Opcode_lddec_funcUnit_uses }, + { "ldinc", ICLASS_xt_iclass_mac16_l, + 0, + Opcode_ldinc_encode_fns, 1, Opcode_ldinc_funcUnit_uses }, + { "rsr.m0", ICLASS_xt_iclass_rsr_m0, + 0, + Opcode_rsr_m0_encode_fns, 0, 0 }, + { "wsr.m0", ICLASS_xt_iclass_wsr_m0, + 0, + Opcode_wsr_m0_encode_fns, 0, 0 }, + { "xsr.m0", ICLASS_xt_iclass_xsr_m0, + 0, + Opcode_xsr_m0_encode_fns, 0, 0 }, + { "rsr.m1", ICLASS_xt_iclass_rsr_m1, + 0, + Opcode_rsr_m1_encode_fns, 0, 0 }, + { "wsr.m1", ICLASS_xt_iclass_wsr_m1, + 0, + Opcode_wsr_m1_encode_fns, 0, 0 }, + { "xsr.m1", ICLASS_xt_iclass_xsr_m1, + 0, + Opcode_xsr_m1_encode_fns, 0, 0 }, + { "rsr.m2", ICLASS_xt_iclass_rsr_m2, + 0, + Opcode_rsr_m2_encode_fns, 0, 0 }, + { "wsr.m2", ICLASS_xt_iclass_wsr_m2, + 0, + Opcode_wsr_m2_encode_fns, 0, 0 }, + { "xsr.m2", ICLASS_xt_iclass_xsr_m2, + 0, + Opcode_xsr_m2_encode_fns, 0, 0 }, + { "rsr.m3", ICLASS_xt_iclass_rsr_m3, + 0, + Opcode_rsr_m3_encode_fns, 0, 0 }, + { "wsr.m3", ICLASS_xt_iclass_wsr_m3, + 0, + Opcode_wsr_m3_encode_fns, 0, 0 }, + { "xsr.m3", ICLASS_xt_iclass_xsr_m3, + 0, + Opcode_xsr_m3_encode_fns, 0, 0 }, + { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, + 0, + Opcode_rsr_acclo_encode_fns, 0, 0 }, + { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, + 0, + Opcode_wsr_acclo_encode_fns, 0, 0 }, + { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, + 0, + Opcode_xsr_acclo_encode_fns, 0, 0 }, + { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, + 0, + Opcode_rsr_acchi_encode_fns, 0, 0 }, + { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, + 0, + Opcode_wsr_acchi_encode_fns, 0, 0 }, + { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, + 0, + Opcode_xsr_acchi_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "lddr32.p", ICLASS_xt_iclass_lddr32_p, + 0, + Opcode_lddr32_p_encode_fns, 1, Opcode_lddr32_p_funcUnit_uses }, + { "sddr32.p", ICLASS_xt_iclass_sddr32_p, + 0, + Opcode_sddr32_p_encode_fns, 1, Opcode_sddr32_p_funcUnit_uses }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "andb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andb_encode_fns, 0, 0 }, + { "andbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andbc_encode_fns, 0, 0 }, + { "orb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orb_encode_fns, 0, 0 }, + { "orbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orbc_encode_fns, 0, 0 }, + { "xorb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_xorb_encode_fns, 0, 0 }, + { "all4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_all4_encode_fns, 0, 0 }, + { "any4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_any4_encode_fns, 0, 0 }, + { "all8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_all8_encode_fns, 0, 0 }, + { "any8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_any8_encode_fns, 0, 0 }, + { "bf", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bf_encode_fns, 0, 0 }, + { "bt", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bt_encode_fns, 0, 0 }, + { "movf", ICLASS_xt_iclass_bmove, + 0, + Opcode_movf_encode_fns, 0, 0 }, + { "movt", ICLASS_xt_iclass_bmove, + 0, + Opcode_movt_encode_fns, 0, 0 }, + { "rsr.br", ICLASS_xt_iclass_RSR_BR, + 0, + Opcode_rsr_br_encode_fns, 0, 0 }, + { "wsr.br", ICLASS_xt_iclass_WSR_BR, + 0, + Opcode_wsr_br_encode_fns, 0, 0 }, + { "xsr.br", ICLASS_xt_iclass_XSR_BR, + 0, + Opcode_xsr_br_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, + 0, + Opcode_rsr_ccompare2_encode_fns, 0, 0 }, + { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, + 0, + Opcode_wsr_ccompare2_encode_fns, 0, 0 }, + { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, + 0, + Opcode_xsr_ccompare2_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 1, Opcode_lict_funcUnit_uses }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 1, Opcode_licw_funcUnit_uses }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 1, Opcode_sict_funcUnit_uses }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 1, Opcode_sicw_funcUnit_uses }, + { "dhwb", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, + 0, + Opcode_diwbui_p_encode_fns, 0, 0 }, + { "diwb", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfro", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfw", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfwo", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dhu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "dpfl", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "sdct", ICLASS_xt_iclass_sdct, + 0, + Opcode_sdct_encode_fns, 1, Opcode_sdct_funcUnit_uses }, + { "ldct", ICLASS_xt_iclass_ldct, + 0, + Opcode_ldct_encode_fns, 1, Opcode_ldct_funcUnit_uses }, + { "sdcw", ICLASS_xt_iclass_sdcw, + 0, + Opcode_sdcw_encode_fns, 1, Opcode_sdcw_funcUnit_uses }, + { "ldcw", ICLASS_xt_iclass_ldcw, + 0, + Opcode_ldcw_encode_fns, 1, Opcode_ldcw_funcUnit_uses }, + { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr, + 0, + Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr, + 0, + Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, + { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr, + 0, + Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid, + 0, + Opcode_rsr_rasid_encode_fns, 0, 0 }, + { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid, + 0, + Opcode_wsr_rasid_encode_fns, 0, 0 }, + { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid, + 0, + Opcode_xsr_rasid_encode_fns, 0, 0 }, + { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg, + 0, + Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, + { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg, + 0, + Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, + { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg, + 0, + Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, + { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg, + 0, + Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, + { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg, + 0, + Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, + { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg, + 0, + Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, + { "idtlb", ICLASS_xt_iclass_idtlb, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", ICLASS_xt_iclass_wdtlb, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", ICLASS_xt_iclass_iitlb, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", ICLASS_xt_iclass_ritlb, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", ICLASS_xt_iclass_witlb, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "ldpte", ICLASS_xt_iclass_ldpte, + 0, + Opcode_ldpte_encode_fns, 1, Opcode_ldpte_funcUnit_uses }, + { "hwwitlba", ICLASS_xt_iclass_hwwitlba, + XTENSA_OPCODE_IS_BRANCH, + Opcode_hwwitlba_encode_fns, 0, 0 }, + { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba, + 0, + Opcode_hwwdtlba_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 1, Opcode_l32ai_funcUnit_uses }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 1, Opcode_s32ri_funcUnit_uses }, + { "s32c1i", ICLASS_xt_iclass_s32c1i, + 0, + Opcode_s32c1i_encode_fns, 1, Opcode_s32c1i_funcUnit_uses }, + { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "quos", ICLASS_xt_iclass_div, + 0, + Opcode_quos_encode_fns, 0, 0 }, + { "quou", ICLASS_xt_iclass_div, + 0, + Opcode_quou_encode_fns, 0, 0 }, + { "rems", ICLASS_xt_iclass_div, + 0, + Opcode_rems_encode_fns, 0, 0 }, + { "remu", ICLASS_xt_iclass_div, + 0, + Opcode_remu_encode_fns, 0, 0 }, + { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess, + 0, + Opcode_rsr_eraccess_encode_fns, 0, 0 }, + { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess, + 0, + Opcode_wsr_eraccess_encode_fns, 0, 0 }, + { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess, + 0, + Opcode_xsr_eraccess_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "rur.fcr", ICLASS_rur_fcr, + 0, + Opcode_rur_fcr_encode_fns, 0, 0 }, + { "wur.fcr", ICLASS_wur_fcr, + 0, + Opcode_wur_fcr_encode_fns, 0, 0 }, + { "rur.fsr", ICLASS_rur_fsr, + 0, + Opcode_rur_fsr_encode_fns, 0, 0 }, + { "wur.fsr", ICLASS_wur_fsr, + 0, + Opcode_wur_fsr_encode_fns, 0, 0 }, + { "read_impwire", ICLASS_iclass_READ_IMPWIRE, + 0, + Opcode_read_impwire_encode_fns, 0, 0 }, + { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, + 0, + Opcode_setb_expstate_encode_fns, 0, 0 }, + { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, + 0, + Opcode_clrb_expstate_encode_fns, 0, 0 }, + { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, + 0, + Opcode_wrmsk_expstate_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "lsi", ICLASS_LSI, + 0, + Opcode_lsi_encode_fns, 1, Opcode_lsi_funcUnit_uses }, + { "lsip", ICLASS_LSIP, + 0, + Opcode_lsip_encode_fns, 1, Opcode_lsip_funcUnit_uses }, + { "lsx", ICLASS_LSX, + 0, + Opcode_lsx_encode_fns, 1, Opcode_lsx_funcUnit_uses }, + { "lsxp", ICLASS_LSXP, + 0, + Opcode_lsxp_encode_fns, 1, Opcode_lsxp_funcUnit_uses }, + { "ssi", ICLASS_SSI, + 0, + Opcode_ssi_encode_fns, 1, Opcode_ssi_funcUnit_uses }, + { "ssip", ICLASS_SSIP, + 0, + Opcode_ssip_encode_fns, 1, Opcode_ssip_funcUnit_uses }, + { "ssx", ICLASS_SSX, + 0, + Opcode_ssx_encode_fns, 1, Opcode_ssx_funcUnit_uses }, + { "ssxp", ICLASS_SSXP, + 0, + Opcode_ssxp_encode_fns, 1, Opcode_ssxp_funcUnit_uses }, + { "ldi", ICLASS_LDI, + 0, + Opcode_ldi_encode_fns, 1, Opcode_ldi_funcUnit_uses }, + { "ldip", ICLASS_LDIP, + 0, + Opcode_ldip_encode_fns, 1, Opcode_ldip_funcUnit_uses }, + { "ldx", ICLASS_LDX, + 0, + Opcode_ldx_encode_fns, 1, Opcode_ldx_funcUnit_uses }, + { "ldxp", ICLASS_LDXP, + 0, + Opcode_ldxp_encode_fns, 1, Opcode_ldxp_funcUnit_uses }, + { "sdi", ICLASS_SDI, + 0, + Opcode_sdi_encode_fns, 1, Opcode_sdi_funcUnit_uses }, + { "sdip", ICLASS_SDIP, + 0, + Opcode_sdip_encode_fns, 1, Opcode_sdip_funcUnit_uses }, + { "sdx", ICLASS_SDX, + 0, + Opcode_sdx_encode_fns, 1, Opcode_sdx_funcUnit_uses }, + { "sdxp", ICLASS_SDXP, + 0, + Opcode_sdxp_encode_fns, 1, Opcode_sdxp_funcUnit_uses }, + { "abs.s", ICLASS_ABS_S, + 0, + Opcode_abs_s_encode_fns, 0, 0 }, + { "neg.s", ICLASS_NEG_S, + 0, + Opcode_neg_s_encode_fns, 0, 0 }, + { "abs.d", ICLASS_ABS_D, + 0, + Opcode_abs_d_encode_fns, 0, 0 }, + { "neg.d", ICLASS_NEG_D, + 0, + Opcode_neg_d_encode_fns, 0, 0 }, + { "mov.s", ICLASS_MOV_S, + 0, + Opcode_mov_s_encode_fns, 0, 0 }, + { "mov.d", ICLASS_MOV_D, + 0, + Opcode_mov_d_encode_fns, 0, 0 }, + { "moveqz.s", ICLASS_MOVEQZ_S, + 0, + Opcode_moveqz_s_encode_fns, 0, 0 }, + { "movnez.s", ICLASS_MOVNEZ_S, + 0, + Opcode_movnez_s_encode_fns, 0, 0 }, + { "movltz.s", ICLASS_MOVLTZ_S, + 0, + Opcode_movltz_s_encode_fns, 0, 0 }, + { "movgez.s", ICLASS_MOVGEZ_S, + 0, + Opcode_movgez_s_encode_fns, 0, 0 }, + { "movf.s", ICLASS_MOVF_S, + 0, + Opcode_movf_s_encode_fns, 0, 0 }, + { "movt.s", ICLASS_MOVT_S, + 0, + Opcode_movt_s_encode_fns, 0, 0 }, + { "wfr", ICLASS_WFR, + 0, + Opcode_wfr_encode_fns, 0, 0 }, + { "rfr", ICLASS_RFR, + 0, + Opcode_rfr_encode_fns, 0, 0 }, + { "rfrd", ICLASS_RFRD, + 0, + Opcode_rfrd_encode_fns, 0, 0 }, + { "wfrd", ICLASS_WFRD, + 0, + Opcode_wfrd_encode_fns, 0, 0 }, + { "round.s", ICLASS_ROUND_S, + 0, + Opcode_round_s_encode_fns, 0, 0 }, + { "round.d", ICLASS_ROUND_D, + 0, + Opcode_round_d_encode_fns, 0, 0 }, + { "ceil.s", ICLASS_CEIL_S, + 0, + Opcode_ceil_s_encode_fns, 0, 0 }, + { "ceil.d", ICLASS_CEIL_D, + 0, + Opcode_ceil_d_encode_fns, 0, 0 }, + { "floor.s", ICLASS_FLOOR_S, + 0, + Opcode_floor_s_encode_fns, 0, 0 }, + { "floor.d", ICLASS_FLOOR_D, + 0, + Opcode_floor_d_encode_fns, 0, 0 }, + { "trunc.s", ICLASS_TRUNC_S, + 0, + Opcode_trunc_s_encode_fns, 0, 0 }, + { "trunc.d", ICLASS_TRUNC_D, + 0, + Opcode_trunc_d_encode_fns, 0, 0 }, + { "utrunc.s", ICLASS_UTRUNC_S, + 0, + Opcode_utrunc_s_encode_fns, 0, 0 }, + { "utrunc.d", ICLASS_UTRUNC_D, + 0, + Opcode_utrunc_d_encode_fns, 0, 0 }, + { "float.s", ICLASS_FLOAT_S, + 0, + Opcode_float_s_encode_fns, 0, 0 }, + { "float.d", ICLASS_FLOAT_D, + 0, + Opcode_float_d_encode_fns, 0, 0 }, + { "ufloat.s", ICLASS_UFLOAT_S, + 0, + Opcode_ufloat_s_encode_fns, 0, 0 }, + { "ufloat.d", ICLASS_UFLOAT_D, + 0, + Opcode_ufloat_d_encode_fns, 0, 0 }, + { "cvtd.s", ICLASS_CVTD_S, + 0, + Opcode_cvtd_s_encode_fns, 0, 0 }, + { "cvts.d", ICLASS_CVTS_D, + 0, + Opcode_cvts_d_encode_fns, 0, 0 }, + { "un.s", ICLASS_UN_S, + 0, + Opcode_un_s_encode_fns, 0, 0 }, + { "un.d", ICLASS_UN_D, + 0, + Opcode_un_d_encode_fns, 0, 0 }, + { "ult.s", ICLASS_ULT_S, + 0, + Opcode_ult_s_encode_fns, 0, 0 }, + { "ult.d", ICLASS_ULT_D, + 0, + Opcode_ult_d_encode_fns, 0, 0 }, + { "ule.s", ICLASS_ULE_S, + 0, + Opcode_ule_s_encode_fns, 0, 0 }, + { "ule.d", ICLASS_ULE_D, + 0, + Opcode_ule_d_encode_fns, 0, 0 }, + { "ueq.s", ICLASS_UEQ_S, + 0, + Opcode_ueq_s_encode_fns, 0, 0 }, + { "ueq.d", ICLASS_UEQ_D, + 0, + Opcode_ueq_d_encode_fns, 0, 0 }, + { "olt.s", ICLASS_OLT_S, + 0, + Opcode_olt_s_encode_fns, 0, 0 }, + { "olt.d", ICLASS_OLT_D, + 0, + Opcode_olt_d_encode_fns, 0, 0 }, + { "ole.s", ICLASS_OLE_S, + 0, + Opcode_ole_s_encode_fns, 0, 0 }, + { "ole.d", ICLASS_OLE_D, + 0, + Opcode_ole_d_encode_fns, 0, 0 }, + { "oeq.s", ICLASS_OEQ_S, + 0, + Opcode_oeq_s_encode_fns, 0, 0 }, + { "oeq.d", ICLASS_OEQ_D, + 0, + Opcode_oeq_d_encode_fns, 0, 0 }, + { "add.s", ICLASS_ADD_S, + 0, + Opcode_add_s_encode_fns, 0, 0 }, + { "add.d", ICLASS_ADD_D, + 0, + Opcode_add_d_encode_fns, 0, 0 }, + { "sub.s", ICLASS_SUB_S, + 0, + Opcode_sub_s_encode_fns, 0, 0 }, + { "sub.d", ICLASS_SUB_D, + 0, + Opcode_sub_d_encode_fns, 0, 0 }, + { "mul.s", ICLASS_MUL_S, + 0, + Opcode_mul_s_encode_fns, 0, 0 }, + { "mul.d", ICLASS_MUL_D, + 0, + Opcode_mul_d_encode_fns, 0, 0 }, + { "madd.s", ICLASS_MADD_S, + 0, + Opcode_madd_s_encode_fns, 0, 0 }, + { "madd.d", ICLASS_MADD_D, + 0, + Opcode_madd_d_encode_fns, 0, 0 }, + { "msub.s", ICLASS_MSUB_S, + 0, + Opcode_msub_s_encode_fns, 0, 0 }, + { "msub.d", ICLASS_MSUB_D, + 0, + Opcode_msub_d_encode_fns, 0, 0 }, + { "sqrt0.s", ICLASS_SQRT0_S, + 0, + Opcode_sqrt0_s_encode_fns, 0, 0 }, + { "sqrt0.d", ICLASS_SQRT0_D, + 0, + Opcode_sqrt0_d_encode_fns, 0, 0 }, + { "div0.s", ICLASS_DIV0_S, + 0, + Opcode_div0_s_encode_fns, 0, 0 }, + { "div0.d", ICLASS_DIV0_D, + 0, + Opcode_div0_d_encode_fns, 0, 0 }, + { "recip0.s", ICLASS_RECIP0_S, + 0, + Opcode_recip0_s_encode_fns, 0, 0 }, + { "recip0.d", ICLASS_RECIP0_D, + 0, + Opcode_recip0_d_encode_fns, 0, 0 }, + { "rsqrt0.s", ICLASS_RSQRT0_S, + 0, + Opcode_rsqrt0_s_encode_fns, 0, 0 }, + { "rsqrt0.d", ICLASS_RSQRT0_D, + 0, + Opcode_rsqrt0_d_encode_fns, 0, 0 }, + { "maddn.s", ICLASS_MADDN_S, + 0, + Opcode_maddn_s_encode_fns, 0, 0 }, + { "maddn.d", ICLASS_MADDN_D, + 0, + Opcode_maddn_d_encode_fns, 0, 0 }, + { "divn.s", ICLASS_DIVN_S, + 0, + Opcode_divn_s_encode_fns, 0, 0 }, + { "divn.d", ICLASS_DIVN_D, + 0, + Opcode_divn_d_encode_fns, 0, 0 }, + { "const.s", ICLASS_CONST_S, + 0, + Opcode_const_s_encode_fns, 0, 0 }, + { "const.d", ICLASS_CONST_D, + 0, + Opcode_const_d_encode_fns, 0, 0 }, + { "nexp01.s", ICLASS_NEXP01_S, + 0, + Opcode_nexp01_s_encode_fns, 0, 0 }, + { "nexp01.d", ICLASS_NEXP01_D, + 0, + Opcode_nexp01_d_encode_fns, 0, 0 }, + { "addexp.s", ICLASS_ADDEXP_S, + 0, + Opcode_addexp_s_encode_fns, 0, 0 }, + { "addexp.d", ICLASS_ADDEXP_D, + 0, + Opcode_addexp_d_encode_fns, 0, 0 }, + { "addexpm.s", ICLASS_ADDEXPM_S, + 0, + Opcode_addexpm_s_encode_fns, 0, 0 }, + { "addexpm.d", ICLASS_ADDEXPM_D, + 0, + Opcode_addexpm_d_encode_fns, 0, 0 }, + { "mkdadj.s", ICLASS_MKDADJ_S, + 0, + Opcode_mkdadj_s_encode_fns, 0, 0 }, + { "mkdadj.d", ICLASS_MKDADJ_D, + 0, + Opcode_mkdadj_d_encode_fns, 0, 0 }, + { "mksadj.s", ICLASS_MKSADJ_S, + 0, + Opcode_mksadj_s_encode_fns, 0, 0 }, + { "mksadj.d", ICLASS_MKSADJ_D, + 0, + Opcode_mksadj_d_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUB, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BNEI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BALL, + OPCODE_BANY, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQ, + OPCODE_BGE, + OPCODE_BGEU, + OPCODE_BLT, + OPCODE_BLTU, + OPCODE_BNALL, + OPCODE_BNE, + OPCODE_BNONE, + OPCODE_BEQZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_BNEZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPGTZ, + OPCODE_LOOPNEZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVGEZ, + OPCODE_MOVLTZ, + OPCODE_MOVNEZ, + OPCODE_ABS, + OPCODE_NEG, + OPCODE_NOP, + OPCODE_RET, + OPCODE_SIMCALL, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S32NB, + OPCODE_S8I, + OPCODE_SSA8B, + OPCODE_SSA8L, + OPCODE_SSL, + OPCODE_SSR, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRA, + OPCODE_SRL, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_DSYNC, + OPCODE_ESYNC, + OPCODE_RSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_MEMCTL, + OPCODE_WSR_MEMCTL, + OPCODE_XSR_MEMCTL, + OPCODE_RSR_CONFIGID0, + OPCODE_WSR_CONFIGID0, + OPCODE_RSR_CONFIGID1, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPC6, + OPCODE_WSR_EPC6, + OPCODE_XSR_EPC6, + OPCODE_RSR_EXCSAVE6, + OPCODE_WSR_EXCSAVE6, + OPCODE_XSR_EXCSAVE6, + OPCODE_RSR_EPC7, + OPCODE_WSR_EPC7, + OPCODE_XSR_EPC7, + OPCODE_RSR_EXCSAVE7, + OPCODE_WSR_EXCSAVE7, + OPCODE_XSR_EXCSAVE7, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EPS6, + OPCODE_WSR_EPS6, + OPCODE_XSR_EPS6, + OPCODE_RSR_EPS7, + OPCODE_WSR_EPS7, + OPCODE_XSR_EPS7, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_MISC0, + OPCODE_WSR_MISC0, + OPCODE_XSR_MISC0, + OPCODE_RSR_MISC1, + OPCODE_WSR_MISC1, + OPCODE_XSR_MISC1, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_SALT, + OPCODE_SALTU, + OPCODE_MUL16S, + OPCODE_MUL16U, + OPCODE_MULL, + OPCODE_MUL_AA_HH, + OPCODE_MUL_AA_HL, + OPCODE_MUL_AA_LH, + OPCODE_MUL_AA_LL, + OPCODE_UMUL_AA_HH, + OPCODE_UMUL_AA_HL, + OPCODE_UMUL_AA_LH, + OPCODE_UMUL_AA_LL, + OPCODE_MUL_AD_HH, + OPCODE_MUL_AD_HL, + OPCODE_MUL_AD_LH, + OPCODE_MUL_AD_LL, + OPCODE_MUL_DA_HH, + OPCODE_MUL_DA_HL, + OPCODE_MUL_DA_LH, + OPCODE_MUL_DA_LL, + OPCODE_MUL_DD_HH, + OPCODE_MUL_DD_HL, + OPCODE_MUL_DD_LH, + OPCODE_MUL_DD_LL, + OPCODE_MULA_AA_HH, + OPCODE_MULA_AA_HL, + OPCODE_MULA_AA_LH, + OPCODE_MULA_AA_LL, + OPCODE_MULS_AA_HH, + OPCODE_MULS_AA_HL, + OPCODE_MULS_AA_LH, + OPCODE_MULS_AA_LL, + OPCODE_MULA_AD_HH, + OPCODE_MULA_AD_HL, + OPCODE_MULA_AD_LH, + OPCODE_MULA_AD_LL, + OPCODE_MULS_AD_HH, + OPCODE_MULS_AD_HL, + OPCODE_MULS_AD_LH, + OPCODE_MULS_AD_LL, + OPCODE_MULA_DA_HH, + OPCODE_MULA_DA_HL, + OPCODE_MULA_DA_LH, + OPCODE_MULA_DA_LL, + OPCODE_MULS_DA_HH, + OPCODE_MULS_DA_HL, + OPCODE_MULS_DA_LH, + OPCODE_MULS_DA_LL, + OPCODE_MULA_DD_HH, + OPCODE_MULA_DD_HL, + OPCODE_MULA_DD_LH, + OPCODE_MULA_DD_LL, + OPCODE_MULS_DD_HH, + OPCODE_MULS_DD_HL, + OPCODE_MULS_DD_LH, + OPCODE_MULS_DD_LL, + OPCODE_MULA_DA_HH_LDDEC, + OPCODE_MULA_DA_HH_LDINC, + OPCODE_MULA_DA_HL_LDDEC, + OPCODE_MULA_DA_HL_LDINC, + OPCODE_MULA_DA_LH_LDDEC, + OPCODE_MULA_DA_LH_LDINC, + OPCODE_MULA_DA_LL_LDDEC, + OPCODE_MULA_DA_LL_LDINC, + OPCODE_MULA_DD_HH_LDDEC, + OPCODE_MULA_DD_HH_LDINC, + OPCODE_MULA_DD_HL_LDDEC, + OPCODE_MULA_DD_HL_LDINC, + OPCODE_MULA_DD_LH_LDDEC, + OPCODE_MULA_DD_LH_LDINC, + OPCODE_MULA_DD_LL_LDDEC, + OPCODE_MULA_DD_LL_LDINC, + OPCODE_LDDEC, + OPCODE_LDINC, + OPCODE_RSR_M0, + OPCODE_WSR_M0, + OPCODE_XSR_M0, + OPCODE_RSR_M1, + OPCODE_WSR_M1, + OPCODE_XSR_M1, + OPCODE_RSR_M2, + OPCODE_WSR_M2, + OPCODE_XSR_M2, + OPCODE_RSR_M3, + OPCODE_WSR_M3, + OPCODE_XSR_M3, + OPCODE_RSR_ACCLO, + OPCODE_WSR_ACCLO, + OPCODE_XSR_ACCLO, + OPCODE_RSR_ACCHI, + OPCODE_WSR_ACCHI, + OPCODE_XSR_ACCHI, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_LDDR32_P, + OPCODE_SDDR32_P, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_ANDB, + OPCODE_ANDBC, + OPCODE_ORB, + OPCODE_ORBC, + OPCODE_XORB, + OPCODE_ALL4, + OPCODE_ANY4, + OPCODE_ALL8, + OPCODE_ANY8, + OPCODE_BF, + OPCODE_BT, + OPCODE_MOVF, + OPCODE_MOVT, + OPCODE_RSR_BR, + OPCODE_WSR_BR, + OPCODE_XSR_BR, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_RSR_CCOMPARE2, + OPCODE_WSR_CCOMPARE2, + OPCODE_XSR_CCOMPARE2, + OPCODE_IHI, + OPCODE_IPF, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_IPFL, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_DHWB, + OPCODE_DHWBI, + OPCODE_DIWBUI_P, + OPCODE_DIWB, + OPCODE_DIWBI, + OPCODE_DHI, + OPCODE_DII, + OPCODE_DPFR, + OPCODE_DPFRO, + OPCODE_DPFW, + OPCODE_DPFWO, + OPCODE_DHU, + OPCODE_DIU, + OPCODE_DPFL, + OPCODE_SDCT, + OPCODE_LDCT, + OPCODE_SDCW, + OPCODE_LDCW, + OPCODE_WSR_PTEVADDR, + OPCODE_RSR_PTEVADDR, + OPCODE_XSR_PTEVADDR, + OPCODE_RSR_RASID, + OPCODE_WSR_RASID, + OPCODE_XSR_RASID, + OPCODE_RSR_ITLBCFG, + OPCODE_WSR_ITLBCFG, + OPCODE_XSR_ITLBCFG, + OPCODE_RSR_DTLBCFG, + OPCODE_WSR_DTLBCFG, + OPCODE_XSR_DTLBCFG, + OPCODE_IDTLB, + OPCODE_PDTLB, + OPCODE_RDTLB0, + OPCODE_RDTLB1, + OPCODE_WDTLB, + OPCODE_IITLB, + OPCODE_PITLB, + OPCODE_RITLB0, + OPCODE_RITLB1, + OPCODE_WITLB, + OPCODE_LDPTE, + OPCODE_HWWITLBA, + OPCODE_HWWDTLBA, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MAX, + OPCODE_MAXU, + OPCODE_MIN, + OPCODE_MINU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_S32C1I, + OPCODE_RSR_SCOMPARE1, + OPCODE_WSR_SCOMPARE1, + OPCODE_XSR_SCOMPARE1, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_QUOS, + OPCODE_QUOU, + OPCODE_REMS, + OPCODE_REMU, + OPCODE_RSR_ERACCESS, + OPCODE_WSR_ERACCESS, + OPCODE_XSR_ERACCESS, + OPCODE_RER, + OPCODE_WER, + OPCODE_RUR_FCR, + OPCODE_WUR_FCR, + OPCODE_RUR_FSR, + OPCODE_WUR_FSR, + OPCODE_READ_IMPWIRE, + OPCODE_SETB_EXPSTATE, + OPCODE_CLRB_EXPSTATE, + OPCODE_WRMSK_EXPSTATE, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_LSI, + OPCODE_LSIP, + OPCODE_LSX, + OPCODE_LSXP, + OPCODE_SSI, + OPCODE_SSIP, + OPCODE_SSX, + OPCODE_SSXP, + OPCODE_LDI, + OPCODE_LDIP, + OPCODE_LDX, + OPCODE_LDXP, + OPCODE_SDI, + OPCODE_SDIP, + OPCODE_SDX, + OPCODE_SDXP, + OPCODE_ABS_S, + OPCODE_NEG_S, + OPCODE_ABS_D, + OPCODE_NEG_D, + OPCODE_MOV_S, + OPCODE_MOV_D, + OPCODE_MOVEQZ_S, + OPCODE_MOVNEZ_S, + OPCODE_MOVLTZ_S, + OPCODE_MOVGEZ_S, + OPCODE_MOVF_S, + OPCODE_MOVT_S, + OPCODE_WFR, + OPCODE_RFR, + OPCODE_RFRD, + OPCODE_WFRD, + OPCODE_ROUND_S, + OPCODE_ROUND_D, + OPCODE_CEIL_S, + OPCODE_CEIL_D, + OPCODE_FLOOR_S, + OPCODE_FLOOR_D, + OPCODE_TRUNC_S, + OPCODE_TRUNC_D, + OPCODE_UTRUNC_S, + OPCODE_UTRUNC_D, + OPCODE_FLOAT_S, + OPCODE_FLOAT_D, + OPCODE_UFLOAT_S, + OPCODE_UFLOAT_D, + OPCODE_CVTD_S, + OPCODE_CVTS_D, + OPCODE_UN_S, + OPCODE_UN_D, + OPCODE_ULT_S, + OPCODE_ULT_D, + OPCODE_ULE_S, + OPCODE_ULE_D, + OPCODE_UEQ_S, + OPCODE_UEQ_D, + OPCODE_OLT_S, + OPCODE_OLT_D, + OPCODE_OLE_S, + OPCODE_OLE_D, + OPCODE_OEQ_S, + OPCODE_OEQ_D, + OPCODE_ADD_S, + OPCODE_ADD_D, + OPCODE_SUB_S, + OPCODE_SUB_D, + OPCODE_MUL_S, + OPCODE_MUL_D, + OPCODE_MADD_S, + OPCODE_MADD_D, + OPCODE_MSUB_S, + OPCODE_MSUB_D, + OPCODE_SQRT0_S, + OPCODE_SQRT0_D, + OPCODE_DIV0_S, + OPCODE_DIV0_D, + OPCODE_RECIP0_S, + OPCODE_RECIP0_D, + OPCODE_RSQRT0_S, + OPCODE_RSQRT0_D, + OPCODE_MADDN_S, + OPCODE_MADDN_D, + OPCODE_DIVN_S, + OPCODE_DIVN_D, + OPCODE_CONST_S, + OPCODE_CONST_D, + OPCODE_NEXP01_S, + OPCODE_NEXP01_D, + OPCODE_ADDEXP_S, + OPCODE_ADDEXP_D, + OPCODE_ADDEXPM_S, + OPCODE_ADDEXPM_D, + OPCODE_MKDADJ_S, + OPCODE_MKDADJ_D, + OPCODE_MKSADJ_S, + OPCODE_MKSADJ_D +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 0) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_r_Slot_inst_get (insn) == 0) + { + if (Field_m_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + if (Field_m_Slot_inst_get (insn) == 2) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_RET; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_RETW; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_JX; + } + if (Field_m_Slot_inst_get (insn) == 3) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALLX0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALLX4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALLX8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALLX12; + } + } + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_MOVSP; + if (Field_r_Slot_inst_get (insn) == 2) + { + if (Field_s_Slot_inst_get (insn) == 0) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_ISYNC; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RSYNC; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_ESYNC; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DSYNC; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_EXCW; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MEMW; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_EXTW; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_NOP; + } + } + if (Field_r_Slot_inst_get (insn) == 3) + { + if (Field_t_Slot_inst_get (insn) == 0) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_RFE; + if (Field_s_Slot_inst_get (insn) == 2) + return OPCODE_RFDE; + if (Field_s_Slot_inst_get (insn) == 4) + return OPCODE_RFWO; + if (Field_s_Slot_inst_get (insn) == 5) + return OPCODE_RFWU; + } + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFI; + } + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BREAK; + if (Field_r_Slot_inst_get (insn) == 5) + { + if (Field_s_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_SIMCALL; + } + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RSIL; + if (Field_r_Slot_inst_get (insn) == 7 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_LDDR32_P; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_SDDR32_P; + } + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_ANY4; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_ALL4; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_ANY8; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_ALL8; + } + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_AND; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OR; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_XOR; + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_r_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_r_Slot_inst_get (insn) == 3 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_RER; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_WER; + if (Field_r_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_NSA; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_NSAU; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_HWWITLBA; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_RITLB0; + if (Field_r_Slot_inst_get (insn) == 4 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IITLB; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_PITLB; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_WITLB; + if (Field_r_Slot_inst_get (insn) == 7) + return OPCODE_RITLB1; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_HWWDTLBA; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_RDTLB0; + if (Field_r_Slot_inst_get (insn) == 12 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IDTLB; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_PDTLB; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_WDTLB; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_RDTLB1; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_NEG; + if (Field_s_Slot_inst_get (insn) == 1) + return OPCODE_ABS; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ADD; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_ADDX2; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_ADDX4; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_ADDX8; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_SUB; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_SUBX2; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_SUBX4; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_SUBX8; + } + if (Field_op1_Slot_inst_get (insn) == 1) + { + if ((Field_op2_Slot_inst_get (insn) == 0 || + Field_op2_Slot_inst_get (insn) == 1)) + return OPCODE_SLLI; + if ((Field_op2_Slot_inst_get (insn) == 2 || + Field_op2_Slot_inst_get (insn) == 3)) + return OPCODE_SRAI; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SRLI; + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_XSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_XSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_XSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_XSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_XSR_BR; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_XSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_XSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_XSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_XSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_XSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_XSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_XSR_M3; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_XSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_XSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 83) + return OPCODE_XSR_PTEVADDR; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_XSR_RASID; + if (Field_sr_Slot_inst_get (insn) == 91) + return OPCODE_XSR_ITLBCFG; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_XSR_DTLBCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_XSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_XSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_XSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_XSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_XSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_XSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_XSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_XSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_XSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_XSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_XSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_XSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_XSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_XSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_XSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_XSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_XSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_XSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_XSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_XSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_XSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_XSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_XSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_XSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_XSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_XSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_XSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_XSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_XSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_XSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_XSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_XSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_XSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_XSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_XSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_XSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_XSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_XSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_XSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_XSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_XSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_XSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_XSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_XSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_XSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_XSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_XSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_SRC; + if (Field_op2_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + if (Field_op2_Slot_inst_get (insn) == 10 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + if (Field_op2_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MUL16U; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MUL16S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LICT; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_SICT; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_LICW; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_SICW; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LDCT; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_SDCT; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LDCW; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_SDCW; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_r_Slot_inst_get (insn) == 14 && + Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_LDPTE; + } + } + if (Field_op1_Slot_inst_get (insn) == 2) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_ANDBC; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_ORB; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_ORBC; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_XORB; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_SALTU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_SALT; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MULL; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_QUOU; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_QUOS; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_REMU; + if (Field_op2_Slot_inst_get (insn) == 15) + return OPCODE_REMS; + } + if (Field_op1_Slot_inst_get (insn) == 3) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_RSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_RSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_RSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_RSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_RSR_BR; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_RSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_RSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_RSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_RSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_RSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_RSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_RSR_M3; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_RSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_RSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 83) + return OPCODE_RSR_PTEVADDR; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_RSR_RASID; + if (Field_sr_Slot_inst_get (insn) == 91) + return OPCODE_RSR_ITLBCFG; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_RSR_DTLBCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_RSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_RSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_RSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_RSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_RSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_RSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_RSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_RSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_RSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_RSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_RSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_RSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_RSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_RSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_RSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_RSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_RSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_RSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_RSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_RSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_RSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_RSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_RSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_RSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_RSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_RSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 208) + return OPCODE_RSR_CONFIGID1; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_RSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_RSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_RSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_RSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_RSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_RSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_RSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_RSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_RSR_INTERRUPT; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_RSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_RSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_RSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_RSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_RSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_RSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 235) + return OPCODE_RSR_PRID; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_RSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_RSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_RSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_RSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_RSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_RSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_RSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_RSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_sr_Slot_inst_get (insn) == 0) + return OPCODE_WSR_LBEG; + if (Field_sr_Slot_inst_get (insn) == 1) + return OPCODE_WSR_LEND; + if (Field_sr_Slot_inst_get (insn) == 2) + return OPCODE_WSR_LCOUNT; + if (Field_sr_Slot_inst_get (insn) == 3) + return OPCODE_WSR_SAR; + if (Field_sr_Slot_inst_get (insn) == 4) + return OPCODE_WSR_BR; + if (Field_sr_Slot_inst_get (insn) == 12) + return OPCODE_WSR_SCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 16) + return OPCODE_WSR_ACCLO; + if (Field_sr_Slot_inst_get (insn) == 17) + return OPCODE_WSR_ACCHI; + if (Field_sr_Slot_inst_get (insn) == 32) + return OPCODE_WSR_M0; + if (Field_sr_Slot_inst_get (insn) == 33) + return OPCODE_WSR_M1; + if (Field_sr_Slot_inst_get (insn) == 34) + return OPCODE_WSR_M2; + if (Field_sr_Slot_inst_get (insn) == 35) + return OPCODE_WSR_M3; + if (Field_sr_Slot_inst_get (insn) == 72) + return OPCODE_WSR_WINDOWBASE; + if (Field_sr_Slot_inst_get (insn) == 73) + return OPCODE_WSR_WINDOWSTART; + if (Field_sr_Slot_inst_get (insn) == 83) + return OPCODE_WSR_PTEVADDR; + if (Field_sr_Slot_inst_get (insn) == 89) + return OPCODE_WSR_MMID; + if (Field_sr_Slot_inst_get (insn) == 90) + return OPCODE_WSR_RASID; + if (Field_sr_Slot_inst_get (insn) == 91) + return OPCODE_WSR_ITLBCFG; + if (Field_sr_Slot_inst_get (insn) == 92) + return OPCODE_WSR_DTLBCFG; + if (Field_sr_Slot_inst_get (insn) == 95) + return OPCODE_WSR_ERACCESS; + if (Field_sr_Slot_inst_get (insn) == 96) + return OPCODE_WSR_IBREAKENABLE; + if (Field_sr_Slot_inst_get (insn) == 97) + return OPCODE_WSR_MEMCTL; + if (Field_sr_Slot_inst_get (insn) == 99) + return OPCODE_WSR_ATOMCTL; + if (Field_sr_Slot_inst_get (insn) == 104) + return OPCODE_WSR_DDR; + if (Field_sr_Slot_inst_get (insn) == 128) + return OPCODE_WSR_IBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 129) + return OPCODE_WSR_IBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 144) + return OPCODE_WSR_DBREAKA0; + if (Field_sr_Slot_inst_get (insn) == 145) + return OPCODE_WSR_DBREAKA1; + if (Field_sr_Slot_inst_get (insn) == 160) + return OPCODE_WSR_DBREAKC0; + if (Field_sr_Slot_inst_get (insn) == 161) + return OPCODE_WSR_DBREAKC1; + if (Field_sr_Slot_inst_get (insn) == 176) + return OPCODE_WSR_CONFIGID0; + if (Field_sr_Slot_inst_get (insn) == 177) + return OPCODE_WSR_EPC1; + if (Field_sr_Slot_inst_get (insn) == 178) + return OPCODE_WSR_EPC2; + if (Field_sr_Slot_inst_get (insn) == 179) + return OPCODE_WSR_EPC3; + if (Field_sr_Slot_inst_get (insn) == 180) + return OPCODE_WSR_EPC4; + if (Field_sr_Slot_inst_get (insn) == 181) + return OPCODE_WSR_EPC5; + if (Field_sr_Slot_inst_get (insn) == 182) + return OPCODE_WSR_EPC6; + if (Field_sr_Slot_inst_get (insn) == 183) + return OPCODE_WSR_EPC7; + if (Field_sr_Slot_inst_get (insn) == 192) + return OPCODE_WSR_DEPC; + if (Field_sr_Slot_inst_get (insn) == 194) + return OPCODE_WSR_EPS2; + if (Field_sr_Slot_inst_get (insn) == 195) + return OPCODE_WSR_EPS3; + if (Field_sr_Slot_inst_get (insn) == 196) + return OPCODE_WSR_EPS4; + if (Field_sr_Slot_inst_get (insn) == 197) + return OPCODE_WSR_EPS5; + if (Field_sr_Slot_inst_get (insn) == 198) + return OPCODE_WSR_EPS6; + if (Field_sr_Slot_inst_get (insn) == 199) + return OPCODE_WSR_EPS7; + if (Field_sr_Slot_inst_get (insn) == 209) + return OPCODE_WSR_EXCSAVE1; + if (Field_sr_Slot_inst_get (insn) == 210) + return OPCODE_WSR_EXCSAVE2; + if (Field_sr_Slot_inst_get (insn) == 211) + return OPCODE_WSR_EXCSAVE3; + if (Field_sr_Slot_inst_get (insn) == 212) + return OPCODE_WSR_EXCSAVE4; + if (Field_sr_Slot_inst_get (insn) == 213) + return OPCODE_WSR_EXCSAVE5; + if (Field_sr_Slot_inst_get (insn) == 214) + return OPCODE_WSR_EXCSAVE6; + if (Field_sr_Slot_inst_get (insn) == 215) + return OPCODE_WSR_EXCSAVE7; + if (Field_sr_Slot_inst_get (insn) == 224) + return OPCODE_WSR_CPENABLE; + if (Field_sr_Slot_inst_get (insn) == 226) + return OPCODE_WSR_INTSET; + if (Field_sr_Slot_inst_get (insn) == 227) + return OPCODE_WSR_INTCLEAR; + if (Field_sr_Slot_inst_get (insn) == 228) + return OPCODE_WSR_INTENABLE; + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WSR_PS; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WSR_VECBASE; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WSR_EXCCAUSE; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WSR_DEBUGCAUSE; + if (Field_sr_Slot_inst_get (insn) == 234) + return OPCODE_WSR_CCOUNT; + if (Field_sr_Slot_inst_get (insn) == 236) + return OPCODE_WSR_ICOUNT; + if (Field_sr_Slot_inst_get (insn) == 237) + return OPCODE_WSR_ICOUNTLEVEL; + if (Field_sr_Slot_inst_get (insn) == 238) + return OPCODE_WSR_EXCVADDR; + if (Field_sr_Slot_inst_get (insn) == 240) + return OPCODE_WSR_CCOMPARE0; + if (Field_sr_Slot_inst_get (insn) == 241) + return OPCODE_WSR_CCOMPARE1; + if (Field_sr_Slot_inst_get (insn) == 242) + return OPCODE_WSR_CCOMPARE2; + if (Field_sr_Slot_inst_get (insn) == 244) + return OPCODE_WSR_MISC0; + if (Field_sr_Slot_inst_get (insn) == 245) + return OPCODE_WSR_MISC1; + } + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_SEXT; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_CLAMPS; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MIN; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MAX; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MINU; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_MAXU; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT; + if (Field_op2_Slot_inst_get (insn) == 14) + { + if (Field_st_Slot_inst_get (insn) == 230) + return OPCODE_RUR_EXPSTATE; + if (Field_st_Slot_inst_get (insn) == 231) + return OPCODE_RUR_THREADPTR; + if (Field_st_Slot_inst_get (insn) == 232) + return OPCODE_RUR_FCR; + if (Field_st_Slot_inst_get (insn) == 233) + return OPCODE_RUR_FSR; + } + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_sr_Slot_inst_get (insn) == 230) + return OPCODE_WUR_EXPSTATE; + if (Field_sr_Slot_inst_get (insn) == 231) + return OPCODE_WUR_THREADPTR; + if (Field_sr_Slot_inst_get (insn) == 232) + return OPCODE_WUR_FCR; + if (Field_sr_Slot_inst_get (insn) == 233) + return OPCODE_WUR_FSR; + } + } + if ((Field_op1_Slot_inst_get (insn) == 4 || + Field_op1_Slot_inst_get (insn) == 5)) + return OPCODE_EXTUI; + if (Field_op1_Slot_inst_get (insn) == 8) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_LSX; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_LSXP; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_LDX; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_LDXP; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_SSX; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_SSXP; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_SDX; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_SDXP; + } + if (Field_op1_Slot_inst_get (insn) == 9) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_L32E; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_S32E; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_S32NB; + } + if (Field_op1_Slot_inst_get (insn) == 10) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ADD_S; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_SUB_S; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_MUL_S; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MADD_S; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MSUB_S; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MADDN_S; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_DIVN_S; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ROUND_S; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_TRUNC_S; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_FLOOR_S; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_CEIL_S; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_FLOAT_S; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_UFLOAT_S; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_UTRUNC_S; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_MOV_S; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_ABS_S; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_CVTD_S; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_CONST_S; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_RFR; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_WFR; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_NEG_S; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DIV0_S; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_RECIP0_S; + if (Field_t_Slot_inst_get (insn) == 9) + return OPCODE_SQRT0_S; + if (Field_t_Slot_inst_get (insn) == 10) + return OPCODE_RSQRT0_S; + if (Field_t_Slot_inst_get (insn) == 11) + return OPCODE_NEXP01_S; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MKSADJ_S; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_MKDADJ_S; + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_ADDEXP_S; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_ADDEXPM_S; + } + } + if (Field_op1_Slot_inst_get (insn) == 11) + { + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_UN_S; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OEQ_S; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_UEQ_S; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_OLT_S; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_ULT_S; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_OLE_S; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_ULE_S; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_MOVEQZ_S; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_MOVNEZ_S; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_MOVLTZ_S; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_MOVGEZ_S; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_MOVF_S; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_MOVT_S; + } + if (Field_op1_Slot_inst_get (insn) == 14) + { + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_UN_D; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_OEQ_D; + if (Field_op2_Slot_inst_get (insn) == 3) + return OPCODE_UEQ_D; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_OLT_D; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_ULT_D; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_OLE_D; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_ULE_D; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_WFRD; + } + if (Field_op1_Slot_inst_get (insn) == 15) + { + if (Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_ADD_D; + if (Field_op2_Slot_inst_get (insn) == 1) + return OPCODE_SUB_D; + if (Field_op2_Slot_inst_get (insn) == 2) + return OPCODE_MUL_D; + if (Field_op2_Slot_inst_get (insn) == 4) + return OPCODE_MADD_D; + if (Field_op2_Slot_inst_get (insn) == 5) + return OPCODE_MSUB_D; + if (Field_op2_Slot_inst_get (insn) == 6) + return OPCODE_MADDN_D; + if (Field_op2_Slot_inst_get (insn) == 7) + return OPCODE_DIVN_D; + if (Field_op2_Slot_inst_get (insn) == 8) + return OPCODE_ROUND_D; + if (Field_op2_Slot_inst_get (insn) == 9) + return OPCODE_TRUNC_D; + if (Field_op2_Slot_inst_get (insn) == 10) + return OPCODE_FLOOR_D; + if (Field_op2_Slot_inst_get (insn) == 11) + return OPCODE_CEIL_D; + if (Field_op2_Slot_inst_get (insn) == 12) + return OPCODE_FLOAT_D; + if (Field_op2_Slot_inst_get (insn) == 13) + return OPCODE_UFLOAT_D; + if (Field_op2_Slot_inst_get (insn) == 14) + return OPCODE_UTRUNC_D; + if (Field_op2_Slot_inst_get (insn) == 15) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_MOV_D; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_ABS_D; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_CVTS_D; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_CONST_D; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_RFRD; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_NEG_D; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DIV0_D; + if (Field_t_Slot_inst_get (insn) == 8) + return OPCODE_RECIP0_D; + if (Field_t_Slot_inst_get (insn) == 9) + return OPCODE_SQRT0_D; + if (Field_t_Slot_inst_get (insn) == 10) + return OPCODE_RSQRT0_D; + if (Field_t_Slot_inst_get (insn) == 11) + return OPCODE_NEXP01_D; + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_MKSADJ_D; + if (Field_t_Slot_inst_get (insn) == 13) + return OPCODE_MKDADJ_D; + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_ADDEXP_D; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_ADDEXPM_D; + } + } + if (Field_r_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_READ_IMPWIRE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 0 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_SETB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 1 && + Field_s3to1_Slot_inst_get (insn) == 1 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_CLRB_EXPSTATE; + if (Field_r_Slot_inst_get (insn) == 2 && + Field_op2_Slot_inst_get (insn) == 0 && + Field_op1_Slot_inst_get (insn) == 14) + return OPCODE_WRMSK_EXPSTATE; + } + if (Field_op0_Slot_inst_get (insn) == 1) + return OPCODE_L32R; + if (Field_op0_Slot_inst_get (insn) == 2) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_L8UI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_L16UI; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_L32I; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_S8I; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_S16I; + if (Field_r_Slot_inst_get (insn) == 6) + return OPCODE_S32I; + if (Field_r_Slot_inst_get (insn) == 7) + { + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_DPFR; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_DPFW; + if (Field_t_Slot_inst_get (insn) == 2) + return OPCODE_DPFRO; + if (Field_t_Slot_inst_get (insn) == 3) + return OPCODE_DPFWO; + if (Field_t_Slot_inst_get (insn) == 4) + return OPCODE_DHWB; + if (Field_t_Slot_inst_get (insn) == 5) + return OPCODE_DHWBI; + if (Field_t_Slot_inst_get (insn) == 6) + return OPCODE_DHI; + if (Field_t_Slot_inst_get (insn) == 7) + return OPCODE_DII; + if (Field_t_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_DPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_DHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_DIU; + if (Field_op1_Slot_inst_get (insn) == 4) + return OPCODE_DIWB; + if (Field_op1_Slot_inst_get (insn) == 5) + return OPCODE_DIWBI; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_op2_Slot_inst_get (insn) == 0) + return OPCODE_DIWBUI_P; + } + if (Field_t_Slot_inst_get (insn) == 12) + return OPCODE_IPF; + if (Field_t_Slot_inst_get (insn) == 13) + { + if (Field_op1_Slot_inst_get (insn) == 0) + return OPCODE_IPFL; + if (Field_op1_Slot_inst_get (insn) == 2) + return OPCODE_IHU; + if (Field_op1_Slot_inst_get (insn) == 3) + return OPCODE_IIU; + } + if (Field_t_Slot_inst_get (insn) == 14) + return OPCODE_IHI; + if (Field_t_Slot_inst_get (insn) == 15) + return OPCODE_III; + } + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_L16SI; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_MOVI; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_L32AI; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_ADDI; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_ADDMI; + if (Field_r_Slot_inst_get (insn) == 14) + return OPCODE_S32C1I; + if (Field_r_Slot_inst_get (insn) == 15) + return OPCODE_S32RI; + } + if (Field_op0_Slot_inst_get (insn) == 3) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_LSI; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_LDI; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_SSI; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_SDI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LSIP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LDIP; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_SSIP; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_SDIP; + } + if (Field_op0_Slot_inst_get (insn) == 4) + { + if (Field_op2_Slot_inst_get (insn) == 0) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDINC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 1) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 2) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DD_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DD_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DD_HH; + } + if (Field_op2_Slot_inst_get (insn) == 3) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AD_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AD_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_r_Slot_inst_get (insn) == 0 && + Field_t3_Slot_inst_get (insn) == 0 && + Field_tlo_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AD_HH; + } + if (Field_op2_Slot_inst_get (insn) == 4) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDINC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDINC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 5) + { + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH_LDDEC; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH_LDDEC; + } + if (Field_op2_Slot_inst_get (insn) == 6) + { + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MUL_DA_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULA_DA_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_s_Slot_inst_get (insn) == 0 && + Field_w_Slot_inst_get (insn) == 0 && + Field_r3_Slot_inst_get (insn) == 0) + return OPCODE_MULS_DA_HH; + } + if (Field_op2_Slot_inst_get (insn) == 7) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 1 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 2 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 3 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_UMUL_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 4 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 5 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 6 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 7 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MUL_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 8 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 9 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 10 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 11 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULA_AA_HH; + if (Field_op1_Slot_inst_get (insn) == 12 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LL; + if (Field_op1_Slot_inst_get (insn) == 13 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HL; + if (Field_op1_Slot_inst_get (insn) == 14 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_LH; + if (Field_op1_Slot_inst_get (insn) == 15 && + Field_r_Slot_inst_get (insn) == 0) + return OPCODE_MULS_AA_HH; + } + if (Field_op2_Slot_inst_get (insn) == 8) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDINC; + } + if (Field_op2_Slot_inst_get (insn) == 9) + { + if (Field_op1_Slot_inst_get (insn) == 0 && + Field_t_Slot_inst_get (insn) == 0 && + Field_rhi_Slot_inst_get (insn) == 0) + return OPCODE_LDDEC; + } + } + if (Field_op0_Slot_inst_get (insn) == 5) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_CALL0; + if (Field_n_Slot_inst_get (insn) == 1) + return OPCODE_CALL4; + if (Field_n_Slot_inst_get (insn) == 2) + return OPCODE_CALL8; + if (Field_n_Slot_inst_get (insn) == 3) + return OPCODE_CALL12; + } + if (Field_op0_Slot_inst_get (insn) == 6) + { + if (Field_n_Slot_inst_get (insn) == 0) + return OPCODE_J; + if (Field_n_Slot_inst_get (insn) == 1) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQZ; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEZ; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTZ; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEZ; + } + if (Field_n_Slot_inst_get (insn) == 2) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_BEQI; + if (Field_m_Slot_inst_get (insn) == 1) + return OPCODE_BNEI; + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEI; + } + if (Field_n_Slot_inst_get (insn) == 3) + { + if (Field_m_Slot_inst_get (insn) == 0) + return OPCODE_ENTRY; + if (Field_m_Slot_inst_get (insn) == 1) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BF; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BT; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_LOOP; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_LOOPNEZ; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_LOOPGTZ; + } + if (Field_m_Slot_inst_get (insn) == 2) + return OPCODE_BLTUI; + if (Field_m_Slot_inst_get (insn) == 3) + return OPCODE_BGEUI; + } + } + if (Field_op0_Slot_inst_get (insn) == 7) + { + if (Field_r_Slot_inst_get (insn) == 0) + return OPCODE_BNONE; + if (Field_r_Slot_inst_get (insn) == 1) + return OPCODE_BEQ; + if (Field_r_Slot_inst_get (insn) == 2) + return OPCODE_BLT; + if (Field_r_Slot_inst_get (insn) == 3) + return OPCODE_BLTU; + if (Field_r_Slot_inst_get (insn) == 4) + return OPCODE_BALL; + if (Field_r_Slot_inst_get (insn) == 5) + return OPCODE_BBC; + if ((Field_r_Slot_inst_get (insn) == 6 || + Field_r_Slot_inst_get (insn) == 7)) + return OPCODE_BBCI; + if (Field_r_Slot_inst_get (insn) == 8) + return OPCODE_BANY; + if (Field_r_Slot_inst_get (insn) == 9) + return OPCODE_BNE; + if (Field_r_Slot_inst_get (insn) == 10) + return OPCODE_BGE; + if (Field_r_Slot_inst_get (insn) == 11) + return OPCODE_BGEU; + if (Field_r_Slot_inst_get (insn) == 12) + return OPCODE_BNALL; + if (Field_r_Slot_inst_get (insn) == 13) + return OPCODE_BBS; + if ((Field_r_Slot_inst_get (insn) == 14 || + Field_r_Slot_inst_get (insn) == 15)) + return OPCODE_BBSI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16b_get (insn) == 12) + { + if (Field_i_Slot_inst16b_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_i_Slot_inst16b_get (insn) == 1) + { + if (Field_z_Slot_inst16b_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_z_Slot_inst16b_get (insn) == 1) + return OPCODE_BNEZ_N; + } + } + if (Field_op0_Slot_inst16b_get (insn) == 13) + { + if (Field_r_Slot_inst16b_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_r_Slot_inst16b_get (insn) == 15) + { + if (Field_t_Slot_inst16b_get (insn) == 0) + return OPCODE_RET_N; + if (Field_t_Slot_inst16b_get (insn) == 1) + return OPCODE_RETW_N; + if (Field_t_Slot_inst16b_get (insn) == 2) + return OPCODE_BREAK_N; + if (Field_t_Slot_inst16b_get (insn) == 3 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + if (Field_t_Slot_inst16b_get (insn) == 6 && + Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + } + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_Slot_inst16a_get (insn) == 8) + return OPCODE_L32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 9) + return OPCODE_S32I_N; + if (Field_op0_Slot_inst16a_get (insn) == 10) + return OPCODE_ADD_N; + if (Field_op0_Slot_inst16a_get (insn) == 11) + return OPCODE_ADDI_N; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_s8_Slot_inst_get, + Field_imms8_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_r_disp_Slot_inst_get, + Field_r_3_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_get, + Field_rbit2_Slot_inst_get, + Field_rhi_Slot_inst_get, + Field_t3_Slot_inst_get, + Field_tbit2_Slot_inst_get, + Field_tlo_Slot_inst_get, + Field_w_Slot_inst_get, + Field_y_Slot_inst_get, + Field_x_Slot_inst_get, + Field_t2_Slot_inst_get, + Field_s2_Slot_inst_get, + Field_r2_Slot_inst_get, + Field_t4_Slot_inst_get, + Field_s4_Slot_inst_get, + Field_r4_Slot_inst_get, + Field_t8_Slot_inst_get, + Field_r8_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Field_bitindex_Slot_inst_get, + Field_s3to1_Slot_inst_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_s8_Slot_inst_set, + Field_imms8_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_r_disp_Slot_inst_set, + Field_r_3_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r3_Slot_inst_set, + Field_rbit2_Slot_inst_set, + Field_rhi_Slot_inst_set, + Field_t3_Slot_inst_set, + Field_tbit2_Slot_inst_set, + Field_tlo_Slot_inst_set, + Field_w_Slot_inst_set, + Field_y_Slot_inst_set, + Field_x_Slot_inst_set, + Field_t2_Slot_inst_set, + Field_s2_Slot_inst_set, + Field_r2_Slot_inst_set, + Field_t4_Slot_inst_set, + Field_s4_Slot_inst_set, + Field_r4_Slot_inst_set, + Field_t8_Slot_inst_set, + Field_r8_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + Field_bitindex_Slot_inst_set, + Field_s3to1_Slot_inst_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_mr0_get, + Implicit_Field_mr1_get, + Implicit_Field_mr2_get, + Implicit_Field_mr3_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc) + return 2; /* x16b */ + return -1; +} + +static int length_table[256] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + -1 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int l = insn[0]; + return length_table[l]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 3 /* insn_size */, 0, + 3, formats, format_decoder, length_decoder, + 3, slots, + 72 /* num_fields */, + 132, operands, + 444, iclasses, + 579, opcodes, 0, + 8, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 1, interfaces, 0, + 1, funcUnits, 0 +}; From patchwork Mon Jul 6 23:47:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 11647255 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2040B739 for ; Tue, 7 Jul 2020 00:41:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DFE1A20663 for ; Tue, 7 Jul 2020 00:41:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NbDlnLSK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DFE1A20663 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsbgA-0000sP-G8 for patchwork-qemu-devel@patchwork.kernel.org; Mon, 06 Jul 2020 20:41:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35582) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jsaqk-0002O0-Ut for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:39 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:45277) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jsaqZ-00012y-PA for qemu-devel@nongnu.org; Mon, 06 Jul 2020 19:48:38 -0400 Received: by mail-pl1-x634.google.com with SMTP id k4so1801053pld.12 for ; Mon, 06 Jul 2020 16:48:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qhtI3J8cjBnFOmNRDElyneQ92UvlNPtcaysL+y+iLBM=; b=NbDlnLSK76iYv/V0VCGcSjZfJuiZbE0S3iLC1fJSns3yXhp0nmk+0NaBrYz0Qq2zhI MpJXWbKJQnD2HBRvlmqYWE2N3Bf6nIX3dL5R6wL0Jpf4o0uPxl0+sbmsilx5TCq5YlXz yXTs5vC+E+5liGBOnyC/Tl0X71gI11m+OIy+UHg6iYsAKPxJGT7x1vKMyBsVZKamNQbx EcCOv7UJWqJin0BDaMEmsZNxjrPLsXnQo3hqfkC+2EMhaVCZICZB3PieKVsHbvhRxynu jv92aTC/dJ7ry6knaTdQI+pDp+VtBmbXapCY7NkqVnWwMMPzxqaExSM8qmNYtkyHvl6l 1ycA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qhtI3J8cjBnFOmNRDElyneQ92UvlNPtcaysL+y+iLBM=; b=NMgN4ZssxIKuFdxSUdUQg64PikQtrMkOGqcW17n9AgzQohzhv1jkylNdhwzyzs2uf8 mKREkXnibpJK/kDkn8SjDw30lWHM/t17UrV3gmq1UXEqeYMkGDzkjsLAnSnsfMzULFIn +jsxo5tlV2JrWiGR7eTx6y/T8p+CexpBsPgotfIuqZqmJqMNyqGHkeyi5VZNkkopT25a 1A/8oCzjYqtU15pDYWUE2OfY2u4iJ4SZkplGJRl3DSfN9DnpwxLRAmXL/+UvbQciIJzO IpcVqRWaXsPoGlLCU2aUV1dflPIZdcsueYms1dgoexutvt8TrV32IPqxchwsQS+5OQ4s Y94Q== X-Gm-Message-State: AOAM530oSOOqUEOXgSDpI4kFIkDk4Lt/IAEjH9F0y44BzTgRcJbtM5V4 xaPe9RrAgNaF1edSkxrfq8g/ienM X-Google-Smtp-Source: ABdhPJxt4Gkk1nu68S78/LVAr9Ljs47qsX5kWBe0vjcM25KjweylnDD3e9qZZWS19UAQij7rjihl3g== X-Received: by 2002:a17:902:fe11:: with SMTP id g17mr43806542plj.145.1594079303258; Mon, 06 Jul 2020 16:48:23 -0700 (PDT) Received: from octofox.cadence.com ([2601:641:400:e00:19b7:f650:7bbe:a7fb]) by smtp.gmail.com with ESMTPSA id e15sm19647649pgt.17.2020.07.06.16.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2020 16:48:21 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Subject: [PATCH 21/21] target/xtensa: import DSP3400 core Date: Mon, 6 Jul 2020 16:47:37 -0700 Message-Id: <20200706234737.32378-22-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com> References: <20200706234737.32378-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=jcmvbkbc@gmail.com; helo=mail-pl1-x634.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-Mailman-Approved-At: Mon, 06 Jul 2020 20:35:57 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" DSP3400 is a DSP core with FPU2000 option. Signed-off-by: Max Filippov --- target/xtensa/Makefile.objs | 1 + target/xtensa/core-dsp3400.c | 31 + target/xtensa/core-dsp3400/core-isa.h | 452 + target/xtensa/core-dsp3400/core-matmap.h | 312 + target/xtensa/core-dsp3400/gdb-config.inc.c | 400 + .../xtensa/core-dsp3400/xtensa-modules.inc.c | 171906 +++++++++++++++ 6 files changed, 173102 insertions(+) create mode 100644 target/xtensa/core-dsp3400.c create mode 100644 target/xtensa/core-dsp3400/core-isa.h create mode 100644 target/xtensa/core-dsp3400/core-matmap.h create mode 100644 target/xtensa/core-dsp3400/gdb-config.inc.c create mode 100644 target/xtensa/core-dsp3400/xtensa-modules.inc.c diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs index e0a3d5e103e6..79b8db6ced27 100644 --- a/target/xtensa/Makefile.objs +++ b/target/xtensa/Makefile.objs @@ -2,6 +2,7 @@ obj-y += core-DE_233L_FPU.o obj-y += core-dc232b.o obj-y += core-dc233c.o obj-y += core-de212.o +obj-y += core-dsp3400.o obj-y += core-fsf.o obj-y += core-sample_controller.o obj-y += core-test_kc705_be.o diff --git a/target/xtensa/core-dsp3400.c b/target/xtensa/core-dsp3400.c new file mode 100644 index 000000000000..753e44d355a5 --- /dev/null +++ b/target/xtensa/core-dsp3400.c @@ -0,0 +1,31 @@ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/gdbstub.h" +#include "qemu-common.h" +#include "qemu/host-utils.h" + +#include "core-dsp3400/core-isa.h" +#include "core-dsp3400/core-matmap.h" +#include "overlay_tool.h" + +#define xtensa_modules xtensa_modules_dsp3400 +#include "core-dsp3400/xtensa-modules.inc.c" + +static XtensaConfig dsp3400 __attribute__((unused)) = { + .name = "dsp3400", + .gdb_regmap = { + .reg = { +#include "core-dsp3400/gdb-config.inc.c" + } + }, + .isa_internal = &xtensa_modules, + .clock_freq_khz = 40000, + .opcode_translators = (const XtensaOpcodeTranslators *[]){ + &xtensa_core_opcodes, + &xtensa_fpu2000_opcodes, + NULL, + }, + DEFAULT_SECTIONS +}; + +REGISTER_CORE(dsp3400) diff --git a/target/xtensa/core-dsp3400/core-isa.h b/target/xtensa/core-dsp3400/core-isa.h new file mode 100644 index 000000000000..336b2467c6ac --- /dev/null +++ b/target/xtensa/core-dsp3400/core-isa.h @@ -0,0 +1,452 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Copyright (c) 1999-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 0 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 4 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* floating point pkg */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 16 /* data width in bytes */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ + +#define XCHAL_SW_VERSION 800002 /* sw version of this header */ + +#define XCHAL_CORE_ID "dsp3400_RC2" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x0002DC22 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC3F3DBFE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x1082C3B0 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX3.0.1" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2300 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 230001 /* major*100+minor */ +#define XCHAL_HW_REL_LX3 1 +#define XCHAL_HW_REL_LX3_0 1 +#define XCHAL_HW_REL_LX3_0_1 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2300 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 230001 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2300 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 230001 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 8192 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 7 +#define XCHAL_DCACHE_SETWIDTH 7 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 2 +#define XCHAL_DCACHE_WAYS 2 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 8 +#define XCHAL_DCACHE_ACCESS_SIZE 16 + +/* Number of encoded cache attr bits (see for decoded bits): */ +#define XCHAL_CA_BITS 4 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x5FFE0000 +#define XCHAL_INSTRAM0_PADDR 0x5FFE0000 +#define XCHAL_INSTRAM0_SIZE 65536 +#define XCHAL_INSTRAM0_ECC_PARITY 0 + +/* Instruction RAM 1: */ +#define XCHAL_INSTRAM1_VADDR 0x5FFF0000 +#define XCHAL_INSTRAM1_PADDR 0x5FFF0000 +#define XCHAL_INSTRAM1_SIZE 65536 +#define XCHAL_INSTRAM1_ECC_PARITY 0 + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x5FFD0000 +#define XCHAL_DATARAM0_PADDR 0x5FFD0000 +#define XCHAL_DATARAM0_SIZE 32768 +#define XCHAL_DATARAM0_ECC_PARITY 0 + +/* Data RAM 1: */ +#define XCHAL_DATARAM1_VADDR 0x5FFD8000 +#define XCHAL_DATARAM1_PADDR 0x5FFD8000 +#define XCHAL_DATARAM1_SIZE 32768 +#define XCHAL_DATARAM1_ECC_PARITY 0 + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 13 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 9 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 4 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x00001200 +#define XCHAL_INTLEVEL2_MASK 0x00000980 +#define XCHAL_INTLEVEL3_MASK 0x00000460 +#define XCHAL_INTLEVEL4_MASK 0x00000019 +#define XCHAL_INTLEVEL5_MASK 0x00000006 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00000000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00001200 +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00001B80 +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00001FE0 +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00001FF9 +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00001FFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00001FFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00001FFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 4 +#define XCHAL_INT1_LEVEL 5 +#define XCHAL_INT2_LEVEL 5 +#define XCHAL_INT3_LEVEL 4 +#define XCHAL_INT4_LEVEL 4 +#define XCHAL_INT5_LEVEL 3 +#define XCHAL_INT6_LEVEL 3 +#define XCHAL_INT7_LEVEL 2 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 1 +#define XCHAL_INT10_LEVEL 3 +#define XCHAL_INT11_LEVEL 2 +#define XCHAL_INT12_LEVEL 1 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_WRITE_ERROR + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFFE000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000400 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x000003FE +#define XCHAL_INTTYPE_MASK_TIMER 0x00000801 +#define XCHAL_INTTYPE_MASK_NMI 0x00000000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00001000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 0 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 11 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_WRITE_ERROR_INTERRUPT 12 /* write-error interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ + + +/* + * External interrupt vectors/levels. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ +#define XCHAL_EXTINT0_NUM 1 /* (intlevel 5) */ +#define XCHAL_EXTINT1_NUM 2 /* (intlevel 5) */ +#define XCHAL_EXTINT2_NUM 3 /* (intlevel 4) */ +#define XCHAL_EXTINT3_NUM 4 /* (intlevel 4) */ +#define XCHAL_EXTINT4_NUM 5 /* (intlevel 3) */ +#define XCHAL_EXTINT5_NUM 6 /* (intlevel 3) */ +#define XCHAL_EXTINT6_NUM 7 /* (intlevel 2) */ +#define XCHAL_EXTINT7_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT8_NUM 9 /* (intlevel 1) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x5FFE0400 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x5FFE0400 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x5FFE0000 +#define XCHAL_RESET_VECTOR0_PADDR 0x5FFE0000 +#define XCHAL_RESET_VECTOR1_VADDR 0xFFFF1000 +#define XCHAL_RESET_VECTOR1_PADDR 0xFFFF1000 +#define XCHAL_RESET_VECTOR_VADDR 0x5FFE0000 +#define XCHAL_RESET_VECTOR_PADDR 0x5FFE0000 +#define XCHAL_USER_VECOFS 0x0000023C +#define XCHAL_USER_VECTOR_VADDR 0x5FFE063C +#define XCHAL_USER_VECTOR_PADDR 0x5FFE063C +#define XCHAL_KERNEL_VECOFS 0x0000021C +#define XCHAL_KERNEL_VECTOR_VADDR 0x5FFE061C +#define XCHAL_KERNEL_VECTOR_PADDR 0x5FFE061C +#define XCHAL_DOUBLEEXC_VECOFS 0x0000025C +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x5FFE065C +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x5FFE065C +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x5FFE0400 +#define XCHAL_WINDOW_VECTORS_PADDR 0x5FFE0400 +#define XCHAL_INTLEVEL2_VECOFS 0x0000017C +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x5FFE057C +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x5FFE057C +#define XCHAL_INTLEVEL3_VECOFS 0x0000019C +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x5FFE059C +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x5FFE059C +#define XCHAL_INTLEVEL4_VECOFS 0x000001BC +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x5FFE05BC +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x5FFE05BC +#define XCHAL_INTLEVEL5_VECOFS 0x000001DC +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x5FFE05DC +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x5FFE05DC +#define XCHAL_INTLEVEL6_VECOFS 0x000001FC +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x5FFE05FC +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x5FFE05FC +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ + diff --git a/target/xtensa/core-dsp3400/core-matmap.h b/target/xtensa/core-dsp3400/core-matmap.h new file mode 100644 index 000000000000..8d1aa8336ec6 --- /dev/null +++ b/target/xtensa/core-dsp3400/core-matmap.h @@ -0,0 +1,312 @@ +/* + * xtensa/config/core-matmap.h -- Memory access and translation mapping + * parameters (CHAL) of the Xtensa processor core configuration. + * + * If you are using Xtensa Tools, see (which includes + * this file) for more details. + * + * In the Xtensa processor products released to date, all parameters + * defined in this file are derivable (at least in theory) from + * information contained in the core-isa.h header file. + * In particular, the following core configuration parameters are relevant: + * XCHAL_HAVE_CACHEATTR + * XCHAL_HAVE_MIMIC_CACHEATTR + * XCHAL_HAVE_XLT_CACHEATTR + * XCHAL_HAVE_PTP_MMU + * XCHAL_ITLB_ARF_ENTRIES_LOG2 + * XCHAL_DTLB_ARF_ENTRIES_LOG2 + * XCHAL_DCACHE_IS_WRITEBACK + * XCHAL_ICACHE_SIZE (presence of I-cache) + * XCHAL_DCACHE_SIZE (presence of D-cache) + * XCHAL_HW_VERSION_MAJOR + * XCHAL_HW_VERSION_MINOR + */ + +/* Copyright (c) 1999-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + + +#ifndef XTENSA_CONFIG_CORE_MATMAP_H +#define XTENSA_CONFIG_CORE_MATMAP_H + + +/*---------------------------------------------------------------------- + CACHE (MEMORY ACCESS) ATTRIBUTES + ----------------------------------------------------------------------*/ + + +/* Cache Attribute encodings -- lists of access modes for each cache attribute: */ +#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION +#define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_ISOLATE XCHAL_SEP \ + XTHAL_LAM_EXCEPTION +#define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \ + XTHAL_SAM_WRITETHRU XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_WRITEBACK XCHAL_SEP \ + XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_ISOLATE XCHAL_SEP \ + XTHAL_SAM_EXCEPTION + + +/* + * Specific encoded cache attribute values of general interest. + * If a specific cache mode is not available, the closest available + * one is returned instead (eg. writethru instead of writeback, + * bypass instead of writethru). + */ +#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */ +#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */ +#define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */ +#define XCHAL_CA_WRITEBACK_NOALLOC 4 /* cache enabled (write-back no-allocate) mode */ +#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */ +#define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* + * General notes on MMU parameters. + * + * Terminology: + * ASID = address-space ID (acts as an "extension" of virtual addresses) + * VPN = virtual page number + * PPN = physical page number + * CA = encoded cache attribute (access modes) + * TLB = translation look-aside buffer (term is stretched somewhat here) + * I = instruction (fetch accesses) + * D = data (load and store accesses) + * way = each TLB (ITLB and DTLB) consists of a number of "ways" + * that simultaneously match the virtual address of an access; + * a TLB successfully translates a virtual address if exactly + * one way matches the vaddr; if none match, it is a miss; + * if multiple match, one gets a "multihit" exception; + * each way can be independently configured in terms of number of + * entries, page sizes, which fields are writable or constant, etc. + * set = group of contiguous ways with exactly identical parameters + * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE + * from the page table and storing it in one of the auto-refill ways; + * if this PTE load also misses, a miss exception is posted for s/w. + * min-wired = a "min-wired" way can be used to map a single (minimum-sized) + * page arbitrarily under program control; it has a single entry, + * is non-auto-refill (some other way(s) must be auto-refill), + * all its fields (VPN, PPN, ASID, CA) are all writable, and it + * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current + * restriction is that this be the only page size it supports). + * + * TLB way entries are virtually indexed. + * TLB ways that support multiple page sizes: + * - must have all writable VPN and PPN fields; + * - can only use one page size at any given time (eg. setup at startup), + * selected by the respective ITLBCFG or DTLBCFG special register, + * whose bits n*4+3 .. n*4 index the list of page sizes for way n + * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); + * this list may be sparse for auto-refill ways because auto-refill + * ways have independent lists of supported page sizes sharing a + * common encoding with PTE entries; the encoding is the index into + * this list; unsupported sizes for a given way are zero in the list; + * selecting unsupported sizes results in undefined hardware behaviour; + * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). + */ + +#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ +#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */ +#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ +#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ +#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */ +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */ + + +/*** Instruction TLB: ***/ + +#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */ +#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */ +#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_ITLB_WAY0_SET 0 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ + + +/* ITLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */ +#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000 +#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000 +#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000 +#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000 +#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000 +#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000 +#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000 +#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000 +/* Reset PPN values for each entry of ITLB way set 0 (because SET0_PPN_RESET is non-zero): */ +#define XCHAL_ITLB_SET0_E0_PPN_RESET 0x00000000 +#define XCHAL_ITLB_SET0_E1_PPN_RESET 0x20000000 +#define XCHAL_ITLB_SET0_E2_PPN_RESET 0x40000000 +#define XCHAL_ITLB_SET0_E3_PPN_RESET 0x60000000 +#define XCHAL_ITLB_SET0_E4_PPN_RESET 0x80000000 +#define XCHAL_ITLB_SET0_E5_PPN_RESET 0xA0000000 +#define XCHAL_ITLB_SET0_E6_PPN_RESET 0xC0000000 +#define XCHAL_ITLB_SET0_E7_PPN_RESET 0xE0000000 +/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */ +#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02 + + +/*** Data TLB: ***/ + +#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */ +#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */ +#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_DTLB_WAY0_SET 0 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ + + +/* DTLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */ +#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000 +#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000 +#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000 +#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000 +#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000 +#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000 +#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000 +#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000 +/* Reset PPN values for each entry of DTLB way set 0 (because SET0_PPN_RESET is non-zero): */ +#define XCHAL_DTLB_SET0_E0_PPN_RESET 0x00000000 +#define XCHAL_DTLB_SET0_E1_PPN_RESET 0x20000000 +#define XCHAL_DTLB_SET0_E2_PPN_RESET 0x40000000 +#define XCHAL_DTLB_SET0_E3_PPN_RESET 0x60000000 +#define XCHAL_DTLB_SET0_E4_PPN_RESET 0x80000000 +#define XCHAL_DTLB_SET0_E5_PPN_RESET 0xA0000000 +#define XCHAL_DTLB_SET0_E6_PPN_RESET 0xC0000000 +#define XCHAL_DTLB_SET0_E7_PPN_RESET 0xE0000000 +/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */ +#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02 + + + + +#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ + diff --git a/target/xtensa/core-dsp3400/gdb-config.inc.c b/target/xtensa/core-dsp3400/gdb-config.inc.c new file mode 100644 index 000000000000..f7f5f75c9875 --- /dev/null +++ b/target/xtensa/core-dsp3400/gdb-config.inc.c @@ -0,0 +1,400 @@ +/* Configuration for the Xtensa architecture for GDB, the GNU debugger. + + Copyright (c) 2003-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0) + XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0) + XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0) + XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0) + XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0) + XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0) + XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0) + XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0) + XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0) + XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0) + XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0) + XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0) + XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0) + XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0) + XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0) + XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0) + XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0) + XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0) + XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0) + XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0) + XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0) + XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0) + XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0) + XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0) + XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0) + XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0) + XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0) + XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0) + XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0) + XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0) + XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0) + XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0) + XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0) + XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0) + XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0) + XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0) + XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0) + XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0) + XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0) + XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0) + XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0) + XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0) + XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0) + XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0) + XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0) + XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0) + XTREG( 46,184,32, 4, 4,0x0300,0x000e,-1, 3,0x0210,expstate, 0,0,0,0,0,0) + XTREG( 47,188,32, 4, 4,0x0030,0x0006, 0, 4,0x0401,f0, + "03:03:44:00","03:03:04:00",0,0,0,0) + XTREG( 48,192,32, 4, 4,0x0031,0x0006, 0, 4,0x0401,f1, + "03:13:44:00","03:13:04:00",0,0,0,0) + XTREG( 49,196,32, 4, 4,0x0032,0x0006, 0, 4,0x0401,f2, + "03:23:44:00","03:23:04:00",0,0,0,0) + XTREG( 50,200,32, 4, 4,0x0033,0x0006, 0, 4,0x0401,f3, + "03:33:44:00","03:33:04:00",0,0,0,0) + XTREG( 51,204,32, 4, 4,0x0034,0x0006, 0, 4,0x0401,f4, + "03:43:44:00","03:43:04:00",0,0,0,0) + XTREG( 52,208,32, 4, 4,0x0035,0x0006, 0, 4,0x0401,f5, + "03:53:44:00","03:53:04:00",0,0,0,0) + XTREG( 53,212,32, 4, 4,0x0036,0x0006, 0, 4,0x0401,f6, + "03:63:44:00","03:63:04:00",0,0,0,0) + XTREG( 54,216,32, 4, 4,0x0037,0x0006, 0, 4,0x0401,f7, + "03:73:44:00","03:73:04:00",0,0,0,0) + XTREG( 55,220,32, 4, 4,0x0038,0x0006, 0, 4,0x0401,f8, + "03:83:44:00","03:83:04:00",0,0,0,0) + XTREG( 56,224,32, 4, 4,0x0039,0x0006, 0, 4,0x0401,f9, + "03:93:44:00","03:93:04:00",0,0,0,0) + XTREG( 57,228,32, 4, 4,0x003a,0x0006, 0, 4,0x0401,f10, + "03:a3:44:00","03:a3:04:00",0,0,0,0) + XTREG( 58,232,32, 4, 4,0x003b,0x0006, 0, 4,0x0401,f11, + "03:b3:44:00","03:b3:04:00",0,0,0,0) + XTREG( 59,236,32, 4, 4,0x003c,0x0006, 0, 4,0x0401,f12, + "03:c3:44:00","03:c3:04:00",0,0,0,0) + XTREG( 60,240,32, 4, 4,0x003d,0x0006, 0, 4,0x0401,f13, + "03:d3:44:00","03:d3:04:00",0,0,0,0) + XTREG( 61,244,32, 4, 4,0x003e,0x0006, 0, 4,0x0401,f14, + "03:e3:44:00","03:e3:04:00",0,0,0,0) + XTREG( 62,248,32, 4, 4,0x003f,0x0006, 0, 4,0x0401,f15, + "03:f3:44:00","03:f3:04:00",0,0,0,0) + XTREG( 63,252,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr, 0,0,0,0,0,0) + XTREG( 64,256,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr, 0,0,0,0,0,0) + XTREG( 65,260, 4, 4, 4,0x0301,0x0006, 2, 3,0x0210,sov, 0,0,0,0,0,0) + XTREG( 66,264, 1, 4, 4,0x0302,0x0006, 2, 3,0x0210,sat_mode, 0,0,0,0,0,0) + XTREG( 67,268, 6, 4, 4,0x0303,0x0006, 2, 3,0x0210,sar0, 0,0,0,0,0,0) + XTREG( 68,272, 6, 4, 4,0x0304,0x0006, 2, 3,0x0210,sar1, 0,0,0,0,0,0) + XTREG( 69,276, 6, 4, 4,0x0305,0x0006, 2, 3,0x0210,sar2, 0,0,0,0,0,0) + XTREG( 70,280, 6, 4, 4,0x0306,0x0006, 2, 3,0x0210,sar3, 0,0,0,0,0,0) + XTREG( 71,284, 6, 4, 4,0x0307,0x0006, 2, 3,0x0210,hsar0, 0,0,0,0,0,0) + XTREG( 72,288, 6, 4, 4,0x0308,0x0006, 2, 3,0x0210,hsar1, 0,0,0,0,0,0) + XTREG( 73,292, 6, 4, 4,0x0309,0x0006, 2, 3,0x0210,hsar2, 0,0,0,0,0,0) + XTREG( 74,296, 6, 4, 4,0x030a,0x0006, 2, 3,0x0210,hsar3, 0,0,0,0,0,0) + XTREG( 75,300,32, 4, 4,0x030b,0x0006, 2, 3,0x0200,max_reg_0, 0,0,0,0,0,0) + XTREG( 76,304,32, 4, 4,0x030c,0x0006, 2, 3,0x0200,max_reg_1, 0,0,0,0,0,0) + XTREG( 77,308,32, 4, 4,0x030d,0x0006, 2, 3,0x0200,max_reg_2, 0,0,0,0,0,0) + XTREG( 78,312,32, 4, 4,0x030e,0x0006, 2, 3,0x0200,max_reg_3, 0,0,0,0,0,0) + XTREG( 79,316,32, 4, 4,0x030f,0x0006, 2, 3,0x0200,arg_max_reg_0,0,0,0,0,0,0) + XTREG( 80,320,32, 4, 4,0x0310,0x0006, 2, 3,0x0200,arg_max_reg_1,0,0,0,0,0,0) + XTREG( 81,324,32, 4, 4,0x0311,0x0006, 2, 3,0x0200,arg_max_reg_2,0,0,0,0,0,0) + XTREG( 82,328,32, 4, 4,0x0312,0x0006, 2, 3,0x0200,arg_max_reg_3,0,0,0,0,0,0) + XTREG( 83,332,32, 4, 4,0x0313,0x0006, 2, 3,0x0200,nco_counter_0,0,0,0,0,0,0) + XTREG( 84,336,32, 4, 4,0x0314,0x0006, 2, 3,0x0200,nco_counter_1,0,0,0,0,0,0) + XTREG( 85,340,32, 4, 4,0x0315,0x0006, 2, 3,0x0200,nco_counter_2,0,0,0,0,0,0) + XTREG( 86,344,32, 4, 4,0x0316,0x0006, 2, 3,0x0200,nco_counter_3,0,0,0,0,0,0) + XTREG( 87,348, 4, 4, 4,0x0317,0x0006, 2, 3,0x0210,interp_ext_n,0,0,0,0,0,0) + XTREG( 88,352, 4, 4, 4,0x0318,0x0006, 2, 3,0x0210,interp_ext_l,0,0,0,0,0,0) + XTREG( 89,356,32, 4, 4,0x0319,0x0006, 2, 3,0x0200,llr_buf_0, 0,0,0,0,0,0) + XTREG( 90,360,32, 4, 4,0x031a,0x0006, 2, 3,0x0200,llr_buf_1, 0,0,0,0,0,0) + XTREG( 91,364,32, 4, 4,0x031b,0x0006, 2, 3,0x0200,llr_buf_2, 0,0,0,0,0,0) + XTREG( 92,368,32, 4, 4,0x031c,0x0006, 2, 3,0x0200,llr_buf_3, 0,0,0,0,0,0) + XTREG( 93,372,32, 4, 4,0x031d,0x0006, 2, 3,0x0200,llr_buf_4, 0,0,0,0,0,0) + XTREG( 94,376,32, 4, 4,0x031e,0x0006, 2, 3,0x0200,llr_buf_5, 0,0,0,0,0,0) + XTREG( 95,380,32, 4, 4,0x031f,0x0006, 2, 3,0x0200,llr_buf_6, 0,0,0,0,0,0) + XTREG( 96,384,32, 4, 4,0x0320,0x0006, 2, 3,0x0200,llr_buf_7, 0,0,0,0,0,0) + XTREG( 97,388,32, 4, 4,0x0321,0x0006, 2, 3,0x0200,llr_buf_8, 0,0,0,0,0,0) + XTREG( 98,392,32, 4, 4,0x0322,0x0006, 2, 3,0x0200,llr_buf_9, 0,0,0,0,0,0) + XTREG( 99,396,32, 4, 4,0x0323,0x0006, 2, 3,0x0200,llr_buf_10, 0,0,0,0,0,0) + XTREG(100,400,32, 4, 4,0x0324,0x0006, 2, 3,0x0200,llr_buf_11, 0,0,0,0,0,0) + XTREG(101,404,32, 4, 4,0x0325,0x0006, 2, 3,0x0200,llr_buf_12, 0,0,0,0,0,0) + XTREG(102,408,32, 4, 4,0x0326,0x0006, 2, 3,0x0200,llr_buf_13, 0,0,0,0,0,0) + XTREG(103,412,32, 4, 4,0x0327,0x0006, 2, 3,0x0200,llr_buf_14, 0,0,0,0,0,0) + XTREG(104,416,32, 4, 4,0x0328,0x0006, 2, 3,0x0200,llr_buf_15, 0,0,0,0,0,0) + XTREG(105,420,32, 4, 4,0x0329,0x0006, 2, 3,0x0200,llr_buf_16, 0,0,0,0,0,0) + XTREG(106,424,32, 4, 4,0x032a,0x0006, 2, 3,0x0200,llr_buf_17, 0,0,0,0,0,0) + XTREG(107,428,32, 4, 4,0x032b,0x0006, 2, 3,0x0200,llr_buf_18, 0,0,0,0,0,0) + XTREG(108,432,32, 4, 4,0x032c,0x0006, 2, 3,0x0200,llr_buf_19, 0,0,0,0,0,0) + XTREG(109,436,32, 4, 4,0x032d,0x0006, 2, 3,0x0200,llr_buf_20, 0,0,0,0,0,0) + XTREG(110,440,32, 4, 4,0x032e,0x0006, 2, 3,0x0200,llr_buf_21, 0,0,0,0,0,0) + XTREG(111,444,32, 4, 4,0x032f,0x0006, 2, 3,0x0200,llr_buf_22, 0,0,0,0,0,0) + XTREG(112,448,32, 4, 4,0x0330,0x0006, 2, 3,0x0200,llr_buf_23, 0,0,0,0,0,0) + XTREG(113,452,32, 4, 4,0x0331,0x0006, 2, 3,0x0200,smod_buf_0, 0,0,0,0,0,0) + XTREG(114,456,32, 4, 4,0x0332,0x0006, 2, 3,0x0200,smod_buf_1, 0,0,0,0,0,0) + XTREG(115,460,32, 4, 4,0x0333,0x0006, 2, 3,0x0200,smod_buf_2, 0,0,0,0,0,0) + XTREG(116,464,32, 4, 4,0x0334,0x0006, 2, 3,0x0200,smod_buf_3, 0,0,0,0,0,0) + XTREG(117,468,32, 4, 4,0x0335,0x0006, 2, 3,0x0200,smod_buf_4, 0,0,0,0,0,0) + XTREG(118,472,32, 4, 4,0x0336,0x0006, 2, 3,0x0200,smod_buf_5, 0,0,0,0,0,0) + XTREG(119,476,32, 4, 4,0x0337,0x0006, 2, 3,0x0200,smod_buf_6, 0,0,0,0,0,0) + XTREG(120,480,32, 4, 4,0x0338,0x0006, 2, 3,0x0200,smod_buf_7, 0,0,0,0,0,0) + XTREG(121,484, 8, 4, 4,0x0339,0x0006, 2, 3,0x0210,weight_reg, 0,0,0,0,0,0) + XTREG(122,488, 5, 4, 4,0x033a,0x0006, 2, 3,0x0210,scale_reg, 0,0,0,0,0,0) + XTREG(123,492, 6, 4, 4,0x033b,0x0006, 2, 3,0x0210,llr_pos, 0,0,0,0,0,0) + XTREG(124,496, 7, 4, 4,0x033c,0x0006, 2, 3,0x0210,smod_pos, 0,0,0,0,0,0) + XTREG(125,500,32, 4, 4,0x033d,0x0006, 2, 3,0x0210,perm_reg, 0,0,0,0,0,0) + XTREG(126,504,32, 4, 4,0x033e,0x0006, 2, 3,0x0200,smod_offset_table_0,0,0,0,0,0,0) + XTREG(127,508,32, 4, 4,0x033f,0x0006, 2, 3,0x0200,smod_offset_table_1,0,0,0,0,0,0) + XTREG(128,512,32, 4, 4,0x0340,0x0006, 2, 3,0x0200,smod_offset_table_2,0,0,0,0,0,0) + XTREG(129,516,32, 4, 4,0x0341,0x0006, 2, 3,0x0200,smod_offset_table_3,0,0,0,0,0,0) + XTREG(130,520, 4, 4, 4,0x0342,0x0006, 2, 3,0x0210,phasor_n, 0,0,0,0,0,0) + XTREG(131,524,16, 4, 4,0x0343,0x0006, 2, 3,0x0210,phasor_offset,0,0,0,0,0,0) + XTREG(132,528,320,64,16,0x1008,0x0006, 2, 4,0x0201,acu0, + "03:00:84:f8:03:10:84:8d:03:20:84:9d:03:30:84:ac","03:43:20:08:03:43:28:03:03:43:20:33:03:43:28:25",0,0,0,0) + XTREG(133,592,320,64,16,0x1009,0x0006, 2, 4,0x0201,acu1, + "03:00:94:f8:03:10:94:8d:03:20:94:9d:03:30:94:ac","03:43:21:08:03:43:29:03:03:43:21:33:03:43:29:25",0,0,0,0) + XTREG(134,656,320,64,16,0x100a,0x0006, 2, 4,0x0201,acu2, + "03:00:a4:f8:03:10:a4:8d:03:20:a4:9d:03:30:a4:ac","03:43:22:08:03:43:2a:03:03:43:22:33:03:43:2a:25",0,0,0,0) + XTREG(135,720,320,64,16,0x100b,0x0006, 2, 4,0x0201,acu3, + "03:00:b4:f8:03:10:b4:8d:03:20:b4:9d:03:30:b4:ac","03:43:23:08:03:43:2b:03:03:43:23:33:03:43:2b:25",0,0,0,0) + XTREG(136,784,320,64,16,0x100c,0x0006, 2, 4,0x0201,acu4, + "03:00:c4:f8:03:10:c4:8d:03:20:c4:9d:03:30:c4:ac","03:43:24:08:03:43:2c:03:03:43:24:33:03:43:2c:25",0,0,0,0) + XTREG(137,848,320,64,16,0x100d,0x0006, 2, 4,0x0201,acu5, + "03:00:d4:f8:03:10:d4:8d:03:20:d4:9d:03:30:d4:ac","03:43:25:08:03:43:2d:03:03:43:25:33:03:43:2d:25",0,0,0,0) + XTREG(138,912,320,64,16,0x100e,0x0006, 2, 4,0x0201,acu6, + "03:00:e4:f8:03:10:e4:8d:03:20:e4:9d:03:30:e4:ac","03:43:26:08:03:43:2e:03:03:43:26:33:03:43:2e:25",0,0,0,0) + XTREG(139,976,320,64,16,0x100f,0x0006, 2, 4,0x0201,acu7, + "03:00:f4:f8:03:10:f4:8d:03:20:f4:9d:03:30:f4:ac","03:43:27:08:03:43:2f:03:03:43:27:33:03:43:2f:25",0,0,0,0) + XTREG(140,1040,128,16,16,0x1010,0x0006, 2, 4,0x0201,cm0, + "03:00:04:5d","03:40:03:07",0,0,0,0) + XTREG(141,1056,128,16,16,0x1011,0x0006, 2, 4,0x0201,cm1, + "03:00:14:5d","03:40:13:07",0,0,0,0) + XTREG(142,1072,128,16,16,0x1012,0x0006, 2, 4,0x0201,cm2, + "03:00:24:5d","03:40:23:07",0,0,0,0) + XTREG(143,1088,128,16,16,0x1013,0x0006, 2, 4,0x0201,cm3, + "03:00:34:5d","03:40:33:07",0,0,0,0) + XTREG(144,1104,128,16,16,0x1014,0x0006, 2, 4,0x0201,cm4, + "03:00:44:5d","03:40:43:07",0,0,0,0) + XTREG(145,1120,128,16,16,0x1015,0x0006, 2, 4,0x0201,cm5, + "03:00:54:5d","03:40:53:07",0,0,0,0) + XTREG(146,1136,128,16,16,0x1016,0x0006, 2, 4,0x0201,cm6, + "03:00:64:5d","03:40:63:07",0,0,0,0) + XTREG(147,1152,128,16,16,0x1017,0x0006, 2, 4,0x0201,cm7, + "03:00:74:5d","03:40:73:07",0,0,0,0) + XTREG(148,1168,128,16,16,0x1018,0x0006, 2, 4,0x0201,cm8, + "03:00:84:5d","03:40:83:07",0,0,0,0) + XTREG(149,1184,128,16,16,0x1019,0x0006, 2, 4,0x0201,cm9, + "03:00:94:5d","03:40:93:07",0,0,0,0) + XTREG(150,1200,128,16,16,0x101a,0x0006, 2, 4,0x0201,cm10, + "03:00:a4:5d","03:40:a3:07",0,0,0,0) + XTREG(151,1216,128,16,16,0x101b,0x0006, 2, 4,0x0201,cm11, + "03:00:b4:5d","03:40:b3:07",0,0,0,0) + XTREG(152,1232,128,16,16,0x101c,0x0006, 2, 4,0x0201,cm12, + "03:00:c4:5d","03:40:c3:07",0,0,0,0) + XTREG(153,1248,128,16,16,0x101d,0x0006, 2, 4,0x0201,cm13, + "03:00:d4:5d","03:40:d3:07",0,0,0,0) + XTREG(154,1264,128,16,16,0x101e,0x0006, 2, 4,0x0201,cm14, + "03:00:e4:5d","03:40:e3:07",0,0,0,0) + XTREG(155,1280,128,16,16,0x101f,0x0006, 2, 4,0x0201,cm15, + "03:00:f4:5d","03:40:f3:07",0,0,0,0) + XTREG(156,1296,256,32,16,0x1020,0x0006, 2, 4,0x0201,pq0, + "03:00:04:7c:03:10:04:cc","03:40:02:07:03:40:0c:07",0,0,0,0) + XTREG(157,1328,256,32,16,0x1021,0x0006, 2, 4,0x0201,pq1, + "03:00:14:7c:03:10:14:cc","03:40:12:07:03:40:1c:07",0,0,0,0) + XTREG(158,1360,256,32,16,0x1022,0x0006, 2, 4,0x0201,pq2, + "03:00:24:7c:03:10:24:cc","03:40:22:07:03:40:2c:07",0,0,0,0) + XTREG(159,1392,256,32,16,0x1023,0x0006, 2, 4,0x0201,pq3, + "03:00:34:7c:03:10:34:cc","03:40:32:07:03:40:3c:07",0,0,0,0) + XTREG(160,1424,256,32,16,0x1024,0x0006, 2, 4,0x0201,pq4, + "03:00:44:7c:03:10:44:cc","03:40:42:07:03:40:4c:07",0,0,0,0) + XTREG(161,1456,256,32,16,0x1025,0x0006, 2, 4,0x0201,pq5, + "03:00:54:7c:03:10:54:cc","03:40:52:07:03:40:5c:07",0,0,0,0) + XTREG(162,1488,256,32,16,0x1026,0x0006, 2, 4,0x0201,pq6, + "03:00:64:7c:03:10:64:cc","03:40:62:07:03:40:6c:07",0,0,0,0) + XTREG(163,1520,256,32,16,0x1027,0x0006, 2, 4,0x0201,pq7, + "03:00:74:7c:03:10:74:cc","03:40:72:07:03:40:7c:07",0,0,0,0) + XTREG(164,1552,256,32,16,0x1028,0x0006, 2, 4,0x0201,pq8, + "03:00:84:7c:03:10:84:cc","03:40:82:07:03:40:8c:07",0,0,0,0) + XTREG(165,1584,256,32,16,0x1029,0x0006, 2, 4,0x0201,pq9, + "03:00:94:7c:03:10:94:cc","03:40:92:07:03:40:9c:07",0,0,0,0) + XTREG(166,1616,256,32,16,0x102a,0x0006, 2, 4,0x0201,pq10, + "03:00:a4:7c:03:10:a4:cc","03:40:a2:07:03:40:ac:07",0,0,0,0) + XTREG(167,1648,256,32,16,0x102b,0x0006, 2, 4,0x0201,pq11, + "03:00:b4:7c:03:10:b4:cc","03:40:b2:07:03:40:bc:07",0,0,0,0) + XTREG(168,1680,256,32,16,0x102c,0x0006, 2, 4,0x0201,pq12, + "03:00:c4:7c:03:10:c4:cc","03:40:c2:07:03:40:cc:07",0,0,0,0) + XTREG(169,1712,256,32,16,0x102d,0x0006, 2, 4,0x0201,pq13, + "03:00:d4:7c:03:10:d4:cc","03:40:d2:07:03:40:dc:07",0,0,0,0) + XTREG(170,1744,256,32,16,0x102e,0x0006, 2, 4,0x0201,pq14, + "03:00:e4:7c:03:10:e4:cc","03:40:e2:07:03:40:ec:07",0,0,0,0) + XTREG(171,1776,256,32,16,0x102f,0x0006, 2, 4,0x0201,pq15, + "03:00:f4:7c:03:10:f4:cc","03:40:f2:07:03:40:fc:07",0,0,0,0) + XTREG(172,1808,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0) + XTREG(173,1812, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0) + XTREG(174,1816, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0) + XTREG(175,1820,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0) + XTREG(176,1824,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0) + XTREG(177,1828,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0) + XTREG(178,1832,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0) + XTREG(179,1836,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0) + XTREG(180,1840,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0) + XTREG(181,1844,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0) + XTREG(182,1848,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0) + XTREG(183,1852,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0) + XTREG(184,1856,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0) + XTREG(185,1860,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0) + XTREG(186,1864,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0) + XTREG(187,1868,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0) + XTREG(188,1872,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0) + XTREG(189,1876,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0) + XTREG(190,1880,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0) + XTREG(191,1884,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0) + XTREG(192,1888,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0) + XTREG(193,1892,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0) + XTREG(194,1896,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0) + XTREG(195,1900,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0) + XTREG(196,1904,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0) + XTREG(197,1908,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0) + XTREG(198,1912,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0) + XTREG(199,1916,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0) + XTREG(200,1920, 4, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0) + XTREG(201,1924,13, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0) + XTREG(202,1928,13, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0) + XTREG(203,1932,13, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0) + XTREG(204,1936,13, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0) + XTREG(205,1940,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0) + XTREG(206,1944, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0) + XTREG(207,1948,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0) + XTREG(208,1952,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0) + XTREG(209,1956,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0) + XTREG(210,1960,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0) + XTREG(211,1964, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0) + XTREG(212,1968,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0) + XTREG(213,1972,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0) + XTREG(214,1976,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0) + XTREG(215,1980,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0) + XTREG(216,1984,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0) + XTREG(217,1988,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0) + XTREG(218,1992,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0) + XTREG(219,1996,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0) + XTREG(220,2000,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0) + XTREG(221,2004,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0) + XTREG(222,2008,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0) + XTREG(223,2012,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0) + XTREG(224,2016,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0) + XTREG(225,2020,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0) + XTREG(226,2024,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0) + XTREG(227,2028,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0) + XTREG(228,2032,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0) + XTREG(229,2036,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0) + XTREG(230,2040,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0) + XTREG(231,2044, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0, + 0,0,&xtensa_mask0,0,0,0) + XTREG(232,2045, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1, + 0,0,&xtensa_mask1,0,0,0) + XTREG(233,2046, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2, + 0,0,&xtensa_mask2,0,0,0) + XTREG(234,2047, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3, + 0,0,&xtensa_mask3,0,0,0) + XTREG(235,2048, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4, + 0,0,&xtensa_mask4,0,0,0) + XTREG(236,2049, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5, + 0,0,&xtensa_mask5,0,0,0) + XTREG(237,2050, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6, + 0,0,&xtensa_mask6,0,0,0) + XTREG(238,2051, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7, + 0,0,&xtensa_mask7,0,0,0) + XTREG(239,2052, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8, + 0,0,&xtensa_mask8,0,0,0) + XTREG(240,2053, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9, + 0,0,&xtensa_mask9,0,0,0) + XTREG(241,2054, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10, + 0,0,&xtensa_mask10,0,0,0) + XTREG(242,2055, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11, + 0,0,&xtensa_mask11,0,0,0) + XTREG(243,2056, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12, + 0,0,&xtensa_mask12,0,0,0) + XTREG(244,2057, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13, + 0,0,&xtensa_mask13,0,0,0) + XTREG(245,2058, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14, + 0,0,&xtensa_mask14,0,0,0) + XTREG(246,2059, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15, + 0,0,&xtensa_mask15,0,0,0) + XTREG(247,2060, 4, 4, 4,0x2007,0x0006,-2, 6,0x1010,psintlevel, + 0,0,&xtensa_mask16,0,0,0) + XTREG(248,2064, 1, 4, 4,0x2008,0x0006,-2, 6,0x1010,psum, + 0,0,&xtensa_mask17,0,0,0) + XTREG(249,2068, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,pswoe, + 0,0,&xtensa_mask18,0,0,0) + XTREG(250,2072, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,psexcm, + 0,0,&xtensa_mask19,0,0,0) + XTREG(251,2076, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,pscallinc, + 0,0,&xtensa_mask20,0,0,0) + XTREG(252,2080, 4, 4, 4,0x200c,0x0006,-2, 6,0x1010,psowb, + 0,0,&xtensa_mask21,0,0,0) + XTREG(253,2084,20, 4, 4,0x200d,0x0006,-2, 6,0x1010,litbaddr, + 0,0,&xtensa_mask22,0,0,0) + XTREG(254,2088, 1, 4, 4,0x200e,0x0006,-2, 6,0x1010,litben, + 0,0,&xtensa_mask23,0,0,0) + XTREG(255,2092, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,dbnum, + 0,0,&xtensa_mask24,0,0,0) + XTREG(256,2096, 2, 4, 4,0x2014,0x0006, 0, 5,0x1010,roundmode, + 0,0,&xtensa_mask25,0,0,0) + XTREG(257,2100, 1, 4, 4,0x2015,0x0006, 0, 5,0x1010,invalidenable, + 0,0,&xtensa_mask26,0,0,0) + XTREG(258,2104, 1, 4, 4,0x2016,0x0006, 0, 5,0x1010,divzeroenable, + 0,0,&xtensa_mask27,0,0,0) + XTREG(259,2108, 1, 4, 4,0x2017,0x0006, 0, 5,0x1010,overflowenable, + 0,0,&xtensa_mask28,0,0,0) + XTREG(260,2112, 1, 4, 4,0x2018,0x0006, 0, 5,0x1010,underflowenable, + 0,0,&xtensa_mask29,0,0,0) + XTREG(261,2116, 1, 4, 4,0x2019,0x0006, 0, 5,0x1010,inexactenable, + 0,0,&xtensa_mask30,0,0,0) + XTREG(262,2120, 1, 4, 4,0x201a,0x0006, 0, 5,0x1010,invalidflag, + 0,0,&xtensa_mask31,0,0,0) + XTREG(263,2124, 1, 4, 4,0x201b,0x0006, 0, 5,0x1010,divzeroflag, + 0,0,&xtensa_mask32,0,0,0) + XTREG(264,2128, 1, 4, 4,0x201c,0x0006, 0, 5,0x1010,overflowflag, + 0,0,&xtensa_mask33,0,0,0) + XTREG(265,2132, 1, 4, 4,0x201d,0x0006, 0, 5,0x1010,underflowflag, + 0,0,&xtensa_mask34,0,0,0) + XTREG(266,2136, 1, 4, 4,0x201e,0x0006, 0, 5,0x1010,inexactflag, + 0,0,&xtensa_mask35,0,0,0) + XTREG(267,2140,20, 4, 4,0x201f,0x0006, 0, 5,0x1010,fpreserved20, + 0,0,&xtensa_mask36,0,0,0) + XTREG(268,2144,20, 4, 4,0x2020,0x0006, 0, 5,0x1010,fpreserved20a, + 0,0,&xtensa_mask37,0,0,0) + XTREG(269,2148, 5, 4, 4,0x2021,0x0006, 0, 5,0x1010,fpreserved5, + 0,0,&xtensa_mask38,0,0,0) + XTREG(270,2152, 7, 4, 4,0x2022,0x0006, 0, 5,0x1010,fpreserved7, + 0,0,&xtensa_mask39,0,0,0) + XTREG(271,2156,128,16, 4,0x2023,0x0006, 2, 5,0x0210,max_reg, + 0,0,&xtensa_mask40,0,0,0) + XTREG(272,2172,128,16, 4,0x2024,0x0006, 2, 5,0x0210,arg_max_reg, + 0,0,&xtensa_mask41,0,0,0) + XTREG(273,2188,128,16, 4,0x2025,0x0006, 2, 5,0x0210,nco_counter, + 0,0,&xtensa_mask42,0,0,0) + XTREG(274,2204,768,96, 4,0x2026,0x0006, 2, 5,0x0210,llr_buf, + 0,0,&xtensa_mask43,0,0,0) + XTREG(275,2300,256,32, 4,0x2027,0x0006, 2, 5,0x0210,smod_buf, + 0,0,&xtensa_mask44,0,0,0) + XTREG_END diff --git a/target/xtensa/core-dsp3400/xtensa-modules.inc.c b/target/xtensa/core-dsp3400/xtensa-modules.inc.c new file mode 100644 index 000000000000..28ea3d75fef0 --- /dev/null +++ b/target/xtensa/core-dsp3400/xtensa-modules.inc.c @@ -0,0 +1,171906 @@ +/* Xtensa configuration-specific ISA information. + + Copyright (c) 2003-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "xtensa-isa.h" +#include "xtensa-isa-internal.h" + + +/* Sysregs. */ + +static xtensa_sysreg_internal sysregs[] = { + { "LBEG", 0, 0 }, + { "LEND", 1, 0 }, + { "LCOUNT", 2, 0 }, + { "BR", 4, 0 }, + { "MMID", 89, 0 }, + { "DDR", 104, 0 }, + { "176", 176, 0 }, + { "208", 208, 0 }, + { "INTERRUPT", 226, 0 }, + { "INTCLEAR", 227, 0 }, + { "CCOUNT", 234, 0 }, + { "PRID", 235, 0 }, + { "ICOUNT", 236, 0 }, + { "CCOMPARE0", 240, 0 }, + { "CCOMPARE1", 241, 0 }, + { "VECBASE", 231, 0 }, + { "EPC1", 177, 0 }, + { "EPC2", 178, 0 }, + { "EPC3", 179, 0 }, + { "EPC4", 180, 0 }, + { "EPC5", 181, 0 }, + { "EPC6", 182, 0 }, + { "EXCSAVE1", 209, 0 }, + { "EXCSAVE2", 210, 0 }, + { "EXCSAVE3", 211, 0 }, + { "EXCSAVE4", 212, 0 }, + { "EXCSAVE5", 213, 0 }, + { "EXCSAVE6", 214, 0 }, + { "EPS2", 194, 0 }, + { "EPS3", 195, 0 }, + { "EPS4", 196, 0 }, + { "EPS5", 197, 0 }, + { "EPS6", 198, 0 }, + { "EXCCAUSE", 232, 0 }, + { "DEPC", 192, 0 }, + { "EXCVADDR", 238, 0 }, + { "WINDOWBASE", 72, 0 }, + { "WINDOWSTART", 73, 0 }, + { "SAR", 3, 0 }, + { "LITBASE", 5, 0 }, + { "PS", 230, 0 }, + { "INTENABLE", 228, 0 }, + { "DBREAKA0", 144, 0 }, + { "DBREAKC0", 160, 0 }, + { "DBREAKA1", 145, 0 }, + { "DBREAKC1", 161, 0 }, + { "IBREAKA0", 128, 0 }, + { "IBREAKA1", 129, 0 }, + { "IBREAKENABLE", 96, 0 }, + { "ICOUNTLEVEL", 237, 0 }, + { "DEBUGCAUSE", 233, 0 }, + { "CPENABLE", 224, 0 }, + { "SCOMPARE1", 12, 0 }, + { "ATOMCTL", 99, 0 }, + { "THREADPTR", 231, 1 }, + { "FCR", 232, 1 }, + { "FSR", 233, 1 }, + { "EXPSTATE", 0, 1 }, + { "SOV", 1, 1 }, + { "SAT_MODE", 2, 1 }, + { "SAR0", 3, 1 }, + { "SAR1", 4, 1 }, + { "SAR2", 5, 1 }, + { "SAR3", 6, 1 }, + { "HSAR0", 7, 1 }, + { "HSAR1", 8, 1 }, + { "HSAR2", 9, 1 }, + { "HSAR3", 10, 1 }, + { "MAX_REG_0", 11, 1 }, + { "MAX_REG_1", 12, 1 }, + { "MAX_REG_2", 13, 1 }, + { "MAX_REG_3", 14, 1 }, + { "ARG_MAX_REG_0", 15, 1 }, + { "ARG_MAX_REG_1", 16, 1 }, + { "ARG_MAX_REG_2", 17, 1 }, + { "ARG_MAX_REG_3", 18, 1 }, + { "NCO_COUNTER_0", 19, 1 }, + { "NCO_COUNTER_1", 20, 1 }, + { "NCO_COUNTER_2", 21, 1 }, + { "NCO_COUNTER_3", 22, 1 }, + { "INTERP_EXT_N", 23, 1 }, + { "INTERP_EXT_L", 24, 1 }, + { "LLR_BUF_0", 25, 1 }, + { "LLR_BUF_1", 26, 1 }, + { "LLR_BUF_2", 27, 1 }, + { "LLR_BUF_3", 28, 1 }, + { "LLR_BUF_4", 29, 1 }, + { "LLR_BUF_5", 30, 1 }, + { "LLR_BUF_6", 31, 1 }, + { "LLR_BUF_7", 32, 1 }, + { "LLR_BUF_8", 33, 1 }, + { "LLR_BUF_9", 34, 1 }, + { "LLR_BUF_10", 35, 1 }, + { "LLR_BUF_11", 36, 1 }, + { "LLR_BUF_12", 37, 1 }, + { "LLR_BUF_13", 38, 1 }, + { "LLR_BUF_14", 39, 1 }, + { "LLR_BUF_15", 40, 1 }, + { "LLR_BUF_16", 41, 1 }, + { "LLR_BUF_17", 42, 1 }, + { "LLR_BUF_18", 43, 1 }, + { "LLR_BUF_19", 44, 1 }, + { "LLR_BUF_20", 45, 1 }, + { "LLR_BUF_21", 46, 1 }, + { "LLR_BUF_22", 47, 1 }, + { "LLR_BUF_23", 48, 1 }, + { "SMOD_BUF_0", 49, 1 }, + { "SMOD_BUF_1", 50, 1 }, + { "SMOD_BUF_2", 51, 1 }, + { "SMOD_BUF_3", 52, 1 }, + { "SMOD_BUF_4", 53, 1 }, + { "SMOD_BUF_5", 54, 1 }, + { "SMOD_BUF_6", 55, 1 }, + { "SMOD_BUF_7", 56, 1 }, + { "WEIGHT_REG", 57, 1 }, + { "SCALE_REG", 58, 1 }, + { "LLR_POS", 59, 1 }, + { "SMOD_POS", 60, 1 }, + { "PERM_REG", 61, 1 }, + { "SMOD_OFFSET_TABLE_0", 62, 1 }, + { "SMOD_OFFSET_TABLE_1", 63, 1 }, + { "SMOD_OFFSET_TABLE_2", 64, 1 }, + { "SMOD_OFFSET_TABLE_3", 65, 1 }, + { "PHASOR_N", 66, 1 }, + { "PHASOR_OFFSET", 67, 1 } +}; + +#define NUM_SYSREGS 125 +#define MAX_SPECIAL_REG 241 +#define MAX_USER_REG 233 + + +/* Processor states. */ + +static xtensa_state_internal states[] = { + { "LCOUNT", 32, 0 }, + { "PC", 32, 0 }, + { "ICOUNT", 32, 0 }, + { "DDR", 32, 0 }, + { "INTERRUPT", 13, 0 }, + { "CCOUNT", 32, 0 }, + { "XTSYNC", 1, 0 }, + { "VECBASE", 22, 0 }, + { "EPC1", 32, 0 }, + { "EPC2", 32, 0 }, + { "EPC3", 32, 0 }, + { "EPC4", 32, 0 }, + { "EPC5", 32, 0 }, + { "EPC6", 32, 0 }, + { "EXCSAVE1", 32, 0 }, + { "EXCSAVE2", 32, 0 }, + { "EXCSAVE3", 32, 0 }, + { "EXCSAVE4", 32, 0 }, + { "EXCSAVE5", 32, 0 }, + { "EXCSAVE6", 32, 0 }, + { "EPS2", 13, 0 }, + { "EPS3", 13, 0 }, + { "EPS4", 13, 0 }, + { "EPS5", 13, 0 }, + { "EPS6", 13, 0 }, + { "EXCCAUSE", 6, 0 }, + { "PSINTLEVEL", 4, 0 }, + { "PSUM", 1, 0 }, + { "PSWOE", 1, 0 }, + { "PSEXCM", 1, 0 }, + { "DEPC", 32, 0 }, + { "EXCVADDR", 32, 0 }, + { "WindowBase", 3, 0 }, + { "WindowStart", 8, 0 }, + { "PSCALLINC", 2, 0 }, + { "PSOWB", 4, 0 }, + { "LBEG", 32, 0 }, + { "LEND", 32, 0 }, + { "SAR", 6, 0 }, + { "THREADPTR", 32, 0 }, + { "LITBADDR", 20, 0 }, + { "LITBEN", 1, 0 }, + { "InOCDMode", 1, 0 }, + { "INTENABLE", 13, 0 }, + { "DBREAKA0", 32, 0 }, + { "DBREAKC0", 8, 0 }, + { "DBREAKA1", 32, 0 }, + { "DBREAKC1", 8, 0 }, + { "IBREAKA0", 32, 0 }, + { "IBREAKA1", 32, 0 }, + { "IBREAKENABLE", 2, 0 }, + { "ICOUNTLEVEL", 4, 0 }, + { "DEBUGCAUSE", 6, 0 }, + { "DBNUM", 4, 0 }, + { "CCOMPARE0", 32, 0 }, + { "CCOMPARE1", 32, 0 }, + { "CPENABLE", 4, 0 }, + { "SCOMPARE1", 32, 0 }, + { "ATOMCTL", 6, 0 }, + { "RoundMode", 2, 0 }, + { "InvalidEnable", 1, 0 }, + { "DivZeroEnable", 1, 0 }, + { "OverflowEnable", 1, 0 }, + { "UnderflowEnable", 1, 0 }, + { "InexactEnable", 1, 0 }, + { "InvalidFlag", 1, 0 }, + { "DivZeroFlag", 1, 0 }, + { "OverflowFlag", 1, 0 }, + { "UnderflowFlag", 1, 0 }, + { "InexactFlag", 1, 0 }, + { "FPreserved20", 20, 0 }, + { "FPreserved20a", 20, 0 }, + { "FPreserved5", 5, 0 }, + { "FPreserved7", 7, 0 }, + { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }, + { "SOV", 4, XTENSA_STATE_IS_SHARED_OR }, + { "SAT_MODE", 1, 0 }, + { "SAR0", 6, 0 }, + { "SAR1", 6, 0 }, + { "SAR2", 6, 0 }, + { "SAR3", 6, 0 }, + { "HSAR0", 6, 0 }, + { "HSAR1", 6, 0 }, + { "HSAR2", 6, 0 }, + { "HSAR3", 6, 0 }, + { "MAX_REG", 128, 0 }, + { "ARG_MAX_REG", 128, 0 }, + { "NCO_COUNTER", 128, 0 }, + { "INTERP_EXT_N", 4, 0 }, + { "INTERP_EXT_L", 4, 0 }, + { "LLR_BUF", 768, 0 }, + { "SMOD_BUF", 256, 0 }, + { "WEIGHT_REG", 8, 0 }, + { "SCALE_REG", 5, 0 }, + { "LLR_POS", 6, 0 }, + { "SMOD_POS", 7, 0 }, + { "PERM_REG", 32, 0 }, + { "SMOD_OFFSET_TABLE", 128, 0 }, + { "PHASOR_N", 4, 0 }, + { "PHASOR_OFFSET", 16, 0 } +}; + +#define NUM_STATES 100 + +enum xtensa_state_id { + STATE_LCOUNT, + STATE_PC, + STATE_ICOUNT, + STATE_DDR, + STATE_INTERRUPT, + STATE_CCOUNT, + STATE_XTSYNC, + STATE_VECBASE, + STATE_EPC1, + STATE_EPC2, + STATE_EPC3, + STATE_EPC4, + STATE_EPC5, + STATE_EPC6, + STATE_EXCSAVE1, + STATE_EXCSAVE2, + STATE_EXCSAVE3, + STATE_EXCSAVE4, + STATE_EXCSAVE5, + STATE_EXCSAVE6, + STATE_EPS2, + STATE_EPS3, + STATE_EPS4, + STATE_EPS5, + STATE_EPS6, + STATE_EXCCAUSE, + STATE_PSINTLEVEL, + STATE_PSUM, + STATE_PSWOE, + STATE_PSEXCM, + STATE_DEPC, + STATE_EXCVADDR, + STATE_WindowBase, + STATE_WindowStart, + STATE_PSCALLINC, + STATE_PSOWB, + STATE_LBEG, + STATE_LEND, + STATE_SAR, + STATE_THREADPTR, + STATE_LITBADDR, + STATE_LITBEN, + STATE_InOCDMode, + STATE_INTENABLE, + STATE_DBREAKA0, + STATE_DBREAKC0, + STATE_DBREAKA1, + STATE_DBREAKC1, + STATE_IBREAKA0, + STATE_IBREAKA1, + STATE_IBREAKENABLE, + STATE_ICOUNTLEVEL, + STATE_DEBUGCAUSE, + STATE_DBNUM, + STATE_CCOMPARE0, + STATE_CCOMPARE1, + STATE_CPENABLE, + STATE_SCOMPARE1, + STATE_ATOMCTL, + STATE_RoundMode, + STATE_InvalidEnable, + STATE_DivZeroEnable, + STATE_OverflowEnable, + STATE_UnderflowEnable, + STATE_InexactEnable, + STATE_InvalidFlag, + STATE_DivZeroFlag, + STATE_OverflowFlag, + STATE_UnderflowFlag, + STATE_InexactFlag, + STATE_FPreserved20, + STATE_FPreserved20a, + STATE_FPreserved5, + STATE_FPreserved7, + STATE_EXPSTATE, + STATE_SOV, + STATE_SAT_MODE, + STATE_SAR0, + STATE_SAR1, + STATE_SAR2, + STATE_SAR3, + STATE_HSAR0, + STATE_HSAR1, + STATE_HSAR2, + STATE_HSAR3, + STATE_MAX_REG, + STATE_ARG_MAX_REG, + STATE_NCO_COUNTER, + STATE_INTERP_EXT_N, + STATE_INTERP_EXT_L, + STATE_LLR_BUF, + STATE_SMOD_BUF, + STATE_WEIGHT_REG, + STATE_SCALE_REG, + STATE_LLR_POS, + STATE_SMOD_POS, + STATE_PERM_REG, + STATE_SMOD_OFFSET_TABLE, + STATE_PHASOR_N, + STATE_PHASOR_OFFSET +}; + + +/* Field definitions. */ + +static unsigned +Field_t_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_s_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_r_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op1_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_op0_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_n_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_m_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_sr_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2098inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2098inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2019_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2019_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld2100inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2100inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2102inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2102inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2186inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2186inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2185inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2185inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2149inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2149inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3627inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3627inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2187inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2187inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2101inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2101inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2103inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2103inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2189inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2189inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2188inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2188inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2104inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2104inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2190inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2190inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2094inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2094inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); + tie_t = (val << 21) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2105inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2105inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2191inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2191inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2192inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2192inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2194inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2194inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2197inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2197inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2160inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2160inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2173inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2173inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2112inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2112inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2199inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2199inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2200inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2200inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2114inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2114inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2113inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2113inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2201inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2201inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2115inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2115inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2215inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2215inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3630inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3630inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld2203inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2203inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 22) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2254_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2254_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2116inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2116inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2117inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2117inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2119inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2119inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2048_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2048_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2089inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2089inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_r2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3631inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3631inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2085inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 11) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2085inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2088inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2088inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3633inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3633inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2082inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2082inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2083inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2083inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2084inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2084inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2086inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2086inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3634_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3634_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld2156inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2156inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2037_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2037_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld2021_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2021_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + return tie_t; +} + +static void +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2035_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2035_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld2225inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2225inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2226inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2226inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2228inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2228inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2230inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2230inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2222inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2222inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld2221inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2221inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2238inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2238inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2239inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2239inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2241inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2241inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2223inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2223inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld2232inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2232inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld2234inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2234inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld2237inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2237inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld2240inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2240inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld2229inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2229inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2224inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2224inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld2227inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2227inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld2231inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2231inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2247inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2247inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2091inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2091inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2153inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2153inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3635inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3635inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld2154inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2154inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3636inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3636inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld2155inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2155inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3637inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3637inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld2134inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2134inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 19) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e00) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2096inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2096inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2244inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2244inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2245inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2245inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2246inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2246inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3638inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3638inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2235inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2235inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2157inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2157inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2253inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2253inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3639inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3639inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2255inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2255inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3640inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3640inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2171inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2171inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 22) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2172inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2172inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 22) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2174inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2174inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 22) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2158inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2158inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2205inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2205inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2159inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2159inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2161inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2161inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2168inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2168inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2136inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2136inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2090inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2090inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2184inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2184inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3642inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3642inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2252inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2252inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3643inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3643inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2092inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2092inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); + tie_t = (val << 21) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2216inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2216inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3644inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3644inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2217inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2217inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_dsp340050b49a6c_fld3645inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3645inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2208inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2208inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2209inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2209inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2210inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2210inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2212inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2212inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2213inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2213inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x600) | (tie_t << 9); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3647inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3647inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2214inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2214inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3648inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3648inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2120inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2120inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); + tie_t = (val << 16) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2122inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2122inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); + tie_t = (val << 16) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2123inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2123inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); + tie_t = (val << 16) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2125inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2125inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); + tie_t = (val << 16) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2129inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2129inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); + tie_t = (val << 22) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); + tie_t = (val << 18) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2124inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2124inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); + tie_t = (val << 16) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2126inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2126inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); + tie_t = (val << 16) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2127inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2127inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); + tie_t = (val << 16) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2128inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2128inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4); + tie_t = (val << 16) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2131inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2131inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); + tie_t = (val << 22) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); + tie_t = (val << 18) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2138inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2138inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2146inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2146inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3649inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3649inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld2147inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2147inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3650inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3650inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2139inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2139inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2140inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2140inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2142inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2142inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2248inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2248inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3651inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3651inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2250inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2250inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3653inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3653inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2257inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2257inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld3654inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3654inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2249inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2249inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3655inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3655inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2107inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2107inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 21) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2118inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2118inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 21) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2108inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2108inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 21) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2109inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2109inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 21) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2111inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2111inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 21) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2110inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2110inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 21) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2145inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 16) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2145inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf800) | (tie_t << 11); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2141inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2141inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2143inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 16) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2143inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff00) | (tie_t << 8); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2144inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2144inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); + tie_t = (val << 21) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2204inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2204inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x700) | (tie_t << 8); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3656inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3656inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2195inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2195inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2196inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2196inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2198inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2198inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2169inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2169inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2220inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2220inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2106inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2106inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2151inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2151inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_dsp340050b49a6c_fld3657inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3657inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2251inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2251inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3658inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3658inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2206inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2206inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2202inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2202inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); + tie_t = (val << 22) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2095inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2095inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); + tie_t = (val << 21) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2132inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2132inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 22) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3659inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3659inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2099inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 7) | ((insn[0] << 16) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2099inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0xfe00) | (tie_t << 9); + tie_t = (val << 21) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2137inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2137inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2133inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2133inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3660inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3660inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2175inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2175inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 19) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2177inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2177inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 19) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2242inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2242inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3661inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3661inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2162inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2162inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2164inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2164inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2163inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2163inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2218inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2218inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2219inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2219inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2207inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2207inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2211inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2211inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2165inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2165inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2166inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2166inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2178inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2178inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 19) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2180inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2180inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 19) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2179inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2179inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 19) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2181inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2181inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 19) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2167inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2167inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2193inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2193inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3662inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3662inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2236inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2236inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2243inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2243inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2182inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2182inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 19) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2183inst_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 20) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2183inst_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0) | (tie_t << 4); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 19) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); + return tie_t; +} + +static void +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf) | (tie_t << 0); +} + +static unsigned +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_sae_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_sae_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_op0_s3_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s3_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_dsp340050b49a6c_fld2260gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2260gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2258gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2258gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2282gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2282gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2281gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2281gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2266gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 13) >> 18); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2266gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 17) >> 18; + insn[0] = (insn[0] & ~0x7ffe0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2302_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2302_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2312gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2312gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2386_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2386_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2283gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2283gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2286gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2286gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2287gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2287gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2289gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2289gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2293gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2293gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2288gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2288gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2290gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2290gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2359gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2359gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); + tie_t = (val << 20) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2384_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2384_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2361gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2361gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); + tie_t = (val << 20) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2362gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 10) | ((insn[0] << 19) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2362gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8) | (tie_t << 3); + tie_t = (val << 21) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3663gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3663gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2364gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2364gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); + tie_t = (val << 23) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); + tie_t = (val << 22) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3664gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3664gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2366gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2366gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3665gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3665gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2308gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2308gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2259gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2259gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 25) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2262gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 13) >> 19); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2262gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2284gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2284gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2275gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2275gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2354gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2354gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2333gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2333gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2310gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2310gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3667gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3667gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2357gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2357gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2376gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2376gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2313_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2313_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2343gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2343gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2342gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2342gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2344gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2344gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2345gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2345gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2346gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2346gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2373gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2373gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2374gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2374gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2375gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2375gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2335gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2335gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2339gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2339gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2334gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2334gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2336gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2336gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2337gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2337gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2338gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2338gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2340gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2340gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2341gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2341gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2369gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2369gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3668gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3668gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2280gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2280gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2309gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2309gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2261gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2261gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2321gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2321gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2322gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2322gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2355gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2355gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2324gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2324gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2372gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2372gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3669gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3669gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2263gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 13) >> 15); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2263gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x7fffc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2044_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2044_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2264gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 13) >> 18); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2264gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 17) >> 18; + insn[0] = (insn[0] & ~0x7ffe0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2368gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2368gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3670gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3670gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2291gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2291gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2292gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2292gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2294gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2294gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2295gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2295gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2297gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2297gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2296gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2296gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2301gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2301gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2272_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2272_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2277gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2277gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2279gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2279gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2278gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2278gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2267gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2267gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2268gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2268gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2269gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2269gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2271gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2271gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 21) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2305_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2305_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld2270gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2270gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2273gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2273gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 21) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2298gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2298gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2299gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2299gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2300gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2300gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2303gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2303gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3671gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3671gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2379gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2379gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3673gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3673gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2274gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 13) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2274gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x7f800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2306gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2306gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2304gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2304gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3674gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3674gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2353gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2353gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2371gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2371gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3675gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3675gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2314gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2314gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2316gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2316gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2317gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2317gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2319gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2319gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2378gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2378gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3676gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3676gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2323gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2323gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2331gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2331gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2347gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2347gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2383gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2383gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3678gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3678gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld2318gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2318gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2332gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2332gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2348gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2348gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2349gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2349gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2351gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2351gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2370gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2370gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2032_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2032_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2320gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2320gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2350gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2350gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2352gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2352gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2325gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2325gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2327gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2327gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2326gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2326gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2328gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2328gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2356gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2356gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2329gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2329gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2381gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2381gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3666_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3666_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2330gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2330gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2385gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2385gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2387gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2387gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2388gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2388gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3679gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3679gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2358gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2358gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2389gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2389gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3680gp_slot2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3680gp_slot2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2399gp_slot1_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2399gp_slot1_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_op0_s4_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s4_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3681gp_slot1_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3681gp_slot1_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 23) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2395gp_slot1_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2395gp_slot1_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2394gp_slot1_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2394gp_slot1_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2397gp_slot1_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2397gp_slot1_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2400gp_slot1_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2400gp_slot1_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3683gp_slot1_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3683gp_slot1_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2402gp_slot1_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2402gp_slot1_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2403gp_slot1_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2403gp_slot1_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3684gp_slot1_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3684gp_slot1_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2405gp_slot1_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2405gp_slot1_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3686gp_slot1_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3686gp_slot1_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2398gp_slot1_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2398gp_slot1_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_sae_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_sae_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_op0_s5_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s5_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_dsp340050b49a6c_fld2447gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2447gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3688gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3688gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2449gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2449gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3689gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3689gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2418gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2418gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2462_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2462_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2464gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2464gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2454gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2454gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2436gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2436gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 21) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3690gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3690gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2438gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 13) >> 19); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2438gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2437gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2437gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2526gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2526gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2460gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2460gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2459gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2459gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2445_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2445_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2427gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2427gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 21) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2420gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2420gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2424gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2424gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2425gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2425gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2480gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2480gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2479gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2479gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2419gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2419gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2481gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2481gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2483gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2483gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2487gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2487gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2482gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2482gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2426gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2426gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2484gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2484gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2422gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2422gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2429gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2429gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2485gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2485gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2486gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2486gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2488gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2488gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2531gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2531gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3691gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3691gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2493gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2493gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2506gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2506gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3692gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3692gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2494gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2494gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2407gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2407gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2413gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2413gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2415gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2415gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2417gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2417gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2441gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2441gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3693gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3693gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2409gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2409gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2410gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2410gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2416gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2416gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2411gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2411gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2412gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2412gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2453gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2453gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2451gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2451gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2452gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2452gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2516gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2516gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2512gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2512gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2514gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2514gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2515gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2515gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2443gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 13) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2443gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2444gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2444gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2067_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2067_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2439gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2439gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 19) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld3695gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3695gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2423gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2423gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2508gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2508gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2058_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2058_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2509gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2509gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2510gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2510gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3696gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3696gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2496gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2496gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_s8_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2527gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2527gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2036_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2036_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2528gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2528gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3697gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3697gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2523gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2523gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3698gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3698gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld2455gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2455gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2456gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2456gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2458gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2458gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2457gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2457gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2440gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2440gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 19) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2524gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2524gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 25) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3699gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3699gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld2503gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2503gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2507gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2507gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3700gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3700gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2498gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2498gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2500gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2500gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2501gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2501gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2502gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2502gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2504gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2504gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2505gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2505gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2433gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2433gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2430gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2430gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2431gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2431gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2432gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2432gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2434gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2434gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2435gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2435gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2517gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2517gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2518gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2518gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2519gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2519gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2520gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2520gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2489gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2489gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2491gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2491gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2490gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2490gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2492gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2492gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2529gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2529gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3702gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3702gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2468gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2468gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2470gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2470gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2448_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2448_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3703gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3703gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2521gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2521gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2530_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2530_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld2461gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2461gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2463gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2463gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2497gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2497gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2499gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2499gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2465gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2465gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2467gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2467gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2471gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2471gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2473gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2473gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2477gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2477gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 21) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3705gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3705gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2472gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2472gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2495gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2495gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3706gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3706gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2466gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2466gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2474gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2474gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2475gp_slot0_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2475gp_slot0_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 19) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2595dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); + tie_t = (tie_t << 9) | ((insn[0] << 21) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2595dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc) | (tie_t << 2); + tie_t = (val << 16) >> 25; + insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); +} + +static unsigned +Field_op0_s6_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s6_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_dsp340050b49a6c_fld3708dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3708dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2579dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2579dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2580dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2580dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2582dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2582dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2586dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2586dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2581dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2581dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2583dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2583dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2599dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 10) | ((insn[0] << 20) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2599dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc) | (tie_t << 2); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3709dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3709dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2614_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2614_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2604dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2604dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 23) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3710dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3710dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2606dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2606dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3711dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3711dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2601dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 10) | ((insn[0] << 20) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2601dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc) | (tie_t << 2); + tie_t = (val << 20) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2602dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2602dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); + tie_t = (val << 21) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3713dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3713dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2645dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2645dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3714dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3714dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2658dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2658dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3716dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3716dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3717dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3717dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld2636dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 12) >> 18); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2636dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2577dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2577dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2635dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2635dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3719dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3719dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2571dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2571dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2547dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2547dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2646dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2646dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_dsp340050b49a6c_fld3721dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3721dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2574dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2574dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2655dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2655dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2029_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2029_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2557dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2557dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2558dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2558dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2560dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2560dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2559dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2559dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2561dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2561dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2562dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2562dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2563dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2563dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2647dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2647dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2549dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2549dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2550dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2550dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2552dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2552dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2556dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2556dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2551dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2551dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2553dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2553dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2554dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2554dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2555dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2555dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2573dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2573dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2628dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2628dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_dsp340050b49a6c_fld3722_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3722_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2642dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2642dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2605_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2605_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2539dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2539dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2578_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2578_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2541dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2541dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2572dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2572dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2542dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2542dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3723dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 18) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3723dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld2591dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 12) >> 14); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2591dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2596dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2596dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 19) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3724dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3724dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2592dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 12) >> 25); + tie_t = (tie_t << 9) | ((insn[0] << 21) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2592dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc) | (tie_t << 2); + tie_t = (val << 16) >> 25; + insn[0] = (insn[0] & ~0xfe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2598dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2598dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2584dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2584dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2585dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2585dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2587dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2587dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2588dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2588dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2590dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2590dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2589dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2589dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2608dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2608dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2609dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2609dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2610dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2610dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2626dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2626dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3715_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3715_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2613dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2613dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 19) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2616dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2616dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 19) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2621dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2621dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 19) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2615dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2615dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 19) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2617dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2617dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 19) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2618dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2618dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 19) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2637dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2637dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 19) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3725dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3725dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2641dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2641dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld3726dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3726dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2619dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2619dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 18) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2620dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2620dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 18) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2622dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2622dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 19) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2623dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2623dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3727dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3727dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2654dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2654dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3728dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3728dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2611dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2611dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2612_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2612_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2624dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2624dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 21) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3729dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3729dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2625_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2625_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3731dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3731dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2643dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2643dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2640dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2640dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 19) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld2569dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2569dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2632dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2632dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_t_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2532dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2532dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2644dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2644dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3732dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3732dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2533dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2533dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2534dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2534dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2536dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2536dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2652dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2652dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3718_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3718_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2540dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2540dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2548dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2548dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2564dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2564dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2657dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2657dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2535dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2535dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2537dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2537dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2565dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2565dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2566dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2566dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2568dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2568dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2630dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2630dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2032_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2032_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2538dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2538dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2633dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2633dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3733dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3733dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2567dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2567dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2544dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2544dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2543dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2543dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2545dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2545dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2546dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2546dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2575dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2575dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2648dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2648dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2649dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2649dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2651dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2651dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2656dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2656dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3712_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3712_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2576dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2576dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2650dot_slot2_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2650dot_slot2_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_op0_s7_Slot_dot_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s7_Slot_dot_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3734dot_slot1_Slot_dot_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 15) >> 17); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3734dot_slot1_Slot_dot_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2068_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2068_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_op0_s8_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s8_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2668dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2668dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2666dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2666dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2674dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2674dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2688dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2688dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3735dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3735dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2705dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2705dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3737dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3737dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2677dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2677dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2678dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2678dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2679dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2679dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2690dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2690dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2680dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2680dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_t_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2697dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2697dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3738dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3738dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2667dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2667dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2704dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2704dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3739dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 21) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3739dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2689dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2689dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_r_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2669dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2669dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2671dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2671dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2675dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2675dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2672dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2672dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2673dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2673dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2676dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2676dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2682dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2682dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2686dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2686dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3736_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3736_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2681dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2681dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2683dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2683dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2684dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2684dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2685dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2685dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2699dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2699dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3740dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3740dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2692dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2692dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2693dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2693dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2695dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2695dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3741dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3741dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3742dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3742dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2700dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2700dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2702dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2702dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2701dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2701dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2703dot_slot0_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2703dot_slot0_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_sae_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_sae_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_op0_s9_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s9_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_dsp340050b49a6c_fld2707pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2707pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2817_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2817_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2739pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2739pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3744pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3744pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2717pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2717pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2713pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 13) >> 18); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2713pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 17) >> 18; + insn[0] = (insn[0] & ~0x7ffe0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld3745pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3745pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_t_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2718pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2718pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2721pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2721pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2722pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2722pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2724pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2724pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2728pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2728pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2736pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2736pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 22) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2819_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2819_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2723pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2723pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2793pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2793pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); + tie_t = (val << 20) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2795pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 11) | ((insn[0] << 19) >> 21); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2795pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x1ffc) | (tie_t << 2); + tie_t = (val << 20) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2796pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 10) | ((insn[0] << 19) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2796pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x1ff8) | (tie_t << 3); + tie_t = (val << 21) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3746pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3746pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2798pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2798pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); + tie_t = (val << 23) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); + tie_t = (val << 22) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3747pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3747pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2801pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2801pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3749pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3749pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2743pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2743pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3750pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3750pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2706pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 13) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2706pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2709pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 13) >> 19); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2709pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2719pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2719pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2715pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2715pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2788pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2788pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2747pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2747pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2791pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2791pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2775pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2775pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2777pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2777pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2776pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2776pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2778pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2778pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2779pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2779pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2780pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2780pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2810pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2810pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2811pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2811pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2767pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2767pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2769pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2769pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2773pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2773pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2768pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2768pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2770pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2770pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2771pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2771pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2772pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2772pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2774pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2774pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2805pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2805pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3751pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3751pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2741pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2741pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2746pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2746pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3752pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3752pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2755pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2755pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2756pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2756pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2789pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2789pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2758pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2758pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2809pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2809pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3753pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3753pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2710pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 17) | ((insn[0] << 13) >> 15); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2710pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 15) >> 15; + insn[0] = (insn[0] & ~0x7fffc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2711pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 13) >> 18); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2711pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 17) >> 18; + insn[0] = (insn[0] & ~0x7ffe0) | (tie_t << 5); +} + +static unsigned +Field_s_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2803pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2803pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3754pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3754pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2725pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2725pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2726pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2726pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2727pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2727pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2729pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2729pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2730pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2730pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2732pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2732pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2731pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2731pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2733pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2733pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2734pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2734pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2735pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2735pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2807pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2807pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3756pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3756pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2742pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2742pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2738pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2738pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 22) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2708pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2708pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2714pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 13) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2714pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x7fe00) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2787pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2787pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2808pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2808pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3757pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3757pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2748pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2748pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2750pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2750pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2751pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2751pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2753pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2753pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2816pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2816pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_imm7_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_imm7_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2757pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2757pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2765pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2765pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2781pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2781pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2814pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2814pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3758pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3758pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld2752pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2752pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2766pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2766pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2782pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2782pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2783pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2783pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2785pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2785pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2806pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2806pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2025_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2025_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2754pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2754pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2784pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2784pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2786pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2786pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2759pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2759pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2761pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2761pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2760pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2760pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2762pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2762pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2790pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2790pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2763pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2763pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2812pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2812pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3748_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3748_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2764pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2764pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2818pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2818pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2737_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2737_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2820pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2820pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2821pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2821pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3759pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3759pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2792pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2792pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2823pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2823pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3760pq_slot2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3760pq_slot2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld2826pq_slot1_Slot_pq_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2826pq_slot1_Slot_pq_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_op0_s10_Slot_pq_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s10_Slot_pq_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_dsp340050b49a6c_fld3761pq_slot1_Slot_pq_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 7) | ((insn[0] << 23) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3761pq_slot1_Slot_pq_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc) | (tie_t << 2); + tie_t = (val << 21) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2825pq_slot1_Slot_pq_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2825pq_slot1_Slot_pq_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_sae_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_sae_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_op0_s11_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s11_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_dsp340050b49a6c_fld2867pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2867pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3763pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3763pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2869pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2869pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3764pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3764pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2838pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2838pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2882_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2882_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2884pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2884pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2874pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2874pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2856pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2856pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 21) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3765pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3765pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2858pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 13) >> 19); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2858pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2857pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2857pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2946pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2946pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2880pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2880pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2879pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2879pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2865_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2865_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2847pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2847pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 21) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2840pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2840pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2844pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2844pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2845pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2845pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2900pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2900pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2899pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2899pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2839pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2839pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2901pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2901pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2903pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2903pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2907pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2907pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2902pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2902pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2846pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2846pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2904pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2904pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2842pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2842pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2849pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2849pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2905pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2905pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2906pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2906pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2908pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2908pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2950pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2950pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3766pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 23) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3766pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2913pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2913pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2926pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2926pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3767pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3767pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2914pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2914pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2827pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2827pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2833pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2833pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2835pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2835pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2837pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2837pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2861pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2861pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3768pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3768pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2829pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2829pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2830pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2830pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2836pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2836pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2831pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2831pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2832pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2832pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2873pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2873pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2871pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2871pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2872pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2872pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2936pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2936pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2932pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2932pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2934pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2934pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2935pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2935pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2863pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 13) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2863pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2864pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2864pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2069_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2069_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2859pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2859pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 19) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2940_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2940_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2843pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2843pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2928pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2928pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2059_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2059_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2929pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2929pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2930pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2930pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3769pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3769pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2916pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2916pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_s8_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2947pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2947pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2036_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2036_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2948pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2948pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3770pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3770pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2942pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2942pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 25) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2875pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2875pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2876pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2876pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2878pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2878pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2877pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2877pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2860pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2860pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 19) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2941pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2941pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3771pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3771pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2923pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2923pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2927pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2927pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3773pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3773pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2918pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2918pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2920pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2920pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2921pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2921pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2922pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2922pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2924pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2924pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2925pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2925pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2853pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2853pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2850pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2850pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2851pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2851pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2852pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2852pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2854pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2854pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2855pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2855pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2943pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2943pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 25) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3775pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3775pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3776pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3776pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3777pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3777pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2945pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2945pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 25) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2909pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2909pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2911pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2911pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2910pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2910pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2912pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2912pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2949pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2949pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3778pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3778pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2888pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2888pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2890pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2890pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2937pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2937pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2939pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2939pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3772_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3772_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2881pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2881pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2883pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2883pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2917pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2917pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2919pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2919pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2885pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2885pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2887pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2887pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2891pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2891pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2893pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2893pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2897pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2897pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 21) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3779pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3779pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2892pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2892pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2915pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2915pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3780pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3780pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2886pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2886pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2894pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2894pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2895pq_slot0_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2895pq_slot0_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 19) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2953acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2953acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_op0_s12_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s12_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3782acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3782acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2956acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2956acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_s_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2967acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2967acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2966acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2966acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld3783acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3783acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2957acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2957acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2958acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2958acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2960acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2960acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3784acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3784acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2964acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2964acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3785acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3785acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2959acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2959acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2963acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2963acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2954acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2954acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3786acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3786acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2955acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2955acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld3788acc2_slot2_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3788acc2_slot2_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2969acc2_slot1_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2969acc2_slot1_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_op0_s13_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s13_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_dsp340050b49a6c_fld3790acc2_slot1_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 8) >> 18); + tie_t = (tie_t << 7) | ((insn[0] << 23) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3790acc2_slot1_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc) | (tie_t << 2); + tie_t = (val << 11) >> 18; + insn[0] = (insn[0] & ~0xfffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2968acc2_slot1_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2968acc2_slot1_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3793acc2_slot1_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 11) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3793acc2_slot1_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); + tie_t = (val << 22) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 18) >> 28; + insn[0] = (insn[0] & ~0x1e0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld2075_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2075_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2031_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 11) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2031_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e0000) | (tie_t << 17); +} + +static unsigned +Field_op0_s14_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s14_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2973acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2973acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3795acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3795acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2980acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2980acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld3796acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3796acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2976acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 18) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2976acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc0) | (tie_t << 6); +} + +static unsigned +Field_t_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2989acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2989acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3798acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3798acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2990acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2990acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld3799acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3799acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2977acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2977acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld3797_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3797_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2981acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2981acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3800acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3800acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2975acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2975acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2982acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2982acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3801acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3801acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2984acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2984acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2985acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2985acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3802acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3802acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2987acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2987acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3803acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3803acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2039_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2039_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2974acc2_slot0_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 18) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2974acc2_slot0_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f00) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3043smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 15) | ((insn[0] << 15) >> 17); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3043smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc) | (tie_t << 2); + tie_t = (val << 16) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_op0_s15_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s15_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_dsp340050b49a6c_fld3805smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3805smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3061smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3061smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 23) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3806smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3806smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3063smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3063smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3807smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3807smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3049smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3049smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3050smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3050smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3052smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3052smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3056smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3056smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); + tie_t = (val << 19) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_dsp340050b49a6c_fld3809smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3809smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3038smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 16) >> 18); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3038smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3091smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3091smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2041_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2041_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3102smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3102smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3810smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3810smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3116smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3116smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3812smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3812smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3813smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3813smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3092smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 12) >> 18); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3092smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3047smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3047smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3090smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3090smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3814smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3814smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3030smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3030smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3006smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3006smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3104smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3104smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_dsp340050b49a6c_fld3816smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3816smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3033smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3033smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3111smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3111smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3016smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3016smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3017smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3017smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3019smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3019smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3018smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3018smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3020smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3020smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3021smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3021smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3022smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3022smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3105smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3105smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3008smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3008smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3009smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3009smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3011smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3011smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3015smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3015smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3010smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3010smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3012smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3012smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3013smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3013smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3014smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3014smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3070_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3070_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3032smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3032smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3084smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3084smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_dsp340050b49a6c_fld3817_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3817_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3098smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3098smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3062_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3062_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2998smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2998smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3048_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3048_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3000smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3000smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3031smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3031smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3001smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3001smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3818smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 18) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3818smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld3039smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 12) >> 14); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3039smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3044smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 9) | ((insn[0] << 21) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3044smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc) | (tie_t << 2); + tie_t = (val << 19) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3819smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3819smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3040smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 15) | ((insn[0] << 15) >> 17); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3040smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x1fffc) | (tie_t << 2); + tie_t = (val << 16) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_dsp340050b49a6c_fld3046smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3046smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3051smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3051smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3053smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3053smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3054smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3054smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3055smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3055smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3058smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3058smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); + tie_t = (val << 19) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_dsp340050b49a6c_fld3059smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3059smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 21) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); + tie_t = (val << 20) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); +} + +static unsigned +Field_dsp340050b49a6c_fld3821smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3821smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3065smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3065smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3066smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3066smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3067smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3067smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3080smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3080smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3069smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3069smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 19) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3071smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3071smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 19) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3072smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3072smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 19) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3074smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3074smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 19) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3073smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3073smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 19) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3075smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3075smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 19) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3093smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3093smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 19) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3822smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3822smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld3097smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 12) >> 21); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3097smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0xffe00) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld3823smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3823smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3076smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3076smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 18) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3077smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3077smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 18) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3078smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3078smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 18) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3079smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 12) >> 22); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3079smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 18) >> 22; + insn[0] = (insn[0] & ~0xffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3036smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 9) | ((insn[0] << 21) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3036smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc) | (tie_t << 2); + tie_t = (val << 21) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3068smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3068smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3081smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3081smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3082smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3082smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3824smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3824smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3100smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3100smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3825smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3825smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3106smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3106smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3099smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 12) >> 23); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3099smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 22) >> 23; + insn[0] = (insn[0] & ~0xff800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3096smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 12) >> 20); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3096smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 19) >> 20; + insn[0] = (insn[0] & ~0xfff00) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3028smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3028smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3087smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3087smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_t_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2991smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2991smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3101smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3101smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3826smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3826smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2992smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2992smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2993smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2993smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2995smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2995smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3113smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3113smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x780) | (tie_t << 7); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3827smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3827smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2999smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2999smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3007smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3007smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3023smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3023smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3115smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3115smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2029_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2029_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2994smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2994smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2996smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2996smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3024smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3024smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3025smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3025smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3027smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3027smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3085smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3085smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2032_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2032_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2997smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2997smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3088smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3088smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3828smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3828smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld3026smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3026smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3003smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3003smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3002smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3002smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3004smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3004smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3005smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3005smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3034smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3034smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3107smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3107smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3109smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3109smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3114smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3114smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3808_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3808_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3108smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3108smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3035smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3035smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3110smod_slot2_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3110smod_slot2_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3118smod_slot1_Slot_smod_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3118smod_slot1_Slot_smod_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_op0_s16_Slot_smod_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s16_Slot_smod_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_dsp340050b49a6c_fld3829smod_slot1_Slot_smod_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 16) >> 26); + tie_t = (tie_t << 7) | ((insn[0] << 23) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3829smod_slot1_Slot_smod_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc) | (tie_t << 2); + tie_t = (val << 19) >> 26; + insn[0] = (insn[0] & ~0xfc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3117smod_slot1_Slot_smod_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3117smod_slot1_Slot_smod_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2080_Slot_smod_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2080_Slot_smod_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_sae_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_sae_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_op0_s17_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s17_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_dsp340050b49a6c_fld3120smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 13) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3120smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x7f000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3122smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3122smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3121smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3121smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3131smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3131smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3126smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3126smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3148smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 13) >> 25); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3148smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 21) >> 25; + insn[0] = (insn[0] & ~0x7f000) | (tie_t << 12); +} + +static unsigned +Field_imm6_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 20) >> 26); + return tie_t; +} + +static void +Field_imm6_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3164smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 13) >> 21); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3164smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 20) >> 21; + insn[0] = (insn[0] & ~0x7ff00) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3832smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3832smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld3160smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 13) >> 19); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3160smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3161smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 13) >> 21); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3161smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 20) >> 21; + insn[0] = (insn[0] & ~0x7ff00) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3159smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3159smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld3165smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3165smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3135smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3135smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3133smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3133smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3119smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3119smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3155smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3155smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3833smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3833smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3149smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3149smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3834_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3834_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3137smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3137smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3138smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3138smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3184smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3184smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3836smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3836smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3182smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3182smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_sas_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3153smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3153smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3186smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3186smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3837smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 23) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3837smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3168smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3168smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3171smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3171smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3175smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3175smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3140smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3140smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3170smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3170smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3152smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3152smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3144smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3144smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3172smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3172smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3173smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3173smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3174smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3174smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3188smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3188smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3838smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3838smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3180smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3180smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3166smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3166smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); + tie_t = (val << 20) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3181smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3181smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); + tie_t = (val << 20) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_s8_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3136smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3136smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3123smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3123smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3134smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3134smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3125smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3125smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3127smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3127smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3128smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3128smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3130smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3130smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3129smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3129smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3132smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3132smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3139smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3139smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3141smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3141smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3142smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3142smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3143smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3143smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3145smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3145smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3146smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 13) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3146smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x7f800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3150_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3150_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3156smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3156smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3157smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3157smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3158smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3158smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3176smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3176smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3177smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3177smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3179smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3179smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3178smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3178smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 19) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3841smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3841smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3842smod_slot0_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3842smod_slot0_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3208llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3208llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); + tie_t = (val << 18) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_op0_s18_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s18_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3843llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3843llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3193llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3193llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3194llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3194llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3196llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3196llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3200llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3200llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3213llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3213llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3845llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3845llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3195llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3195llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3206_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 20) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3206_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3225_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3225_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3205_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3205_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3847llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3847llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3212_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3212_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld3848llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3848llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3216llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3216llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld3849llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3849llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3215llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3215llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3850llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3850llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3234llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3234llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3232llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3232llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3237llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 14) >> 25); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3237llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 21) >> 25; + insn[0] = (insn[0] & ~0x3f800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2074_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2074_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3192llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3192llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3230_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3230_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld3191llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3191llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3243llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3243llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_t_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3218llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3218llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld3851llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3851llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3244llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3244llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3853llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3853llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3242llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3242llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3855llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3855llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); + tie_t = (val << 26) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3231llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3231llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3856llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3856llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld3203llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 14) >> 16); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3203llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x3fffc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3204llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + tie_t = (tie_t << 10) | ((insn[0] << 20) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3204llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc) | (tie_t << 2); + tie_t = (val << 17) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3844_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3844_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3207llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + tie_t = (tie_t << 10) | ((insn[0] << 20) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3207llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc) | (tie_t << 2); + tie_t = (val << 17) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3197llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3197llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3198llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3198llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3199llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3199llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3201llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3201llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3202llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3202llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3210llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3210llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); + tie_t = (val << 22) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3857llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3857llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3217_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3217_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld3859llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3859llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 23) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3221llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3221llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3222llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3222llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3860llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3860llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3224llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3224llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3861llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3861llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3220llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3220llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3246_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3246_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3214_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3214_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3863llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 15) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3863llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x1f800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3226llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3226llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3864llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3864llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3235llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 14) >> 25); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3235llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 21) >> 25; + insn[0] = (insn[0] & ~0x3f800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3238llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3238llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3862_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3862_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3241llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3241llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3865llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3865llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3236_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 14) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3236_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3240llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3240llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3228llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3228llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x100) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3866llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3866llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); +} + +static unsigned +Field_dsp340050b49a6c_fld3247llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3247llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3867llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3867llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_s_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3233_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3233_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld2029_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2029_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3245llr_slot2_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3245llr_slot2_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3868_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3868_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3250llr_slot1_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3250llr_slot1_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_op0_s19_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s19_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_dsp340050b49a6c_fld3869llr_slot1_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3869llr_slot1_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 22) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); + tie_t = (val << 18) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3254llr_slot1_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3254llr_slot1_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3872llr_slot1_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3872llr_slot1_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 21) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3252llr_slot1_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3252llr_slot1_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3875llr_slot1_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3875llr_slot1_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3253llr_slot1_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3253llr_slot1_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3876llr_slot1_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3876llr_slot1_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3251llr_slot1_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3251llr_slot1_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3878llr_slot1_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3878llr_slot1_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3248llr_slot1_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3248llr_slot1_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3870_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3870_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2071_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2071_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_op0_s20_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s20_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3260llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3260llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3258llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3258llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3266llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3266llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3286llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3286llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3879llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3879llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3303llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3303llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3269llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3269llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3293llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3293llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3297llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3297llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3881llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3881llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3272llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3272llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3274llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3274llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3302llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3302llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3883llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3883llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3275llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3275llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3289llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3289llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3292llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3292llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3277llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3277llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3276llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3276llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3270llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3270llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3312llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3312llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3885llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3885llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3304llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3304llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3887llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3887llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3283llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3283llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3310llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3310llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3888llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3888llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3288llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3288llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld3284llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3284llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2041_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2041_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld3305llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3305llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); + tie_t = (val << 24) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3306llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3306llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3890llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3890llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3259llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3259llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3291llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3291llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3261llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3261llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3263llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3263llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3267llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3267llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3264llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3264llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3265llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3265llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3268llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3268llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3308llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3308llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3892llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3892llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3294llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3294llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3295llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3295llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3296llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3296llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3298llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3298llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3299llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3299llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3300llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3300llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3893llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3893llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3278llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3278llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3279llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3279llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3280llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3280llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3282llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3282llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3281llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3281llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); + tie_t = (val << 26) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3311llr_slot0_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3311llr_slot0_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_r_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3364_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3364_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_op0_s21_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s21_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); +} + +static unsigned +Field_dsp340050b49a6c_fld3464dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3464dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3894dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3894dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3465dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3465dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3895dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3895dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 25) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3459dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3459dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld3896dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 11) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3896dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3468dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3468dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3897dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3897dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_dsp340050b49a6c_fld3467dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3467dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3899dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3899dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_dsp340050b49a6c_fld3414dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3414dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3313dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3313dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3316dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3316dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3334dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3334dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_t_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3314_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3314_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3418dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3418dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3425dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3425dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3408dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3408dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3901dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3901dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_dsp340050b49a6c_fld3315dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3315dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3421dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3421dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3443dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3443dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3420dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3420dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3423dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3423dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3422dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3422dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3424dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3424dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3416dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3416dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3461dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3461dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3415dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3415dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3426dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3426dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3417dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3417dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3419dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3419dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3318_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3318_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3904dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3904dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3482dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3482dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld3903dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3903dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_dsp340050b49a6c_fld2044_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2044_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); +} + +static unsigned +Field_dsp340050b49a6c_fld3407_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3407_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_dsp340050b49a6c_fld3905dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3905dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3479dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3479dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 23) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3906dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3906dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3475dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3475dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 20) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3898dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3898dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3353dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + tie_t = (tie_t << 13) | ((insn[0] << 17) >> 19); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3353dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc) | (tie_t << 2); + tie_t = (val << 12) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3907dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3907dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3388dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 13) | ((insn[0] << 8) >> 19); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3388dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 15) >> 19; + insn[0] = (insn[0] & ~0xfff800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3913dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3913dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3387dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3387dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3396dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3396dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 21) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3909dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 15) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3909dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3404dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3404dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3910dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3910dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); + tie_t = (val << 21) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3385dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3385dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 18) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3478dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3478dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 21) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3908dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3908dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3477dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3477dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 20) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3469dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 8) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3469dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0xff8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3484dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3484dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld3916dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3916dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); +} + +static unsigned +Field_dsp340050b49a6c_fld3451dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3451dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 21) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3914dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3914dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3450dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3450dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 19) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3453dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 8) >> 18); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3453dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0xfffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3365dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3365dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3366dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3366dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3368dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3368dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3372dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3372dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3367dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3367dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3369dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3369dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3345dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 12) | ((insn[0] << 18) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3345dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc) | (tie_t << 2); + tie_t = (val << 14) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3457dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3457dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 21) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3917dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3917dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3358dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3358dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 19) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3918dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3918dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 27) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3347dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 12) | ((insn[0] << 18) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3347dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc) | (tie_t << 2); + tie_t = (val << 14) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3348dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 12) | ((insn[0] << 18) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3348dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc) | (tie_t << 2); + tie_t = (val << 14) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3354dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 10) | ((insn[0] << 18) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3354dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff0) | (tie_t << 4); + tie_t = (val << 16) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_s4_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3397dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3397dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3919dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3919dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3462dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3462dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3394dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3394dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3920dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 16) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3920dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3363dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3363dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3481dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3481dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3339dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3339dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3384dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3384dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 18) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3360dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3360dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3437dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3437dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3439dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3439dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3438dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3438dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3440dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3440dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3441dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3441dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3442dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3442dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3444dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3444dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3460dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3460dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3921dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3921dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3429dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3429dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3431dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3431dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3435dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3435dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3430dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3430dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3432dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3432dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3433dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3433dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3434dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3434dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3436dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3436dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3361dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3361dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3403dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3403dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3922dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3922dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3386dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3386dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 18) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld3923dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3923dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); + tie_t = (val << 18) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3324dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3324dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3325dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3325dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3340dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3340dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3327dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3327dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3342dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3342dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); + tie_t = (val << 24) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3356dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3356dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); + tie_t = (val << 23) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); + tie_t = (val << 17) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3924dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3924dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3349dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 22) | ((insn[0] << 8) >> 10); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3349dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 10) >> 10; + insn[0] = (insn[0] & ~0xfffffc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3350dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 8) >> 25); + tie_t = (tie_t << 13) | ((insn[0] << 17) >> 19); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3350dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 19) >> 19; + insn[0] = (insn[0] & ~0x7ffc) | (tie_t << 2); + tie_t = (val << 12) >> 25; + insn[0] = (insn[0] & ~0xfe0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3341dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3341dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3370dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3370dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3371dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3371dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3373dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3373dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3374dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3374dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3376dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3376dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3375dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3375dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3377dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3377dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3378dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3378dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3379dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 8) >> 22); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3379dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 14) >> 22; + insn[0] = (insn[0] & ~0xffc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3381dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3381dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3448dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3448dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 19) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3925dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3925dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3454dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3454dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3466_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3466_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3412dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3412dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3927dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3927dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3382dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 7) | ((insn[0] << 22) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3382dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8) | (tie_t << 3); + tie_t = (val << 19) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3928dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3928dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3410_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3410_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3929dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3929dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); + tie_t = (val << 17) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3390dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3390dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3413dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3413dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3930dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 13) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3930dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x7fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3456dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3456dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3392dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 8) >> 21); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3392dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 17) >> 21; + insn[0] = (insn[0] & ~0xffe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3900_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3900_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3337dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3337dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3446dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3446dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 20) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3317dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3317dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3458dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3458dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3319dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3319dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3320dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3320dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3322dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3322dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3399dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3399dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld3931dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 11) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3931dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x1c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3326dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3326dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3427dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3427dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3470dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3470dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3411dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3411dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3933dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3933dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); + tie_t = (val << 23) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_dsp340050b49a6c_fld3321dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3321dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3428dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3428dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_s_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_r_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3471dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3471dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3472dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3472dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3474dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3474dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3323dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3323dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3480dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3480dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3473dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3473dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3328dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3328dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3330dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3330dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3329dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3329dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3331dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3331dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3362dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3362dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3332dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3332dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3445dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3445dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3333dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3333dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3335dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3335dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3401dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 8) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3401dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 27) >> 30; + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); + tie_t = (val << 25) >> 30; + insn[0] = (insn[0] & ~0xc00000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3934dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3934dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3406dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3406dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); +} + +static unsigned +Field_dsp340050b49a6c_fld3935dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3935dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3380dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3380dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 18) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3336dual_slot2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 8) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3336dual_slot2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0xfc0000) | (tie_t << 18); +} + +static unsigned +Field_op0_s22_Slot_dual_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); + return tie_t; +} + +static void +Field_op0_s22_Slot_dual_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1) | (tie_t << 0); +} + +static unsigned +Field_imm8_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_op0_s23_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30); + return tie_t; +} + +static void +Field_op0_s23_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3) | (tie_t << 0); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); +} + +static unsigned +Field_dsp340050b49a6c_fld3532dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3532dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 24) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3602_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3602_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3533dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 10) >> 27); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3533dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 25) >> 27; + insn[0] = (insn[0] & ~0x3e0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3936dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3936dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2057_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2057_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3625dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3625dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 25) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_r_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_t_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3487dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3487dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld3584_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3584_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3937dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3937dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3489dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3489dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3488dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3488dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_dsp340050b49a6c_fld3620dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3620dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2048_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2048_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3588dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 10) >> 27); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3588dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x3e0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3938dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3938dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3544dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3544dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3519dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3519dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 18) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3939dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3939dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3523dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 11) | ((insn[0] << 10) >> 21); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3523dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 21) >> 21; + insn[0] = (insn[0] & ~0x3ff800) | (tie_t << 11); +} + +static unsigned +Field_bbi_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3520dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3520dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 19) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld3507dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 10) >> 16); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3507dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0x3fffc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld3506dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 10) >> 17); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3506dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0x3fff80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld3614dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3614dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2079_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2079_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3550dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3550dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3549dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3549dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3531_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 10) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3531_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x3f8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3500dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3500dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 18) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3502dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3502dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 17) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3606dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3606dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3607dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3607dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3608dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3608dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_sae_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_sae_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3619_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3619_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld3940dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 11) >> 25); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3940dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3613dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 10) >> 27); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3613dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 23) >> 27; + insn[0] = (insn[0] & ~0x3e0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3509dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3509dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3510dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3510dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3562dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3562dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3560dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3560dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3499dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3499dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 19) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3563dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3563dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3565dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3565dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3564dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3564dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3566dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3566dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3512dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3512dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3567dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3567dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3504dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3504dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 17) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3516dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3516dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3568dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3568dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3570dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3570dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3580dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3580dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3559dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3559dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3573dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3573dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3599dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3599dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3941dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3941dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3575dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3575dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3535dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3535dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2066_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2066_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3494dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3494dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3497dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3497dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3496dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3496dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3498dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3498dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); + tie_t = (val << 23) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3490dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3490dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3491dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3491dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3493dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3493dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3527dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3527dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 26) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3492dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3492dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3589dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3589dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_s8_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3541dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3541dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2037_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2037_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld3542dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3542dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3543dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3543dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3552_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3552_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 23) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3626dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3626dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 25) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3621dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 10) >> 25); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3621dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 24) >> 25; + insn[0] = (insn[0] & ~0x3f8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3623dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 10) >> 25); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3623dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 24) >> 25; + insn[0] = (insn[0] & ~0x3f8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3622dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 10) >> 25); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3622dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 24) >> 25; + insn[0] = (insn[0] & ~0x3f8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3624dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 10) >> 25); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3624dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 24) >> 25; + insn[0] = (insn[0] & ~0x3f8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3529dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 10) | ((insn[0] << 10) >> 22); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3529dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 22) >> 22; + insn[0] = (insn[0] & ~0x3ff000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld3530dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 10) >> 25); + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3530dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); + tie_t = (val << 23) >> 25; + insn[0] = (insn[0] & ~0x3f8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2072_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2072_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3524dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3524dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3943dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 6) | ((insn[0] << 21) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3943dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e0) | (tie_t << 5); + tie_t = (val << 25) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3508dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3508dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3601dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3601dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3945dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3945dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3603dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3603dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3604dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3604dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3946dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3946dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3545dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3545dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3616dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3616dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld3947dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3947dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 25) >> 26; + insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3618dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3618dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld3949dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 11) >> 25); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3949dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 24) >> 25; + insn[0] = (insn[0] & ~0x1fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3609dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3609dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3546dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3546dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3548dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3548dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3554dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3554dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3547dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3547dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3522dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3522dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 19) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3950dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3950dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld3611dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3611dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3592dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3592dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3594dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3594dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3598dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3598dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3951dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3951dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3600dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 10) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3600dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 24) >> 27; + insn[0] = (insn[0] & ~0x3e0000) | (tie_t << 17); +} + +static unsigned +Field_dsp340050b49a6c_fld3952dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3952dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3593dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3593dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3595dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3595dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3596dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3596dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3597dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3597dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3511dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3511dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3513dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3513dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3514dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3514dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3515dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3515dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3517dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3517dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3518dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3518dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 17) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld3536dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3536dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld2060_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2060_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3539dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3539dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3954dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27); + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3954dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); + tie_t = (val << 26) >> 27; + insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3537dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3537dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3538dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 10) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3538dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c0000) | (tie_t << 18); +} + +static unsigned +Field_dsp340050b49a6c_fld3957dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3957dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld3587dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3587dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 21) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3610_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 22) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3610_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x3e0) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld3571dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3571dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3572dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3572dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3574dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3574dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3569dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3569dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3505dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 14) | ((insn[0] << 10) >> 18); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3505dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 18) >> 18; + insn[0] = (insn[0] & ~0x3fff00) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld3612dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 10) >> 26); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3612dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 22) >> 26; + insn[0] = (insn[0] & ~0x3f0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld3576dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3576dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 15) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3577dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3577dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 15) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3615dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3615dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); +} + +static unsigned +Field_dsp340050b49a6c_fld3958dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 13) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3958dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x7e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3551dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3551dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3553dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3553dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3590dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3590dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3591dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3591dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); + tie_t = (val << 20) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3555dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3555dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3557dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3557dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3578dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3578dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 15) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3579dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3579dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 15) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3581dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 8) | ((insn[0] << 22) >> 24); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3581dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc) | (tie_t << 2); + tie_t = (val << 16) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3582dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3582dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 25) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 17) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3959dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3959dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3556dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3556dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3558dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 9) | ((insn[0] << 10) >> 23); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3558dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 19) >> 23; + insn[0] = (insn[0] & ~0x3fe000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3583dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3583dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); + tie_t = (val << 18) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3960dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3960dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); + tie_t = (val << 29) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld3585dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3585dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x200) | (tie_t << 9); + tie_t = (val << 19) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld3961dual_slot0_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 18) >> 31); + tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld3961dual_slot0_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0x180) | (tie_t << 7); + tie_t = (val << 28) >> 31; + insn[0] = (insn[0] & ~0x2000) | (tie_t << 13); +} + +static unsigned +Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_t_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_t_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_t_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_t_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_t_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_t_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_t_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_bbi_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 21) >> 27); + return tie_t; +} + +static void +Field_bbi_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c0) | (tie_t << 6); +} + +static unsigned +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); +} + +static unsigned +Field_imm12_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 14) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0) | (tie_t << 6); +} + +static unsigned +Field_imm12_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 14) >> 20); + return tie_t; +} + +static void +Field_imm12_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 20) >> 20; + insn[0] = (insn[0] & ~0x3ffc0) | (tie_t << 6); +} + +static unsigned +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_imm8_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 10) >> 24); + return tie_t; +} + +static void +Field_imm8_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc000) | (tie_t << 14); +} + +static unsigned +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_s_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_s_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_s_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_s_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_s_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_s_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_s_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_s_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_s_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_s_Slot_smod_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_smod_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_s_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_s_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_s_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_s_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); + tie_t = (val << 20) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm12b_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_imm12b_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_imm12b_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 20) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); + return tie_t; +} + +static void +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 16) >> 16; + insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); +} + +static unsigned +Field_imm16_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 12) | ((insn[0] << 10) >> 20); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_imm16_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 16) >> 20; + insn[0] = (insn[0] & ~0x3ffc00) | (tie_t << 10); +} + +static unsigned +Field_offset_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_op2_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_op2_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_op2_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_op2_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_op2_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_op2_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_op2_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_op2_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_r_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_r_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_r_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_r_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_r_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_r_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_r_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_r_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_r_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_r_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_r_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_r_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_r_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_r_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_sae_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); +} + +static unsigned +Field_sae_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_sae_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_sal_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sal_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sal_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sal_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sal_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sal_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sal_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sal_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_sal_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_sargt_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sargt_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_sargt_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_sas_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); +} + +static unsigned +Field_sas_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); +} + +static unsigned +Field_sas_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); +} + +static unsigned +Field_sas_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_sas_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); +} + +static unsigned +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + return tie_t; +} + +static void +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 24) >> 28; + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); +} + +static unsigned +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_mn_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); + tie_t = (val << 28) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + return tie_t; +} + +static void +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); + return tie_t; +} + +static void +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x40) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 26) >> 30; + insn[0] = (insn[0] & ~0x30) | (tie_t << 4); +} + +static unsigned +Field_imm6_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 20) >> 26); + return tie_t; +} + +static void +Field_imm6_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 20) >> 26); + return tie_t; +} + +static void +Field_imm6_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 20) >> 26); + return tie_t; +} + +static void +Field_imm6_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0) | (tie_t << 6); +} + +static unsigned +Field_imm6_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 20) >> 26); + return tie_t; +} + +static void +Field_imm6_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc0) | (tie_t << 6); +} + +static unsigned +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); + tie_t = (val << 25) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_imm7_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_imm7_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_imm7_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_imm7_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_imm7_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_imm7_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_imm7_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_imm7_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_imm7_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_imm7_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_imm7_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_imm7_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_imm7_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_imm7_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_imm7_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_imm7_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_imm7_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 7) | ((insn[0] << 19) >> 25); + return tie_t; +} + +static void +Field_imm7_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 25) >> 25; + insn[0] = (insn[0] & ~0x1fc0) | (tie_t << 6); +} + +static unsigned +Field_t2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); + return tie_t; +} + +static void +Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); +} + +static unsigned +Field_s2_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); + return tie_t; +} + +static void +Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); +} + +static unsigned +Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static unsigned +Field_t4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_s4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_s4_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_s4_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_s4_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_s4_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_s4_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_r4_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + return tie_t; +} + +static void +Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_t8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_s8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_s8_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_s8_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_r8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); +} + +static unsigned +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); + return tie_t; +} + +static void +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 17) >> 17; + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); +} + +static unsigned +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); + return tie_t; +} + +static void +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 14) >> 14; + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); +} + +static unsigned +Field_fimm8_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); + return tie_t; +} + +static void +Field_fimm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); +} + +static unsigned +Field_fimm8_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 8) | ((insn[0] << 14) >> 24); + return tie_t; +} + +static void +Field_fimm8_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 24) >> 24; + insn[0] = (insn[0] & ~0x3fc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2029_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2029_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld2029_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2029_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2029_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2029_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2029_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2029_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2029_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2029_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2029_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2029_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2029_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2029_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2029_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2029_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2029_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2029_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2029_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2029_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2030_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2030_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld2030_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2030_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2030_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2030_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2030_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2030_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2030_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2030_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2030_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2030_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2030_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2030_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2030_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2030_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2030_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2030_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2030_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2030_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2032_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2032_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x300) | (tie_t << 8); +} + +static unsigned +Field_dsp340050b49a6c_fld2032_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2032_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2032_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2032_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2032_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2032_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2032_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2032_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2032_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2032_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2032_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2032_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2032_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2032_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2032_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2032_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2032_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2032_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2035_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2035_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2035_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2035_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2035_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2035_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2035_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 27) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2035_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x18) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2036_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2036_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2036_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2036_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2036_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2036_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2037_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2037_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2037_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2037_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2037_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2037_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2037_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2037_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2038_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2038_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld2038_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2038_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2038_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2038_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2038_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2038_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2038_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2038_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2038_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2038_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2038_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2038_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); +} + +static unsigned +Field_dsp340050b49a6c_fld2039_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2039_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld2039_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2039_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2039_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2039_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2039_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2039_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2039_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2039_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2040_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2040_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2040_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2040_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2040_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2040_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2040_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2040_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2040_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2040_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2041_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2041_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x10) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld2041_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2041_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2041_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2041_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2041_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2041_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2041_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2041_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x80) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2042_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2042_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); + tie_t = (val << 30) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2042_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2042_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2042_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2042_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2042_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 17) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2042_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x6000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2043_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2043_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2043_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2043_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2043_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2043_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2043_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2043_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2043_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2043_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2043_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2043_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2043_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2043_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2044_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2044_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld2044_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2044_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2044_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 25) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2044_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2044_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2044_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2044_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2044_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x400) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2045_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2045_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_smod_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_smod_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2046_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2046_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2047_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2047_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2048_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2048_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2048_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2048_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2048_Slot_dot_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2048_Slot_dot_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2048_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2048_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2048_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2048_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2048_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2048_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); +} + +static unsigned +Field_dsp340050b49a6c_fld2048_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2048_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2048_Slot_smod_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2048_Slot_smod_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2048_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2048_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 19) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0x1800) | (tie_t << 11); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_pq_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_pq_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2049_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2049_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 30) >> 30; + insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_dot_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 15) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_dot_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x1e000) | (tie_t << 13); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_pq_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_pq_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2050_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 25) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2050_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x78) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2051_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 22) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2051_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0x3f0) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld2051_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2051_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2051_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2051_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2051_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2051_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2051_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2051_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2051_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2051_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2051_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2051_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2051_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2051_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2051_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2051_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2051_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 6) | ((insn[0] << 24) >> 26); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2051_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 26) >> 26; + insn[0] = (insn[0] & ~0xfc) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + tie_t = (tie_t << 1) | ((insn[0] << 29) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x4) | (tie_t << 2); + tie_t = (val << 28) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2052_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2052_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2053_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2053_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x800) | (tie_t << 11); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); +} + +static unsigned +Field_dsp340050b49a6c_fld2053_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2053_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2053_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2053_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2053_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2053_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2053_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2053_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2053_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2053_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); + tie_t = (val << 27) >> 31; + insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2053_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2053_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 27) >> 27; + insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2053_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 14) >> 28); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2053_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 27) >> 28; + insn[0] = (insn[0] & ~0x3c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2054_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2054_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld2054_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2054_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2054_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2054_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2054_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2054_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2054_Slot_smod_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); + tie_t = (tie_t << 1) | ((insn[0] << 26) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2054_Slot_smod_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x20) | (tie_t << 5); + tie_t = (val << 29) >> 30; + insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2054_Slot_llr_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2054_Slot_llr_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2054_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2054_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2055_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2055_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld2055_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2055_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2055_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2055_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2055_Slot_acc2_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2055_Slot_acc2_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2055_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2055_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2055_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2055_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); +} + +static unsigned +Field_dsp340050b49a6c_fld2055_Slot_dual_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2055_Slot_dual_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_inst_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_inst_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x70) | (tie_t << 4); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_gp_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_gp_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 26) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x38) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_dot_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_dot_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_pq_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_pq_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_smod_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_smod_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_smod_slot0_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_smod_slot0_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x380) | (tie_t << 7); +} + +static unsigned +Field_dsp340050b49a6c_fld2056_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2056_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2025_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2025_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2025_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2025_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2025_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2025_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2025_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2025_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2025_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2025_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 31) >> 31; + insn[0] = (insn[0] & ~0x8) | (tie_t << 3); +} + +static unsigned +Field_dsp340050b49a6c_fld2027_Slot_gp_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2027_Slot_gp_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2027_Slot_dot_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2027_Slot_dot_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2027_Slot_pq_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2027_Slot_pq_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2027_Slot_acc2_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2027_Slot_acc2_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2027_Slot_smod_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2027_Slot_smod_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2027_Slot_llr_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2027_Slot_llr_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2027_Slot_dual_slot2_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2027_Slot_dual_slot2_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2026_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2026_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2026_Slot_dot_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2026_Slot_dot_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2026_Slot_pq_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2026_Slot_pq_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2026_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2026_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2026_Slot_smod_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2026_Slot_smod_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2026_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2026_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2031_Slot_gp_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2031_Slot_gp_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2031_Slot_dot_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2031_Slot_dot_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2031_Slot_pq_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2031_Slot_pq_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2031_Slot_smod_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 26) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2031_Slot_smod_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2031_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 4) | ((insn[0] << 22) >> 28); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2031_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 28) >> 28; + insn[0] = (insn[0] & ~0x3c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2028_Slot_acc2_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 15) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2028_Slot_acc2_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c000) | (tie_t << 14); +} + +static unsigned +Field_dsp340050b49a6c_fld2028_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 27) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2028_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c) | (tie_t << 2); +} + +static unsigned +Field_dsp340050b49a6c_fld2033_Slot_smod_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 23) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2033_Slot_smod_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c0) | (tie_t << 6); +} + +static unsigned +Field_dsp340050b49a6c_fld2033_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 19) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2033_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0x1c00) | (tie_t << 10); +} + +static unsigned +Field_dsp340050b49a6c_fld2034_Slot_llr_slot1_get (const xtensa_insnbuf insn) +{ + unsigned tie_t = 0; + tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); + return tie_t; +} + +static void +Field_dsp340050b49a6c_fld2034_Slot_llr_slot1_set (xtensa_insnbuf insn, uint32 val) +{ + uint32 tie_t; + tie_t = (val << 29) >> 29; + insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); +} + +static void +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, + uint32 val ATTRIBUTE_UNUSED) +{ + /* Do nothing. */ +} + +static unsigned +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 4; +} + +static unsigned +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 8; +} + +static unsigned +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 12; +} + +static unsigned +Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static unsigned +Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +enum xtensa_field_id { + FIELD_t, + FIELD_bbi4, + FIELD_bbi, + FIELD_imm12, + FIELD_imm8, + FIELD_s, + FIELD_imm12b, + FIELD_imm16, + FIELD_m, + FIELD_n, + FIELD_offset, + FIELD_op0, + FIELD_op1, + FIELD_op2, + FIELD_r, + FIELD_sa4, + FIELD_sae4, + FIELD_sae, + FIELD_sal, + FIELD_sargt, + FIELD_sas4, + FIELD_sas, + FIELD_sr, + FIELD_st, + FIELD_thi3, + FIELD_imm4, + FIELD_mn, + FIELD_i, + FIELD_imm6lo, + FIELD_imm6hi, + FIELD_imm7lo, + FIELD_imm7hi, + FIELD_z, + FIELD_imm6, + FIELD_imm7, + FIELD_t2, + FIELD_s2, + FIELD_r2, + FIELD_t4, + FIELD_s4, + FIELD_r4, + FIELD_t8, + FIELD_s8, + FIELD_r8, + FIELD_xt_wbr15_imm, + FIELD_xt_wbr18_imm, + FIELD_fimm8, + FIELD_dsp340050b49a6c_fld2019, + FIELD_dsp340050b49a6c_fld2021, + FIELD_dsp340050b49a6c_fld2029, + FIELD_dsp340050b49a6c_fld2030, + FIELD_dsp340050b49a6c_fld2032, + FIELD_dsp340050b49a6c_fld2035, + FIELD_dsp340050b49a6c_fld2036, + FIELD_dsp340050b49a6c_fld2037, + FIELD_dsp340050b49a6c_fld2038, + FIELD_dsp340050b49a6c_fld2039, + FIELD_dsp340050b49a6c_fld2040, + FIELD_dsp340050b49a6c_fld2041, + FIELD_dsp340050b49a6c_fld2042, + FIELD_dsp340050b49a6c_fld2043, + FIELD_dsp340050b49a6c_fld2044, + FIELD_dsp340050b49a6c_fld2045, + FIELD_dsp340050b49a6c_fld2046, + FIELD_dsp340050b49a6c_fld2047, + FIELD_dsp340050b49a6c_fld2048, + FIELD_dsp340050b49a6c_fld2049, + FIELD_dsp340050b49a6c_fld2050, + FIELD_dsp340050b49a6c_fld2051, + FIELD_dsp340050b49a6c_fld2052, + FIELD_dsp340050b49a6c_fld2053, + FIELD_dsp340050b49a6c_fld2054, + FIELD_dsp340050b49a6c_fld2055, + FIELD_dsp340050b49a6c_fld2056, + FIELD_dsp340050b49a6c_fld2082Inst, + FIELD_dsp340050b49a6c_fld2083Inst, + FIELD_dsp340050b49a6c_fld2084Inst, + FIELD_dsp340050b49a6c_fld2085Inst, + FIELD_dsp340050b49a6c_fld2086Inst, + FIELD_dsp340050b49a6c_fld2088Inst, + FIELD_dsp340050b49a6c_fld2089Inst, + FIELD_dsp340050b49a6c_fld2090Inst, + FIELD_dsp340050b49a6c_fld2091Inst, + FIELD_dsp340050b49a6c_fld2092Inst, + FIELD_dsp340050b49a6c_fld2094Inst, + FIELD_dsp340050b49a6c_fld2095Inst, + FIELD_dsp340050b49a6c_fld2096Inst, + FIELD_dsp340050b49a6c_fld2098Inst, + FIELD_dsp340050b49a6c_fld2099Inst, + FIELD_dsp340050b49a6c_fld2100Inst, + FIELD_dsp340050b49a6c_fld2101Inst, + FIELD_dsp340050b49a6c_fld2102Inst, + FIELD_dsp340050b49a6c_fld2103Inst, + FIELD_dsp340050b49a6c_fld2104Inst, + FIELD_dsp340050b49a6c_fld2105Inst, + FIELD_dsp340050b49a6c_fld2106Inst, + FIELD_dsp340050b49a6c_fld2107Inst, + FIELD_dsp340050b49a6c_fld2108Inst, + FIELD_dsp340050b49a6c_fld2109Inst, + FIELD_dsp340050b49a6c_fld2110Inst, + FIELD_dsp340050b49a6c_fld2111Inst, + FIELD_dsp340050b49a6c_fld2112Inst, + FIELD_dsp340050b49a6c_fld2113Inst, + FIELD_dsp340050b49a6c_fld2114Inst, + FIELD_dsp340050b49a6c_fld2115Inst, + FIELD_dsp340050b49a6c_fld2116Inst, + FIELD_dsp340050b49a6c_fld2117Inst, + FIELD_dsp340050b49a6c_fld2118Inst, + FIELD_dsp340050b49a6c_fld2119Inst, + FIELD_dsp340050b49a6c_fld2120Inst, + FIELD_dsp340050b49a6c_fld2122Inst, + FIELD_dsp340050b49a6c_fld2123Inst, + FIELD_dsp340050b49a6c_fld2124Inst, + FIELD_dsp340050b49a6c_fld2125Inst, + FIELD_dsp340050b49a6c_fld2126Inst, + FIELD_dsp340050b49a6c_fld2127Inst, + FIELD_dsp340050b49a6c_fld2128Inst, + FIELD_dsp340050b49a6c_fld2129Inst, + FIELD_dsp340050b49a6c_fld2131Inst, + FIELD_dsp340050b49a6c_fld2132Inst, + FIELD_dsp340050b49a6c_fld2133Inst, + FIELD_dsp340050b49a6c_fld2134Inst, + FIELD_dsp340050b49a6c_fld2136Inst, + FIELD_dsp340050b49a6c_fld2137Inst, + FIELD_dsp340050b49a6c_fld2138Inst, + FIELD_dsp340050b49a6c_fld2139Inst, + FIELD_dsp340050b49a6c_fld2140Inst, + FIELD_dsp340050b49a6c_fld2141Inst, + FIELD_dsp340050b49a6c_fld2142Inst, + FIELD_dsp340050b49a6c_fld2143Inst, + FIELD_dsp340050b49a6c_fld2144Inst, + FIELD_dsp340050b49a6c_fld2145Inst, + FIELD_dsp340050b49a6c_fld2146Inst, + FIELD_dsp340050b49a6c_fld2147Inst, + FIELD_dsp340050b49a6c_fld2149Inst, + FIELD_dsp340050b49a6c_fld2151Inst, + FIELD_dsp340050b49a6c_fld2153Inst, + FIELD_dsp340050b49a6c_fld2154Inst, + FIELD_dsp340050b49a6c_fld2155Inst, + FIELD_dsp340050b49a6c_fld2156Inst, + FIELD_dsp340050b49a6c_fld2157Inst, + FIELD_dsp340050b49a6c_fld2158Inst, + FIELD_dsp340050b49a6c_fld2159Inst, + FIELD_dsp340050b49a6c_fld2160Inst, + FIELD_dsp340050b49a6c_fld2161Inst, + FIELD_dsp340050b49a6c_fld2162Inst, + FIELD_dsp340050b49a6c_fld2163Inst, + FIELD_dsp340050b49a6c_fld2164Inst, + FIELD_dsp340050b49a6c_fld2165Inst, + FIELD_dsp340050b49a6c_fld2166Inst, + FIELD_dsp340050b49a6c_fld2167Inst, + FIELD_dsp340050b49a6c_fld2168Inst, + FIELD_dsp340050b49a6c_fld2169Inst, + FIELD_dsp340050b49a6c_fld2171Inst, + FIELD_dsp340050b49a6c_fld2172Inst, + FIELD_dsp340050b49a6c_fld2173Inst, + FIELD_dsp340050b49a6c_fld2174Inst, + FIELD_dsp340050b49a6c_fld2175Inst, + FIELD_dsp340050b49a6c_fld2177Inst, + FIELD_dsp340050b49a6c_fld2178Inst, + FIELD_dsp340050b49a6c_fld2179Inst, + FIELD_dsp340050b49a6c_fld2180Inst, + FIELD_dsp340050b49a6c_fld2181Inst, + FIELD_dsp340050b49a6c_fld2182Inst, + FIELD_dsp340050b49a6c_fld2183Inst, + FIELD_dsp340050b49a6c_fld2184Inst, + FIELD_dsp340050b49a6c_fld2185Inst, + FIELD_dsp340050b49a6c_fld2186Inst, + FIELD_dsp340050b49a6c_fld2187Inst, + FIELD_dsp340050b49a6c_fld2188Inst, + FIELD_dsp340050b49a6c_fld2189Inst, + FIELD_dsp340050b49a6c_fld2190Inst, + FIELD_dsp340050b49a6c_fld2191Inst, + FIELD_dsp340050b49a6c_fld2192Inst, + FIELD_dsp340050b49a6c_fld2193Inst, + FIELD_dsp340050b49a6c_fld2194Inst, + FIELD_dsp340050b49a6c_fld2195Inst, + FIELD_dsp340050b49a6c_fld2196Inst, + FIELD_dsp340050b49a6c_fld2197Inst, + FIELD_dsp340050b49a6c_fld2198Inst, + FIELD_dsp340050b49a6c_fld2199Inst, + FIELD_dsp340050b49a6c_fld2200Inst, + FIELD_dsp340050b49a6c_fld2201Inst, + FIELD_dsp340050b49a6c_fld2202Inst, + FIELD_dsp340050b49a6c_fld2203Inst, + FIELD_dsp340050b49a6c_fld2204Inst, + FIELD_dsp340050b49a6c_fld2205Inst, + FIELD_dsp340050b49a6c_fld2206Inst, + FIELD_dsp340050b49a6c_fld2207Inst, + FIELD_dsp340050b49a6c_fld2208Inst, + FIELD_dsp340050b49a6c_fld2209Inst, + FIELD_dsp340050b49a6c_fld2210Inst, + FIELD_dsp340050b49a6c_fld2211Inst, + FIELD_dsp340050b49a6c_fld2212Inst, + FIELD_dsp340050b49a6c_fld2213Inst, + FIELD_dsp340050b49a6c_fld2214Inst, + FIELD_dsp340050b49a6c_fld2215Inst, + FIELD_dsp340050b49a6c_fld2216Inst, + FIELD_dsp340050b49a6c_fld2217Inst, + FIELD_dsp340050b49a6c_fld2218Inst, + FIELD_dsp340050b49a6c_fld2219Inst, + FIELD_dsp340050b49a6c_fld2220Inst, + FIELD_dsp340050b49a6c_fld2221Inst, + FIELD_dsp340050b49a6c_fld2222Inst, + FIELD_dsp340050b49a6c_fld2223Inst, + FIELD_dsp340050b49a6c_fld2224Inst, + FIELD_dsp340050b49a6c_fld2225Inst, + FIELD_dsp340050b49a6c_fld2226Inst, + FIELD_dsp340050b49a6c_fld2227Inst, + FIELD_dsp340050b49a6c_fld2228Inst, + FIELD_dsp340050b49a6c_fld2229Inst, + FIELD_dsp340050b49a6c_fld2230Inst, + FIELD_dsp340050b49a6c_fld2231Inst, + FIELD_dsp340050b49a6c_fld2232Inst, + FIELD_dsp340050b49a6c_fld2234Inst, + FIELD_dsp340050b49a6c_fld2235Inst, + FIELD_dsp340050b49a6c_fld2236Inst, + FIELD_dsp340050b49a6c_fld2237Inst, + FIELD_dsp340050b49a6c_fld2238Inst, + FIELD_dsp340050b49a6c_fld2239Inst, + FIELD_dsp340050b49a6c_fld2240Inst, + FIELD_dsp340050b49a6c_fld2241Inst, + FIELD_dsp340050b49a6c_fld2242Inst, + FIELD_dsp340050b49a6c_fld2243Inst, + FIELD_dsp340050b49a6c_fld2244Inst, + FIELD_dsp340050b49a6c_fld2245Inst, + FIELD_dsp340050b49a6c_fld2246Inst, + FIELD_dsp340050b49a6c_fld2247Inst, + FIELD_dsp340050b49a6c_fld2248Inst, + FIELD_dsp340050b49a6c_fld2249Inst, + FIELD_dsp340050b49a6c_fld2250Inst, + FIELD_dsp340050b49a6c_fld2251Inst, + FIELD_dsp340050b49a6c_fld2252Inst, + FIELD_dsp340050b49a6c_fld2253Inst, + FIELD_dsp340050b49a6c_fld2254, + FIELD_dsp340050b49a6c_fld2255Inst, + FIELD_dsp340050b49a6c_fld2257Inst, + FIELD_dsp340050b49a6c_fld3627Inst, + FIELD_dsp340050b49a6c_fld3630Inst, + FIELD_dsp340050b49a6c_fld3631Inst, + FIELD_dsp340050b49a6c_fld3633Inst, + FIELD_dsp340050b49a6c_fld3634, + FIELD_dsp340050b49a6c_fld3635Inst, + FIELD_dsp340050b49a6c_fld3636Inst, + FIELD_dsp340050b49a6c_fld3637Inst, + FIELD_dsp340050b49a6c_fld3638Inst, + FIELD_dsp340050b49a6c_fld3639Inst, + FIELD_dsp340050b49a6c_fld3640Inst, + FIELD_dsp340050b49a6c_fld3642Inst, + FIELD_dsp340050b49a6c_fld3643Inst, + FIELD_dsp340050b49a6c_fld3644Inst, + FIELD_dsp340050b49a6c_fld3645Inst, + FIELD_dsp340050b49a6c_fld3647Inst, + FIELD_dsp340050b49a6c_fld3648Inst, + FIELD_dsp340050b49a6c_fld3649Inst, + FIELD_dsp340050b49a6c_fld3650Inst, + FIELD_dsp340050b49a6c_fld3651Inst, + FIELD_dsp340050b49a6c_fld3653Inst, + FIELD_dsp340050b49a6c_fld3654Inst, + FIELD_dsp340050b49a6c_fld3655Inst, + FIELD_dsp340050b49a6c_fld3656Inst, + FIELD_dsp340050b49a6c_fld3657Inst, + FIELD_dsp340050b49a6c_fld3658Inst, + FIELD_dsp340050b49a6c_fld3659Inst, + FIELD_dsp340050b49a6c_fld3660Inst, + FIELD_dsp340050b49a6c_fld3661Inst, + FIELD_dsp340050b49a6c_fld3662Inst, + FIELD_op0_s3, + FIELD_dsp340050b49a6c_fld2025, + FIELD_dsp340050b49a6c_fld2027, + FIELD_dsp340050b49a6c_fld2258GP_slot2, + FIELD_dsp340050b49a6c_fld2259GP_slot2, + FIELD_dsp340050b49a6c_fld2260GP_slot2, + FIELD_dsp340050b49a6c_fld2261GP_slot2, + FIELD_dsp340050b49a6c_fld2262GP_slot2, + FIELD_dsp340050b49a6c_fld2263GP_slot2, + FIELD_dsp340050b49a6c_fld2264GP_slot2, + FIELD_dsp340050b49a6c_fld2266GP_slot2, + FIELD_dsp340050b49a6c_fld2267GP_slot2, + FIELD_dsp340050b49a6c_fld2268GP_slot2, + FIELD_dsp340050b49a6c_fld2269GP_slot2, + FIELD_dsp340050b49a6c_fld2270GP_slot2, + FIELD_dsp340050b49a6c_fld2271GP_slot2, + FIELD_dsp340050b49a6c_fld2272, + FIELD_dsp340050b49a6c_fld2273GP_slot2, + FIELD_dsp340050b49a6c_fld2274GP_slot2, + FIELD_dsp340050b49a6c_fld2275GP_slot2, + FIELD_dsp340050b49a6c_fld2277GP_slot2, + FIELD_dsp340050b49a6c_fld2278GP_slot2, + FIELD_dsp340050b49a6c_fld2279GP_slot2, + FIELD_dsp340050b49a6c_fld2280GP_slot2, + FIELD_dsp340050b49a6c_fld2281GP_slot2, + FIELD_dsp340050b49a6c_fld2282GP_slot2, + FIELD_dsp340050b49a6c_fld2283GP_slot2, + FIELD_dsp340050b49a6c_fld2284GP_slot2, + FIELD_dsp340050b49a6c_fld2286GP_slot2, + FIELD_dsp340050b49a6c_fld2287GP_slot2, + FIELD_dsp340050b49a6c_fld2288GP_slot2, + FIELD_dsp340050b49a6c_fld2289GP_slot2, + FIELD_dsp340050b49a6c_fld2290GP_slot2, + FIELD_dsp340050b49a6c_fld2291GP_slot2, + FIELD_dsp340050b49a6c_fld2292GP_slot2, + FIELD_dsp340050b49a6c_fld2293GP_slot2, + FIELD_dsp340050b49a6c_fld2294GP_slot2, + FIELD_dsp340050b49a6c_fld2295GP_slot2, + FIELD_dsp340050b49a6c_fld2296GP_slot2, + FIELD_dsp340050b49a6c_fld2297GP_slot2, + FIELD_dsp340050b49a6c_fld2298GP_slot2, + FIELD_dsp340050b49a6c_fld2299GP_slot2, + FIELD_dsp340050b49a6c_fld2300GP_slot2, + FIELD_dsp340050b49a6c_fld2301GP_slot2, + FIELD_dsp340050b49a6c_fld2302, + FIELD_dsp340050b49a6c_fld2303GP_slot2, + FIELD_dsp340050b49a6c_fld2304GP_slot2, + FIELD_dsp340050b49a6c_fld2305, + FIELD_dsp340050b49a6c_fld2306GP_slot2, + FIELD_dsp340050b49a6c_fld2308GP_slot2, + FIELD_dsp340050b49a6c_fld2309GP_slot2, + FIELD_dsp340050b49a6c_fld2310GP_slot2, + FIELD_dsp340050b49a6c_fld2312GP_slot2, + FIELD_dsp340050b49a6c_fld2313, + FIELD_dsp340050b49a6c_fld2314GP_slot2, + FIELD_dsp340050b49a6c_fld2316GP_slot2, + FIELD_dsp340050b49a6c_fld2317GP_slot2, + FIELD_dsp340050b49a6c_fld2318GP_slot2, + FIELD_dsp340050b49a6c_fld2319GP_slot2, + FIELD_dsp340050b49a6c_fld2320GP_slot2, + FIELD_dsp340050b49a6c_fld2321GP_slot2, + FIELD_dsp340050b49a6c_fld2322GP_slot2, + FIELD_dsp340050b49a6c_fld2323GP_slot2, + FIELD_dsp340050b49a6c_fld2324GP_slot2, + FIELD_dsp340050b49a6c_fld2325GP_slot2, + FIELD_dsp340050b49a6c_fld2326GP_slot2, + FIELD_dsp340050b49a6c_fld2327GP_slot2, + FIELD_dsp340050b49a6c_fld2328GP_slot2, + FIELD_dsp340050b49a6c_fld2329GP_slot2, + FIELD_dsp340050b49a6c_fld2330GP_slot2, + FIELD_dsp340050b49a6c_fld2331GP_slot2, + FIELD_dsp340050b49a6c_fld2332GP_slot2, + FIELD_dsp340050b49a6c_fld2333GP_slot2, + FIELD_dsp340050b49a6c_fld2334GP_slot2, + FIELD_dsp340050b49a6c_fld2335GP_slot2, + FIELD_dsp340050b49a6c_fld2336GP_slot2, + FIELD_dsp340050b49a6c_fld2337GP_slot2, + FIELD_dsp340050b49a6c_fld2338GP_slot2, + FIELD_dsp340050b49a6c_fld2339GP_slot2, + FIELD_dsp340050b49a6c_fld2340GP_slot2, + FIELD_dsp340050b49a6c_fld2341GP_slot2, + FIELD_dsp340050b49a6c_fld2342GP_slot2, + FIELD_dsp340050b49a6c_fld2343GP_slot2, + FIELD_dsp340050b49a6c_fld2344GP_slot2, + FIELD_dsp340050b49a6c_fld2345GP_slot2, + FIELD_dsp340050b49a6c_fld2346GP_slot2, + FIELD_dsp340050b49a6c_fld2347GP_slot2, + FIELD_dsp340050b49a6c_fld2348GP_slot2, + FIELD_dsp340050b49a6c_fld2349GP_slot2, + FIELD_dsp340050b49a6c_fld2350GP_slot2, + FIELD_dsp340050b49a6c_fld2351GP_slot2, + FIELD_dsp340050b49a6c_fld2352GP_slot2, + FIELD_dsp340050b49a6c_fld2353GP_slot2, + FIELD_dsp340050b49a6c_fld2354GP_slot2, + FIELD_dsp340050b49a6c_fld2355GP_slot2, + FIELD_dsp340050b49a6c_fld2356GP_slot2, + FIELD_dsp340050b49a6c_fld2357GP_slot2, + FIELD_dsp340050b49a6c_fld2358GP_slot2, + FIELD_dsp340050b49a6c_fld2359GP_slot2, + FIELD_dsp340050b49a6c_fld2361GP_slot2, + FIELD_dsp340050b49a6c_fld2362GP_slot2, + FIELD_dsp340050b49a6c_fld2364GP_slot2, + FIELD_dsp340050b49a6c_fld2366GP_slot2, + FIELD_dsp340050b49a6c_fld2368GP_slot2, + FIELD_dsp340050b49a6c_fld2369GP_slot2, + FIELD_dsp340050b49a6c_fld2370GP_slot2, + FIELD_dsp340050b49a6c_fld2371GP_slot2, + FIELD_dsp340050b49a6c_fld2372GP_slot2, + FIELD_dsp340050b49a6c_fld2373GP_slot2, + FIELD_dsp340050b49a6c_fld2374GP_slot2, + FIELD_dsp340050b49a6c_fld2375GP_slot2, + FIELD_dsp340050b49a6c_fld2376GP_slot2, + FIELD_dsp340050b49a6c_fld2378GP_slot2, + FIELD_dsp340050b49a6c_fld2379GP_slot2, + FIELD_dsp340050b49a6c_fld2381GP_slot2, + FIELD_dsp340050b49a6c_fld2383GP_slot2, + FIELD_dsp340050b49a6c_fld2384, + FIELD_dsp340050b49a6c_fld2385GP_slot2, + FIELD_dsp340050b49a6c_fld2386, + FIELD_dsp340050b49a6c_fld2387GP_slot2, + FIELD_dsp340050b49a6c_fld2388GP_slot2, + FIELD_dsp340050b49a6c_fld2389GP_slot2, + FIELD_dsp340050b49a6c_fld3663GP_slot2, + FIELD_dsp340050b49a6c_fld3664GP_slot2, + FIELD_dsp340050b49a6c_fld3665GP_slot2, + FIELD_dsp340050b49a6c_fld3666, + FIELD_dsp340050b49a6c_fld3667GP_slot2, + FIELD_dsp340050b49a6c_fld3668GP_slot2, + FIELD_dsp340050b49a6c_fld3669GP_slot2, + FIELD_dsp340050b49a6c_fld3670GP_slot2, + FIELD_dsp340050b49a6c_fld3671GP_slot2, + FIELD_dsp340050b49a6c_fld3673GP_slot2, + FIELD_dsp340050b49a6c_fld3674GP_slot2, + FIELD_dsp340050b49a6c_fld3675GP_slot2, + FIELD_dsp340050b49a6c_fld3676GP_slot2, + FIELD_dsp340050b49a6c_fld3678GP_slot2, + FIELD_dsp340050b49a6c_fld3679GP_slot2, + FIELD_dsp340050b49a6c_fld3680GP_slot2, + FIELD_op0_s4, + FIELD_dsp340050b49a6c_fld2026, + FIELD_dsp340050b49a6c_fld2031, + FIELD_dsp340050b49a6c_fld2394GP_slot1, + FIELD_dsp340050b49a6c_fld2395GP_slot1, + FIELD_dsp340050b49a6c_fld2397GP_slot1, + FIELD_dsp340050b49a6c_fld2398GP_slot1, + FIELD_dsp340050b49a6c_fld2399GP_slot1, + FIELD_dsp340050b49a6c_fld2400GP_slot1, + FIELD_dsp340050b49a6c_fld2402GP_slot1, + FIELD_dsp340050b49a6c_fld2403GP_slot1, + FIELD_dsp340050b49a6c_fld2405GP_slot1, + FIELD_dsp340050b49a6c_fld3681GP_slot1, + FIELD_dsp340050b49a6c_fld3683GP_slot1, + FIELD_dsp340050b49a6c_fld3684GP_slot1, + FIELD_dsp340050b49a6c_fld3686GP_slot1, + FIELD_op0_s5, + FIELD_dsp340050b49a6c_fld2058, + FIELD_dsp340050b49a6c_fld2067, + FIELD_dsp340050b49a6c_fld2407GP_slot0, + FIELD_dsp340050b49a6c_fld2409GP_slot0, + FIELD_dsp340050b49a6c_fld2410GP_slot0, + FIELD_dsp340050b49a6c_fld2411GP_slot0, + FIELD_dsp340050b49a6c_fld2412GP_slot0, + FIELD_dsp340050b49a6c_fld2413GP_slot0, + FIELD_dsp340050b49a6c_fld2415GP_slot0, + FIELD_dsp340050b49a6c_fld2416GP_slot0, + FIELD_dsp340050b49a6c_fld2417GP_slot0, + FIELD_dsp340050b49a6c_fld2418GP_slot0, + FIELD_dsp340050b49a6c_fld2419GP_slot0, + FIELD_dsp340050b49a6c_fld2420GP_slot0, + FIELD_dsp340050b49a6c_fld2422GP_slot0, + FIELD_dsp340050b49a6c_fld2423GP_slot0, + FIELD_dsp340050b49a6c_fld2424GP_slot0, + FIELD_dsp340050b49a6c_fld2425GP_slot0, + FIELD_dsp340050b49a6c_fld2426GP_slot0, + FIELD_dsp340050b49a6c_fld2427GP_slot0, + FIELD_dsp340050b49a6c_fld2429GP_slot0, + FIELD_dsp340050b49a6c_fld2430GP_slot0, + FIELD_dsp340050b49a6c_fld2431GP_slot0, + FIELD_dsp340050b49a6c_fld2432GP_slot0, + FIELD_dsp340050b49a6c_fld2433GP_slot0, + FIELD_dsp340050b49a6c_fld2434GP_slot0, + FIELD_dsp340050b49a6c_fld2435GP_slot0, + FIELD_dsp340050b49a6c_fld2436GP_slot0, + FIELD_dsp340050b49a6c_fld2437GP_slot0, + FIELD_dsp340050b49a6c_fld2438GP_slot0, + FIELD_dsp340050b49a6c_fld2439GP_slot0, + FIELD_dsp340050b49a6c_fld2440GP_slot0, + FIELD_dsp340050b49a6c_fld2441GP_slot0, + FIELD_dsp340050b49a6c_fld2443GP_slot0, + FIELD_dsp340050b49a6c_fld2444GP_slot0, + FIELD_dsp340050b49a6c_fld2445, + FIELD_dsp340050b49a6c_fld2447GP_slot0, + FIELD_dsp340050b49a6c_fld2448, + FIELD_dsp340050b49a6c_fld2449GP_slot0, + FIELD_dsp340050b49a6c_fld2451GP_slot0, + FIELD_dsp340050b49a6c_fld2452GP_slot0, + FIELD_dsp340050b49a6c_fld2453GP_slot0, + FIELD_dsp340050b49a6c_fld2454GP_slot0, + FIELD_dsp340050b49a6c_fld2455GP_slot0, + FIELD_dsp340050b49a6c_fld2456GP_slot0, + FIELD_dsp340050b49a6c_fld2457GP_slot0, + FIELD_dsp340050b49a6c_fld2458GP_slot0, + FIELD_dsp340050b49a6c_fld2459GP_slot0, + FIELD_dsp340050b49a6c_fld2460GP_slot0, + FIELD_dsp340050b49a6c_fld2461GP_slot0, + FIELD_dsp340050b49a6c_fld2462, + FIELD_dsp340050b49a6c_fld2463GP_slot0, + FIELD_dsp340050b49a6c_fld2464GP_slot0, + FIELD_dsp340050b49a6c_fld2465GP_slot0, + FIELD_dsp340050b49a6c_fld2466GP_slot0, + FIELD_dsp340050b49a6c_fld2467GP_slot0, + FIELD_dsp340050b49a6c_fld2468GP_slot0, + FIELD_dsp340050b49a6c_fld2470GP_slot0, + FIELD_dsp340050b49a6c_fld2471GP_slot0, + FIELD_dsp340050b49a6c_fld2472GP_slot0, + FIELD_dsp340050b49a6c_fld2473GP_slot0, + FIELD_dsp340050b49a6c_fld2474GP_slot0, + FIELD_dsp340050b49a6c_fld2475GP_slot0, + FIELD_dsp340050b49a6c_fld2477GP_slot0, + FIELD_dsp340050b49a6c_fld2479GP_slot0, + FIELD_dsp340050b49a6c_fld2480GP_slot0, + FIELD_dsp340050b49a6c_fld2481GP_slot0, + FIELD_dsp340050b49a6c_fld2482GP_slot0, + FIELD_dsp340050b49a6c_fld2483GP_slot0, + FIELD_dsp340050b49a6c_fld2484GP_slot0, + FIELD_dsp340050b49a6c_fld2485GP_slot0, + FIELD_dsp340050b49a6c_fld2486GP_slot0, + FIELD_dsp340050b49a6c_fld2487GP_slot0, + FIELD_dsp340050b49a6c_fld2488GP_slot0, + FIELD_dsp340050b49a6c_fld2489GP_slot0, + FIELD_dsp340050b49a6c_fld2490GP_slot0, + FIELD_dsp340050b49a6c_fld2491GP_slot0, + FIELD_dsp340050b49a6c_fld2492GP_slot0, + FIELD_dsp340050b49a6c_fld2493GP_slot0, + FIELD_dsp340050b49a6c_fld2494GP_slot0, + FIELD_dsp340050b49a6c_fld2495GP_slot0, + FIELD_dsp340050b49a6c_fld2496GP_slot0, + FIELD_dsp340050b49a6c_fld2497GP_slot0, + FIELD_dsp340050b49a6c_fld2498GP_slot0, + FIELD_dsp340050b49a6c_fld2499GP_slot0, + FIELD_dsp340050b49a6c_fld2500GP_slot0, + FIELD_dsp340050b49a6c_fld2501GP_slot0, + FIELD_dsp340050b49a6c_fld2502GP_slot0, + FIELD_dsp340050b49a6c_fld2503GP_slot0, + FIELD_dsp340050b49a6c_fld2504GP_slot0, + FIELD_dsp340050b49a6c_fld2505GP_slot0, + FIELD_dsp340050b49a6c_fld2506GP_slot0, + FIELD_dsp340050b49a6c_fld2507GP_slot0, + FIELD_dsp340050b49a6c_fld2508GP_slot0, + FIELD_dsp340050b49a6c_fld2509GP_slot0, + FIELD_dsp340050b49a6c_fld2510GP_slot0, + FIELD_dsp340050b49a6c_fld2512GP_slot0, + FIELD_dsp340050b49a6c_fld2514GP_slot0, + FIELD_dsp340050b49a6c_fld2515GP_slot0, + FIELD_dsp340050b49a6c_fld2516GP_slot0, + FIELD_dsp340050b49a6c_fld2517GP_slot0, + FIELD_dsp340050b49a6c_fld2518GP_slot0, + FIELD_dsp340050b49a6c_fld2519GP_slot0, + FIELD_dsp340050b49a6c_fld2520GP_slot0, + FIELD_dsp340050b49a6c_fld2521GP_slot0, + FIELD_dsp340050b49a6c_fld2523GP_slot0, + FIELD_dsp340050b49a6c_fld2524GP_slot0, + FIELD_dsp340050b49a6c_fld2526GP_slot0, + FIELD_dsp340050b49a6c_fld2527GP_slot0, + FIELD_dsp340050b49a6c_fld2528GP_slot0, + FIELD_dsp340050b49a6c_fld2529GP_slot0, + FIELD_dsp340050b49a6c_fld2530, + FIELD_dsp340050b49a6c_fld2531GP_slot0, + FIELD_dsp340050b49a6c_fld3688GP_slot0, + FIELD_dsp340050b49a6c_fld3689GP_slot0, + FIELD_dsp340050b49a6c_fld3690GP_slot0, + FIELD_dsp340050b49a6c_fld3691GP_slot0, + FIELD_dsp340050b49a6c_fld3692GP_slot0, + FIELD_dsp340050b49a6c_fld3693GP_slot0, + FIELD_dsp340050b49a6c_fld3695GP_slot0, + FIELD_dsp340050b49a6c_fld3696GP_slot0, + FIELD_dsp340050b49a6c_fld3697GP_slot0, + FIELD_dsp340050b49a6c_fld3698GP_slot0, + FIELD_dsp340050b49a6c_fld3699GP_slot0, + FIELD_dsp340050b49a6c_fld3700GP_slot0, + FIELD_dsp340050b49a6c_fld3702GP_slot0, + FIELD_dsp340050b49a6c_fld3703GP_slot0, + FIELD_dsp340050b49a6c_fld3705GP_slot0, + FIELD_dsp340050b49a6c_fld3706GP_slot0, + FIELD_op0_s6, + FIELD_dsp340050b49a6c_fld2532DOT_slot2, + FIELD_dsp340050b49a6c_fld2533DOT_slot2, + FIELD_dsp340050b49a6c_fld2534DOT_slot2, + FIELD_dsp340050b49a6c_fld2535DOT_slot2, + FIELD_dsp340050b49a6c_fld2536DOT_slot2, + FIELD_dsp340050b49a6c_fld2537DOT_slot2, + FIELD_dsp340050b49a6c_fld2538DOT_slot2, + FIELD_dsp340050b49a6c_fld2539DOT_slot2, + FIELD_dsp340050b49a6c_fld2540DOT_slot2, + FIELD_dsp340050b49a6c_fld2541DOT_slot2, + FIELD_dsp340050b49a6c_fld2542DOT_slot2, + FIELD_dsp340050b49a6c_fld2543DOT_slot2, + FIELD_dsp340050b49a6c_fld2544DOT_slot2, + FIELD_dsp340050b49a6c_fld2545DOT_slot2, + FIELD_dsp340050b49a6c_fld2546DOT_slot2, + FIELD_dsp340050b49a6c_fld2547DOT_slot2, + FIELD_dsp340050b49a6c_fld2548DOT_slot2, + FIELD_dsp340050b49a6c_fld2549DOT_slot2, + FIELD_dsp340050b49a6c_fld2550DOT_slot2, + FIELD_dsp340050b49a6c_fld2551DOT_slot2, + FIELD_dsp340050b49a6c_fld2552DOT_slot2, + FIELD_dsp340050b49a6c_fld2553DOT_slot2, + FIELD_dsp340050b49a6c_fld2554DOT_slot2, + FIELD_dsp340050b49a6c_fld2555DOT_slot2, + FIELD_dsp340050b49a6c_fld2556DOT_slot2, + FIELD_dsp340050b49a6c_fld2557DOT_slot2, + FIELD_dsp340050b49a6c_fld2558DOT_slot2, + FIELD_dsp340050b49a6c_fld2559DOT_slot2, + FIELD_dsp340050b49a6c_fld2560DOT_slot2, + FIELD_dsp340050b49a6c_fld2561DOT_slot2, + FIELD_dsp340050b49a6c_fld2562DOT_slot2, + FIELD_dsp340050b49a6c_fld2563DOT_slot2, + FIELD_dsp340050b49a6c_fld2564DOT_slot2, + FIELD_dsp340050b49a6c_fld2565DOT_slot2, + FIELD_dsp340050b49a6c_fld2566DOT_slot2, + FIELD_dsp340050b49a6c_fld2567DOT_slot2, + FIELD_dsp340050b49a6c_fld2568DOT_slot2, + FIELD_dsp340050b49a6c_fld2569DOT_slot2, + FIELD_dsp340050b49a6c_fld2571DOT_slot2, + FIELD_dsp340050b49a6c_fld2572DOT_slot2, + FIELD_dsp340050b49a6c_fld2573DOT_slot2, + FIELD_dsp340050b49a6c_fld2574DOT_slot2, + FIELD_dsp340050b49a6c_fld2575DOT_slot2, + FIELD_dsp340050b49a6c_fld2576DOT_slot2, + FIELD_dsp340050b49a6c_fld2577DOT_slot2, + FIELD_dsp340050b49a6c_fld2578, + FIELD_dsp340050b49a6c_fld2579DOT_slot2, + FIELD_dsp340050b49a6c_fld2580DOT_slot2, + FIELD_dsp340050b49a6c_fld2581DOT_slot2, + FIELD_dsp340050b49a6c_fld2582DOT_slot2, + FIELD_dsp340050b49a6c_fld2583DOT_slot2, + FIELD_dsp340050b49a6c_fld2584DOT_slot2, + FIELD_dsp340050b49a6c_fld2585DOT_slot2, + FIELD_dsp340050b49a6c_fld2586DOT_slot2, + FIELD_dsp340050b49a6c_fld2587DOT_slot2, + FIELD_dsp340050b49a6c_fld2588DOT_slot2, + FIELD_dsp340050b49a6c_fld2589DOT_slot2, + FIELD_dsp340050b49a6c_fld2590DOT_slot2, + FIELD_dsp340050b49a6c_fld2591DOT_slot2, + FIELD_dsp340050b49a6c_fld2592DOT_slot2, + FIELD_dsp340050b49a6c_fld2595DOT_slot2, + FIELD_dsp340050b49a6c_fld2596DOT_slot2, + FIELD_dsp340050b49a6c_fld2598DOT_slot2, + FIELD_dsp340050b49a6c_fld2599DOT_slot2, + FIELD_dsp340050b49a6c_fld2601DOT_slot2, + FIELD_dsp340050b49a6c_fld2602DOT_slot2, + FIELD_dsp340050b49a6c_fld2604DOT_slot2, + FIELD_dsp340050b49a6c_fld2605, + FIELD_dsp340050b49a6c_fld2606DOT_slot2, + FIELD_dsp340050b49a6c_fld2608DOT_slot2, + FIELD_dsp340050b49a6c_fld2609DOT_slot2, + FIELD_dsp340050b49a6c_fld2610DOT_slot2, + FIELD_dsp340050b49a6c_fld2611DOT_slot2, + FIELD_dsp340050b49a6c_fld2612, + FIELD_dsp340050b49a6c_fld2613DOT_slot2, + FIELD_dsp340050b49a6c_fld2614, + FIELD_dsp340050b49a6c_fld2615DOT_slot2, + FIELD_dsp340050b49a6c_fld2616DOT_slot2, + FIELD_dsp340050b49a6c_fld2617DOT_slot2, + FIELD_dsp340050b49a6c_fld2618DOT_slot2, + FIELD_dsp340050b49a6c_fld2619DOT_slot2, + FIELD_dsp340050b49a6c_fld2620DOT_slot2, + FIELD_dsp340050b49a6c_fld2621DOT_slot2, + FIELD_dsp340050b49a6c_fld2622DOT_slot2, + FIELD_dsp340050b49a6c_fld2623DOT_slot2, + FIELD_dsp340050b49a6c_fld2624DOT_slot2, + FIELD_dsp340050b49a6c_fld2625, + FIELD_dsp340050b49a6c_fld2626DOT_slot2, + FIELD_dsp340050b49a6c_fld2628DOT_slot2, + FIELD_dsp340050b49a6c_fld2630DOT_slot2, + FIELD_dsp340050b49a6c_fld2632DOT_slot2, + FIELD_dsp340050b49a6c_fld2633DOT_slot2, + FIELD_dsp340050b49a6c_fld2635DOT_slot2, + FIELD_dsp340050b49a6c_fld2636DOT_slot2, + FIELD_dsp340050b49a6c_fld2637DOT_slot2, + FIELD_dsp340050b49a6c_fld2640DOT_slot2, + FIELD_dsp340050b49a6c_fld2641DOT_slot2, + FIELD_dsp340050b49a6c_fld2642DOT_slot2, + FIELD_dsp340050b49a6c_fld2643DOT_slot2, + FIELD_dsp340050b49a6c_fld2644DOT_slot2, + FIELD_dsp340050b49a6c_fld2645DOT_slot2, + FIELD_dsp340050b49a6c_fld2646DOT_slot2, + FIELD_dsp340050b49a6c_fld2647DOT_slot2, + FIELD_dsp340050b49a6c_fld2648DOT_slot2, + FIELD_dsp340050b49a6c_fld2649DOT_slot2, + FIELD_dsp340050b49a6c_fld2650DOT_slot2, + FIELD_dsp340050b49a6c_fld2651DOT_slot2, + FIELD_dsp340050b49a6c_fld2652DOT_slot2, + FIELD_dsp340050b49a6c_fld2654DOT_slot2, + FIELD_dsp340050b49a6c_fld2655DOT_slot2, + FIELD_dsp340050b49a6c_fld2656DOT_slot2, + FIELD_dsp340050b49a6c_fld2657DOT_slot2, + FIELD_dsp340050b49a6c_fld2658DOT_slot2, + FIELD_dsp340050b49a6c_fld3708DOT_slot2, + FIELD_dsp340050b49a6c_fld3709DOT_slot2, + FIELD_dsp340050b49a6c_fld3710DOT_slot2, + FIELD_dsp340050b49a6c_fld3711DOT_slot2, + FIELD_dsp340050b49a6c_fld3712, + FIELD_dsp340050b49a6c_fld3713DOT_slot2, + FIELD_dsp340050b49a6c_fld3714DOT_slot2, + FIELD_dsp340050b49a6c_fld3715, + FIELD_dsp340050b49a6c_fld3716DOT_slot2, + FIELD_dsp340050b49a6c_fld3717DOT_slot2, + FIELD_dsp340050b49a6c_fld3718, + FIELD_dsp340050b49a6c_fld3719DOT_slot2, + FIELD_dsp340050b49a6c_fld3721DOT_slot2, + FIELD_dsp340050b49a6c_fld3722, + FIELD_dsp340050b49a6c_fld3723DOT_slot2, + FIELD_dsp340050b49a6c_fld3724DOT_slot2, + FIELD_dsp340050b49a6c_fld3725DOT_slot2, + FIELD_dsp340050b49a6c_fld3726DOT_slot2, + FIELD_dsp340050b49a6c_fld3727DOT_slot2, + FIELD_dsp340050b49a6c_fld3728DOT_slot2, + FIELD_dsp340050b49a6c_fld3729DOT_slot2, + FIELD_dsp340050b49a6c_fld3731DOT_slot2, + FIELD_dsp340050b49a6c_fld3732DOT_slot2, + FIELD_dsp340050b49a6c_fld3733DOT_slot2, + FIELD_op0_s7, + FIELD_dsp340050b49a6c_fld3734DOT_slot1, + FIELD_op0_s8, + FIELD_dsp340050b49a6c_fld2068, + FIELD_dsp340050b49a6c_fld2666DOT_slot0, + FIELD_dsp340050b49a6c_fld2667DOT_slot0, + FIELD_dsp340050b49a6c_fld2668DOT_slot0, + FIELD_dsp340050b49a6c_fld2669DOT_slot0, + FIELD_dsp340050b49a6c_fld2671DOT_slot0, + FIELD_dsp340050b49a6c_fld2672DOT_slot0, + FIELD_dsp340050b49a6c_fld2673DOT_slot0, + FIELD_dsp340050b49a6c_fld2674DOT_slot0, + FIELD_dsp340050b49a6c_fld2675DOT_slot0, + FIELD_dsp340050b49a6c_fld2676DOT_slot0, + FIELD_dsp340050b49a6c_fld2677DOT_slot0, + FIELD_dsp340050b49a6c_fld2678DOT_slot0, + FIELD_dsp340050b49a6c_fld2679DOT_slot0, + FIELD_dsp340050b49a6c_fld2680DOT_slot0, + FIELD_dsp340050b49a6c_fld2681DOT_slot0, + FIELD_dsp340050b49a6c_fld2682DOT_slot0, + FIELD_dsp340050b49a6c_fld2683DOT_slot0, + FIELD_dsp340050b49a6c_fld2684DOT_slot0, + FIELD_dsp340050b49a6c_fld2685DOT_slot0, + FIELD_dsp340050b49a6c_fld2686DOT_slot0, + FIELD_dsp340050b49a6c_fld2688DOT_slot0, + FIELD_dsp340050b49a6c_fld2689DOT_slot0, + FIELD_dsp340050b49a6c_fld2690DOT_slot0, + FIELD_dsp340050b49a6c_fld2692DOT_slot0, + FIELD_dsp340050b49a6c_fld2693DOT_slot0, + FIELD_dsp340050b49a6c_fld2695DOT_slot0, + FIELD_dsp340050b49a6c_fld2697DOT_slot0, + FIELD_dsp340050b49a6c_fld2699DOT_slot0, + FIELD_dsp340050b49a6c_fld2700DOT_slot0, + FIELD_dsp340050b49a6c_fld2701DOT_slot0, + FIELD_dsp340050b49a6c_fld2702DOT_slot0, + FIELD_dsp340050b49a6c_fld2703DOT_slot0, + FIELD_dsp340050b49a6c_fld2704DOT_slot0, + FIELD_dsp340050b49a6c_fld2705DOT_slot0, + FIELD_dsp340050b49a6c_fld3735DOT_slot0, + FIELD_dsp340050b49a6c_fld3736, + FIELD_dsp340050b49a6c_fld3737DOT_slot0, + FIELD_dsp340050b49a6c_fld3738DOT_slot0, + FIELD_dsp340050b49a6c_fld3739DOT_slot0, + FIELD_dsp340050b49a6c_fld3740DOT_slot0, + FIELD_dsp340050b49a6c_fld3741DOT_slot0, + FIELD_dsp340050b49a6c_fld3742DOT_slot0, + FIELD_op0_s9, + FIELD_dsp340050b49a6c_fld2706PQ_slot2, + FIELD_dsp340050b49a6c_fld2707PQ_slot2, + FIELD_dsp340050b49a6c_fld2708PQ_slot2, + FIELD_dsp340050b49a6c_fld2709PQ_slot2, + FIELD_dsp340050b49a6c_fld2710PQ_slot2, + FIELD_dsp340050b49a6c_fld2711PQ_slot2, + FIELD_dsp340050b49a6c_fld2713PQ_slot2, + FIELD_dsp340050b49a6c_fld2714PQ_slot2, + FIELD_dsp340050b49a6c_fld2715PQ_slot2, + FIELD_dsp340050b49a6c_fld2717PQ_slot2, + FIELD_dsp340050b49a6c_fld2718PQ_slot2, + FIELD_dsp340050b49a6c_fld2719PQ_slot2, + FIELD_dsp340050b49a6c_fld2721PQ_slot2, + FIELD_dsp340050b49a6c_fld2722PQ_slot2, + FIELD_dsp340050b49a6c_fld2723PQ_slot2, + FIELD_dsp340050b49a6c_fld2724PQ_slot2, + FIELD_dsp340050b49a6c_fld2725PQ_slot2, + FIELD_dsp340050b49a6c_fld2726PQ_slot2, + FIELD_dsp340050b49a6c_fld2727PQ_slot2, + FIELD_dsp340050b49a6c_fld2728PQ_slot2, + FIELD_dsp340050b49a6c_fld2729PQ_slot2, + FIELD_dsp340050b49a6c_fld2730PQ_slot2, + FIELD_dsp340050b49a6c_fld2731PQ_slot2, + FIELD_dsp340050b49a6c_fld2732PQ_slot2, + FIELD_dsp340050b49a6c_fld2733PQ_slot2, + FIELD_dsp340050b49a6c_fld2734PQ_slot2, + FIELD_dsp340050b49a6c_fld2735PQ_slot2, + FIELD_dsp340050b49a6c_fld2736PQ_slot2, + FIELD_dsp340050b49a6c_fld2737, + FIELD_dsp340050b49a6c_fld2738PQ_slot2, + FIELD_dsp340050b49a6c_fld2739PQ_slot2, + FIELD_dsp340050b49a6c_fld2741PQ_slot2, + FIELD_dsp340050b49a6c_fld2742PQ_slot2, + FIELD_dsp340050b49a6c_fld2743PQ_slot2, + FIELD_dsp340050b49a6c_fld2746PQ_slot2, + FIELD_dsp340050b49a6c_fld2747PQ_slot2, + FIELD_dsp340050b49a6c_fld2748PQ_slot2, + FIELD_dsp340050b49a6c_fld2750PQ_slot2, + FIELD_dsp340050b49a6c_fld2751PQ_slot2, + FIELD_dsp340050b49a6c_fld2752PQ_slot2, + FIELD_dsp340050b49a6c_fld2753PQ_slot2, + FIELD_dsp340050b49a6c_fld2754PQ_slot2, + FIELD_dsp340050b49a6c_fld2755PQ_slot2, + FIELD_dsp340050b49a6c_fld2756PQ_slot2, + FIELD_dsp340050b49a6c_fld2757PQ_slot2, + FIELD_dsp340050b49a6c_fld2758PQ_slot2, + FIELD_dsp340050b49a6c_fld2759PQ_slot2, + FIELD_dsp340050b49a6c_fld2760PQ_slot2, + FIELD_dsp340050b49a6c_fld2761PQ_slot2, + FIELD_dsp340050b49a6c_fld2762PQ_slot2, + FIELD_dsp340050b49a6c_fld2763PQ_slot2, + FIELD_dsp340050b49a6c_fld2764PQ_slot2, + FIELD_dsp340050b49a6c_fld2765PQ_slot2, + FIELD_dsp340050b49a6c_fld2766PQ_slot2, + FIELD_dsp340050b49a6c_fld2767PQ_slot2, + FIELD_dsp340050b49a6c_fld2768PQ_slot2, + FIELD_dsp340050b49a6c_fld2769PQ_slot2, + FIELD_dsp340050b49a6c_fld2770PQ_slot2, + FIELD_dsp340050b49a6c_fld2771PQ_slot2, + FIELD_dsp340050b49a6c_fld2772PQ_slot2, + FIELD_dsp340050b49a6c_fld2773PQ_slot2, + FIELD_dsp340050b49a6c_fld2774PQ_slot2, + FIELD_dsp340050b49a6c_fld2775PQ_slot2, + FIELD_dsp340050b49a6c_fld2776PQ_slot2, + FIELD_dsp340050b49a6c_fld2777PQ_slot2, + FIELD_dsp340050b49a6c_fld2778PQ_slot2, + FIELD_dsp340050b49a6c_fld2779PQ_slot2, + FIELD_dsp340050b49a6c_fld2780PQ_slot2, + FIELD_dsp340050b49a6c_fld2781PQ_slot2, + FIELD_dsp340050b49a6c_fld2782PQ_slot2, + FIELD_dsp340050b49a6c_fld2783PQ_slot2, + FIELD_dsp340050b49a6c_fld2784PQ_slot2, + FIELD_dsp340050b49a6c_fld2785PQ_slot2, + FIELD_dsp340050b49a6c_fld2786PQ_slot2, + FIELD_dsp340050b49a6c_fld2787PQ_slot2, + FIELD_dsp340050b49a6c_fld2788PQ_slot2, + FIELD_dsp340050b49a6c_fld2789PQ_slot2, + FIELD_dsp340050b49a6c_fld2790PQ_slot2, + FIELD_dsp340050b49a6c_fld2791PQ_slot2, + FIELD_dsp340050b49a6c_fld2792PQ_slot2, + FIELD_dsp340050b49a6c_fld2793PQ_slot2, + FIELD_dsp340050b49a6c_fld2795PQ_slot2, + FIELD_dsp340050b49a6c_fld2796PQ_slot2, + FIELD_dsp340050b49a6c_fld2798PQ_slot2, + FIELD_dsp340050b49a6c_fld2801PQ_slot2, + FIELD_dsp340050b49a6c_fld2803PQ_slot2, + FIELD_dsp340050b49a6c_fld2805PQ_slot2, + FIELD_dsp340050b49a6c_fld2806PQ_slot2, + FIELD_dsp340050b49a6c_fld2807PQ_slot2, + FIELD_dsp340050b49a6c_fld2808PQ_slot2, + FIELD_dsp340050b49a6c_fld2809PQ_slot2, + FIELD_dsp340050b49a6c_fld2810PQ_slot2, + FIELD_dsp340050b49a6c_fld2811PQ_slot2, + FIELD_dsp340050b49a6c_fld2812PQ_slot2, + FIELD_dsp340050b49a6c_fld2814PQ_slot2, + FIELD_dsp340050b49a6c_fld2816PQ_slot2, + FIELD_dsp340050b49a6c_fld2817, + FIELD_dsp340050b49a6c_fld2818PQ_slot2, + FIELD_dsp340050b49a6c_fld2819, + FIELD_dsp340050b49a6c_fld2820PQ_slot2, + FIELD_dsp340050b49a6c_fld2821PQ_slot2, + FIELD_dsp340050b49a6c_fld2823PQ_slot2, + FIELD_dsp340050b49a6c_fld3744PQ_slot2, + FIELD_dsp340050b49a6c_fld3745PQ_slot2, + FIELD_dsp340050b49a6c_fld3746PQ_slot2, + FIELD_dsp340050b49a6c_fld3747PQ_slot2, + FIELD_dsp340050b49a6c_fld3748, + FIELD_dsp340050b49a6c_fld3749PQ_slot2, + FIELD_dsp340050b49a6c_fld3750PQ_slot2, + FIELD_dsp340050b49a6c_fld3751PQ_slot2, + FIELD_dsp340050b49a6c_fld3752PQ_slot2, + FIELD_dsp340050b49a6c_fld3753PQ_slot2, + FIELD_dsp340050b49a6c_fld3754PQ_slot2, + FIELD_dsp340050b49a6c_fld3756PQ_slot2, + FIELD_dsp340050b49a6c_fld3757PQ_slot2, + FIELD_dsp340050b49a6c_fld3758PQ_slot2, + FIELD_dsp340050b49a6c_fld3759PQ_slot2, + FIELD_dsp340050b49a6c_fld3760PQ_slot2, + FIELD_op0_s10, + FIELD_dsp340050b49a6c_fld2825PQ_slot1, + FIELD_dsp340050b49a6c_fld2826PQ_slot1, + FIELD_dsp340050b49a6c_fld3761PQ_slot1, + FIELD_op0_s11, + FIELD_dsp340050b49a6c_fld2059, + FIELD_dsp340050b49a6c_fld2069, + FIELD_dsp340050b49a6c_fld2827PQ_slot0, + FIELD_dsp340050b49a6c_fld2829PQ_slot0, + FIELD_dsp340050b49a6c_fld2830PQ_slot0, + FIELD_dsp340050b49a6c_fld2831PQ_slot0, + FIELD_dsp340050b49a6c_fld2832PQ_slot0, + FIELD_dsp340050b49a6c_fld2833PQ_slot0, + FIELD_dsp340050b49a6c_fld2835PQ_slot0, + FIELD_dsp340050b49a6c_fld2836PQ_slot0, + FIELD_dsp340050b49a6c_fld2837PQ_slot0, + FIELD_dsp340050b49a6c_fld2838PQ_slot0, + FIELD_dsp340050b49a6c_fld2839PQ_slot0, + FIELD_dsp340050b49a6c_fld2840PQ_slot0, + FIELD_dsp340050b49a6c_fld2842PQ_slot0, + FIELD_dsp340050b49a6c_fld2843PQ_slot0, + FIELD_dsp340050b49a6c_fld2844PQ_slot0, + FIELD_dsp340050b49a6c_fld2845PQ_slot0, + FIELD_dsp340050b49a6c_fld2846PQ_slot0, + FIELD_dsp340050b49a6c_fld2847PQ_slot0, + FIELD_dsp340050b49a6c_fld2849PQ_slot0, + FIELD_dsp340050b49a6c_fld2850PQ_slot0, + FIELD_dsp340050b49a6c_fld2851PQ_slot0, + FIELD_dsp340050b49a6c_fld2852PQ_slot0, + FIELD_dsp340050b49a6c_fld2853PQ_slot0, + FIELD_dsp340050b49a6c_fld2854PQ_slot0, + FIELD_dsp340050b49a6c_fld2855PQ_slot0, + FIELD_dsp340050b49a6c_fld2856PQ_slot0, + FIELD_dsp340050b49a6c_fld2857PQ_slot0, + FIELD_dsp340050b49a6c_fld2858PQ_slot0, + FIELD_dsp340050b49a6c_fld2859PQ_slot0, + FIELD_dsp340050b49a6c_fld2860PQ_slot0, + FIELD_dsp340050b49a6c_fld2861PQ_slot0, + FIELD_dsp340050b49a6c_fld2863PQ_slot0, + FIELD_dsp340050b49a6c_fld2864PQ_slot0, + FIELD_dsp340050b49a6c_fld2865, + FIELD_dsp340050b49a6c_fld2867PQ_slot0, + FIELD_dsp340050b49a6c_fld2869PQ_slot0, + FIELD_dsp340050b49a6c_fld2871PQ_slot0, + FIELD_dsp340050b49a6c_fld2872PQ_slot0, + FIELD_dsp340050b49a6c_fld2873PQ_slot0, + FIELD_dsp340050b49a6c_fld2874PQ_slot0, + FIELD_dsp340050b49a6c_fld2875PQ_slot0, + FIELD_dsp340050b49a6c_fld2876PQ_slot0, + FIELD_dsp340050b49a6c_fld2877PQ_slot0, + FIELD_dsp340050b49a6c_fld2878PQ_slot0, + FIELD_dsp340050b49a6c_fld2879PQ_slot0, + FIELD_dsp340050b49a6c_fld2880PQ_slot0, + FIELD_dsp340050b49a6c_fld2881PQ_slot0, + FIELD_dsp340050b49a6c_fld2882, + FIELD_dsp340050b49a6c_fld2883PQ_slot0, + FIELD_dsp340050b49a6c_fld2884PQ_slot0, + FIELD_dsp340050b49a6c_fld2885PQ_slot0, + FIELD_dsp340050b49a6c_fld2886PQ_slot0, + FIELD_dsp340050b49a6c_fld2887PQ_slot0, + FIELD_dsp340050b49a6c_fld2888PQ_slot0, + FIELD_dsp340050b49a6c_fld2890PQ_slot0, + FIELD_dsp340050b49a6c_fld2891PQ_slot0, + FIELD_dsp340050b49a6c_fld2892PQ_slot0, + FIELD_dsp340050b49a6c_fld2893PQ_slot0, + FIELD_dsp340050b49a6c_fld2894PQ_slot0, + FIELD_dsp340050b49a6c_fld2895PQ_slot0, + FIELD_dsp340050b49a6c_fld2897PQ_slot0, + FIELD_dsp340050b49a6c_fld2899PQ_slot0, + FIELD_dsp340050b49a6c_fld2900PQ_slot0, + FIELD_dsp340050b49a6c_fld2901PQ_slot0, + FIELD_dsp340050b49a6c_fld2902PQ_slot0, + FIELD_dsp340050b49a6c_fld2903PQ_slot0, + FIELD_dsp340050b49a6c_fld2904PQ_slot0, + FIELD_dsp340050b49a6c_fld2905PQ_slot0, + FIELD_dsp340050b49a6c_fld2906PQ_slot0, + FIELD_dsp340050b49a6c_fld2907PQ_slot0, + FIELD_dsp340050b49a6c_fld2908PQ_slot0, + FIELD_dsp340050b49a6c_fld2909PQ_slot0, + FIELD_dsp340050b49a6c_fld2910PQ_slot0, + FIELD_dsp340050b49a6c_fld2911PQ_slot0, + FIELD_dsp340050b49a6c_fld2912PQ_slot0, + FIELD_dsp340050b49a6c_fld2913PQ_slot0, + FIELD_dsp340050b49a6c_fld2914PQ_slot0, + FIELD_dsp340050b49a6c_fld2915PQ_slot0, + FIELD_dsp340050b49a6c_fld2916PQ_slot0, + FIELD_dsp340050b49a6c_fld2917PQ_slot0, + FIELD_dsp340050b49a6c_fld2918PQ_slot0, + FIELD_dsp340050b49a6c_fld2919PQ_slot0, + FIELD_dsp340050b49a6c_fld2920PQ_slot0, + FIELD_dsp340050b49a6c_fld2921PQ_slot0, + FIELD_dsp340050b49a6c_fld2922PQ_slot0, + FIELD_dsp340050b49a6c_fld2923PQ_slot0, + FIELD_dsp340050b49a6c_fld2924PQ_slot0, + FIELD_dsp340050b49a6c_fld2925PQ_slot0, + FIELD_dsp340050b49a6c_fld2926PQ_slot0, + FIELD_dsp340050b49a6c_fld2927PQ_slot0, + FIELD_dsp340050b49a6c_fld2928PQ_slot0, + FIELD_dsp340050b49a6c_fld2929PQ_slot0, + FIELD_dsp340050b49a6c_fld2930PQ_slot0, + FIELD_dsp340050b49a6c_fld2932PQ_slot0, + FIELD_dsp340050b49a6c_fld2934PQ_slot0, + FIELD_dsp340050b49a6c_fld2935PQ_slot0, + FIELD_dsp340050b49a6c_fld2936PQ_slot0, + FIELD_dsp340050b49a6c_fld2937PQ_slot0, + FIELD_dsp340050b49a6c_fld2939PQ_slot0, + FIELD_dsp340050b49a6c_fld2940, + FIELD_dsp340050b49a6c_fld2941PQ_slot0, + FIELD_dsp340050b49a6c_fld2942PQ_slot0, + FIELD_dsp340050b49a6c_fld2943PQ_slot0, + FIELD_dsp340050b49a6c_fld2945PQ_slot0, + FIELD_dsp340050b49a6c_fld2946PQ_slot0, + FIELD_dsp340050b49a6c_fld2947PQ_slot0, + FIELD_dsp340050b49a6c_fld2948PQ_slot0, + FIELD_dsp340050b49a6c_fld2949PQ_slot0, + FIELD_dsp340050b49a6c_fld2950PQ_slot0, + FIELD_dsp340050b49a6c_fld3763PQ_slot0, + FIELD_dsp340050b49a6c_fld3764PQ_slot0, + FIELD_dsp340050b49a6c_fld3765PQ_slot0, + FIELD_dsp340050b49a6c_fld3766PQ_slot0, + FIELD_dsp340050b49a6c_fld3767PQ_slot0, + FIELD_dsp340050b49a6c_fld3768PQ_slot0, + FIELD_dsp340050b49a6c_fld3769PQ_slot0, + FIELD_dsp340050b49a6c_fld3770PQ_slot0, + FIELD_dsp340050b49a6c_fld3771PQ_slot0, + FIELD_dsp340050b49a6c_fld3772, + FIELD_dsp340050b49a6c_fld3773PQ_slot0, + FIELD_dsp340050b49a6c_fld3775PQ_slot0, + FIELD_dsp340050b49a6c_fld3776PQ_slot0, + FIELD_dsp340050b49a6c_fld3777PQ_slot0, + FIELD_dsp340050b49a6c_fld3778PQ_slot0, + FIELD_dsp340050b49a6c_fld3779PQ_slot0, + FIELD_dsp340050b49a6c_fld3780PQ_slot0, + FIELD_op0_s12, + FIELD_dsp340050b49a6c_fld2953ACC2_slot2, + FIELD_dsp340050b49a6c_fld2954ACC2_slot2, + FIELD_dsp340050b49a6c_fld2955ACC2_slot2, + FIELD_dsp340050b49a6c_fld2956ACC2_slot2, + FIELD_dsp340050b49a6c_fld2957ACC2_slot2, + FIELD_dsp340050b49a6c_fld2958ACC2_slot2, + FIELD_dsp340050b49a6c_fld2959ACC2_slot2, + FIELD_dsp340050b49a6c_fld2960ACC2_slot2, + FIELD_dsp340050b49a6c_fld2963ACC2_slot2, + FIELD_dsp340050b49a6c_fld2964ACC2_slot2, + FIELD_dsp340050b49a6c_fld2966ACC2_slot2, + FIELD_dsp340050b49a6c_fld2967ACC2_slot2, + FIELD_dsp340050b49a6c_fld3782ACC2_slot2, + FIELD_dsp340050b49a6c_fld3783ACC2_slot2, + FIELD_dsp340050b49a6c_fld3784ACC2_slot2, + FIELD_dsp340050b49a6c_fld3785ACC2_slot2, + FIELD_dsp340050b49a6c_fld3786ACC2_slot2, + FIELD_dsp340050b49a6c_fld3788ACC2_slot2, + FIELD_op0_s13, + FIELD_dsp340050b49a6c_fld2028, + FIELD_dsp340050b49a6c_fld2075, + FIELD_dsp340050b49a6c_fld2968ACC2_slot1, + FIELD_dsp340050b49a6c_fld2969ACC2_slot1, + FIELD_dsp340050b49a6c_fld3790ACC2_slot1, + FIELD_dsp340050b49a6c_fld3793ACC2_slot1, + FIELD_op0_s14, + FIELD_dsp340050b49a6c_fld2973ACC2_slot0, + FIELD_dsp340050b49a6c_fld2974ACC2_slot0, + FIELD_dsp340050b49a6c_fld2975ACC2_slot0, + FIELD_dsp340050b49a6c_fld2976ACC2_slot0, + FIELD_dsp340050b49a6c_fld2977ACC2_slot0, + FIELD_dsp340050b49a6c_fld2980ACC2_slot0, + FIELD_dsp340050b49a6c_fld2981ACC2_slot0, + FIELD_dsp340050b49a6c_fld2982ACC2_slot0, + FIELD_dsp340050b49a6c_fld2984ACC2_slot0, + FIELD_dsp340050b49a6c_fld2985ACC2_slot0, + FIELD_dsp340050b49a6c_fld2987ACC2_slot0, + FIELD_dsp340050b49a6c_fld2989ACC2_slot0, + FIELD_dsp340050b49a6c_fld2990ACC2_slot0, + FIELD_dsp340050b49a6c_fld3795ACC2_slot0, + FIELD_dsp340050b49a6c_fld3796ACC2_slot0, + FIELD_dsp340050b49a6c_fld3797, + FIELD_dsp340050b49a6c_fld3798ACC2_slot0, + FIELD_dsp340050b49a6c_fld3799ACC2_slot0, + FIELD_dsp340050b49a6c_fld3800ACC2_slot0, + FIELD_dsp340050b49a6c_fld3801ACC2_slot0, + FIELD_dsp340050b49a6c_fld3802ACC2_slot0, + FIELD_dsp340050b49a6c_fld3803ACC2_slot0, + FIELD_op0_s15, + FIELD_dsp340050b49a6c_fld2991SMOD_slot2, + FIELD_dsp340050b49a6c_fld2992SMOD_slot2, + FIELD_dsp340050b49a6c_fld2993SMOD_slot2, + FIELD_dsp340050b49a6c_fld2994SMOD_slot2, + FIELD_dsp340050b49a6c_fld2995SMOD_slot2, + FIELD_dsp340050b49a6c_fld2996SMOD_slot2, + FIELD_dsp340050b49a6c_fld2997SMOD_slot2, + FIELD_dsp340050b49a6c_fld2998SMOD_slot2, + FIELD_dsp340050b49a6c_fld2999SMOD_slot2, + FIELD_dsp340050b49a6c_fld3000SMOD_slot2, + FIELD_dsp340050b49a6c_fld3001SMOD_slot2, + FIELD_dsp340050b49a6c_fld3002SMOD_slot2, + FIELD_dsp340050b49a6c_fld3003SMOD_slot2, + FIELD_dsp340050b49a6c_fld3004SMOD_slot2, + FIELD_dsp340050b49a6c_fld3005SMOD_slot2, + FIELD_dsp340050b49a6c_fld3006SMOD_slot2, + FIELD_dsp340050b49a6c_fld3007SMOD_slot2, + FIELD_dsp340050b49a6c_fld3008SMOD_slot2, + FIELD_dsp340050b49a6c_fld3009SMOD_slot2, + FIELD_dsp340050b49a6c_fld3010SMOD_slot2, + FIELD_dsp340050b49a6c_fld3011SMOD_slot2, + FIELD_dsp340050b49a6c_fld3012SMOD_slot2, + FIELD_dsp340050b49a6c_fld3013SMOD_slot2, + FIELD_dsp340050b49a6c_fld3014SMOD_slot2, + FIELD_dsp340050b49a6c_fld3015SMOD_slot2, + FIELD_dsp340050b49a6c_fld3016SMOD_slot2, + FIELD_dsp340050b49a6c_fld3017SMOD_slot2, + FIELD_dsp340050b49a6c_fld3018SMOD_slot2, + FIELD_dsp340050b49a6c_fld3019SMOD_slot2, + FIELD_dsp340050b49a6c_fld3020SMOD_slot2, + FIELD_dsp340050b49a6c_fld3021SMOD_slot2, + FIELD_dsp340050b49a6c_fld3022SMOD_slot2, + FIELD_dsp340050b49a6c_fld3023SMOD_slot2, + FIELD_dsp340050b49a6c_fld3024SMOD_slot2, + FIELD_dsp340050b49a6c_fld3025SMOD_slot2, + FIELD_dsp340050b49a6c_fld3026SMOD_slot2, + FIELD_dsp340050b49a6c_fld3027SMOD_slot2, + FIELD_dsp340050b49a6c_fld3028SMOD_slot2, + FIELD_dsp340050b49a6c_fld3030SMOD_slot2, + FIELD_dsp340050b49a6c_fld3031SMOD_slot2, + FIELD_dsp340050b49a6c_fld3032SMOD_slot2, + FIELD_dsp340050b49a6c_fld3033SMOD_slot2, + FIELD_dsp340050b49a6c_fld3034SMOD_slot2, + FIELD_dsp340050b49a6c_fld3035SMOD_slot2, + FIELD_dsp340050b49a6c_fld3036SMOD_slot2, + FIELD_dsp340050b49a6c_fld3038SMOD_slot2, + FIELD_dsp340050b49a6c_fld3039SMOD_slot2, + FIELD_dsp340050b49a6c_fld3040SMOD_slot2, + FIELD_dsp340050b49a6c_fld3043SMOD_slot2, + FIELD_dsp340050b49a6c_fld3044SMOD_slot2, + FIELD_dsp340050b49a6c_fld3046SMOD_slot2, + FIELD_dsp340050b49a6c_fld3047SMOD_slot2, + FIELD_dsp340050b49a6c_fld3048, + FIELD_dsp340050b49a6c_fld3049SMOD_slot2, + FIELD_dsp340050b49a6c_fld3050SMOD_slot2, + FIELD_dsp340050b49a6c_fld3051SMOD_slot2, + FIELD_dsp340050b49a6c_fld3052SMOD_slot2, + FIELD_dsp340050b49a6c_fld3053SMOD_slot2, + FIELD_dsp340050b49a6c_fld3054SMOD_slot2, + FIELD_dsp340050b49a6c_fld3055SMOD_slot2, + FIELD_dsp340050b49a6c_fld3056SMOD_slot2, + FIELD_dsp340050b49a6c_fld3058SMOD_slot2, + FIELD_dsp340050b49a6c_fld3059SMOD_slot2, + FIELD_dsp340050b49a6c_fld3061SMOD_slot2, + FIELD_dsp340050b49a6c_fld3062, + FIELD_dsp340050b49a6c_fld3063SMOD_slot2, + FIELD_dsp340050b49a6c_fld3065SMOD_slot2, + FIELD_dsp340050b49a6c_fld3066SMOD_slot2, + FIELD_dsp340050b49a6c_fld3067SMOD_slot2, + FIELD_dsp340050b49a6c_fld3068SMOD_slot2, + FIELD_dsp340050b49a6c_fld3069SMOD_slot2, + FIELD_dsp340050b49a6c_fld3070, + FIELD_dsp340050b49a6c_fld3071SMOD_slot2, + FIELD_dsp340050b49a6c_fld3072SMOD_slot2, + FIELD_dsp340050b49a6c_fld3073SMOD_slot2, + FIELD_dsp340050b49a6c_fld3074SMOD_slot2, + FIELD_dsp340050b49a6c_fld3075SMOD_slot2, + FIELD_dsp340050b49a6c_fld3076SMOD_slot2, + FIELD_dsp340050b49a6c_fld3077SMOD_slot2, + FIELD_dsp340050b49a6c_fld3078SMOD_slot2, + FIELD_dsp340050b49a6c_fld3079SMOD_slot2, + FIELD_dsp340050b49a6c_fld3080SMOD_slot2, + FIELD_dsp340050b49a6c_fld3081SMOD_slot2, + FIELD_dsp340050b49a6c_fld3082SMOD_slot2, + FIELD_dsp340050b49a6c_fld3084SMOD_slot2, + FIELD_dsp340050b49a6c_fld3085SMOD_slot2, + FIELD_dsp340050b49a6c_fld3087SMOD_slot2, + FIELD_dsp340050b49a6c_fld3088SMOD_slot2, + FIELD_dsp340050b49a6c_fld3090SMOD_slot2, + FIELD_dsp340050b49a6c_fld3091SMOD_slot2, + FIELD_dsp340050b49a6c_fld3092SMOD_slot2, + FIELD_dsp340050b49a6c_fld3093SMOD_slot2, + FIELD_dsp340050b49a6c_fld3096SMOD_slot2, + FIELD_dsp340050b49a6c_fld3097SMOD_slot2, + FIELD_dsp340050b49a6c_fld3098SMOD_slot2, + FIELD_dsp340050b49a6c_fld3099SMOD_slot2, + FIELD_dsp340050b49a6c_fld3100SMOD_slot2, + FIELD_dsp340050b49a6c_fld3101SMOD_slot2, + FIELD_dsp340050b49a6c_fld3102SMOD_slot2, + FIELD_dsp340050b49a6c_fld3104SMOD_slot2, + FIELD_dsp340050b49a6c_fld3105SMOD_slot2, + FIELD_dsp340050b49a6c_fld3106SMOD_slot2, + FIELD_dsp340050b49a6c_fld3107SMOD_slot2, + FIELD_dsp340050b49a6c_fld3108SMOD_slot2, + FIELD_dsp340050b49a6c_fld3109SMOD_slot2, + FIELD_dsp340050b49a6c_fld3110SMOD_slot2, + FIELD_dsp340050b49a6c_fld3111SMOD_slot2, + FIELD_dsp340050b49a6c_fld3113SMOD_slot2, + FIELD_dsp340050b49a6c_fld3114SMOD_slot2, + FIELD_dsp340050b49a6c_fld3115SMOD_slot2, + FIELD_dsp340050b49a6c_fld3116SMOD_slot2, + FIELD_dsp340050b49a6c_fld3805SMOD_slot2, + FIELD_dsp340050b49a6c_fld3806SMOD_slot2, + FIELD_dsp340050b49a6c_fld3807SMOD_slot2, + FIELD_dsp340050b49a6c_fld3808, + FIELD_dsp340050b49a6c_fld3809SMOD_slot2, + FIELD_dsp340050b49a6c_fld3810SMOD_slot2, + FIELD_dsp340050b49a6c_fld3812SMOD_slot2, + FIELD_dsp340050b49a6c_fld3813SMOD_slot2, + FIELD_dsp340050b49a6c_fld3814SMOD_slot2, + FIELD_dsp340050b49a6c_fld3816SMOD_slot2, + FIELD_dsp340050b49a6c_fld3817, + FIELD_dsp340050b49a6c_fld3818SMOD_slot2, + FIELD_dsp340050b49a6c_fld3819SMOD_slot2, + FIELD_dsp340050b49a6c_fld3821SMOD_slot2, + FIELD_dsp340050b49a6c_fld3822SMOD_slot2, + FIELD_dsp340050b49a6c_fld3823SMOD_slot2, + FIELD_dsp340050b49a6c_fld3824SMOD_slot2, + FIELD_dsp340050b49a6c_fld3825SMOD_slot2, + FIELD_dsp340050b49a6c_fld3826SMOD_slot2, + FIELD_dsp340050b49a6c_fld3827SMOD_slot2, + FIELD_dsp340050b49a6c_fld3828SMOD_slot2, + FIELD_op0_s16, + FIELD_dsp340050b49a6c_fld2033, + FIELD_dsp340050b49a6c_fld2080, + FIELD_dsp340050b49a6c_fld3117SMOD_slot1, + FIELD_dsp340050b49a6c_fld3118SMOD_slot1, + FIELD_dsp340050b49a6c_fld3829SMOD_slot1, + FIELD_op0_s17, + FIELD_dsp340050b49a6c_fld3119SMOD_slot0, + FIELD_dsp340050b49a6c_fld3120SMOD_slot0, + FIELD_dsp340050b49a6c_fld3121SMOD_slot0, + FIELD_dsp340050b49a6c_fld3122SMOD_slot0, + FIELD_dsp340050b49a6c_fld3123SMOD_slot0, + FIELD_dsp340050b49a6c_fld3125SMOD_slot0, + FIELD_dsp340050b49a6c_fld3126SMOD_slot0, + FIELD_dsp340050b49a6c_fld3127SMOD_slot0, + FIELD_dsp340050b49a6c_fld3128SMOD_slot0, + FIELD_dsp340050b49a6c_fld3129SMOD_slot0, + FIELD_dsp340050b49a6c_fld3130SMOD_slot0, + FIELD_dsp340050b49a6c_fld3131SMOD_slot0, + FIELD_dsp340050b49a6c_fld3132SMOD_slot0, + FIELD_dsp340050b49a6c_fld3133SMOD_slot0, + FIELD_dsp340050b49a6c_fld3134SMOD_slot0, + FIELD_dsp340050b49a6c_fld3135SMOD_slot0, + FIELD_dsp340050b49a6c_fld3136SMOD_slot0, + FIELD_dsp340050b49a6c_fld3137SMOD_slot0, + FIELD_dsp340050b49a6c_fld3138SMOD_slot0, + FIELD_dsp340050b49a6c_fld3139SMOD_slot0, + FIELD_dsp340050b49a6c_fld3140SMOD_slot0, + FIELD_dsp340050b49a6c_fld3141SMOD_slot0, + FIELD_dsp340050b49a6c_fld3142SMOD_slot0, + FIELD_dsp340050b49a6c_fld3143SMOD_slot0, + FIELD_dsp340050b49a6c_fld3144SMOD_slot0, + FIELD_dsp340050b49a6c_fld3145SMOD_slot0, + FIELD_dsp340050b49a6c_fld3146SMOD_slot0, + FIELD_dsp340050b49a6c_fld3148SMOD_slot0, + FIELD_dsp340050b49a6c_fld3149SMOD_slot0, + FIELD_dsp340050b49a6c_fld3150, + FIELD_dsp340050b49a6c_fld3152SMOD_slot0, + FIELD_dsp340050b49a6c_fld3153SMOD_slot0, + FIELD_dsp340050b49a6c_fld3155SMOD_slot0, + FIELD_dsp340050b49a6c_fld3156SMOD_slot0, + FIELD_dsp340050b49a6c_fld3157SMOD_slot0, + FIELD_dsp340050b49a6c_fld3158SMOD_slot0, + FIELD_dsp340050b49a6c_fld3159SMOD_slot0, + FIELD_dsp340050b49a6c_fld3160SMOD_slot0, + FIELD_dsp340050b49a6c_fld3161SMOD_slot0, + FIELD_dsp340050b49a6c_fld3164SMOD_slot0, + FIELD_dsp340050b49a6c_fld3165SMOD_slot0, + FIELD_dsp340050b49a6c_fld3166SMOD_slot0, + FIELD_dsp340050b49a6c_fld3168SMOD_slot0, + FIELD_dsp340050b49a6c_fld3170SMOD_slot0, + FIELD_dsp340050b49a6c_fld3171SMOD_slot0, + FIELD_dsp340050b49a6c_fld3172SMOD_slot0, + FIELD_dsp340050b49a6c_fld3173SMOD_slot0, + FIELD_dsp340050b49a6c_fld3174SMOD_slot0, + FIELD_dsp340050b49a6c_fld3175SMOD_slot0, + FIELD_dsp340050b49a6c_fld3176SMOD_slot0, + FIELD_dsp340050b49a6c_fld3177SMOD_slot0, + FIELD_dsp340050b49a6c_fld3178SMOD_slot0, + FIELD_dsp340050b49a6c_fld3179SMOD_slot0, + FIELD_dsp340050b49a6c_fld3180SMOD_slot0, + FIELD_dsp340050b49a6c_fld3181SMOD_slot0, + FIELD_dsp340050b49a6c_fld3182SMOD_slot0, + FIELD_dsp340050b49a6c_fld3184SMOD_slot0, + FIELD_dsp340050b49a6c_fld3186SMOD_slot0, + FIELD_dsp340050b49a6c_fld3188SMOD_slot0, + FIELD_dsp340050b49a6c_fld3832SMOD_slot0, + FIELD_dsp340050b49a6c_fld3833SMOD_slot0, + FIELD_dsp340050b49a6c_fld3834, + FIELD_dsp340050b49a6c_fld3836SMOD_slot0, + FIELD_dsp340050b49a6c_fld3837SMOD_slot0, + FIELD_dsp340050b49a6c_fld3838SMOD_slot0, + FIELD_dsp340050b49a6c_fld3841SMOD_slot0, + FIELD_dsp340050b49a6c_fld3842SMOD_slot0, + FIELD_op0_s18, + FIELD_dsp340050b49a6c_fld2074, + FIELD_dsp340050b49a6c_fld3191LLR_slot2, + FIELD_dsp340050b49a6c_fld3192LLR_slot2, + FIELD_dsp340050b49a6c_fld3193LLR_slot2, + FIELD_dsp340050b49a6c_fld3194LLR_slot2, + FIELD_dsp340050b49a6c_fld3195LLR_slot2, + FIELD_dsp340050b49a6c_fld3196LLR_slot2, + FIELD_dsp340050b49a6c_fld3197LLR_slot2, + FIELD_dsp340050b49a6c_fld3198LLR_slot2, + FIELD_dsp340050b49a6c_fld3199LLR_slot2, + FIELD_dsp340050b49a6c_fld3200LLR_slot2, + FIELD_dsp340050b49a6c_fld3201LLR_slot2, + FIELD_dsp340050b49a6c_fld3202LLR_slot2, + FIELD_dsp340050b49a6c_fld3203LLR_slot2, + FIELD_dsp340050b49a6c_fld3204LLR_slot2, + FIELD_dsp340050b49a6c_fld3205, + FIELD_dsp340050b49a6c_fld3206, + FIELD_dsp340050b49a6c_fld3207LLR_slot2, + FIELD_dsp340050b49a6c_fld3208LLR_slot2, + FIELD_dsp340050b49a6c_fld3210LLR_slot2, + FIELD_dsp340050b49a6c_fld3212, + FIELD_dsp340050b49a6c_fld3213LLR_slot2, + FIELD_dsp340050b49a6c_fld3214, + FIELD_dsp340050b49a6c_fld3215LLR_slot2, + FIELD_dsp340050b49a6c_fld3216LLR_slot2, + FIELD_dsp340050b49a6c_fld3217, + FIELD_dsp340050b49a6c_fld3218LLR_slot2, + FIELD_dsp340050b49a6c_fld3220LLR_slot2, + FIELD_dsp340050b49a6c_fld3221LLR_slot2, + FIELD_dsp340050b49a6c_fld3222LLR_slot2, + FIELD_dsp340050b49a6c_fld3224LLR_slot2, + FIELD_dsp340050b49a6c_fld3225, + FIELD_dsp340050b49a6c_fld3226LLR_slot2, + FIELD_dsp340050b49a6c_fld3228LLR_slot2, + FIELD_dsp340050b49a6c_fld3230, + FIELD_dsp340050b49a6c_fld3231LLR_slot2, + FIELD_dsp340050b49a6c_fld3232LLR_slot2, + FIELD_dsp340050b49a6c_fld3233, + FIELD_dsp340050b49a6c_fld3234LLR_slot2, + FIELD_dsp340050b49a6c_fld3235LLR_slot2, + FIELD_dsp340050b49a6c_fld3236, + FIELD_dsp340050b49a6c_fld3237LLR_slot2, + FIELD_dsp340050b49a6c_fld3238LLR_slot2, + FIELD_dsp340050b49a6c_fld3240LLR_slot2, + FIELD_dsp340050b49a6c_fld3241LLR_slot2, + FIELD_dsp340050b49a6c_fld3242LLR_slot2, + FIELD_dsp340050b49a6c_fld3243LLR_slot2, + FIELD_dsp340050b49a6c_fld3244LLR_slot2, + FIELD_dsp340050b49a6c_fld3245LLR_slot2, + FIELD_dsp340050b49a6c_fld3246, + FIELD_dsp340050b49a6c_fld3247LLR_slot2, + FIELD_dsp340050b49a6c_fld3843LLR_slot2, + FIELD_dsp340050b49a6c_fld3844, + FIELD_dsp340050b49a6c_fld3845LLR_slot2, + FIELD_dsp340050b49a6c_fld3847LLR_slot2, + FIELD_dsp340050b49a6c_fld3848LLR_slot2, + FIELD_dsp340050b49a6c_fld3849LLR_slot2, + FIELD_dsp340050b49a6c_fld3850LLR_slot2, + FIELD_dsp340050b49a6c_fld3851LLR_slot2, + FIELD_dsp340050b49a6c_fld3853LLR_slot2, + FIELD_dsp340050b49a6c_fld3855LLR_slot2, + FIELD_dsp340050b49a6c_fld3856LLR_slot2, + FIELD_dsp340050b49a6c_fld3857LLR_slot2, + FIELD_dsp340050b49a6c_fld3859LLR_slot2, + FIELD_dsp340050b49a6c_fld3860LLR_slot2, + FIELD_dsp340050b49a6c_fld3861LLR_slot2, + FIELD_dsp340050b49a6c_fld3862, + FIELD_dsp340050b49a6c_fld3863LLR_slot2, + FIELD_dsp340050b49a6c_fld3864LLR_slot2, + FIELD_dsp340050b49a6c_fld3865LLR_slot2, + FIELD_dsp340050b49a6c_fld3866LLR_slot2, + FIELD_dsp340050b49a6c_fld3867LLR_slot2, + FIELD_dsp340050b49a6c_fld3868, + FIELD_op0_s19, + FIELD_dsp340050b49a6c_fld2034, + FIELD_dsp340050b49a6c_fld3248LLR_slot1, + FIELD_dsp340050b49a6c_fld3250LLR_slot1, + FIELD_dsp340050b49a6c_fld3251LLR_slot1, + FIELD_dsp340050b49a6c_fld3252LLR_slot1, + FIELD_dsp340050b49a6c_fld3253LLR_slot1, + FIELD_dsp340050b49a6c_fld3254LLR_slot1, + FIELD_dsp340050b49a6c_fld3869LLR_slot1, + FIELD_dsp340050b49a6c_fld3870, + FIELD_dsp340050b49a6c_fld3872LLR_slot1, + FIELD_dsp340050b49a6c_fld3875LLR_slot1, + FIELD_dsp340050b49a6c_fld3876LLR_slot1, + FIELD_dsp340050b49a6c_fld3878LLR_slot1, + FIELD_op0_s20, + FIELD_dsp340050b49a6c_fld2071, + FIELD_dsp340050b49a6c_fld3258LLR_slot0, + FIELD_dsp340050b49a6c_fld3259LLR_slot0, + FIELD_dsp340050b49a6c_fld3260LLR_slot0, + FIELD_dsp340050b49a6c_fld3261LLR_slot0, + FIELD_dsp340050b49a6c_fld3263LLR_slot0, + FIELD_dsp340050b49a6c_fld3264LLR_slot0, + FIELD_dsp340050b49a6c_fld3265LLR_slot0, + FIELD_dsp340050b49a6c_fld3266LLR_slot0, + FIELD_dsp340050b49a6c_fld3267LLR_slot0, + FIELD_dsp340050b49a6c_fld3268LLR_slot0, + FIELD_dsp340050b49a6c_fld3269LLR_slot0, + FIELD_dsp340050b49a6c_fld3270LLR_slot0, + FIELD_dsp340050b49a6c_fld3272LLR_slot0, + FIELD_dsp340050b49a6c_fld3274LLR_slot0, + FIELD_dsp340050b49a6c_fld3275LLR_slot0, + FIELD_dsp340050b49a6c_fld3276LLR_slot0, + FIELD_dsp340050b49a6c_fld3277LLR_slot0, + FIELD_dsp340050b49a6c_fld3278LLR_slot0, + FIELD_dsp340050b49a6c_fld3279LLR_slot0, + FIELD_dsp340050b49a6c_fld3280LLR_slot0, + FIELD_dsp340050b49a6c_fld3281LLR_slot0, + FIELD_dsp340050b49a6c_fld3282LLR_slot0, + FIELD_dsp340050b49a6c_fld3283LLR_slot0, + FIELD_dsp340050b49a6c_fld3284LLR_slot0, + FIELD_dsp340050b49a6c_fld3286LLR_slot0, + FIELD_dsp340050b49a6c_fld3288LLR_slot0, + FIELD_dsp340050b49a6c_fld3289LLR_slot0, + FIELD_dsp340050b49a6c_fld3291LLR_slot0, + FIELD_dsp340050b49a6c_fld3292LLR_slot0, + FIELD_dsp340050b49a6c_fld3293LLR_slot0, + FIELD_dsp340050b49a6c_fld3294LLR_slot0, + FIELD_dsp340050b49a6c_fld3295LLR_slot0, + FIELD_dsp340050b49a6c_fld3296LLR_slot0, + FIELD_dsp340050b49a6c_fld3297LLR_slot0, + FIELD_dsp340050b49a6c_fld3298LLR_slot0, + FIELD_dsp340050b49a6c_fld3299LLR_slot0, + FIELD_dsp340050b49a6c_fld3300LLR_slot0, + FIELD_dsp340050b49a6c_fld3302LLR_slot0, + FIELD_dsp340050b49a6c_fld3303LLR_slot0, + FIELD_dsp340050b49a6c_fld3304LLR_slot0, + FIELD_dsp340050b49a6c_fld3305LLR_slot0, + FIELD_dsp340050b49a6c_fld3306LLR_slot0, + FIELD_dsp340050b49a6c_fld3308LLR_slot0, + FIELD_dsp340050b49a6c_fld3310LLR_slot0, + FIELD_dsp340050b49a6c_fld3311LLR_slot0, + FIELD_dsp340050b49a6c_fld3312LLR_slot0, + FIELD_dsp340050b49a6c_fld3879LLR_slot0, + FIELD_dsp340050b49a6c_fld3881LLR_slot0, + FIELD_dsp340050b49a6c_fld3883LLR_slot0, + FIELD_dsp340050b49a6c_fld3885LLR_slot0, + FIELD_dsp340050b49a6c_fld3887LLR_slot0, + FIELD_dsp340050b49a6c_fld3888LLR_slot0, + FIELD_dsp340050b49a6c_fld3890LLR_slot0, + FIELD_dsp340050b49a6c_fld3892LLR_slot0, + FIELD_dsp340050b49a6c_fld3893LLR_slot0, + FIELD_op0_s21, + FIELD_dsp340050b49a6c_fld3313DUAL_slot2, + FIELD_dsp340050b49a6c_fld3314, + FIELD_dsp340050b49a6c_fld3315DUAL_slot2, + FIELD_dsp340050b49a6c_fld3316DUAL_slot2, + FIELD_dsp340050b49a6c_fld3317DUAL_slot2, + FIELD_dsp340050b49a6c_fld3318, + FIELD_dsp340050b49a6c_fld3319DUAL_slot2, + FIELD_dsp340050b49a6c_fld3320DUAL_slot2, + FIELD_dsp340050b49a6c_fld3321DUAL_slot2, + FIELD_dsp340050b49a6c_fld3322DUAL_slot2, + FIELD_dsp340050b49a6c_fld3323DUAL_slot2, + FIELD_dsp340050b49a6c_fld3324DUAL_slot2, + FIELD_dsp340050b49a6c_fld3325DUAL_slot2, + FIELD_dsp340050b49a6c_fld3326DUAL_slot2, + FIELD_dsp340050b49a6c_fld3327DUAL_slot2, + FIELD_dsp340050b49a6c_fld3328DUAL_slot2, + FIELD_dsp340050b49a6c_fld3329DUAL_slot2, + FIELD_dsp340050b49a6c_fld3330DUAL_slot2, + FIELD_dsp340050b49a6c_fld3331DUAL_slot2, + FIELD_dsp340050b49a6c_fld3332DUAL_slot2, + FIELD_dsp340050b49a6c_fld3333DUAL_slot2, + FIELD_dsp340050b49a6c_fld3334DUAL_slot2, + FIELD_dsp340050b49a6c_fld3335DUAL_slot2, + FIELD_dsp340050b49a6c_fld3336DUAL_slot2, + FIELD_dsp340050b49a6c_fld3337DUAL_slot2, + FIELD_dsp340050b49a6c_fld3339DUAL_slot2, + FIELD_dsp340050b49a6c_fld3340DUAL_slot2, + FIELD_dsp340050b49a6c_fld3341DUAL_slot2, + FIELD_dsp340050b49a6c_fld3342DUAL_slot2, + FIELD_dsp340050b49a6c_fld3345DUAL_slot2, + FIELD_dsp340050b49a6c_fld3347DUAL_slot2, + FIELD_dsp340050b49a6c_fld3348DUAL_slot2, + FIELD_dsp340050b49a6c_fld3349DUAL_slot2, + FIELD_dsp340050b49a6c_fld3350DUAL_slot2, + FIELD_dsp340050b49a6c_fld3353DUAL_slot2, + FIELD_dsp340050b49a6c_fld3354DUAL_slot2, + FIELD_dsp340050b49a6c_fld3356DUAL_slot2, + FIELD_dsp340050b49a6c_fld3358DUAL_slot2, + FIELD_dsp340050b49a6c_fld3360DUAL_slot2, + FIELD_dsp340050b49a6c_fld3361DUAL_slot2, + FIELD_dsp340050b49a6c_fld3362DUAL_slot2, + FIELD_dsp340050b49a6c_fld3363DUAL_slot2, + FIELD_dsp340050b49a6c_fld3364, + FIELD_dsp340050b49a6c_fld3365DUAL_slot2, + FIELD_dsp340050b49a6c_fld3366DUAL_slot2, + FIELD_dsp340050b49a6c_fld3367DUAL_slot2, + FIELD_dsp340050b49a6c_fld3368DUAL_slot2, + FIELD_dsp340050b49a6c_fld3369DUAL_slot2, + FIELD_dsp340050b49a6c_fld3370DUAL_slot2, + FIELD_dsp340050b49a6c_fld3371DUAL_slot2, + FIELD_dsp340050b49a6c_fld3372DUAL_slot2, + FIELD_dsp340050b49a6c_fld3373DUAL_slot2, + FIELD_dsp340050b49a6c_fld3374DUAL_slot2, + FIELD_dsp340050b49a6c_fld3375DUAL_slot2, + FIELD_dsp340050b49a6c_fld3376DUAL_slot2, + FIELD_dsp340050b49a6c_fld3377DUAL_slot2, + FIELD_dsp340050b49a6c_fld3378DUAL_slot2, + FIELD_dsp340050b49a6c_fld3379DUAL_slot2, + FIELD_dsp340050b49a6c_fld3380DUAL_slot2, + FIELD_dsp340050b49a6c_fld3381DUAL_slot2, + FIELD_dsp340050b49a6c_fld3382DUAL_slot2, + FIELD_dsp340050b49a6c_fld3384DUAL_slot2, + FIELD_dsp340050b49a6c_fld3385DUAL_slot2, + FIELD_dsp340050b49a6c_fld3386DUAL_slot2, + FIELD_dsp340050b49a6c_fld3387DUAL_slot2, + FIELD_dsp340050b49a6c_fld3388DUAL_slot2, + FIELD_dsp340050b49a6c_fld3390DUAL_slot2, + FIELD_dsp340050b49a6c_fld3392DUAL_slot2, + FIELD_dsp340050b49a6c_fld3394DUAL_slot2, + FIELD_dsp340050b49a6c_fld3396DUAL_slot2, + FIELD_dsp340050b49a6c_fld3397DUAL_slot2, + FIELD_dsp340050b49a6c_fld3399DUAL_slot2, + FIELD_dsp340050b49a6c_fld3401DUAL_slot2, + FIELD_dsp340050b49a6c_fld3403DUAL_slot2, + FIELD_dsp340050b49a6c_fld3404DUAL_slot2, + FIELD_dsp340050b49a6c_fld3406DUAL_slot2, + FIELD_dsp340050b49a6c_fld3407, + FIELD_dsp340050b49a6c_fld3408DUAL_slot2, + FIELD_dsp340050b49a6c_fld3410, + FIELD_dsp340050b49a6c_fld3411DUAL_slot2, + FIELD_dsp340050b49a6c_fld3412DUAL_slot2, + FIELD_dsp340050b49a6c_fld3413DUAL_slot2, + FIELD_dsp340050b49a6c_fld3414DUAL_slot2, + FIELD_dsp340050b49a6c_fld3415DUAL_slot2, + FIELD_dsp340050b49a6c_fld3416DUAL_slot2, + FIELD_dsp340050b49a6c_fld3417DUAL_slot2, + FIELD_dsp340050b49a6c_fld3418DUAL_slot2, + FIELD_dsp340050b49a6c_fld3419DUAL_slot2, + FIELD_dsp340050b49a6c_fld3420DUAL_slot2, + FIELD_dsp340050b49a6c_fld3421DUAL_slot2, + FIELD_dsp340050b49a6c_fld3422DUAL_slot2, + FIELD_dsp340050b49a6c_fld3423DUAL_slot2, + FIELD_dsp340050b49a6c_fld3424DUAL_slot2, + FIELD_dsp340050b49a6c_fld3425DUAL_slot2, + FIELD_dsp340050b49a6c_fld3426DUAL_slot2, + FIELD_dsp340050b49a6c_fld3427DUAL_slot2, + FIELD_dsp340050b49a6c_fld3428DUAL_slot2, + FIELD_dsp340050b49a6c_fld3429DUAL_slot2, + FIELD_dsp340050b49a6c_fld3430DUAL_slot2, + FIELD_dsp340050b49a6c_fld3431DUAL_slot2, + FIELD_dsp340050b49a6c_fld3432DUAL_slot2, + FIELD_dsp340050b49a6c_fld3433DUAL_slot2, + FIELD_dsp340050b49a6c_fld3434DUAL_slot2, + FIELD_dsp340050b49a6c_fld3435DUAL_slot2, + FIELD_dsp340050b49a6c_fld3436DUAL_slot2, + FIELD_dsp340050b49a6c_fld3437DUAL_slot2, + FIELD_dsp340050b49a6c_fld3438DUAL_slot2, + FIELD_dsp340050b49a6c_fld3439DUAL_slot2, + FIELD_dsp340050b49a6c_fld3440DUAL_slot2, + FIELD_dsp340050b49a6c_fld3441DUAL_slot2, + FIELD_dsp340050b49a6c_fld3442DUAL_slot2, + FIELD_dsp340050b49a6c_fld3443DUAL_slot2, + FIELD_dsp340050b49a6c_fld3444DUAL_slot2, + FIELD_dsp340050b49a6c_fld3445DUAL_slot2, + FIELD_dsp340050b49a6c_fld3446DUAL_slot2, + FIELD_dsp340050b49a6c_fld3448DUAL_slot2, + FIELD_dsp340050b49a6c_fld3450DUAL_slot2, + FIELD_dsp340050b49a6c_fld3451DUAL_slot2, + FIELD_dsp340050b49a6c_fld3453DUAL_slot2, + FIELD_dsp340050b49a6c_fld3454DUAL_slot2, + FIELD_dsp340050b49a6c_fld3456DUAL_slot2, + FIELD_dsp340050b49a6c_fld3457DUAL_slot2, + FIELD_dsp340050b49a6c_fld3458DUAL_slot2, + FIELD_dsp340050b49a6c_fld3459DUAL_slot2, + FIELD_dsp340050b49a6c_fld3460DUAL_slot2, + FIELD_dsp340050b49a6c_fld3461DUAL_slot2, + FIELD_dsp340050b49a6c_fld3462DUAL_slot2, + FIELD_dsp340050b49a6c_fld3464DUAL_slot2, + FIELD_dsp340050b49a6c_fld3465DUAL_slot2, + FIELD_dsp340050b49a6c_fld3466, + FIELD_dsp340050b49a6c_fld3467DUAL_slot2, + FIELD_dsp340050b49a6c_fld3468DUAL_slot2, + FIELD_dsp340050b49a6c_fld3469DUAL_slot2, + FIELD_dsp340050b49a6c_fld3470DUAL_slot2, + FIELD_dsp340050b49a6c_fld3471DUAL_slot2, + FIELD_dsp340050b49a6c_fld3472DUAL_slot2, + FIELD_dsp340050b49a6c_fld3473DUAL_slot2, + FIELD_dsp340050b49a6c_fld3474DUAL_slot2, + FIELD_dsp340050b49a6c_fld3475DUAL_slot2, + FIELD_dsp340050b49a6c_fld3477DUAL_slot2, + FIELD_dsp340050b49a6c_fld3478DUAL_slot2, + FIELD_dsp340050b49a6c_fld3479DUAL_slot2, + FIELD_dsp340050b49a6c_fld3480DUAL_slot2, + FIELD_dsp340050b49a6c_fld3481DUAL_slot2, + FIELD_dsp340050b49a6c_fld3482DUAL_slot2, + FIELD_dsp340050b49a6c_fld3484DUAL_slot2, + FIELD_dsp340050b49a6c_fld3894DUAL_slot2, + FIELD_dsp340050b49a6c_fld3895DUAL_slot2, + FIELD_dsp340050b49a6c_fld3896DUAL_slot2, + FIELD_dsp340050b49a6c_fld3897DUAL_slot2, + FIELD_dsp340050b49a6c_fld3898DUAL_slot2, + FIELD_dsp340050b49a6c_fld3899DUAL_slot2, + FIELD_dsp340050b49a6c_fld3900, + FIELD_dsp340050b49a6c_fld3901DUAL_slot2, + FIELD_dsp340050b49a6c_fld3903DUAL_slot2, + FIELD_dsp340050b49a6c_fld3904DUAL_slot2, + FIELD_dsp340050b49a6c_fld3905DUAL_slot2, + FIELD_dsp340050b49a6c_fld3906DUAL_slot2, + FIELD_dsp340050b49a6c_fld3907DUAL_slot2, + FIELD_dsp340050b49a6c_fld3908DUAL_slot2, + FIELD_dsp340050b49a6c_fld3909DUAL_slot2, + FIELD_dsp340050b49a6c_fld3910DUAL_slot2, + FIELD_dsp340050b49a6c_fld3913DUAL_slot2, + FIELD_dsp340050b49a6c_fld3914DUAL_slot2, + FIELD_dsp340050b49a6c_fld3916DUAL_slot2, + FIELD_dsp340050b49a6c_fld3917DUAL_slot2, + FIELD_dsp340050b49a6c_fld3918DUAL_slot2, + FIELD_dsp340050b49a6c_fld3919DUAL_slot2, + FIELD_dsp340050b49a6c_fld3920DUAL_slot2, + FIELD_dsp340050b49a6c_fld3921DUAL_slot2, + FIELD_dsp340050b49a6c_fld3922DUAL_slot2, + FIELD_dsp340050b49a6c_fld3923DUAL_slot2, + FIELD_dsp340050b49a6c_fld3924DUAL_slot2, + FIELD_dsp340050b49a6c_fld3925DUAL_slot2, + FIELD_dsp340050b49a6c_fld3927DUAL_slot2, + FIELD_dsp340050b49a6c_fld3928DUAL_slot2, + FIELD_dsp340050b49a6c_fld3929DUAL_slot2, + FIELD_dsp340050b49a6c_fld3930DUAL_slot2, + FIELD_dsp340050b49a6c_fld3931DUAL_slot2, + FIELD_dsp340050b49a6c_fld3933DUAL_slot2, + FIELD_dsp340050b49a6c_fld3934DUAL_slot2, + FIELD_dsp340050b49a6c_fld3935DUAL_slot2, + FIELD_op0_s22, + FIELD_op0_s23, + FIELD_dsp340050b49a6c_fld2057, + FIELD_dsp340050b49a6c_fld2060, + FIELD_dsp340050b49a6c_fld2066, + FIELD_dsp340050b49a6c_fld2072, + FIELD_dsp340050b49a6c_fld2079, + FIELD_dsp340050b49a6c_fld3487DUAL_slot0, + FIELD_dsp340050b49a6c_fld3488DUAL_slot0, + FIELD_dsp340050b49a6c_fld3489DUAL_slot0, + FIELD_dsp340050b49a6c_fld3490DUAL_slot0, + FIELD_dsp340050b49a6c_fld3491DUAL_slot0, + FIELD_dsp340050b49a6c_fld3492DUAL_slot0, + FIELD_dsp340050b49a6c_fld3493DUAL_slot0, + FIELD_dsp340050b49a6c_fld3494DUAL_slot0, + FIELD_dsp340050b49a6c_fld3496DUAL_slot0, + FIELD_dsp340050b49a6c_fld3497DUAL_slot0, + FIELD_dsp340050b49a6c_fld3498DUAL_slot0, + FIELD_dsp340050b49a6c_fld3499DUAL_slot0, + FIELD_dsp340050b49a6c_fld3500DUAL_slot0, + FIELD_dsp340050b49a6c_fld3502DUAL_slot0, + FIELD_dsp340050b49a6c_fld3504DUAL_slot0, + FIELD_dsp340050b49a6c_fld3505DUAL_slot0, + FIELD_dsp340050b49a6c_fld3506DUAL_slot0, + FIELD_dsp340050b49a6c_fld3507DUAL_slot0, + FIELD_dsp340050b49a6c_fld3508DUAL_slot0, + FIELD_dsp340050b49a6c_fld3509DUAL_slot0, + FIELD_dsp340050b49a6c_fld3510DUAL_slot0, + FIELD_dsp340050b49a6c_fld3511DUAL_slot0, + FIELD_dsp340050b49a6c_fld3512DUAL_slot0, + FIELD_dsp340050b49a6c_fld3513DUAL_slot0, + FIELD_dsp340050b49a6c_fld3514DUAL_slot0, + FIELD_dsp340050b49a6c_fld3515DUAL_slot0, + FIELD_dsp340050b49a6c_fld3516DUAL_slot0, + FIELD_dsp340050b49a6c_fld3517DUAL_slot0, + FIELD_dsp340050b49a6c_fld3518DUAL_slot0, + FIELD_dsp340050b49a6c_fld3519DUAL_slot0, + FIELD_dsp340050b49a6c_fld3520DUAL_slot0, + FIELD_dsp340050b49a6c_fld3522DUAL_slot0, + FIELD_dsp340050b49a6c_fld3523DUAL_slot0, + FIELD_dsp340050b49a6c_fld3524DUAL_slot0, + FIELD_dsp340050b49a6c_fld3527DUAL_slot0, + FIELD_dsp340050b49a6c_fld3529DUAL_slot0, + FIELD_dsp340050b49a6c_fld3530DUAL_slot0, + FIELD_dsp340050b49a6c_fld3531, + FIELD_dsp340050b49a6c_fld3532DUAL_slot0, + FIELD_dsp340050b49a6c_fld3533DUAL_slot0, + FIELD_dsp340050b49a6c_fld3535DUAL_slot0, + FIELD_dsp340050b49a6c_fld3536DUAL_slot0, + FIELD_dsp340050b49a6c_fld3537DUAL_slot0, + FIELD_dsp340050b49a6c_fld3538DUAL_slot0, + FIELD_dsp340050b49a6c_fld3539DUAL_slot0, + FIELD_dsp340050b49a6c_fld3541DUAL_slot0, + FIELD_dsp340050b49a6c_fld3542DUAL_slot0, + FIELD_dsp340050b49a6c_fld3543DUAL_slot0, + FIELD_dsp340050b49a6c_fld3544DUAL_slot0, + FIELD_dsp340050b49a6c_fld3545DUAL_slot0, + FIELD_dsp340050b49a6c_fld3546DUAL_slot0, + FIELD_dsp340050b49a6c_fld3547DUAL_slot0, + FIELD_dsp340050b49a6c_fld3548DUAL_slot0, + FIELD_dsp340050b49a6c_fld3549DUAL_slot0, + FIELD_dsp340050b49a6c_fld3550DUAL_slot0, + FIELD_dsp340050b49a6c_fld3551DUAL_slot0, + FIELD_dsp340050b49a6c_fld3552, + FIELD_dsp340050b49a6c_fld3553DUAL_slot0, + FIELD_dsp340050b49a6c_fld3554DUAL_slot0, + FIELD_dsp340050b49a6c_fld3555DUAL_slot0, + FIELD_dsp340050b49a6c_fld3556DUAL_slot0, + FIELD_dsp340050b49a6c_fld3557DUAL_slot0, + FIELD_dsp340050b49a6c_fld3558DUAL_slot0, + FIELD_dsp340050b49a6c_fld3559DUAL_slot0, + FIELD_dsp340050b49a6c_fld3560DUAL_slot0, + FIELD_dsp340050b49a6c_fld3562DUAL_slot0, + FIELD_dsp340050b49a6c_fld3563DUAL_slot0, + FIELD_dsp340050b49a6c_fld3564DUAL_slot0, + FIELD_dsp340050b49a6c_fld3565DUAL_slot0, + FIELD_dsp340050b49a6c_fld3566DUAL_slot0, + FIELD_dsp340050b49a6c_fld3567DUAL_slot0, + FIELD_dsp340050b49a6c_fld3568DUAL_slot0, + FIELD_dsp340050b49a6c_fld3569DUAL_slot0, + FIELD_dsp340050b49a6c_fld3570DUAL_slot0, + FIELD_dsp340050b49a6c_fld3571DUAL_slot0, + FIELD_dsp340050b49a6c_fld3572DUAL_slot0, + FIELD_dsp340050b49a6c_fld3573DUAL_slot0, + FIELD_dsp340050b49a6c_fld3574DUAL_slot0, + FIELD_dsp340050b49a6c_fld3575DUAL_slot0, + FIELD_dsp340050b49a6c_fld3576DUAL_slot0, + FIELD_dsp340050b49a6c_fld3577DUAL_slot0, + FIELD_dsp340050b49a6c_fld3578DUAL_slot0, + FIELD_dsp340050b49a6c_fld3579DUAL_slot0, + FIELD_dsp340050b49a6c_fld3580DUAL_slot0, + FIELD_dsp340050b49a6c_fld3581DUAL_slot0, + FIELD_dsp340050b49a6c_fld3582DUAL_slot0, + FIELD_dsp340050b49a6c_fld3583DUAL_slot0, + FIELD_dsp340050b49a6c_fld3584, + FIELD_dsp340050b49a6c_fld3585DUAL_slot0, + FIELD_dsp340050b49a6c_fld3587DUAL_slot0, + FIELD_dsp340050b49a6c_fld3588DUAL_slot0, + FIELD_dsp340050b49a6c_fld3589DUAL_slot0, + FIELD_dsp340050b49a6c_fld3590DUAL_slot0, + FIELD_dsp340050b49a6c_fld3591DUAL_slot0, + FIELD_dsp340050b49a6c_fld3592DUAL_slot0, + FIELD_dsp340050b49a6c_fld3593DUAL_slot0, + FIELD_dsp340050b49a6c_fld3594DUAL_slot0, + FIELD_dsp340050b49a6c_fld3595DUAL_slot0, + FIELD_dsp340050b49a6c_fld3596DUAL_slot0, + FIELD_dsp340050b49a6c_fld3597DUAL_slot0, + FIELD_dsp340050b49a6c_fld3598DUAL_slot0, + FIELD_dsp340050b49a6c_fld3599DUAL_slot0, + FIELD_dsp340050b49a6c_fld3600DUAL_slot0, + FIELD_dsp340050b49a6c_fld3601DUAL_slot0, + FIELD_dsp340050b49a6c_fld3602, + FIELD_dsp340050b49a6c_fld3603DUAL_slot0, + FIELD_dsp340050b49a6c_fld3604DUAL_slot0, + FIELD_dsp340050b49a6c_fld3606DUAL_slot0, + FIELD_dsp340050b49a6c_fld3607DUAL_slot0, + FIELD_dsp340050b49a6c_fld3608DUAL_slot0, + FIELD_dsp340050b49a6c_fld3609DUAL_slot0, + FIELD_dsp340050b49a6c_fld3610, + FIELD_dsp340050b49a6c_fld3611DUAL_slot0, + FIELD_dsp340050b49a6c_fld3612DUAL_slot0, + FIELD_dsp340050b49a6c_fld3613DUAL_slot0, + FIELD_dsp340050b49a6c_fld3614DUAL_slot0, + FIELD_dsp340050b49a6c_fld3615DUAL_slot0, + FIELD_dsp340050b49a6c_fld3616DUAL_slot0, + FIELD_dsp340050b49a6c_fld3618DUAL_slot0, + FIELD_dsp340050b49a6c_fld3619, + FIELD_dsp340050b49a6c_fld3620DUAL_slot0, + FIELD_dsp340050b49a6c_fld3621DUAL_slot0, + FIELD_dsp340050b49a6c_fld3622DUAL_slot0, + FIELD_dsp340050b49a6c_fld3623DUAL_slot0, + FIELD_dsp340050b49a6c_fld3624DUAL_slot0, + FIELD_dsp340050b49a6c_fld3625DUAL_slot0, + FIELD_dsp340050b49a6c_fld3626DUAL_slot0, + FIELD_dsp340050b49a6c_fld3936DUAL_slot0, + FIELD_dsp340050b49a6c_fld3937DUAL_slot0, + FIELD_dsp340050b49a6c_fld3938DUAL_slot0, + FIELD_dsp340050b49a6c_fld3939DUAL_slot0, + FIELD_dsp340050b49a6c_fld3940DUAL_slot0, + FIELD_dsp340050b49a6c_fld3941DUAL_slot0, + FIELD_dsp340050b49a6c_fld3943DUAL_slot0, + FIELD_dsp340050b49a6c_fld3945DUAL_slot0, + FIELD_dsp340050b49a6c_fld3946DUAL_slot0, + FIELD_dsp340050b49a6c_fld3947DUAL_slot0, + FIELD_dsp340050b49a6c_fld3949DUAL_slot0, + FIELD_dsp340050b49a6c_fld3950DUAL_slot0, + FIELD_dsp340050b49a6c_fld3951DUAL_slot0, + FIELD_dsp340050b49a6c_fld3952DUAL_slot0, + FIELD_dsp340050b49a6c_fld3954DUAL_slot0, + FIELD_dsp340050b49a6c_fld3957DUAL_slot0, + FIELD_dsp340050b49a6c_fld3958DUAL_slot0, + FIELD_dsp340050b49a6c_fld3959DUAL_slot0, + FIELD_dsp340050b49a6c_fld3960DUAL_slot0, + FIELD_dsp340050b49a6c_fld3961DUAL_slot0, + FIELD__ar0, + FIELD__ar4, + FIELD__ar8, + FIELD__ar12, + FIELD__bt16, + FIELD__bs16, + FIELD__br16, + FIELD__brall +}; + + +/* Functional units. */ + +static xtensa_funcUnit_internal funcUnits[] = { + +}; + + +/* Register files. */ + +enum xtensa_regfile_id { + REGFILE_AR, + REGFILE_BR, + REGFILE_FR, + REGFILE_ACU, + REGFILE_CM, + REGFILE_PQ, + REGFILE_BR2, + REGFILE_BR4, + REGFILE_BR8, + REGFILE_BR16 +}; + +static xtensa_regfile_internal regfiles[] = { + { "AR", "a", REGFILE_AR, 32, 32 }, + { "BR", "b", REGFILE_BR, 1, 16 }, + { "FR", "f", REGFILE_FR, 32, 16 }, + { "ACU", "ACU", REGFILE_ACU, 320, 8 }, + { "CM", "CM", REGFILE_CM, 128, 16 }, + { "PQ", "PQ", REGFILE_PQ, 256, 16 }, + { "BR2", "b", REGFILE_BR, 2, 8 }, + { "BR4", "b", REGFILE_BR, 4, 4 }, + { "BR8", "b", REGFILE_BR, 8, 2 }, + { "BR16", "b", REGFILE_BR, 16, 1 } +}; + + +/* Interfaces. */ + +static xtensa_interface_internal interfaces[] = { + { "INQ0_32_Empty", 1, 0, 0, 'i' }, + { "INQ0_32", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 0, 'i' }, + { "INQ0_32_NOTRDY", 1, 0, 0, 'i' }, + { "INQ0_32_KILL", 1, 0, 0, 'o' }, + { "INQ1_32_Empty", 1, 0, 1, 'i' }, + { "INQ1_32", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 1, 'i' }, + { "INQ1_32_NOTRDY", 1, 0, 1, 'i' }, + { "INQ1_32_KILL", 1, 0, 1, 'o' }, + { "INQ2_32_Empty", 1, 0, 2, 'i' }, + { "INQ2_32", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 2, 'i' }, + { "INQ2_32_NOTRDY", 1, 0, 2, 'i' }, + { "INQ2_32_KILL", 1, 0, 2, 'o' }, + { "INQ3_32_Empty", 1, 0, 3, 'i' }, + { "INQ3_32", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 3, 'i' }, + { "INQ3_32_NOTRDY", 1, 0, 3, 'i' }, + { "INQ3_32_KILL", 1, 0, 3, 'o' }, + { "OUTQ0_32_Full", 1, 0, 4, 'i' }, + { "OUTQ0_32", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 4, 'o' }, + { "OUTQ0_32_NOTRDY", 1, 0, 4, 'i' }, + { "OUTQ0_32_KILL", 1, 0, 4, 'o' }, + { "OUTQ1_32_Full", 1, 0, 5, 'i' }, + { "OUTQ1_32", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 5, 'o' }, + { "OUTQ1_32_NOTRDY", 1, 0, 5, 'i' }, + { "OUTQ1_32_KILL", 1, 0, 5, 'o' }, + { "OUTQ2_32_Full", 1, 0, 6, 'i' }, + { "OUTQ2_32", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 6, 'o' }, + { "OUTQ2_32_NOTRDY", 1, 0, 6, 'i' }, + { "OUTQ2_32_KILL", 1, 0, 6, 'o' }, + { "OUTQ3_32_Full", 1, 0, 7, 'i' }, + { "OUTQ3_32", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 7, 'o' }, + { "OUTQ3_32_NOTRDY", 1, 0, 7, 'i' }, + { "OUTQ3_32_KILL", 1, 0, 7, 'o' }, + { "OUTQ4_32_Full", 1, 0, 8, 'i' }, + { "OUTQ4_32", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 8, 'o' }, + { "OUTQ4_32_NOTRDY", 1, 0, 8, 'i' }, + { "OUTQ4_32_KILL", 1, 0, 8, 'o' }, + { "OUTQ5_32_Full", 1, 0, 9, 'i' }, + { "OUTQ5_32", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 9, 'o' }, + { "OUTQ5_32_NOTRDY", 1, 0, 9, 'i' }, + { "OUTQ5_32_KILL", 1, 0, 9, 'o' }, + { "SIGNALQ_Full", 1, 0, 10, 'i' }, + { "SIGNALQ", 32, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 10, 'o' }, + { "SIGNALQ_NOTRDY", 1, 0, 10, 'i' }, + { "SIGNALQ_KILL", 1, 0, 10, 'o' }, + { "INQ0_128_Empty", 1, 0, 11, 'i' }, + { "INQ0_128", 128, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 11, 'i' }, + { "INQ0_128_NOTRDY", 1, 0, 11, 'i' }, + { "INQ0_128_KILL", 1, 0, 11, 'o' }, + { "INQ1_128_Empty", 1, 0, 12, 'i' }, + { "INQ1_128", 128, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 12, 'i' }, + { "INQ1_128_NOTRDY", 1, 0, 12, 'i' }, + { "INQ1_128_KILL", 1, 0, 12, 'o' }, + { "INQ2_128_Empty", 1, 0, 13, 'i' }, + { "INQ2_128", 128, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 13, 'i' }, + { "INQ2_128_NOTRDY", 1, 0, 13, 'i' }, + { "INQ2_128_KILL", 1, 0, 13, 'o' }, + { "INQ3_128_Empty", 1, 0, 14, 'i' }, + { "INQ3_128", 128, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 14, 'i' }, + { "INQ3_128_NOTRDY", 1, 0, 14, 'i' }, + { "INQ3_128_KILL", 1, 0, 14, 'o' }, + { "INQ4_128_Empty", 1, 0, 15, 'i' }, + { "INQ4_128", 128, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 15, 'i' }, + { "INQ4_128_NOTRDY", 1, 0, 15, 'i' }, + { "INQ4_128_KILL", 1, 0, 15, 'o' }, + { "INQ5_128_Empty", 1, 0, 16, 'i' }, + { "INQ5_128", 128, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 16, 'i' }, + { "INQ5_128_NOTRDY", 1, 0, 16, 'i' }, + { "INQ5_128_KILL", 1, 0, 16, 'o' }, + { "OUTQ0_128_Full", 1, 0, 17, 'i' }, + { "OUTQ0_128", 128, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 17, 'o' }, + { "OUTQ0_128_NOTRDY", 1, 0, 17, 'i' }, + { "OUTQ0_128_KILL", 1, 0, 17, 'o' }, + { "OUTQ1_128_Full", 1, 0, 18, 'i' }, + { "OUTQ1_128", 128, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 18, 'o' }, + { "OUTQ1_128_NOTRDY", 1, 0, 18, 'i' }, + { "OUTQ1_128_KILL", 1, 0, 18, 'o' }, + { "OUTQ2_128_Full", 1, 0, 19, 'i' }, + { "OUTQ2_128", 128, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 19, 'o' }, + { "OUTQ2_128_NOTRDY", 1, 0, 19, 'i' }, + { "OUTQ2_128_KILL", 1, 0, 19, 'o' }, + { "OUTQ3_128_Full", 1, 0, 20, 'i' }, + { "OUTQ3_128", 128, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 20, 'o' }, + { "OUTQ3_128_NOTRDY", 1, 0, 20, 'i' }, + { "OUTQ3_128_KILL", 1, 0, 20, 'o' }, + { "OUTQ4_128_Full", 1, 0, 21, 'i' }, + { "OUTQ4_128", 128, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 21, 'o' }, + { "OUTQ4_128_NOTRDY", 1, 0, 21, 'i' }, + { "OUTQ4_128_KILL", 1, 0, 21, 'o' }, + { "OUTQ5_128_Full", 1, 0, 22, 'i' }, + { "OUTQ5_128", 128, XTENSA_INTERFACE_HAS_SIDE_EFFECT, 22, 'o' }, + { "OUTQ5_128_NOTRDY", 1, 0, 22, 'i' }, + { "OUTQ5_128_KILL", 1, 0, 22, 'o' }, + { "IMPWIRE", 32, 0, 23, 'i' }, + { "LU128_Out", 128, 0, 24, 'o' }, + { "LU128_In", 128, 0, 25, 'i' } +}; + +enum xtensa_interface_id { + INTERFACE_INQ0_32_Empty, + INTERFACE_INQ0_32, + INTERFACE_INQ0_32_NOTRDY, + INTERFACE_INQ0_32_KILL, + INTERFACE_INQ1_32_Empty, + INTERFACE_INQ1_32, + INTERFACE_INQ1_32_NOTRDY, + INTERFACE_INQ1_32_KILL, + INTERFACE_INQ2_32_Empty, + INTERFACE_INQ2_32, + INTERFACE_INQ2_32_NOTRDY, + INTERFACE_INQ2_32_KILL, + INTERFACE_INQ3_32_Empty, + INTERFACE_INQ3_32, + INTERFACE_INQ3_32_NOTRDY, + INTERFACE_INQ3_32_KILL, + INTERFACE_OUTQ0_32_Full, + INTERFACE_OUTQ0_32, + INTERFACE_OUTQ0_32_NOTRDY, + INTERFACE_OUTQ0_32_KILL, + INTERFACE_OUTQ1_32_Full, + INTERFACE_OUTQ1_32, + INTERFACE_OUTQ1_32_NOTRDY, + INTERFACE_OUTQ1_32_KILL, + INTERFACE_OUTQ2_32_Full, + INTERFACE_OUTQ2_32, + INTERFACE_OUTQ2_32_NOTRDY, + INTERFACE_OUTQ2_32_KILL, + INTERFACE_OUTQ3_32_Full, + INTERFACE_OUTQ3_32, + INTERFACE_OUTQ3_32_NOTRDY, + INTERFACE_OUTQ3_32_KILL, + INTERFACE_OUTQ4_32_Full, + INTERFACE_OUTQ4_32, + INTERFACE_OUTQ4_32_NOTRDY, + INTERFACE_OUTQ4_32_KILL, + INTERFACE_OUTQ5_32_Full, + INTERFACE_OUTQ5_32, + INTERFACE_OUTQ5_32_NOTRDY, + INTERFACE_OUTQ5_32_KILL, + INTERFACE_SIGNALQ_Full, + INTERFACE_SIGNALQ, + INTERFACE_SIGNALQ_NOTRDY, + INTERFACE_SIGNALQ_KILL, + INTERFACE_INQ0_128_Empty, + INTERFACE_INQ0_128, + INTERFACE_INQ0_128_NOTRDY, + INTERFACE_INQ0_128_KILL, + INTERFACE_INQ1_128_Empty, + INTERFACE_INQ1_128, + INTERFACE_INQ1_128_NOTRDY, + INTERFACE_INQ1_128_KILL, + INTERFACE_INQ2_128_Empty, + INTERFACE_INQ2_128, + INTERFACE_INQ2_128_NOTRDY, + INTERFACE_INQ2_128_KILL, + INTERFACE_INQ3_128_Empty, + INTERFACE_INQ3_128, + INTERFACE_INQ3_128_NOTRDY, + INTERFACE_INQ3_128_KILL, + INTERFACE_INQ4_128_Empty, + INTERFACE_INQ4_128, + INTERFACE_INQ4_128_NOTRDY, + INTERFACE_INQ4_128_KILL, + INTERFACE_INQ5_128_Empty, + INTERFACE_INQ5_128, + INTERFACE_INQ5_128_NOTRDY, + INTERFACE_INQ5_128_KILL, + INTERFACE_OUTQ0_128_Full, + INTERFACE_OUTQ0_128, + INTERFACE_OUTQ0_128_NOTRDY, + INTERFACE_OUTQ0_128_KILL, + INTERFACE_OUTQ1_128_Full, + INTERFACE_OUTQ1_128, + INTERFACE_OUTQ1_128_NOTRDY, + INTERFACE_OUTQ1_128_KILL, + INTERFACE_OUTQ2_128_Full, + INTERFACE_OUTQ2_128, + INTERFACE_OUTQ2_128_NOTRDY, + INTERFACE_OUTQ2_128_KILL, + INTERFACE_OUTQ3_128_Full, + INTERFACE_OUTQ3_128, + INTERFACE_OUTQ3_128_NOTRDY, + INTERFACE_OUTQ3_128_KILL, + INTERFACE_OUTQ4_128_Full, + INTERFACE_OUTQ4_128, + INTERFACE_OUTQ4_128_NOTRDY, + INTERFACE_OUTQ4_128_KILL, + INTERFACE_OUTQ5_128_Full, + INTERFACE_OUTQ5_128, + INTERFACE_OUTQ5_128_NOTRDY, + INTERFACE_OUTQ5_128_KILL, + INTERFACE_IMPWIRE, + INTERFACE_LU128_Out, + INTERFACE_LU128_In +}; + + +/* Constant tables. */ + +/* constant table ai4c */ +static const unsigned CONST_TBL_ai4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0x9, + 0xa, + 0xb, + 0xc, + 0xd, + 0xe, + 0xf, + 0 +}; + +/* constant table b4c */ +static const unsigned CONST_TBL_b4c_0[] = { + 0xffffffff, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table b4cu */ +static const unsigned CONST_TBL_b4cu_0[] = { + 0x8000, + 0x10000, + 0x2, + 0x3, + 0x4, + 0x5, + 0x6, + 0x7, + 0x8, + 0xa, + 0xc, + 0x10, + 0x20, + 0x40, + 0x80, + 0x100, + 0 +}; + +/* constant table LLR_CONSTELLATION_TABLE */ +static const unsigned CONST_TBL_LLR_CONSTELLATION_TABLE_0[] = { + 0x1 & 0xf, + 0x2 & 0xf, + 0x8 & 0xf, + 0x4 & 0xf, + 0x8 & 0xf, + 0x6 & 0xf, + 0x8 & 0xf, + 0x8 & 0xf, + 0 +}; + + +/* Instruction operands. */ + +static int +Operand_soffsetx4_decode (uint32 *valp) +{ + unsigned soffsetx4_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); + *valp = soffsetx4_0; + return 0; +} + +static int +Operand_soffsetx4_encode (uint32 *valp) +{ + unsigned offset_0, soffsetx4_0; + soffsetx4_0 = *valp; + offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffsetx4_ator (uint32 *valp, uint32 pc) +{ + *valp -= (pc & ~0x3); + return 0; +} + +static int +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += (pc & ~0x3); + return 0; +} + +static int +Operand_uimm12x8_decode (uint32 *valp) +{ + unsigned uimm12x8_0, imm12_0; + imm12_0 = *valp & 0xfff; + uimm12x8_0 = imm12_0 << 3; + *valp = uimm12x8_0; + return 0; +} + +static int +Operand_uimm12x8_encode (uint32 *valp) +{ + unsigned imm12_0, uimm12x8_0; + uimm12x8_0 = *valp; + imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); + *valp = imm12_0; + return 0; +} + +static int +Operand_simm4_decode (uint32 *valp) +{ + unsigned simm4_0, mn_0; + mn_0 = *valp & 0xf; + simm4_0 = ((int) mn_0 << 28) >> 28; + *valp = simm4_0; + return 0; +} + +static int +Operand_simm4_encode (uint32 *valp) +{ + unsigned mn_0, simm4_0; + simm4_0 = *valp; + mn_0 = (simm4_0 & 0xf); + *valp = mn_0; + return 0; +} + +static int +Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_arr_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_art_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar0_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar4_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar8_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ar12_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_ars_entry_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x1f) != 0; + return error; +} + +static int +Operand_immrx4_decode (uint32 *valp) +{ + unsigned immrx4_0, r_0; + r_0 = *valp & 0xf; + immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; + *valp = immrx4_0; + return 0; +} + +static int +Operand_immrx4_encode (uint32 *valp) +{ + unsigned r_0, immrx4_0; + immrx4_0 = *valp; + r_0 = ((immrx4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_lsi4x4_decode (uint32 *valp) +{ + unsigned lsi4x4_0, r_0; + r_0 = *valp & 0xf; + lsi4x4_0 = r_0 << 2; + *valp = lsi4x4_0; + return 0; +} + +static int +Operand_lsi4x4_encode (uint32 *valp) +{ + unsigned r_0, lsi4x4_0; + lsi4x4_0 = *valp; + r_0 = ((lsi4x4_0 >> 2) & 0xf); + *valp = r_0; + return 0; +} + +static int +Operand_simm7_decode (uint32 *valp) +{ + unsigned simm7_0, imm7_0; + imm7_0 = *valp & 0x7f; + simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; + *valp = simm7_0; + return 0; +} + +static int +Operand_simm7_encode (uint32 *valp) +{ + unsigned imm7_0, simm7_0; + simm7_0 = *valp; + imm7_0 = (simm7_0 & 0x7f); + *valp = imm7_0; + return 0; +} + +static int +Operand_uimm6_decode (uint32 *valp) +{ + unsigned uimm6_0, imm6_0; + imm6_0 = *valp & 0x3f; + uimm6_0 = 0x4 + (((0) << 6) | imm6_0); + *valp = uimm6_0; + return 0; +} + +static int +Operand_uimm6_encode (uint32 *valp) +{ + unsigned imm6_0, uimm6_0; + uimm6_0 = *valp; + imm6_0 = (uimm6_0 - 0x4) & 0x3f; + *valp = imm6_0; + return 0; +} + +static int +Operand_uimm6_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_uimm6_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ai4const_decode (uint32 *valp) +{ + unsigned ai4const_0, t_0; + t_0 = *valp & 0xf; + ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; + *valp = ai4const_0; + return 0; +} + +static int +Operand_ai4const_encode (uint32 *valp) +{ + unsigned t_0, ai4const_0; + ai4const_0 = *valp; + switch (ai4const_0) + { + case 0xffffffff: t_0 = 0; break; + case 0x1: t_0 = 0x1; break; + case 0x2: t_0 = 0x2; break; + case 0x3: t_0 = 0x3; break; + case 0x4: t_0 = 0x4; break; + case 0x5: t_0 = 0x5; break; + case 0x6: t_0 = 0x6; break; + case 0x7: t_0 = 0x7; break; + case 0x8: t_0 = 0x8; break; + case 0x9: t_0 = 0x9; break; + case 0xa: t_0 = 0xa; break; + case 0xb: t_0 = 0xb; break; + case 0xc: t_0 = 0xc; break; + case 0xd: t_0 = 0xd; break; + case 0xe: t_0 = 0xe; break; + default: t_0 = 0xf; break; + } + *valp = t_0; + return 0; +} + +static int +Operand_b4const_decode (uint32 *valp) +{ + unsigned b4const_0, r_0; + r_0 = *valp & 0xf; + b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; + *valp = b4const_0; + return 0; +} + +static int +Operand_b4const_encode (uint32 *valp) +{ + unsigned r_0, b4const_0; + b4const_0 = *valp; + switch (b4const_0) + { + case 0xffffffff: r_0 = 0; break; + case 0x1: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_b4constu_decode (uint32 *valp) +{ + unsigned b4constu_0, r_0; + r_0 = *valp & 0xf; + b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; + *valp = b4constu_0; + return 0; +} + +static int +Operand_b4constu_encode (uint32 *valp) +{ + unsigned r_0, b4constu_0; + b4constu_0 = *valp; + switch (b4constu_0) + { + case 0x8000: r_0 = 0; break; + case 0x10000: r_0 = 0x1; break; + case 0x2: r_0 = 0x2; break; + case 0x3: r_0 = 0x3; break; + case 0x4: r_0 = 0x4; break; + case 0x5: r_0 = 0x5; break; + case 0x6: r_0 = 0x6; break; + case 0x7: r_0 = 0x7; break; + case 0x8: r_0 = 0x8; break; + case 0xa: r_0 = 0x9; break; + case 0xc: r_0 = 0xa; break; + case 0x10: r_0 = 0xb; break; + case 0x20: r_0 = 0xc; break; + case 0x40: r_0 = 0xd; break; + case 0x80: r_0 = 0xe; break; + default: r_0 = 0xf; break; + } + *valp = r_0; + return 0; +} + +static int +Operand_uimm8_decode (uint32 *valp) +{ + unsigned uimm8_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8_0 = imm8_0; + *valp = uimm8_0; + return 0; +} + +static int +Operand_uimm8_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8_0; + uimm8_0 = *valp; + imm8_0 = (uimm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x2_decode (uint32 *valp) +{ + unsigned uimm8x2_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x2_0 = imm8_0 << 1; + *valp = uimm8x2_0; + return 0; +} + +static int +Operand_uimm8x2_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x2_0; + uimm8x2_0 = *valp; + imm8_0 = ((uimm8x2_0 >> 1) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm8x4_decode (uint32 *valp) +{ + unsigned uimm8x4_0, imm8_0; + imm8_0 = *valp & 0xff; + uimm8x4_0 = imm8_0 << 2; + *valp = uimm8x4_0; + return 0; +} + +static int +Operand_uimm8x4_encode (uint32 *valp) +{ + unsigned imm8_0, uimm8x4_0; + uimm8x4_0 = *valp; + imm8_0 = ((uimm8x4_0 >> 2) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_uimm4x16_decode (uint32 *valp) +{ + unsigned uimm4x16_0, op2_0; + op2_0 = *valp & 0xf; + uimm4x16_0 = op2_0 << 4; + *valp = uimm4x16_0; + return 0; +} + +static int +Operand_uimm4x16_encode (uint32 *valp) +{ + unsigned op2_0, uimm4x16_0; + uimm4x16_0 = *valp; + op2_0 = ((uimm4x16_0 >> 4) & 0xf); + *valp = op2_0; + return 0; +} + +static int +Operand_simm8_decode (uint32 *valp) +{ + unsigned simm8_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8_0 = ((int) imm8_0 << 24) >> 24; + *valp = simm8_0; + return 0; +} + +static int +Operand_simm8_encode (uint32 *valp) +{ + unsigned imm8_0, simm8_0; + simm8_0 = *valp; + imm8_0 = (simm8_0 & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm8x256_decode (uint32 *valp) +{ + unsigned simm8x256_0, imm8_0; + imm8_0 = *valp & 0xff; + simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; + *valp = simm8x256_0; + return 0; +} + +static int +Operand_simm8x256_encode (uint32 *valp) +{ + unsigned imm8_0, simm8x256_0; + simm8x256_0 = *valp; + imm8_0 = ((simm8x256_0 >> 8) & 0xff); + *valp = imm8_0; + return 0; +} + +static int +Operand_simm12b_decode (uint32 *valp) +{ + unsigned simm12b_0, imm12b_0; + imm12b_0 = *valp & 0xfff; + simm12b_0 = ((int) imm12b_0 << 20) >> 20; + *valp = simm12b_0; + return 0; +} + +static int +Operand_simm12b_encode (uint32 *valp) +{ + unsigned imm12b_0, simm12b_0; + simm12b_0 = *valp; + imm12b_0 = (simm12b_0 & 0xfff); + *valp = imm12b_0; + return 0; +} + +static int +Operand_msalp32_decode (uint32 *valp) +{ + unsigned msalp32_0, sal_0; + sal_0 = *valp & 0x1f; + msalp32_0 = 0x20 - sal_0; + *valp = msalp32_0; + return 0; +} + +static int +Operand_msalp32_encode (uint32 *valp) +{ + unsigned sal_0, msalp32_0; + msalp32_0 = *valp; + sal_0 = (0x20 - msalp32_0) & 0x1f; + *valp = sal_0; + return 0; +} + +static int +Operand_op2p1_decode (uint32 *valp) +{ + unsigned op2p1_0, op2_0; + op2_0 = *valp & 0xf; + op2p1_0 = op2_0 + 0x1; + *valp = op2p1_0; + return 0; +} + +static int +Operand_op2p1_encode (uint32 *valp) +{ + unsigned op2_0, op2p1_0; + op2p1_0 = *valp; + op2_0 = (op2p1_0 - 0x1) & 0xf; + *valp = op2_0; + return 0; +} + +static int +Operand_label8_decode (uint32 *valp) +{ + unsigned label8_0, imm8_0; + imm8_0 = *valp & 0xff; + label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); + *valp = label8_0; + return 0; +} + +static int +Operand_label8_encode (uint32 *valp) +{ + unsigned imm8_0, label8_0; + label8_0 = *valp; + imm8_0 = (label8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_label8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_ulabel8_decode (uint32 *valp) +{ + unsigned ulabel8_0, imm8_0; + imm8_0 = *valp & 0xff; + ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); + *valp = ulabel8_0; + return 0; +} + +static int +Operand_ulabel8_encode (uint32 *valp) +{ + unsigned imm8_0, ulabel8_0; + ulabel8_0 = *valp; + imm8_0 = (ulabel8_0 - 0x4) & 0xff; + *valp = imm8_0; + return 0; +} + +static int +Operand_ulabel8_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_label12_decode (uint32 *valp) +{ + unsigned label12_0, imm12_0; + imm12_0 = *valp & 0xfff; + label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); + *valp = label12_0; + return 0; +} + +static int +Operand_label12_encode (uint32 *valp) +{ + unsigned imm12_0, label12_0; + label12_0 = *valp; + imm12_0 = (label12_0 - 0x4) & 0xfff; + *valp = imm12_0; + return 0; +} + +static int +Operand_label12_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_label12_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_soffset_decode (uint32 *valp) +{ + unsigned soffset_0, offset_0; + offset_0 = *valp & 0x3ffff; + soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); + *valp = soffset_0; + return 0; +} + +static int +Operand_soffset_encode (uint32 *valp) +{ + unsigned offset_0, soffset_0; + soffset_0 = *valp; + offset_0 = (soffset_0 - 0x4) & 0x3ffff; + *valp = offset_0; + return 0; +} + +static int +Operand_soffset_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_soffset_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_uimm16x4_decode (uint32 *valp) +{ + unsigned uimm16x4_0, imm16_0; + imm16_0 = *valp & 0xffff; + uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; + *valp = uimm16x4_0; + return 0; +} + +static int +Operand_uimm16x4_encode (uint32 *valp) +{ + unsigned imm16_0, uimm16x4_0; + uimm16x4_0 = *valp; + imm16_0 = (uimm16x4_0 >> 2) & 0xffff; + *valp = imm16_0; + return 0; +} + +static int +Operand_uimm16x4_ator (uint32 *valp, uint32 pc) +{ + *valp -= ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) +{ + *valp += ((pc + 3) & ~0x3); + return 0; +} + +static int +Operand_immt_decode (uint32 *valp) +{ + unsigned immt_0, t_0; + t_0 = *valp & 0xf; + immt_0 = t_0; + *valp = immt_0; + return 0; +} + +static int +Operand_immt_encode (uint32 *valp) +{ + unsigned t_0, immt_0; + immt_0 = *valp; + t_0 = immt_0 & 0xf; + *valp = t_0; + return 0; +} + +static int +Operand_imms_decode (uint32 *valp) +{ + unsigned imms_0, s_0; + s_0 = *valp & 0xf; + imms_0 = s_0; + *valp = imms_0; + return 0; +} + +static int +Operand_imms_encode (uint32 *valp) +{ + unsigned s_0, imms_0; + imms_0 = *valp; + s_0 = imms_0 & 0xf; + *valp = s_0; + return 0; +} + +static int +Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_bt_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_bs_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_br_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_bt2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +Operand_bt2_encode (uint32 *valp) +{ + int error; + error = (*valp & ~(0x7 << 1)) != 0; + *valp = *valp >> 1; + return error; +} + +static int +Operand_bs2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +Operand_bs2_encode (uint32 *valp) +{ + int error; + error = (*valp & ~(0x7 << 1)) != 0; + *valp = *valp >> 1; + return error; +} + +static int +Operand_br2_decode (uint32 *valp) +{ + *valp = *valp << 1; + return 0; +} + +static int +Operand_br2_encode (uint32 *valp) +{ + int error; + error = (*valp & ~(0x7 << 1)) != 0; + *valp = *valp >> 1; + return error; +} + +static int +Operand_bt4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +Operand_bt4_encode (uint32 *valp) +{ + int error; + error = (*valp & ~(0x3 << 2)) != 0; + *valp = *valp >> 2; + return error; +} + +static int +Operand_bs4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +Operand_bs4_encode (uint32 *valp) +{ + int error; + error = (*valp & ~(0x3 << 2)) != 0; + *valp = *valp >> 2; + return error; +} + +static int +Operand_br4_decode (uint32 *valp) +{ + *valp = *valp << 2; + return 0; +} + +static int +Operand_br4_encode (uint32 *valp) +{ + int error; + error = (*valp & ~(0x3 << 2)) != 0; + *valp = *valp >> 2; + return error; +} + +static int +Operand_bt8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +Operand_bt8_encode (uint32 *valp) +{ + int error; + error = (*valp & ~(0x1 << 3)) != 0; + *valp = *valp >> 3; + return error; +} + +static int +Operand_bs8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +Operand_bs8_encode (uint32 *valp) +{ + int error; + error = (*valp & ~(0x1 << 3)) != 0; + *valp = *valp >> 3; + return error; +} + +static int +Operand_br8_decode (uint32 *valp) +{ + *valp = *valp << 3; + return 0; +} + +static int +Operand_br8_encode (uint32 *valp) +{ + int error; + error = (*valp & ~(0x1 << 3)) != 0; + *valp = *valp >> 3; + return error; +} + +static int +Operand_bt16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +Operand_bt16_encode (uint32 *valp) +{ + int error; + error = (*valp & ~(0 << 4)) != 0; + *valp = *valp >> 4; + return error; +} + +static int +Operand_bs16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +Operand_bs16_encode (uint32 *valp) +{ + int error; + error = (*valp & ~(0 << 4)) != 0; + *valp = *valp >> 4; + return error; +} + +static int +Operand_br16_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +Operand_br16_encode (uint32 *valp) +{ + int error; + error = (*valp & ~(0 << 4)) != 0; + *valp = *valp >> 4; + return error; +} + +static int +Operand_brall_decode (uint32 *valp) +{ + *valp = *valp << 4; + return 0; +} + +static int +Operand_brall_encode (uint32 *valp) +{ + int error; + error = (*valp & ~(0 << 4)) != 0; + *valp = *valp >> 4; + return error; +} + +static int +Operand_tp7_decode (uint32 *valp) +{ + unsigned tp7_0, t_0; + t_0 = *valp & 0xf; + tp7_0 = t_0 + 0x7; + *valp = tp7_0; + return 0; +} + +static int +Operand_tp7_encode (uint32 *valp) +{ + unsigned t_0, tp7_0; + tp7_0 = *valp; + t_0 = (tp7_0 - 0x7) & 0xf; + *valp = t_0; + return 0; +} + +static int +Operand_xt_wbr15_label_decode (uint32 *valp) +{ + unsigned xt_wbr15_label_0, xt_wbr15_imm_0; + xt_wbr15_imm_0 = *valp & 0x7fff; + xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); + *valp = xt_wbr15_label_0; + return 0; +} + +static int +Operand_xt_wbr15_label_encode (uint32 *valp) +{ + unsigned xt_wbr15_imm_0, xt_wbr15_label_0; + xt_wbr15_label_0 = *valp; + xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; + *valp = xt_wbr15_imm_0; + return 0; +} + +static int +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_xt_wbr18_label_decode (uint32 *valp) +{ + unsigned xt_wbr18_label_0, xt_wbr18_imm_0; + xt_wbr18_imm_0 = *valp & 0x3ffff; + xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); + *valp = xt_wbr18_label_0; + return 0; +} + +static int +Operand_xt_wbr18_label_encode (uint32 *valp) +{ + unsigned xt_wbr18_imm_0, xt_wbr18_label_0; + xt_wbr18_label_0 = *valp; + xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; + *valp = xt_wbr18_imm_0; + return 0; +} + +static int +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) +{ + *valp -= pc; + return 0; +} + +static int +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) +{ + *valp += pc; + return 0; +} + +static int +Operand_cimm8x4_decode (uint32 *valp) +{ + unsigned cimm8x4_0, fimm8_0; + fimm8_0 = *valp & 0xff; + cimm8x4_0 = (fimm8_0 << 2) | 0; + *valp = cimm8x4_0; + return 0; +} + +static int +Operand_cimm8x4_encode (uint32 *valp) +{ + unsigned fimm8_0, cimm8x4_0; + cimm8x4_0 = *valp; + fimm8_0 = (cimm8x4_0 >> 2) & 0xff; + *valp = fimm8_0; + return 0; +} + +static int +Operand_frr_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_frr_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_frs_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_frs_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_frt_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_frt_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper45_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper45_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper46_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper46_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper47_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper47_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper48_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper48_imm_0, dsp340050b49a6c_fld2047_0; + dsp340050b49a6c_fld2047_0 = *valp & 0x1; + dsp340050b49a6c_oper48_imm_0 = (0 << 1) | dsp340050b49a6c_fld2047_0; + *valp = dsp340050b49a6c_oper48_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper48_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2047_0, dsp340050b49a6c_oper48_imm_0; + dsp340050b49a6c_oper48_imm_0 = *valp; + dsp340050b49a6c_fld2047_0 = (((dsp340050b49a6c_oper48_imm_0 >> 0) & 1)) & 0x1; + *valp = dsp340050b49a6c_fld2047_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper49_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper49_imm_0, dsp340050b49a6c_fld2025_0; + dsp340050b49a6c_fld2025_0 = *valp & 0x1; + dsp340050b49a6c_oper49_imm_0 = (0 << 1) | dsp340050b49a6c_fld2025_0; + *valp = dsp340050b49a6c_oper49_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper49_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2025_0, dsp340050b49a6c_oper49_imm_0; + dsp340050b49a6c_oper49_imm_0 = *valp; + dsp340050b49a6c_fld2025_0 = (((dsp340050b49a6c_oper49_imm_0 >> 0) & 1)) & 0x1; + *valp = dsp340050b49a6c_fld2025_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper50_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper50_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper51_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper51_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x7) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper52_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper52_imm_0, dsp340050b49a6c_fld2049_0; + dsp340050b49a6c_fld2049_0 = *valp & 0x3; + dsp340050b49a6c_oper52_imm_0 = (0 << 2) | dsp340050b49a6c_fld2049_0; + *valp = dsp340050b49a6c_oper52_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper52_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2049_0, dsp340050b49a6c_oper52_imm_0; + dsp340050b49a6c_oper52_imm_0 = *valp; + dsp340050b49a6c_fld2049_0 = (dsp340050b49a6c_oper52_imm_0 & 0x3); + *valp = dsp340050b49a6c_fld2049_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper53_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper53_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper54_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper54_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x7) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper55_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper55_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper56_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper56_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper57_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper57_imm_0, dsp340050b49a6c_fld2041_0; + dsp340050b49a6c_fld2041_0 = *valp & 0x1; + dsp340050b49a6c_oper57_imm_0 = (0 << 1) | dsp340050b49a6c_fld2041_0; + *valp = dsp340050b49a6c_oper57_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper57_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2041_0, dsp340050b49a6c_oper57_imm_0; + dsp340050b49a6c_oper57_imm_0 = *valp; + dsp340050b49a6c_fld2041_0 = (((dsp340050b49a6c_oper57_imm_0 >> 0) & 1)) & 0x1; + *valp = dsp340050b49a6c_fld2041_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper58_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper58_imm_0, dsp340050b49a6c_fld2051_0; + dsp340050b49a6c_fld2051_0 = *valp & 0x3f; + dsp340050b49a6c_oper58_imm_0 = ((int) dsp340050b49a6c_fld2051_0 << 26) >> 26; + *valp = dsp340050b49a6c_oper58_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper58_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2051_0, dsp340050b49a6c_oper58_imm_0; + dsp340050b49a6c_oper58_imm_0 = *valp; + dsp340050b49a6c_fld2051_0 = (dsp340050b49a6c_oper58_imm_0 & 0x3f); + *valp = dsp340050b49a6c_fld2051_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper59_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper59_imm_0, dsp340050b49a6c_fld2052_0; + dsp340050b49a6c_fld2052_0 = *valp & 0xf; + dsp340050b49a6c_oper59_imm_0 = (0 << 4) | dsp340050b49a6c_fld2052_0; + *valp = dsp340050b49a6c_oper59_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper59_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2052_0, dsp340050b49a6c_oper59_imm_0; + dsp340050b49a6c_oper59_imm_0 = *valp; + dsp340050b49a6c_fld2052_0 = (dsp340050b49a6c_oper59_imm_0 & 0xf); + *valp = dsp340050b49a6c_fld2052_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper60_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper60_imm_0, dsp340050b49a6c_fld2053_0; + dsp340050b49a6c_fld2053_0 = *valp & 0x1f; + dsp340050b49a6c_oper60_imm_0 = (0 << 5) | dsp340050b49a6c_fld2053_0; + *valp = dsp340050b49a6c_oper60_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper60_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2053_0, dsp340050b49a6c_oper60_imm_0; + dsp340050b49a6c_oper60_imm_0 = *valp; + dsp340050b49a6c_fld2053_0 = (dsp340050b49a6c_oper60_imm_0 & 0x1f); + *valp = dsp340050b49a6c_fld2053_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper61_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper61_imm_0, dsp340050b49a6c_fld2044_0; + dsp340050b49a6c_fld2044_0 = *valp & 0x1f; + dsp340050b49a6c_oper61_imm_0 = (0 << 5) | dsp340050b49a6c_fld2044_0; + *valp = dsp340050b49a6c_oper61_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper61_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2044_0, dsp340050b49a6c_oper61_imm_0; + dsp340050b49a6c_oper61_imm_0 = *valp; + dsp340050b49a6c_fld2044_0 = (dsp340050b49a6c_oper61_imm_0 & 0x1f); + *valp = dsp340050b49a6c_fld2044_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper62_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper62_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper63_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper63_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x7) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper64_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper64_imm_0, dsp340050b49a6c_fld2032_0; + dsp340050b49a6c_fld2032_0 = *valp & 0x3; + dsp340050b49a6c_oper64_imm_0 = (0 << 2) | dsp340050b49a6c_fld2032_0; + *valp = dsp340050b49a6c_oper64_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper64_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2032_0, dsp340050b49a6c_oper64_imm_0; + dsp340050b49a6c_oper64_imm_0 = *valp; + dsp340050b49a6c_fld2032_0 = (dsp340050b49a6c_oper64_imm_0 & 0x3); + *valp = dsp340050b49a6c_fld2032_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper65_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper65_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper66_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper66_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x7) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper67_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper67_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x7) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper68_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper68_imm_0, dsp340050b49a6c_fld2035_0; + dsp340050b49a6c_fld2035_0 = *valp & 0x3; + dsp340050b49a6c_oper68_imm_0 = (0 << 2) | dsp340050b49a6c_fld2035_0; + *valp = dsp340050b49a6c_oper68_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper68_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2035_0, dsp340050b49a6c_oper68_imm_0; + dsp340050b49a6c_oper68_imm_0 = *valp; + dsp340050b49a6c_fld2035_0 = (dsp340050b49a6c_oper68_imm_0 & 0x3); + *valp = dsp340050b49a6c_fld2035_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper69_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper69_imm_0, dsp340050b49a6c_fld2036_0; + dsp340050b49a6c_fld2036_0 = *valp & 0x1; + dsp340050b49a6c_oper69_imm_0 = (0 << 1) | dsp340050b49a6c_fld2036_0; + *valp = dsp340050b49a6c_oper69_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper69_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2036_0, dsp340050b49a6c_oper69_imm_0; + dsp340050b49a6c_oper69_imm_0 = *valp; + dsp340050b49a6c_fld2036_0 = (((dsp340050b49a6c_oper69_imm_0 >> 0) & 1)) & 0x1; + *valp = dsp340050b49a6c_fld2036_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper70_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper70_imm_0, dsp340050b49a6c_fld2037_0; + dsp340050b49a6c_fld2037_0 = *valp & 0x7; + dsp340050b49a6c_oper70_imm_0 = (0 << 3) | dsp340050b49a6c_fld2037_0; + *valp = dsp340050b49a6c_oper70_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper70_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2037_0, dsp340050b49a6c_oper70_imm_0; + dsp340050b49a6c_oper70_imm_0 = *valp; + dsp340050b49a6c_fld2037_0 = (dsp340050b49a6c_oper70_imm_0 & 0x7); + *valp = dsp340050b49a6c_fld2037_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper71_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper71_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0x7) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper72_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper72_imm_0, dsp340050b49a6c_fld2042_0; + dsp340050b49a6c_fld2042_0 = *valp & 0x3; + dsp340050b49a6c_oper72_imm_0 = (0 << 2) | dsp340050b49a6c_fld2042_0; + *valp = dsp340050b49a6c_oper72_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper72_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2042_0, dsp340050b49a6c_oper72_imm_0; + dsp340050b49a6c_oper72_imm_0 = *valp; + dsp340050b49a6c_fld2042_0 = (dsp340050b49a6c_oper72_imm_0 & 0x3); + *valp = dsp340050b49a6c_fld2042_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper73_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper73_imm_0, dsp340050b49a6c_fld2038_0; + dsp340050b49a6c_fld2038_0 = *valp & 0xf; + dsp340050b49a6c_oper73_imm_0 = ((0 << 4) | dsp340050b49a6c_fld2038_0) << 3; + *valp = dsp340050b49a6c_oper73_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper73_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2038_0, dsp340050b49a6c_oper73_imm_0; + dsp340050b49a6c_oper73_imm_0 = *valp; + dsp340050b49a6c_fld2038_0 = ((dsp340050b49a6c_oper73_imm_0 >> 3) & 0xf); + *valp = dsp340050b49a6c_fld2038_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper74_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper74_imm_0, dsp340050b49a6c_fld2038_0; + dsp340050b49a6c_fld2038_0 = *valp & 0xf; + dsp340050b49a6c_oper74_imm_0 = ((0 << 4) | dsp340050b49a6c_fld2038_0) << 4; + *valp = dsp340050b49a6c_oper74_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper74_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2038_0, dsp340050b49a6c_oper74_imm_0; + dsp340050b49a6c_oper74_imm_0 = *valp; + dsp340050b49a6c_fld2038_0 = ((dsp340050b49a6c_oper74_imm_0 >> 4) & 0xf); + *valp = dsp340050b49a6c_fld2038_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper75_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper75_imm_0, dsp340050b49a6c_fld2038_0; + dsp340050b49a6c_fld2038_0 = *valp & 0xf; + dsp340050b49a6c_oper75_imm_0 = ((0 << 4) | dsp340050b49a6c_fld2038_0) << 2; + *valp = dsp340050b49a6c_oper75_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper75_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2038_0, dsp340050b49a6c_oper75_imm_0; + dsp340050b49a6c_oper75_imm_0 = *valp; + dsp340050b49a6c_fld2038_0 = ((dsp340050b49a6c_oper75_imm_0 >> 2) & 0xf); + *valp = dsp340050b49a6c_fld2038_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper76_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper76_imm_0, dsp340050b49a6c_fld2053_0; + dsp340050b49a6c_fld2053_0 = *valp & 0x1f; + dsp340050b49a6c_oper76_imm_0 = ((0 << 5) | dsp340050b49a6c_fld2053_0) << 4; + *valp = dsp340050b49a6c_oper76_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper76_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2053_0, dsp340050b49a6c_oper76_imm_0; + dsp340050b49a6c_oper76_imm_0 = *valp; + dsp340050b49a6c_fld2053_0 = ((dsp340050b49a6c_oper76_imm_0 >> 4) & 0x1f); + *valp = dsp340050b49a6c_fld2053_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper77_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper77_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper78_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper78_imm_0, dsp340050b49a6c_fld2056_0; + dsp340050b49a6c_fld2056_0 = *valp & 0x7; + dsp340050b49a6c_oper78_imm_0 = (0 << 3) | dsp340050b49a6c_fld2056_0; + *valp = dsp340050b49a6c_oper78_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper78_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2056_0, dsp340050b49a6c_oper78_imm_0; + dsp340050b49a6c_oper78_imm_0 = *valp; + dsp340050b49a6c_fld2056_0 = (dsp340050b49a6c_oper78_imm_0 & 0x7); + *valp = dsp340050b49a6c_fld2056_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper79_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper79_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper80_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper80_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper81_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper81_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper82_reg_decode (uint32 *valp ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +Operand_dsp340050b49a6c_oper82_reg_encode (uint32 *valp) +{ + int error; + error = (*valp & ~0xf) != 0; + return error; +} + +static int +Operand_dsp340050b49a6c_oper83_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper83_imm_0, dsp340050b49a6c_fld2040_0; + dsp340050b49a6c_fld2040_0 = *valp & 0x1f; + dsp340050b49a6c_oper83_imm_0 = ((0 << 5) | dsp340050b49a6c_fld2040_0) << 4; + *valp = dsp340050b49a6c_oper83_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper83_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2040_0, dsp340050b49a6c_oper83_imm_0; + dsp340050b49a6c_oper83_imm_0 = *valp; + dsp340050b49a6c_fld2040_0 = ((dsp340050b49a6c_oper83_imm_0 >> 4) & 0x1f); + *valp = dsp340050b49a6c_fld2040_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper84_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper84_imm_0, dsp340050b49a6c_fld2029_0; + dsp340050b49a6c_fld2029_0 = *valp & 0xf; + dsp340050b49a6c_oper84_imm_0 = ((0 << 4) | dsp340050b49a6c_fld2029_0) << 3; + *valp = dsp340050b49a6c_oper84_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper84_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2029_0, dsp340050b49a6c_oper84_imm_0; + dsp340050b49a6c_oper84_imm_0 = *valp; + dsp340050b49a6c_fld2029_0 = ((dsp340050b49a6c_oper84_imm_0 >> 3) & 0xf); + *valp = dsp340050b49a6c_fld2029_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper85_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper85_imm_0, dsp340050b49a6c_fld2029_0; + dsp340050b49a6c_fld2029_0 = *valp & 0xf; + dsp340050b49a6c_oper85_imm_0 = ((0 << 4) | dsp340050b49a6c_fld2029_0) << 4; + *valp = dsp340050b49a6c_oper85_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper85_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2029_0, dsp340050b49a6c_oper85_imm_0; + dsp340050b49a6c_oper85_imm_0 = *valp; + dsp340050b49a6c_fld2029_0 = ((dsp340050b49a6c_oper85_imm_0 >> 4) & 0xf); + *valp = dsp340050b49a6c_fld2029_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper86_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper86_imm_0, dsp340050b49a6c_fld2029_0; + dsp340050b49a6c_fld2029_0 = *valp & 0xf; + dsp340050b49a6c_oper86_imm_0 = ((0 << 4) | dsp340050b49a6c_fld2029_0) << 2; + *valp = dsp340050b49a6c_oper86_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper86_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2029_0, dsp340050b49a6c_oper86_imm_0; + dsp340050b49a6c_oper86_imm_0 = *valp; + dsp340050b49a6c_fld2029_0 = ((dsp340050b49a6c_oper86_imm_0 >> 2) & 0xf); + *valp = dsp340050b49a6c_fld2029_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper87_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper87_imm_0, dsp340050b49a6c_fld2043_0; + dsp340050b49a6c_fld2043_0 = *valp & 0x1f; + dsp340050b49a6c_oper87_imm_0 = ((0 << 5) | dsp340050b49a6c_fld2043_0) << 4; + *valp = dsp340050b49a6c_oper87_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper87_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2043_0, dsp340050b49a6c_oper87_imm_0; + dsp340050b49a6c_oper87_imm_0 = *valp; + dsp340050b49a6c_fld2043_0 = ((dsp340050b49a6c_oper87_imm_0 >> 4) & 0x1f); + *valp = dsp340050b49a6c_fld2043_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper88_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper88_imm_0, dsp340050b49a6c_fld2030_0; + dsp340050b49a6c_fld2030_0 = *valp & 0xf; + dsp340050b49a6c_oper88_imm_0 = (0 << 4) | dsp340050b49a6c_fld2030_0; + *valp = dsp340050b49a6c_oper88_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper88_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2030_0, dsp340050b49a6c_oper88_imm_0; + dsp340050b49a6c_oper88_imm_0 = *valp; + dsp340050b49a6c_fld2030_0 = (dsp340050b49a6c_oper88_imm_0 & 0xf); + *valp = dsp340050b49a6c_fld2030_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper89_imm_decode (uint32 *valp) +{ + unsigned dsp340050b49a6c_oper89_imm_0, dsp340050b49a6c_fld2052_0; + dsp340050b49a6c_fld2052_0 = *valp & 0xf; + dsp340050b49a6c_oper89_imm_0 = ((0 << 4) | dsp340050b49a6c_fld2052_0) << 2; + *valp = dsp340050b49a6c_oper89_imm_0; + return 0; +} + +static int +Operand_dsp340050b49a6c_oper89_imm_encode (uint32 *valp) +{ + unsigned dsp340050b49a6c_fld2052_0, dsp340050b49a6c_oper89_imm_0; + dsp340050b49a6c_oper89_imm_0 = *valp; + dsp340050b49a6c_fld2052_0 = ((dsp340050b49a6c_oper89_imm_0 >> 2) & 0xf); + *valp = dsp340050b49a6c_fld2052_0; + return 0; +} + +static xtensa_operand_internal operands[] = { + { "soffsetx4", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffsetx4_encode, Operand_soffsetx4_decode, + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, + { "uimm12x8", FIELD_imm12, -1, 0, + 0, + Operand_uimm12x8_encode, Operand_uimm12x8_decode, + 0, 0 }, + { "simm4", FIELD_mn, -1, 0, + 0, + Operand_simm4_encode, Operand_simm4_decode, + 0, 0 }, + { "arr", FIELD_r, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_arr_encode, Operand_arr_decode, + 0, 0 }, + { "ars", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "*ars_invisible", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ars_encode, Operand_ars_decode, + 0, 0 }, + { "art", FIELD_t, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_art_encode, Operand_art_decode, + 0, 0 }, + { "ar0", FIELD__ar0, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar0_encode, Operand_ar0_decode, + 0, 0 }, + { "ar4", FIELD__ar4, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar4_encode, Operand_ar4_decode, + 0, 0 }, + { "ar8", FIELD__ar8, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar8_encode, Operand_ar8_decode, + 0, 0 }, + { "ar12", FIELD__ar12, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_ar12_encode, Operand_ar12_decode, + 0, 0 }, + { "ars_entry", FIELD_s, REGFILE_AR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_ars_entry_encode, Operand_ars_entry_decode, + 0, 0 }, + { "immrx4", FIELD_r, -1, 0, + 0, + Operand_immrx4_encode, Operand_immrx4_decode, + 0, 0 }, + { "lsi4x4", FIELD_r, -1, 0, + 0, + Operand_lsi4x4_encode, Operand_lsi4x4_decode, + 0, 0 }, + { "simm7", FIELD_imm7, -1, 0, + 0, + Operand_simm7_encode, Operand_simm7_decode, + 0, 0 }, + { "uimm6", FIELD_imm6, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm6_encode, Operand_uimm6_decode, + Operand_uimm6_ator, Operand_uimm6_rtoa }, + { "ai4const", FIELD_t, -1, 0, + 0, + Operand_ai4const_encode, Operand_ai4const_decode, + 0, 0 }, + { "b4const", FIELD_r, -1, 0, + 0, + Operand_b4const_encode, Operand_b4const_decode, + 0, 0 }, + { "b4constu", FIELD_r, -1, 0, + 0, + Operand_b4constu_encode, Operand_b4constu_decode, + 0, 0 }, + { "uimm8", FIELD_imm8, -1, 0, + 0, + Operand_uimm8_encode, Operand_uimm8_decode, + 0, 0 }, + { "uimm8x2", FIELD_imm8, -1, 0, + 0, + Operand_uimm8x2_encode, Operand_uimm8x2_decode, + 0, 0 }, + { "uimm8x4", FIELD_imm8, -1, 0, + 0, + Operand_uimm8x4_encode, Operand_uimm8x4_decode, + 0, 0 }, + { "uimm4x16", FIELD_op2, -1, 0, + 0, + Operand_uimm4x16_encode, Operand_uimm4x16_decode, + 0, 0 }, + { "simm8", FIELD_imm8, -1, 0, + 0, + Operand_simm8_encode, Operand_simm8_decode, + 0, 0 }, + { "simm8x256", FIELD_imm8, -1, 0, + 0, + Operand_simm8x256_encode, Operand_simm8x256_decode, + 0, 0 }, + { "simm12b", FIELD_imm12b, -1, 0, + 0, + Operand_simm12b_encode, Operand_simm12b_decode, + 0, 0 }, + { "msalp32", FIELD_sal, -1, 0, + 0, + Operand_msalp32_encode, Operand_msalp32_decode, + 0, 0 }, + { "op2p1", FIELD_op2, -1, 0, + 0, + Operand_op2p1_encode, Operand_op2p1_decode, + 0, 0 }, + { "label8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label8_encode, Operand_label8_decode, + Operand_label8_ator, Operand_label8_rtoa }, + { "ulabel8", FIELD_imm8, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_ulabel8_encode, Operand_ulabel8_decode, + Operand_ulabel8_ator, Operand_ulabel8_rtoa }, + { "label12", FIELD_imm12, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_label12_encode, Operand_label12_decode, + Operand_label12_ator, Operand_label12_rtoa }, + { "soffset", FIELD_offset, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_soffset_encode, Operand_soffset_decode, + Operand_soffset_ator, Operand_soffset_rtoa }, + { "uimm16x4", FIELD_imm16, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_uimm16x4_encode, Operand_uimm16x4_decode, + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, + { "immt", FIELD_t, -1, 0, + 0, + Operand_immt_encode, Operand_immt_decode, + 0, 0 }, + { "imms", FIELD_s, -1, 0, + 0, + Operand_imms_encode, Operand_imms_decode, + 0, 0 }, + { "bt", FIELD_t, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_bt_encode, Operand_bt_decode, + 0, 0 }, + { "bs", FIELD_s, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_bs_encode, Operand_bs_decode, + 0, 0 }, + { "br", FIELD_r, REGFILE_BR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_br_encode, Operand_br_decode, + 0, 0 }, + { "bt2", FIELD_t2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + Operand_bt2_encode, Operand_bt2_decode, + 0, 0 }, + { "bs2", FIELD_s2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + Operand_bs2_encode, Operand_bs2_decode, + 0, 0 }, + { "br2", FIELD_r2, REGFILE_BR, 2, + XTENSA_OPERAND_IS_REGISTER, + Operand_br2_encode, Operand_br2_decode, + 0, 0 }, + { "bt4", FIELD_t4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + Operand_bt4_encode, Operand_bt4_decode, + 0, 0 }, + { "bs4", FIELD_s4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + Operand_bs4_encode, Operand_bs4_decode, + 0, 0 }, + { "br4", FIELD_r4, REGFILE_BR, 4, + XTENSA_OPERAND_IS_REGISTER, + Operand_br4_encode, Operand_br4_decode, + 0, 0 }, + { "bt8", FIELD_t8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + Operand_bt8_encode, Operand_bt8_decode, + 0, 0 }, + { "bs8", FIELD_s8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + Operand_bs8_encode, Operand_bs8_decode, + 0, 0 }, + { "br8", FIELD_r8, REGFILE_BR, 8, + XTENSA_OPERAND_IS_REGISTER, + Operand_br8_encode, Operand_br8_decode, + 0, 0 }, + { "bt16", FIELD__bt16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + Operand_bt16_encode, Operand_bt16_decode, + 0, 0 }, + { "bs16", FIELD__bs16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + Operand_bs16_encode, Operand_bs16_decode, + 0, 0 }, + { "br16", FIELD__br16, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER, + Operand_br16_encode, Operand_br16_decode, + 0, 0 }, + { "brall", FIELD__brall, REGFILE_BR, 16, + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, + Operand_brall_encode, Operand_brall_decode, + 0, 0 }, + { "tp7", FIELD_t, -1, 0, + 0, + Operand_tp7_encode, Operand_tp7_decode, + 0, 0 }, + { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, + { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, + XTENSA_OPERAND_IS_PCRELATIVE, + Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, + { "cimm8x4", FIELD_fimm8, -1, 0, + 0, + Operand_cimm8x4_encode, Operand_cimm8x4_decode, + 0, 0 }, + { "frr", FIELD_r, REGFILE_FR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_frr_encode, Operand_frr_decode, + 0, 0 }, + { "frs", FIELD_s, REGFILE_FR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_frs_encode, Operand_frs_decode, + 0, 0 }, + { "frt", FIELD_t, REGFILE_FR, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_frt_encode, Operand_frt_decode, + 0, 0 }, + { "dsp340050b49a6c_oper45_reg", FIELD_dsp340050b49a6c_fld2045, REGFILE_CM, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper45_reg_encode, Operand_dsp340050b49a6c_oper45_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper46_reg", FIELD_dsp340050b49a6c_fld2046, REGFILE_CM, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper46_reg_encode, Operand_dsp340050b49a6c_oper46_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper47_reg", FIELD_dsp340050b49a6c_fld2029, REGFILE_CM, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper47_reg_encode, Operand_dsp340050b49a6c_oper47_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper48_imm", FIELD_dsp340050b49a6c_fld2047, -1, 0, + 0, + Operand_dsp340050b49a6c_oper48_imm_encode, Operand_dsp340050b49a6c_oper48_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper49_imm", FIELD_dsp340050b49a6c_fld2025, -1, 0, + 0, + Operand_dsp340050b49a6c_oper49_imm_encode, Operand_dsp340050b49a6c_oper49_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper50_reg", FIELD_dsp340050b49a6c_fld2026, REGFILE_CM, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper50_reg_encode, Operand_dsp340050b49a6c_oper50_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper51_reg", FIELD_dsp340050b49a6c_fld2048, REGFILE_ACU, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper51_reg_encode, Operand_dsp340050b49a6c_oper51_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper52_imm", FIELD_dsp340050b49a6c_fld2049, -1, 0, + 0, + Operand_dsp340050b49a6c_oper52_imm_encode, Operand_dsp340050b49a6c_oper52_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper53_reg", FIELD_dsp340050b49a6c_fld2027, REGFILE_CM, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper53_reg_encode, Operand_dsp340050b49a6c_oper53_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper54_reg", FIELD_dsp340050b49a6c_fld2028, REGFILE_ACU, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper54_reg_encode, Operand_dsp340050b49a6c_oper54_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper55_reg", FIELD_dsp340050b49a6c_fld2030, REGFILE_CM, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper55_reg_encode, Operand_dsp340050b49a6c_oper55_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper56_reg", FIELD_dsp340050b49a6c_fld2050, REGFILE_PQ, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper56_reg_encode, Operand_dsp340050b49a6c_oper56_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper57_imm", FIELD_dsp340050b49a6c_fld2041, -1, 0, + 0, + Operand_dsp340050b49a6c_oper57_imm_encode, Operand_dsp340050b49a6c_oper57_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper58_imm", FIELD_dsp340050b49a6c_fld2051, -1, 0, + 0, + Operand_dsp340050b49a6c_oper58_imm_encode, Operand_dsp340050b49a6c_oper58_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper59_imm", FIELD_dsp340050b49a6c_fld2052, -1, 0, + 0, + Operand_dsp340050b49a6c_oper59_imm_encode, Operand_dsp340050b49a6c_oper59_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper60_imm", FIELD_dsp340050b49a6c_fld2053, -1, 0, + 0, + Operand_dsp340050b49a6c_oper60_imm_encode, Operand_dsp340050b49a6c_oper60_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper61_imm", FIELD_dsp340050b49a6c_fld2044, -1, 0, + 0, + Operand_dsp340050b49a6c_oper61_imm_encode, Operand_dsp340050b49a6c_oper61_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper62_reg", FIELD_dsp340050b49a6c_fld2031, REGFILE_CM, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper62_reg_encode, Operand_dsp340050b49a6c_oper62_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper63_reg", FIELD_dsp340050b49a6c_fld2054, REGFILE_ACU, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper63_reg_encode, Operand_dsp340050b49a6c_oper63_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper64_imm", FIELD_dsp340050b49a6c_fld2032, -1, 0, + 0, + Operand_dsp340050b49a6c_oper64_imm_encode, Operand_dsp340050b49a6c_oper64_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper65_reg", FIELD_dsp340050b49a6c_fld2055, REGFILE_PQ, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper65_reg_encode, Operand_dsp340050b49a6c_oper65_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper66_reg", FIELD_dsp340050b49a6c_fld2033, REGFILE_ACU, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper66_reg_encode, Operand_dsp340050b49a6c_oper66_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper67_reg", FIELD_dsp340050b49a6c_fld2034, REGFILE_ACU, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper67_reg_encode, Operand_dsp340050b49a6c_oper67_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper68_imm", FIELD_dsp340050b49a6c_fld2035, -1, 0, + 0, + Operand_dsp340050b49a6c_oper68_imm_encode, Operand_dsp340050b49a6c_oper68_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper69_imm", FIELD_dsp340050b49a6c_fld2036, -1, 0, + 0, + Operand_dsp340050b49a6c_oper69_imm_encode, Operand_dsp340050b49a6c_oper69_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper70_imm", FIELD_dsp340050b49a6c_fld2037, -1, 0, + 0, + Operand_dsp340050b49a6c_oper70_imm_encode, Operand_dsp340050b49a6c_oper70_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper71_reg", FIELD_dsp340050b49a6c_fld2037, REGFILE_ACU, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper71_reg_encode, Operand_dsp340050b49a6c_oper71_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper72_imm", FIELD_dsp340050b49a6c_fld2042, -1, 0, + 0, + Operand_dsp340050b49a6c_oper72_imm_encode, Operand_dsp340050b49a6c_oper72_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper73_imm", FIELD_dsp340050b49a6c_fld2038, -1, 0, + 0, + Operand_dsp340050b49a6c_oper73_imm_encode, Operand_dsp340050b49a6c_oper73_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper74_imm", FIELD_dsp340050b49a6c_fld2038, -1, 0, + 0, + Operand_dsp340050b49a6c_oper74_imm_encode, Operand_dsp340050b49a6c_oper74_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper75_imm", FIELD_dsp340050b49a6c_fld2038, -1, 0, + 0, + Operand_dsp340050b49a6c_oper75_imm_encode, Operand_dsp340050b49a6c_oper75_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper76_imm", FIELD_dsp340050b49a6c_fld2053, -1, 0, + 0, + Operand_dsp340050b49a6c_oper76_imm_encode, Operand_dsp340050b49a6c_oper76_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper77_reg", FIELD_r, REGFILE_CM, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper77_reg_encode, Operand_dsp340050b49a6c_oper77_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper78_imm", FIELD_dsp340050b49a6c_fld2056, -1, 0, + 0, + Operand_dsp340050b49a6c_oper78_imm_encode, Operand_dsp340050b49a6c_oper78_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper79_reg", FIELD_r, REGFILE_PQ, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper79_reg_encode, Operand_dsp340050b49a6c_oper79_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper80_reg", FIELD_s, REGFILE_CM, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper80_reg_encode, Operand_dsp340050b49a6c_oper80_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper81_reg", FIELD_dsp340050b49a6c_fld2039, REGFILE_PQ, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper81_reg_encode, Operand_dsp340050b49a6c_oper81_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper82_reg", FIELD_dsp340050b49a6c_fld2052, REGFILE_CM, 1, + XTENSA_OPERAND_IS_REGISTER, + Operand_dsp340050b49a6c_oper82_reg_encode, Operand_dsp340050b49a6c_oper82_reg_decode, + 0, 0 }, + { "dsp340050b49a6c_oper83_imm", FIELD_dsp340050b49a6c_fld2040, -1, 0, + 0, + Operand_dsp340050b49a6c_oper83_imm_encode, Operand_dsp340050b49a6c_oper83_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper84_imm", FIELD_dsp340050b49a6c_fld2029, -1, 0, + 0, + Operand_dsp340050b49a6c_oper84_imm_encode, Operand_dsp340050b49a6c_oper84_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper85_imm", FIELD_dsp340050b49a6c_fld2029, -1, 0, + 0, + Operand_dsp340050b49a6c_oper85_imm_encode, Operand_dsp340050b49a6c_oper85_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper86_imm", FIELD_dsp340050b49a6c_fld2029, -1, 0, + 0, + Operand_dsp340050b49a6c_oper86_imm_encode, Operand_dsp340050b49a6c_oper86_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper87_imm", FIELD_dsp340050b49a6c_fld2043, -1, 0, + 0, + Operand_dsp340050b49a6c_oper87_imm_encode, Operand_dsp340050b49a6c_oper87_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper88_imm", FIELD_dsp340050b49a6c_fld2030, -1, 0, + 0, + Operand_dsp340050b49a6c_oper88_imm_encode, Operand_dsp340050b49a6c_oper88_imm_decode, + 0, 0 }, + { "dsp340050b49a6c_oper89_imm", FIELD_dsp340050b49a6c_fld2052, -1, 0, + 0, + Operand_dsp340050b49a6c_oper89_imm_encode, Operand_dsp340050b49a6c_oper89_imm_decode, + 0, 0 }, + { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, + { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, + { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, + { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 }, + { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, + { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, + { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, + { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, + { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, + { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, + { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, + { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, + { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, + { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, + { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 }, + { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, + { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 }, + { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, + { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 }, + { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, + { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, + { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, + { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, + { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, + { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, + { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, + { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, + { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, + { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, + { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, + { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, + { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, + { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, + { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, + { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, + { "fimm8", FIELD_fimm8, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2019", FIELD_dsp340050b49a6c_fld2019, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2021", FIELD_dsp340050b49a6c_fld2021, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2029", FIELD_dsp340050b49a6c_fld2029, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2030", FIELD_dsp340050b49a6c_fld2030, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2032", FIELD_dsp340050b49a6c_fld2032, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2035", FIELD_dsp340050b49a6c_fld2035, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2036", FIELD_dsp340050b49a6c_fld2036, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2037", FIELD_dsp340050b49a6c_fld2037, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2038", FIELD_dsp340050b49a6c_fld2038, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2039", FIELD_dsp340050b49a6c_fld2039, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2040", FIELD_dsp340050b49a6c_fld2040, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2041", FIELD_dsp340050b49a6c_fld2041, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2042", FIELD_dsp340050b49a6c_fld2042, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2043", FIELD_dsp340050b49a6c_fld2043, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2044", FIELD_dsp340050b49a6c_fld2044, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2045", FIELD_dsp340050b49a6c_fld2045, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2046", FIELD_dsp340050b49a6c_fld2046, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2047", FIELD_dsp340050b49a6c_fld2047, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2048", FIELD_dsp340050b49a6c_fld2048, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2049", FIELD_dsp340050b49a6c_fld2049, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2050", FIELD_dsp340050b49a6c_fld2050, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2051", FIELD_dsp340050b49a6c_fld2051, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2052", FIELD_dsp340050b49a6c_fld2052, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2053", FIELD_dsp340050b49a6c_fld2053, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2054", FIELD_dsp340050b49a6c_fld2054, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2055", FIELD_dsp340050b49a6c_fld2055, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2056", FIELD_dsp340050b49a6c_fld2056, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2082Inst", FIELD_dsp340050b49a6c_fld2082Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2083Inst", FIELD_dsp340050b49a6c_fld2083Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2084Inst", FIELD_dsp340050b49a6c_fld2084Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2085Inst", FIELD_dsp340050b49a6c_fld2085Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2086Inst", FIELD_dsp340050b49a6c_fld2086Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2088Inst", FIELD_dsp340050b49a6c_fld2088Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2089Inst", FIELD_dsp340050b49a6c_fld2089Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2090Inst", FIELD_dsp340050b49a6c_fld2090Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2091Inst", FIELD_dsp340050b49a6c_fld2091Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2092Inst", FIELD_dsp340050b49a6c_fld2092Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2094Inst", FIELD_dsp340050b49a6c_fld2094Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2095Inst", FIELD_dsp340050b49a6c_fld2095Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2096Inst", FIELD_dsp340050b49a6c_fld2096Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2098Inst", FIELD_dsp340050b49a6c_fld2098Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2099Inst", FIELD_dsp340050b49a6c_fld2099Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2100Inst", FIELD_dsp340050b49a6c_fld2100Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2101Inst", FIELD_dsp340050b49a6c_fld2101Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2102Inst", FIELD_dsp340050b49a6c_fld2102Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2103Inst", FIELD_dsp340050b49a6c_fld2103Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2104Inst", FIELD_dsp340050b49a6c_fld2104Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2105Inst", FIELD_dsp340050b49a6c_fld2105Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2106Inst", FIELD_dsp340050b49a6c_fld2106Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2107Inst", FIELD_dsp340050b49a6c_fld2107Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2108Inst", FIELD_dsp340050b49a6c_fld2108Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2109Inst", FIELD_dsp340050b49a6c_fld2109Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2110Inst", FIELD_dsp340050b49a6c_fld2110Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2111Inst", FIELD_dsp340050b49a6c_fld2111Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2112Inst", FIELD_dsp340050b49a6c_fld2112Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2113Inst", FIELD_dsp340050b49a6c_fld2113Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2114Inst", FIELD_dsp340050b49a6c_fld2114Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2115Inst", FIELD_dsp340050b49a6c_fld2115Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2116Inst", FIELD_dsp340050b49a6c_fld2116Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2117Inst", FIELD_dsp340050b49a6c_fld2117Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2118Inst", FIELD_dsp340050b49a6c_fld2118Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2119Inst", FIELD_dsp340050b49a6c_fld2119Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2120Inst", FIELD_dsp340050b49a6c_fld2120Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2122Inst", FIELD_dsp340050b49a6c_fld2122Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2123Inst", FIELD_dsp340050b49a6c_fld2123Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2124Inst", FIELD_dsp340050b49a6c_fld2124Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2125Inst", FIELD_dsp340050b49a6c_fld2125Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2126Inst", FIELD_dsp340050b49a6c_fld2126Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2127Inst", FIELD_dsp340050b49a6c_fld2127Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2128Inst", FIELD_dsp340050b49a6c_fld2128Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2129Inst", FIELD_dsp340050b49a6c_fld2129Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2131Inst", FIELD_dsp340050b49a6c_fld2131Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2132Inst", FIELD_dsp340050b49a6c_fld2132Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2133Inst", FIELD_dsp340050b49a6c_fld2133Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2134Inst", FIELD_dsp340050b49a6c_fld2134Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2136Inst", FIELD_dsp340050b49a6c_fld2136Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2137Inst", FIELD_dsp340050b49a6c_fld2137Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2138Inst", FIELD_dsp340050b49a6c_fld2138Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2139Inst", FIELD_dsp340050b49a6c_fld2139Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2140Inst", FIELD_dsp340050b49a6c_fld2140Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2141Inst", FIELD_dsp340050b49a6c_fld2141Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2142Inst", FIELD_dsp340050b49a6c_fld2142Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2143Inst", FIELD_dsp340050b49a6c_fld2143Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2144Inst", FIELD_dsp340050b49a6c_fld2144Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2145Inst", FIELD_dsp340050b49a6c_fld2145Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2146Inst", FIELD_dsp340050b49a6c_fld2146Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2147Inst", FIELD_dsp340050b49a6c_fld2147Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2149Inst", FIELD_dsp340050b49a6c_fld2149Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2151Inst", FIELD_dsp340050b49a6c_fld2151Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2153Inst", FIELD_dsp340050b49a6c_fld2153Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2154Inst", FIELD_dsp340050b49a6c_fld2154Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2155Inst", FIELD_dsp340050b49a6c_fld2155Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2156Inst", FIELD_dsp340050b49a6c_fld2156Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2157Inst", FIELD_dsp340050b49a6c_fld2157Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2158Inst", FIELD_dsp340050b49a6c_fld2158Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2159Inst", FIELD_dsp340050b49a6c_fld2159Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2160Inst", FIELD_dsp340050b49a6c_fld2160Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2161Inst", FIELD_dsp340050b49a6c_fld2161Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2162Inst", FIELD_dsp340050b49a6c_fld2162Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2163Inst", FIELD_dsp340050b49a6c_fld2163Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2164Inst", FIELD_dsp340050b49a6c_fld2164Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2165Inst", FIELD_dsp340050b49a6c_fld2165Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2166Inst", FIELD_dsp340050b49a6c_fld2166Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2167Inst", FIELD_dsp340050b49a6c_fld2167Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2168Inst", FIELD_dsp340050b49a6c_fld2168Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2169Inst", FIELD_dsp340050b49a6c_fld2169Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2171Inst", FIELD_dsp340050b49a6c_fld2171Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2172Inst", FIELD_dsp340050b49a6c_fld2172Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2173Inst", FIELD_dsp340050b49a6c_fld2173Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2174Inst", FIELD_dsp340050b49a6c_fld2174Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2175Inst", FIELD_dsp340050b49a6c_fld2175Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2177Inst", FIELD_dsp340050b49a6c_fld2177Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2178Inst", FIELD_dsp340050b49a6c_fld2178Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2179Inst", FIELD_dsp340050b49a6c_fld2179Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2180Inst", FIELD_dsp340050b49a6c_fld2180Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2181Inst", FIELD_dsp340050b49a6c_fld2181Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2182Inst", FIELD_dsp340050b49a6c_fld2182Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2183Inst", FIELD_dsp340050b49a6c_fld2183Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2184Inst", FIELD_dsp340050b49a6c_fld2184Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2185Inst", FIELD_dsp340050b49a6c_fld2185Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2186Inst", FIELD_dsp340050b49a6c_fld2186Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2187Inst", FIELD_dsp340050b49a6c_fld2187Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2188Inst", FIELD_dsp340050b49a6c_fld2188Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2189Inst", FIELD_dsp340050b49a6c_fld2189Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2190Inst", FIELD_dsp340050b49a6c_fld2190Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2191Inst", FIELD_dsp340050b49a6c_fld2191Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2192Inst", FIELD_dsp340050b49a6c_fld2192Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2193Inst", FIELD_dsp340050b49a6c_fld2193Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2194Inst", FIELD_dsp340050b49a6c_fld2194Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2195Inst", FIELD_dsp340050b49a6c_fld2195Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2196Inst", FIELD_dsp340050b49a6c_fld2196Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2197Inst", FIELD_dsp340050b49a6c_fld2197Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2198Inst", FIELD_dsp340050b49a6c_fld2198Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2199Inst", FIELD_dsp340050b49a6c_fld2199Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2200Inst", FIELD_dsp340050b49a6c_fld2200Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2201Inst", FIELD_dsp340050b49a6c_fld2201Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2202Inst", FIELD_dsp340050b49a6c_fld2202Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2203Inst", FIELD_dsp340050b49a6c_fld2203Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2204Inst", FIELD_dsp340050b49a6c_fld2204Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2205Inst", FIELD_dsp340050b49a6c_fld2205Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2206Inst", FIELD_dsp340050b49a6c_fld2206Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2207Inst", FIELD_dsp340050b49a6c_fld2207Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2208Inst", FIELD_dsp340050b49a6c_fld2208Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2209Inst", FIELD_dsp340050b49a6c_fld2209Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2210Inst", FIELD_dsp340050b49a6c_fld2210Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2211Inst", FIELD_dsp340050b49a6c_fld2211Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2212Inst", FIELD_dsp340050b49a6c_fld2212Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2213Inst", FIELD_dsp340050b49a6c_fld2213Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2214Inst", FIELD_dsp340050b49a6c_fld2214Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2215Inst", FIELD_dsp340050b49a6c_fld2215Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2216Inst", FIELD_dsp340050b49a6c_fld2216Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2217Inst", FIELD_dsp340050b49a6c_fld2217Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2218Inst", FIELD_dsp340050b49a6c_fld2218Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2219Inst", FIELD_dsp340050b49a6c_fld2219Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2220Inst", FIELD_dsp340050b49a6c_fld2220Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2221Inst", FIELD_dsp340050b49a6c_fld2221Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2222Inst", FIELD_dsp340050b49a6c_fld2222Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2223Inst", FIELD_dsp340050b49a6c_fld2223Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2224Inst", FIELD_dsp340050b49a6c_fld2224Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2225Inst", FIELD_dsp340050b49a6c_fld2225Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2226Inst", FIELD_dsp340050b49a6c_fld2226Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2227Inst", FIELD_dsp340050b49a6c_fld2227Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2228Inst", FIELD_dsp340050b49a6c_fld2228Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2229Inst", FIELD_dsp340050b49a6c_fld2229Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2230Inst", FIELD_dsp340050b49a6c_fld2230Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2231Inst", FIELD_dsp340050b49a6c_fld2231Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2232Inst", FIELD_dsp340050b49a6c_fld2232Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2234Inst", FIELD_dsp340050b49a6c_fld2234Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2235Inst", FIELD_dsp340050b49a6c_fld2235Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2236Inst", FIELD_dsp340050b49a6c_fld2236Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2237Inst", FIELD_dsp340050b49a6c_fld2237Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2238Inst", FIELD_dsp340050b49a6c_fld2238Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2239Inst", FIELD_dsp340050b49a6c_fld2239Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2240Inst", FIELD_dsp340050b49a6c_fld2240Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2241Inst", FIELD_dsp340050b49a6c_fld2241Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2242Inst", FIELD_dsp340050b49a6c_fld2242Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2243Inst", FIELD_dsp340050b49a6c_fld2243Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2244Inst", FIELD_dsp340050b49a6c_fld2244Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2245Inst", FIELD_dsp340050b49a6c_fld2245Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2246Inst", FIELD_dsp340050b49a6c_fld2246Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2247Inst", FIELD_dsp340050b49a6c_fld2247Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2248Inst", FIELD_dsp340050b49a6c_fld2248Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2249Inst", FIELD_dsp340050b49a6c_fld2249Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2250Inst", FIELD_dsp340050b49a6c_fld2250Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2251Inst", FIELD_dsp340050b49a6c_fld2251Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2252Inst", FIELD_dsp340050b49a6c_fld2252Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2253Inst", FIELD_dsp340050b49a6c_fld2253Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2254", FIELD_dsp340050b49a6c_fld2254, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2255Inst", FIELD_dsp340050b49a6c_fld2255Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2257Inst", FIELD_dsp340050b49a6c_fld2257Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3627Inst", FIELD_dsp340050b49a6c_fld3627Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3630Inst", FIELD_dsp340050b49a6c_fld3630Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3631Inst", FIELD_dsp340050b49a6c_fld3631Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3633Inst", FIELD_dsp340050b49a6c_fld3633Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3634", FIELD_dsp340050b49a6c_fld3634, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3635Inst", FIELD_dsp340050b49a6c_fld3635Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3636Inst", FIELD_dsp340050b49a6c_fld3636Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3637Inst", FIELD_dsp340050b49a6c_fld3637Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3638Inst", FIELD_dsp340050b49a6c_fld3638Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3639Inst", FIELD_dsp340050b49a6c_fld3639Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3640Inst", FIELD_dsp340050b49a6c_fld3640Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3642Inst", FIELD_dsp340050b49a6c_fld3642Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3643Inst", FIELD_dsp340050b49a6c_fld3643Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3644Inst", FIELD_dsp340050b49a6c_fld3644Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3645Inst", FIELD_dsp340050b49a6c_fld3645Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3647Inst", FIELD_dsp340050b49a6c_fld3647Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3648Inst", FIELD_dsp340050b49a6c_fld3648Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3649Inst", FIELD_dsp340050b49a6c_fld3649Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3650Inst", FIELD_dsp340050b49a6c_fld3650Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3651Inst", FIELD_dsp340050b49a6c_fld3651Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3653Inst", FIELD_dsp340050b49a6c_fld3653Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3654Inst", FIELD_dsp340050b49a6c_fld3654Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3655Inst", FIELD_dsp340050b49a6c_fld3655Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3656Inst", FIELD_dsp340050b49a6c_fld3656Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3657Inst", FIELD_dsp340050b49a6c_fld3657Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3658Inst", FIELD_dsp340050b49a6c_fld3658Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3659Inst", FIELD_dsp340050b49a6c_fld3659Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3660Inst", FIELD_dsp340050b49a6c_fld3660Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3661Inst", FIELD_dsp340050b49a6c_fld3661Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3662Inst", FIELD_dsp340050b49a6c_fld3662Inst, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2025", FIELD_dsp340050b49a6c_fld2025, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2027", FIELD_dsp340050b49a6c_fld2027, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2258GP_slot2", FIELD_dsp340050b49a6c_fld2258GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2259GP_slot2", FIELD_dsp340050b49a6c_fld2259GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2260GP_slot2", FIELD_dsp340050b49a6c_fld2260GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2261GP_slot2", FIELD_dsp340050b49a6c_fld2261GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2262GP_slot2", FIELD_dsp340050b49a6c_fld2262GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2263GP_slot2", FIELD_dsp340050b49a6c_fld2263GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2264GP_slot2", FIELD_dsp340050b49a6c_fld2264GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2266GP_slot2", FIELD_dsp340050b49a6c_fld2266GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2267GP_slot2", FIELD_dsp340050b49a6c_fld2267GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2268GP_slot2", FIELD_dsp340050b49a6c_fld2268GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2269GP_slot2", FIELD_dsp340050b49a6c_fld2269GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2270GP_slot2", FIELD_dsp340050b49a6c_fld2270GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2271GP_slot2", FIELD_dsp340050b49a6c_fld2271GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2272", FIELD_dsp340050b49a6c_fld2272, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2273GP_slot2", FIELD_dsp340050b49a6c_fld2273GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2274GP_slot2", FIELD_dsp340050b49a6c_fld2274GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2275GP_slot2", FIELD_dsp340050b49a6c_fld2275GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2277GP_slot2", FIELD_dsp340050b49a6c_fld2277GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2278GP_slot2", FIELD_dsp340050b49a6c_fld2278GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2279GP_slot2", FIELD_dsp340050b49a6c_fld2279GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2280GP_slot2", FIELD_dsp340050b49a6c_fld2280GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2281GP_slot2", FIELD_dsp340050b49a6c_fld2281GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2282GP_slot2", FIELD_dsp340050b49a6c_fld2282GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2283GP_slot2", FIELD_dsp340050b49a6c_fld2283GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2284GP_slot2", FIELD_dsp340050b49a6c_fld2284GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2286GP_slot2", FIELD_dsp340050b49a6c_fld2286GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2287GP_slot2", FIELD_dsp340050b49a6c_fld2287GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2288GP_slot2", FIELD_dsp340050b49a6c_fld2288GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2289GP_slot2", FIELD_dsp340050b49a6c_fld2289GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2290GP_slot2", FIELD_dsp340050b49a6c_fld2290GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2291GP_slot2", FIELD_dsp340050b49a6c_fld2291GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2292GP_slot2", FIELD_dsp340050b49a6c_fld2292GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2293GP_slot2", FIELD_dsp340050b49a6c_fld2293GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2294GP_slot2", FIELD_dsp340050b49a6c_fld2294GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2295GP_slot2", FIELD_dsp340050b49a6c_fld2295GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2296GP_slot2", FIELD_dsp340050b49a6c_fld2296GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2297GP_slot2", FIELD_dsp340050b49a6c_fld2297GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2298GP_slot2", FIELD_dsp340050b49a6c_fld2298GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2299GP_slot2", FIELD_dsp340050b49a6c_fld2299GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2300GP_slot2", FIELD_dsp340050b49a6c_fld2300GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2301GP_slot2", FIELD_dsp340050b49a6c_fld2301GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2302", FIELD_dsp340050b49a6c_fld2302, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2303GP_slot2", FIELD_dsp340050b49a6c_fld2303GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2304GP_slot2", FIELD_dsp340050b49a6c_fld2304GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2305", FIELD_dsp340050b49a6c_fld2305, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2306GP_slot2", FIELD_dsp340050b49a6c_fld2306GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2308GP_slot2", FIELD_dsp340050b49a6c_fld2308GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2309GP_slot2", FIELD_dsp340050b49a6c_fld2309GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2310GP_slot2", FIELD_dsp340050b49a6c_fld2310GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2312GP_slot2", FIELD_dsp340050b49a6c_fld2312GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2313", FIELD_dsp340050b49a6c_fld2313, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2314GP_slot2", FIELD_dsp340050b49a6c_fld2314GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2316GP_slot2", FIELD_dsp340050b49a6c_fld2316GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2317GP_slot2", FIELD_dsp340050b49a6c_fld2317GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2318GP_slot2", FIELD_dsp340050b49a6c_fld2318GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2319GP_slot2", FIELD_dsp340050b49a6c_fld2319GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2320GP_slot2", FIELD_dsp340050b49a6c_fld2320GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2321GP_slot2", FIELD_dsp340050b49a6c_fld2321GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2322GP_slot2", FIELD_dsp340050b49a6c_fld2322GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2323GP_slot2", FIELD_dsp340050b49a6c_fld2323GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2324GP_slot2", FIELD_dsp340050b49a6c_fld2324GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2325GP_slot2", FIELD_dsp340050b49a6c_fld2325GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2326GP_slot2", FIELD_dsp340050b49a6c_fld2326GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2327GP_slot2", FIELD_dsp340050b49a6c_fld2327GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2328GP_slot2", FIELD_dsp340050b49a6c_fld2328GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2329GP_slot2", FIELD_dsp340050b49a6c_fld2329GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2330GP_slot2", FIELD_dsp340050b49a6c_fld2330GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2331GP_slot2", FIELD_dsp340050b49a6c_fld2331GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2332GP_slot2", FIELD_dsp340050b49a6c_fld2332GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2333GP_slot2", FIELD_dsp340050b49a6c_fld2333GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2334GP_slot2", FIELD_dsp340050b49a6c_fld2334GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2335GP_slot2", FIELD_dsp340050b49a6c_fld2335GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2336GP_slot2", FIELD_dsp340050b49a6c_fld2336GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2337GP_slot2", FIELD_dsp340050b49a6c_fld2337GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2338GP_slot2", FIELD_dsp340050b49a6c_fld2338GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2339GP_slot2", FIELD_dsp340050b49a6c_fld2339GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2340GP_slot2", FIELD_dsp340050b49a6c_fld2340GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2341GP_slot2", FIELD_dsp340050b49a6c_fld2341GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2342GP_slot2", FIELD_dsp340050b49a6c_fld2342GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2343GP_slot2", FIELD_dsp340050b49a6c_fld2343GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2344GP_slot2", FIELD_dsp340050b49a6c_fld2344GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2345GP_slot2", FIELD_dsp340050b49a6c_fld2345GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2346GP_slot2", FIELD_dsp340050b49a6c_fld2346GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2347GP_slot2", FIELD_dsp340050b49a6c_fld2347GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2348GP_slot2", FIELD_dsp340050b49a6c_fld2348GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2349GP_slot2", FIELD_dsp340050b49a6c_fld2349GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2350GP_slot2", FIELD_dsp340050b49a6c_fld2350GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2351GP_slot2", FIELD_dsp340050b49a6c_fld2351GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2352GP_slot2", FIELD_dsp340050b49a6c_fld2352GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2353GP_slot2", FIELD_dsp340050b49a6c_fld2353GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2354GP_slot2", FIELD_dsp340050b49a6c_fld2354GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2355GP_slot2", FIELD_dsp340050b49a6c_fld2355GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2356GP_slot2", FIELD_dsp340050b49a6c_fld2356GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2357GP_slot2", FIELD_dsp340050b49a6c_fld2357GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2358GP_slot2", FIELD_dsp340050b49a6c_fld2358GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2359GP_slot2", FIELD_dsp340050b49a6c_fld2359GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2361GP_slot2", FIELD_dsp340050b49a6c_fld2361GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2362GP_slot2", FIELD_dsp340050b49a6c_fld2362GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2364GP_slot2", FIELD_dsp340050b49a6c_fld2364GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2366GP_slot2", FIELD_dsp340050b49a6c_fld2366GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2368GP_slot2", FIELD_dsp340050b49a6c_fld2368GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2369GP_slot2", FIELD_dsp340050b49a6c_fld2369GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2370GP_slot2", FIELD_dsp340050b49a6c_fld2370GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2371GP_slot2", FIELD_dsp340050b49a6c_fld2371GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2372GP_slot2", FIELD_dsp340050b49a6c_fld2372GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2373GP_slot2", FIELD_dsp340050b49a6c_fld2373GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2374GP_slot2", FIELD_dsp340050b49a6c_fld2374GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2375GP_slot2", FIELD_dsp340050b49a6c_fld2375GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2376GP_slot2", FIELD_dsp340050b49a6c_fld2376GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2378GP_slot2", FIELD_dsp340050b49a6c_fld2378GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2379GP_slot2", FIELD_dsp340050b49a6c_fld2379GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2381GP_slot2", FIELD_dsp340050b49a6c_fld2381GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2383GP_slot2", FIELD_dsp340050b49a6c_fld2383GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2384", FIELD_dsp340050b49a6c_fld2384, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2385GP_slot2", FIELD_dsp340050b49a6c_fld2385GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2386", FIELD_dsp340050b49a6c_fld2386, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2387GP_slot2", FIELD_dsp340050b49a6c_fld2387GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2388GP_slot2", FIELD_dsp340050b49a6c_fld2388GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2389GP_slot2", FIELD_dsp340050b49a6c_fld2389GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3663GP_slot2", FIELD_dsp340050b49a6c_fld3663GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3664GP_slot2", FIELD_dsp340050b49a6c_fld3664GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3665GP_slot2", FIELD_dsp340050b49a6c_fld3665GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3666", FIELD_dsp340050b49a6c_fld3666, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3667GP_slot2", FIELD_dsp340050b49a6c_fld3667GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3668GP_slot2", FIELD_dsp340050b49a6c_fld3668GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3669GP_slot2", FIELD_dsp340050b49a6c_fld3669GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3670GP_slot2", FIELD_dsp340050b49a6c_fld3670GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3671GP_slot2", FIELD_dsp340050b49a6c_fld3671GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3673GP_slot2", FIELD_dsp340050b49a6c_fld3673GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3674GP_slot2", FIELD_dsp340050b49a6c_fld3674GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3675GP_slot2", FIELD_dsp340050b49a6c_fld3675GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3676GP_slot2", FIELD_dsp340050b49a6c_fld3676GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3678GP_slot2", FIELD_dsp340050b49a6c_fld3678GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3679GP_slot2", FIELD_dsp340050b49a6c_fld3679GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3680GP_slot2", FIELD_dsp340050b49a6c_fld3680GP_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s4", FIELD_op0_s4, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2026", FIELD_dsp340050b49a6c_fld2026, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2031", FIELD_dsp340050b49a6c_fld2031, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2394GP_slot1", FIELD_dsp340050b49a6c_fld2394GP_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2395GP_slot1", FIELD_dsp340050b49a6c_fld2395GP_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2397GP_slot1", FIELD_dsp340050b49a6c_fld2397GP_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2398GP_slot1", FIELD_dsp340050b49a6c_fld2398GP_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2399GP_slot1", FIELD_dsp340050b49a6c_fld2399GP_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2400GP_slot1", FIELD_dsp340050b49a6c_fld2400GP_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2402GP_slot1", FIELD_dsp340050b49a6c_fld2402GP_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2403GP_slot1", FIELD_dsp340050b49a6c_fld2403GP_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2405GP_slot1", FIELD_dsp340050b49a6c_fld2405GP_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3681GP_slot1", FIELD_dsp340050b49a6c_fld3681GP_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3683GP_slot1", FIELD_dsp340050b49a6c_fld3683GP_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3684GP_slot1", FIELD_dsp340050b49a6c_fld3684GP_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3686GP_slot1", FIELD_dsp340050b49a6c_fld3686GP_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s5", FIELD_op0_s5, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2058", FIELD_dsp340050b49a6c_fld2058, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2067", FIELD_dsp340050b49a6c_fld2067, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2407GP_slot0", FIELD_dsp340050b49a6c_fld2407GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2409GP_slot0", FIELD_dsp340050b49a6c_fld2409GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2410GP_slot0", FIELD_dsp340050b49a6c_fld2410GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2411GP_slot0", FIELD_dsp340050b49a6c_fld2411GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2412GP_slot0", FIELD_dsp340050b49a6c_fld2412GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2413GP_slot0", FIELD_dsp340050b49a6c_fld2413GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2415GP_slot0", FIELD_dsp340050b49a6c_fld2415GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2416GP_slot0", FIELD_dsp340050b49a6c_fld2416GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2417GP_slot0", FIELD_dsp340050b49a6c_fld2417GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2418GP_slot0", FIELD_dsp340050b49a6c_fld2418GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2419GP_slot0", FIELD_dsp340050b49a6c_fld2419GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2420GP_slot0", FIELD_dsp340050b49a6c_fld2420GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2422GP_slot0", FIELD_dsp340050b49a6c_fld2422GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2423GP_slot0", FIELD_dsp340050b49a6c_fld2423GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2424GP_slot0", FIELD_dsp340050b49a6c_fld2424GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2425GP_slot0", FIELD_dsp340050b49a6c_fld2425GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2426GP_slot0", FIELD_dsp340050b49a6c_fld2426GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2427GP_slot0", FIELD_dsp340050b49a6c_fld2427GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2429GP_slot0", FIELD_dsp340050b49a6c_fld2429GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2430GP_slot0", FIELD_dsp340050b49a6c_fld2430GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2431GP_slot0", FIELD_dsp340050b49a6c_fld2431GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2432GP_slot0", FIELD_dsp340050b49a6c_fld2432GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2433GP_slot0", FIELD_dsp340050b49a6c_fld2433GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2434GP_slot0", FIELD_dsp340050b49a6c_fld2434GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2435GP_slot0", FIELD_dsp340050b49a6c_fld2435GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2436GP_slot0", FIELD_dsp340050b49a6c_fld2436GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2437GP_slot0", FIELD_dsp340050b49a6c_fld2437GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2438GP_slot0", FIELD_dsp340050b49a6c_fld2438GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2439GP_slot0", FIELD_dsp340050b49a6c_fld2439GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2440GP_slot0", FIELD_dsp340050b49a6c_fld2440GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2441GP_slot0", FIELD_dsp340050b49a6c_fld2441GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2443GP_slot0", FIELD_dsp340050b49a6c_fld2443GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2444GP_slot0", FIELD_dsp340050b49a6c_fld2444GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2445", FIELD_dsp340050b49a6c_fld2445, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2447GP_slot0", FIELD_dsp340050b49a6c_fld2447GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2448", FIELD_dsp340050b49a6c_fld2448, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2449GP_slot0", FIELD_dsp340050b49a6c_fld2449GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2451GP_slot0", FIELD_dsp340050b49a6c_fld2451GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2452GP_slot0", FIELD_dsp340050b49a6c_fld2452GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2453GP_slot0", FIELD_dsp340050b49a6c_fld2453GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2454GP_slot0", FIELD_dsp340050b49a6c_fld2454GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2455GP_slot0", FIELD_dsp340050b49a6c_fld2455GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2456GP_slot0", FIELD_dsp340050b49a6c_fld2456GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2457GP_slot0", FIELD_dsp340050b49a6c_fld2457GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2458GP_slot0", FIELD_dsp340050b49a6c_fld2458GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2459GP_slot0", FIELD_dsp340050b49a6c_fld2459GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2460GP_slot0", FIELD_dsp340050b49a6c_fld2460GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2461GP_slot0", FIELD_dsp340050b49a6c_fld2461GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2462", FIELD_dsp340050b49a6c_fld2462, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2463GP_slot0", FIELD_dsp340050b49a6c_fld2463GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2464GP_slot0", FIELD_dsp340050b49a6c_fld2464GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2465GP_slot0", FIELD_dsp340050b49a6c_fld2465GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2466GP_slot0", FIELD_dsp340050b49a6c_fld2466GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2467GP_slot0", FIELD_dsp340050b49a6c_fld2467GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2468GP_slot0", FIELD_dsp340050b49a6c_fld2468GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2470GP_slot0", FIELD_dsp340050b49a6c_fld2470GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2471GP_slot0", FIELD_dsp340050b49a6c_fld2471GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2472GP_slot0", FIELD_dsp340050b49a6c_fld2472GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2473GP_slot0", FIELD_dsp340050b49a6c_fld2473GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2474GP_slot0", FIELD_dsp340050b49a6c_fld2474GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2475GP_slot0", FIELD_dsp340050b49a6c_fld2475GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2477GP_slot0", FIELD_dsp340050b49a6c_fld2477GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2479GP_slot0", FIELD_dsp340050b49a6c_fld2479GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2480GP_slot0", FIELD_dsp340050b49a6c_fld2480GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2481GP_slot0", FIELD_dsp340050b49a6c_fld2481GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2482GP_slot0", FIELD_dsp340050b49a6c_fld2482GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2483GP_slot0", FIELD_dsp340050b49a6c_fld2483GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2484GP_slot0", FIELD_dsp340050b49a6c_fld2484GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2485GP_slot0", FIELD_dsp340050b49a6c_fld2485GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2486GP_slot0", FIELD_dsp340050b49a6c_fld2486GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2487GP_slot0", FIELD_dsp340050b49a6c_fld2487GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2488GP_slot0", FIELD_dsp340050b49a6c_fld2488GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2489GP_slot0", FIELD_dsp340050b49a6c_fld2489GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2490GP_slot0", FIELD_dsp340050b49a6c_fld2490GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2491GP_slot0", FIELD_dsp340050b49a6c_fld2491GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2492GP_slot0", FIELD_dsp340050b49a6c_fld2492GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2493GP_slot0", FIELD_dsp340050b49a6c_fld2493GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2494GP_slot0", FIELD_dsp340050b49a6c_fld2494GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2495GP_slot0", FIELD_dsp340050b49a6c_fld2495GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2496GP_slot0", FIELD_dsp340050b49a6c_fld2496GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2497GP_slot0", FIELD_dsp340050b49a6c_fld2497GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2498GP_slot0", FIELD_dsp340050b49a6c_fld2498GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2499GP_slot0", FIELD_dsp340050b49a6c_fld2499GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2500GP_slot0", FIELD_dsp340050b49a6c_fld2500GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2501GP_slot0", FIELD_dsp340050b49a6c_fld2501GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2502GP_slot0", FIELD_dsp340050b49a6c_fld2502GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2503GP_slot0", FIELD_dsp340050b49a6c_fld2503GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2504GP_slot0", FIELD_dsp340050b49a6c_fld2504GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2505GP_slot0", FIELD_dsp340050b49a6c_fld2505GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2506GP_slot0", FIELD_dsp340050b49a6c_fld2506GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2507GP_slot0", FIELD_dsp340050b49a6c_fld2507GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2508GP_slot0", FIELD_dsp340050b49a6c_fld2508GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2509GP_slot0", FIELD_dsp340050b49a6c_fld2509GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2510GP_slot0", FIELD_dsp340050b49a6c_fld2510GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2512GP_slot0", FIELD_dsp340050b49a6c_fld2512GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2514GP_slot0", FIELD_dsp340050b49a6c_fld2514GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2515GP_slot0", FIELD_dsp340050b49a6c_fld2515GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2516GP_slot0", FIELD_dsp340050b49a6c_fld2516GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2517GP_slot0", FIELD_dsp340050b49a6c_fld2517GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2518GP_slot0", FIELD_dsp340050b49a6c_fld2518GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2519GP_slot0", FIELD_dsp340050b49a6c_fld2519GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2520GP_slot0", FIELD_dsp340050b49a6c_fld2520GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2521GP_slot0", FIELD_dsp340050b49a6c_fld2521GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2523GP_slot0", FIELD_dsp340050b49a6c_fld2523GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2524GP_slot0", FIELD_dsp340050b49a6c_fld2524GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2526GP_slot0", FIELD_dsp340050b49a6c_fld2526GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2527GP_slot0", FIELD_dsp340050b49a6c_fld2527GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2528GP_slot0", FIELD_dsp340050b49a6c_fld2528GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2529GP_slot0", FIELD_dsp340050b49a6c_fld2529GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2530", FIELD_dsp340050b49a6c_fld2530, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2531GP_slot0", FIELD_dsp340050b49a6c_fld2531GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3688GP_slot0", FIELD_dsp340050b49a6c_fld3688GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3689GP_slot0", FIELD_dsp340050b49a6c_fld3689GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3690GP_slot0", FIELD_dsp340050b49a6c_fld3690GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3691GP_slot0", FIELD_dsp340050b49a6c_fld3691GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3692GP_slot0", FIELD_dsp340050b49a6c_fld3692GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3693GP_slot0", FIELD_dsp340050b49a6c_fld3693GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3695GP_slot0", FIELD_dsp340050b49a6c_fld3695GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3696GP_slot0", FIELD_dsp340050b49a6c_fld3696GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3697GP_slot0", FIELD_dsp340050b49a6c_fld3697GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3698GP_slot0", FIELD_dsp340050b49a6c_fld3698GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3699GP_slot0", FIELD_dsp340050b49a6c_fld3699GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3700GP_slot0", FIELD_dsp340050b49a6c_fld3700GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3702GP_slot0", FIELD_dsp340050b49a6c_fld3702GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3703GP_slot0", FIELD_dsp340050b49a6c_fld3703GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3705GP_slot0", FIELD_dsp340050b49a6c_fld3705GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3706GP_slot0", FIELD_dsp340050b49a6c_fld3706GP_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s6", FIELD_op0_s6, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2532DOT_slot2", FIELD_dsp340050b49a6c_fld2532DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2533DOT_slot2", FIELD_dsp340050b49a6c_fld2533DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2534DOT_slot2", FIELD_dsp340050b49a6c_fld2534DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2535DOT_slot2", FIELD_dsp340050b49a6c_fld2535DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2536DOT_slot2", FIELD_dsp340050b49a6c_fld2536DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2537DOT_slot2", FIELD_dsp340050b49a6c_fld2537DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2538DOT_slot2", FIELD_dsp340050b49a6c_fld2538DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2539DOT_slot2", FIELD_dsp340050b49a6c_fld2539DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2540DOT_slot2", FIELD_dsp340050b49a6c_fld2540DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2541DOT_slot2", FIELD_dsp340050b49a6c_fld2541DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2542DOT_slot2", FIELD_dsp340050b49a6c_fld2542DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2543DOT_slot2", FIELD_dsp340050b49a6c_fld2543DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2544DOT_slot2", FIELD_dsp340050b49a6c_fld2544DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2545DOT_slot2", FIELD_dsp340050b49a6c_fld2545DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2546DOT_slot2", FIELD_dsp340050b49a6c_fld2546DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2547DOT_slot2", FIELD_dsp340050b49a6c_fld2547DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2548DOT_slot2", FIELD_dsp340050b49a6c_fld2548DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2549DOT_slot2", FIELD_dsp340050b49a6c_fld2549DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2550DOT_slot2", FIELD_dsp340050b49a6c_fld2550DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2551DOT_slot2", FIELD_dsp340050b49a6c_fld2551DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2552DOT_slot2", FIELD_dsp340050b49a6c_fld2552DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2553DOT_slot2", FIELD_dsp340050b49a6c_fld2553DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2554DOT_slot2", FIELD_dsp340050b49a6c_fld2554DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2555DOT_slot2", FIELD_dsp340050b49a6c_fld2555DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2556DOT_slot2", FIELD_dsp340050b49a6c_fld2556DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2557DOT_slot2", FIELD_dsp340050b49a6c_fld2557DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2558DOT_slot2", FIELD_dsp340050b49a6c_fld2558DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2559DOT_slot2", FIELD_dsp340050b49a6c_fld2559DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2560DOT_slot2", FIELD_dsp340050b49a6c_fld2560DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2561DOT_slot2", FIELD_dsp340050b49a6c_fld2561DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2562DOT_slot2", FIELD_dsp340050b49a6c_fld2562DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2563DOT_slot2", FIELD_dsp340050b49a6c_fld2563DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2564DOT_slot2", FIELD_dsp340050b49a6c_fld2564DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2565DOT_slot2", FIELD_dsp340050b49a6c_fld2565DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2566DOT_slot2", FIELD_dsp340050b49a6c_fld2566DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2567DOT_slot2", FIELD_dsp340050b49a6c_fld2567DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2568DOT_slot2", FIELD_dsp340050b49a6c_fld2568DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2569DOT_slot2", FIELD_dsp340050b49a6c_fld2569DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2571DOT_slot2", FIELD_dsp340050b49a6c_fld2571DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2572DOT_slot2", FIELD_dsp340050b49a6c_fld2572DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2573DOT_slot2", FIELD_dsp340050b49a6c_fld2573DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2574DOT_slot2", FIELD_dsp340050b49a6c_fld2574DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2575DOT_slot2", FIELD_dsp340050b49a6c_fld2575DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2576DOT_slot2", FIELD_dsp340050b49a6c_fld2576DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2577DOT_slot2", FIELD_dsp340050b49a6c_fld2577DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2578", FIELD_dsp340050b49a6c_fld2578, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2579DOT_slot2", FIELD_dsp340050b49a6c_fld2579DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2580DOT_slot2", FIELD_dsp340050b49a6c_fld2580DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2581DOT_slot2", FIELD_dsp340050b49a6c_fld2581DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2582DOT_slot2", FIELD_dsp340050b49a6c_fld2582DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2583DOT_slot2", FIELD_dsp340050b49a6c_fld2583DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2584DOT_slot2", FIELD_dsp340050b49a6c_fld2584DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2585DOT_slot2", FIELD_dsp340050b49a6c_fld2585DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2586DOT_slot2", FIELD_dsp340050b49a6c_fld2586DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2587DOT_slot2", FIELD_dsp340050b49a6c_fld2587DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2588DOT_slot2", FIELD_dsp340050b49a6c_fld2588DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2589DOT_slot2", FIELD_dsp340050b49a6c_fld2589DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2590DOT_slot2", FIELD_dsp340050b49a6c_fld2590DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2591DOT_slot2", FIELD_dsp340050b49a6c_fld2591DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2592DOT_slot2", FIELD_dsp340050b49a6c_fld2592DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2595DOT_slot2", FIELD_dsp340050b49a6c_fld2595DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2596DOT_slot2", FIELD_dsp340050b49a6c_fld2596DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2598DOT_slot2", FIELD_dsp340050b49a6c_fld2598DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2599DOT_slot2", FIELD_dsp340050b49a6c_fld2599DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2601DOT_slot2", FIELD_dsp340050b49a6c_fld2601DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2602DOT_slot2", FIELD_dsp340050b49a6c_fld2602DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2604DOT_slot2", FIELD_dsp340050b49a6c_fld2604DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2605", FIELD_dsp340050b49a6c_fld2605, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2606DOT_slot2", FIELD_dsp340050b49a6c_fld2606DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2608DOT_slot2", FIELD_dsp340050b49a6c_fld2608DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2609DOT_slot2", FIELD_dsp340050b49a6c_fld2609DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2610DOT_slot2", FIELD_dsp340050b49a6c_fld2610DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2611DOT_slot2", FIELD_dsp340050b49a6c_fld2611DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2612", FIELD_dsp340050b49a6c_fld2612, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2613DOT_slot2", FIELD_dsp340050b49a6c_fld2613DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2614", FIELD_dsp340050b49a6c_fld2614, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2615DOT_slot2", FIELD_dsp340050b49a6c_fld2615DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2616DOT_slot2", FIELD_dsp340050b49a6c_fld2616DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2617DOT_slot2", FIELD_dsp340050b49a6c_fld2617DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2618DOT_slot2", FIELD_dsp340050b49a6c_fld2618DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2619DOT_slot2", FIELD_dsp340050b49a6c_fld2619DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2620DOT_slot2", FIELD_dsp340050b49a6c_fld2620DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2621DOT_slot2", FIELD_dsp340050b49a6c_fld2621DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2622DOT_slot2", FIELD_dsp340050b49a6c_fld2622DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2623DOT_slot2", FIELD_dsp340050b49a6c_fld2623DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2624DOT_slot2", FIELD_dsp340050b49a6c_fld2624DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2625", FIELD_dsp340050b49a6c_fld2625, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2626DOT_slot2", FIELD_dsp340050b49a6c_fld2626DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2628DOT_slot2", FIELD_dsp340050b49a6c_fld2628DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2630DOT_slot2", FIELD_dsp340050b49a6c_fld2630DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2632DOT_slot2", FIELD_dsp340050b49a6c_fld2632DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2633DOT_slot2", FIELD_dsp340050b49a6c_fld2633DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2635DOT_slot2", FIELD_dsp340050b49a6c_fld2635DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2636DOT_slot2", FIELD_dsp340050b49a6c_fld2636DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2637DOT_slot2", FIELD_dsp340050b49a6c_fld2637DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2640DOT_slot2", FIELD_dsp340050b49a6c_fld2640DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2641DOT_slot2", FIELD_dsp340050b49a6c_fld2641DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2642DOT_slot2", FIELD_dsp340050b49a6c_fld2642DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2643DOT_slot2", FIELD_dsp340050b49a6c_fld2643DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2644DOT_slot2", FIELD_dsp340050b49a6c_fld2644DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2645DOT_slot2", FIELD_dsp340050b49a6c_fld2645DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2646DOT_slot2", FIELD_dsp340050b49a6c_fld2646DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2647DOT_slot2", FIELD_dsp340050b49a6c_fld2647DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2648DOT_slot2", FIELD_dsp340050b49a6c_fld2648DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2649DOT_slot2", FIELD_dsp340050b49a6c_fld2649DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2650DOT_slot2", FIELD_dsp340050b49a6c_fld2650DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2651DOT_slot2", FIELD_dsp340050b49a6c_fld2651DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2652DOT_slot2", FIELD_dsp340050b49a6c_fld2652DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2654DOT_slot2", FIELD_dsp340050b49a6c_fld2654DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2655DOT_slot2", FIELD_dsp340050b49a6c_fld2655DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2656DOT_slot2", FIELD_dsp340050b49a6c_fld2656DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2657DOT_slot2", FIELD_dsp340050b49a6c_fld2657DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2658DOT_slot2", FIELD_dsp340050b49a6c_fld2658DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3708DOT_slot2", FIELD_dsp340050b49a6c_fld3708DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3709DOT_slot2", FIELD_dsp340050b49a6c_fld3709DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3710DOT_slot2", FIELD_dsp340050b49a6c_fld3710DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3711DOT_slot2", FIELD_dsp340050b49a6c_fld3711DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3712", FIELD_dsp340050b49a6c_fld3712, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3713DOT_slot2", FIELD_dsp340050b49a6c_fld3713DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3714DOT_slot2", FIELD_dsp340050b49a6c_fld3714DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3715", FIELD_dsp340050b49a6c_fld3715, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3716DOT_slot2", FIELD_dsp340050b49a6c_fld3716DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3717DOT_slot2", FIELD_dsp340050b49a6c_fld3717DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3718", FIELD_dsp340050b49a6c_fld3718, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3719DOT_slot2", FIELD_dsp340050b49a6c_fld3719DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3721DOT_slot2", FIELD_dsp340050b49a6c_fld3721DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3722", FIELD_dsp340050b49a6c_fld3722, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3723DOT_slot2", FIELD_dsp340050b49a6c_fld3723DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3724DOT_slot2", FIELD_dsp340050b49a6c_fld3724DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3725DOT_slot2", FIELD_dsp340050b49a6c_fld3725DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3726DOT_slot2", FIELD_dsp340050b49a6c_fld3726DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3727DOT_slot2", FIELD_dsp340050b49a6c_fld3727DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3728DOT_slot2", FIELD_dsp340050b49a6c_fld3728DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3729DOT_slot2", FIELD_dsp340050b49a6c_fld3729DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3731DOT_slot2", FIELD_dsp340050b49a6c_fld3731DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3732DOT_slot2", FIELD_dsp340050b49a6c_fld3732DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3733DOT_slot2", FIELD_dsp340050b49a6c_fld3733DOT_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s7", FIELD_op0_s7, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3734DOT_slot1", FIELD_dsp340050b49a6c_fld3734DOT_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s8", FIELD_op0_s8, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2068", FIELD_dsp340050b49a6c_fld2068, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2666DOT_slot0", FIELD_dsp340050b49a6c_fld2666DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2667DOT_slot0", FIELD_dsp340050b49a6c_fld2667DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2668DOT_slot0", FIELD_dsp340050b49a6c_fld2668DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2669DOT_slot0", FIELD_dsp340050b49a6c_fld2669DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2671DOT_slot0", FIELD_dsp340050b49a6c_fld2671DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2672DOT_slot0", FIELD_dsp340050b49a6c_fld2672DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2673DOT_slot0", FIELD_dsp340050b49a6c_fld2673DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2674DOT_slot0", FIELD_dsp340050b49a6c_fld2674DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2675DOT_slot0", FIELD_dsp340050b49a6c_fld2675DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2676DOT_slot0", FIELD_dsp340050b49a6c_fld2676DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2677DOT_slot0", FIELD_dsp340050b49a6c_fld2677DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2678DOT_slot0", FIELD_dsp340050b49a6c_fld2678DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2679DOT_slot0", FIELD_dsp340050b49a6c_fld2679DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2680DOT_slot0", FIELD_dsp340050b49a6c_fld2680DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2681DOT_slot0", FIELD_dsp340050b49a6c_fld2681DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2682DOT_slot0", FIELD_dsp340050b49a6c_fld2682DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2683DOT_slot0", FIELD_dsp340050b49a6c_fld2683DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2684DOT_slot0", FIELD_dsp340050b49a6c_fld2684DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2685DOT_slot0", FIELD_dsp340050b49a6c_fld2685DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2686DOT_slot0", FIELD_dsp340050b49a6c_fld2686DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2688DOT_slot0", FIELD_dsp340050b49a6c_fld2688DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2689DOT_slot0", FIELD_dsp340050b49a6c_fld2689DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2690DOT_slot0", FIELD_dsp340050b49a6c_fld2690DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2692DOT_slot0", FIELD_dsp340050b49a6c_fld2692DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2693DOT_slot0", FIELD_dsp340050b49a6c_fld2693DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2695DOT_slot0", FIELD_dsp340050b49a6c_fld2695DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2697DOT_slot0", FIELD_dsp340050b49a6c_fld2697DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2699DOT_slot0", FIELD_dsp340050b49a6c_fld2699DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2700DOT_slot0", FIELD_dsp340050b49a6c_fld2700DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2701DOT_slot0", FIELD_dsp340050b49a6c_fld2701DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2702DOT_slot0", FIELD_dsp340050b49a6c_fld2702DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2703DOT_slot0", FIELD_dsp340050b49a6c_fld2703DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2704DOT_slot0", FIELD_dsp340050b49a6c_fld2704DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2705DOT_slot0", FIELD_dsp340050b49a6c_fld2705DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3735DOT_slot0", FIELD_dsp340050b49a6c_fld3735DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3736", FIELD_dsp340050b49a6c_fld3736, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3737DOT_slot0", FIELD_dsp340050b49a6c_fld3737DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3738DOT_slot0", FIELD_dsp340050b49a6c_fld3738DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3739DOT_slot0", FIELD_dsp340050b49a6c_fld3739DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3740DOT_slot0", FIELD_dsp340050b49a6c_fld3740DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3741DOT_slot0", FIELD_dsp340050b49a6c_fld3741DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3742DOT_slot0", FIELD_dsp340050b49a6c_fld3742DOT_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s9", FIELD_op0_s9, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2706PQ_slot2", FIELD_dsp340050b49a6c_fld2706PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2707PQ_slot2", FIELD_dsp340050b49a6c_fld2707PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2708PQ_slot2", FIELD_dsp340050b49a6c_fld2708PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2709PQ_slot2", FIELD_dsp340050b49a6c_fld2709PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2710PQ_slot2", FIELD_dsp340050b49a6c_fld2710PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2711PQ_slot2", FIELD_dsp340050b49a6c_fld2711PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2713PQ_slot2", FIELD_dsp340050b49a6c_fld2713PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2714PQ_slot2", FIELD_dsp340050b49a6c_fld2714PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2715PQ_slot2", FIELD_dsp340050b49a6c_fld2715PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2717PQ_slot2", FIELD_dsp340050b49a6c_fld2717PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2718PQ_slot2", FIELD_dsp340050b49a6c_fld2718PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2719PQ_slot2", FIELD_dsp340050b49a6c_fld2719PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2721PQ_slot2", FIELD_dsp340050b49a6c_fld2721PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2722PQ_slot2", FIELD_dsp340050b49a6c_fld2722PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2723PQ_slot2", FIELD_dsp340050b49a6c_fld2723PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2724PQ_slot2", FIELD_dsp340050b49a6c_fld2724PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2725PQ_slot2", FIELD_dsp340050b49a6c_fld2725PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2726PQ_slot2", FIELD_dsp340050b49a6c_fld2726PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2727PQ_slot2", FIELD_dsp340050b49a6c_fld2727PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2728PQ_slot2", FIELD_dsp340050b49a6c_fld2728PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2729PQ_slot2", FIELD_dsp340050b49a6c_fld2729PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2730PQ_slot2", FIELD_dsp340050b49a6c_fld2730PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2731PQ_slot2", FIELD_dsp340050b49a6c_fld2731PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2732PQ_slot2", FIELD_dsp340050b49a6c_fld2732PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2733PQ_slot2", FIELD_dsp340050b49a6c_fld2733PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2734PQ_slot2", FIELD_dsp340050b49a6c_fld2734PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2735PQ_slot2", FIELD_dsp340050b49a6c_fld2735PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2736PQ_slot2", FIELD_dsp340050b49a6c_fld2736PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2737", FIELD_dsp340050b49a6c_fld2737, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2738PQ_slot2", FIELD_dsp340050b49a6c_fld2738PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2739PQ_slot2", FIELD_dsp340050b49a6c_fld2739PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2741PQ_slot2", FIELD_dsp340050b49a6c_fld2741PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2742PQ_slot2", FIELD_dsp340050b49a6c_fld2742PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2743PQ_slot2", FIELD_dsp340050b49a6c_fld2743PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2746PQ_slot2", FIELD_dsp340050b49a6c_fld2746PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2747PQ_slot2", FIELD_dsp340050b49a6c_fld2747PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2748PQ_slot2", FIELD_dsp340050b49a6c_fld2748PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2750PQ_slot2", FIELD_dsp340050b49a6c_fld2750PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2751PQ_slot2", FIELD_dsp340050b49a6c_fld2751PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2752PQ_slot2", FIELD_dsp340050b49a6c_fld2752PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2753PQ_slot2", FIELD_dsp340050b49a6c_fld2753PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2754PQ_slot2", FIELD_dsp340050b49a6c_fld2754PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2755PQ_slot2", FIELD_dsp340050b49a6c_fld2755PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2756PQ_slot2", FIELD_dsp340050b49a6c_fld2756PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2757PQ_slot2", FIELD_dsp340050b49a6c_fld2757PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2758PQ_slot2", FIELD_dsp340050b49a6c_fld2758PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2759PQ_slot2", FIELD_dsp340050b49a6c_fld2759PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2760PQ_slot2", FIELD_dsp340050b49a6c_fld2760PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2761PQ_slot2", FIELD_dsp340050b49a6c_fld2761PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2762PQ_slot2", FIELD_dsp340050b49a6c_fld2762PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2763PQ_slot2", FIELD_dsp340050b49a6c_fld2763PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2764PQ_slot2", FIELD_dsp340050b49a6c_fld2764PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2765PQ_slot2", FIELD_dsp340050b49a6c_fld2765PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2766PQ_slot2", FIELD_dsp340050b49a6c_fld2766PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2767PQ_slot2", FIELD_dsp340050b49a6c_fld2767PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2768PQ_slot2", FIELD_dsp340050b49a6c_fld2768PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2769PQ_slot2", FIELD_dsp340050b49a6c_fld2769PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2770PQ_slot2", FIELD_dsp340050b49a6c_fld2770PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2771PQ_slot2", FIELD_dsp340050b49a6c_fld2771PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2772PQ_slot2", FIELD_dsp340050b49a6c_fld2772PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2773PQ_slot2", FIELD_dsp340050b49a6c_fld2773PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2774PQ_slot2", FIELD_dsp340050b49a6c_fld2774PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2775PQ_slot2", FIELD_dsp340050b49a6c_fld2775PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2776PQ_slot2", FIELD_dsp340050b49a6c_fld2776PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2777PQ_slot2", FIELD_dsp340050b49a6c_fld2777PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2778PQ_slot2", FIELD_dsp340050b49a6c_fld2778PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2779PQ_slot2", FIELD_dsp340050b49a6c_fld2779PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2780PQ_slot2", FIELD_dsp340050b49a6c_fld2780PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2781PQ_slot2", FIELD_dsp340050b49a6c_fld2781PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2782PQ_slot2", FIELD_dsp340050b49a6c_fld2782PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2783PQ_slot2", FIELD_dsp340050b49a6c_fld2783PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2784PQ_slot2", FIELD_dsp340050b49a6c_fld2784PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2785PQ_slot2", FIELD_dsp340050b49a6c_fld2785PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2786PQ_slot2", FIELD_dsp340050b49a6c_fld2786PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2787PQ_slot2", FIELD_dsp340050b49a6c_fld2787PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2788PQ_slot2", FIELD_dsp340050b49a6c_fld2788PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2789PQ_slot2", FIELD_dsp340050b49a6c_fld2789PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2790PQ_slot2", FIELD_dsp340050b49a6c_fld2790PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2791PQ_slot2", FIELD_dsp340050b49a6c_fld2791PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2792PQ_slot2", FIELD_dsp340050b49a6c_fld2792PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2793PQ_slot2", FIELD_dsp340050b49a6c_fld2793PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2795PQ_slot2", FIELD_dsp340050b49a6c_fld2795PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2796PQ_slot2", FIELD_dsp340050b49a6c_fld2796PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2798PQ_slot2", FIELD_dsp340050b49a6c_fld2798PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2801PQ_slot2", FIELD_dsp340050b49a6c_fld2801PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2803PQ_slot2", FIELD_dsp340050b49a6c_fld2803PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2805PQ_slot2", FIELD_dsp340050b49a6c_fld2805PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2806PQ_slot2", FIELD_dsp340050b49a6c_fld2806PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2807PQ_slot2", FIELD_dsp340050b49a6c_fld2807PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2808PQ_slot2", FIELD_dsp340050b49a6c_fld2808PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2809PQ_slot2", FIELD_dsp340050b49a6c_fld2809PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2810PQ_slot2", FIELD_dsp340050b49a6c_fld2810PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2811PQ_slot2", FIELD_dsp340050b49a6c_fld2811PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2812PQ_slot2", FIELD_dsp340050b49a6c_fld2812PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2814PQ_slot2", FIELD_dsp340050b49a6c_fld2814PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2816PQ_slot2", FIELD_dsp340050b49a6c_fld2816PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2817", FIELD_dsp340050b49a6c_fld2817, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2818PQ_slot2", FIELD_dsp340050b49a6c_fld2818PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2819", FIELD_dsp340050b49a6c_fld2819, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2820PQ_slot2", FIELD_dsp340050b49a6c_fld2820PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2821PQ_slot2", FIELD_dsp340050b49a6c_fld2821PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2823PQ_slot2", FIELD_dsp340050b49a6c_fld2823PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3744PQ_slot2", FIELD_dsp340050b49a6c_fld3744PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3745PQ_slot2", FIELD_dsp340050b49a6c_fld3745PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3746PQ_slot2", FIELD_dsp340050b49a6c_fld3746PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3747PQ_slot2", FIELD_dsp340050b49a6c_fld3747PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3748", FIELD_dsp340050b49a6c_fld3748, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3749PQ_slot2", FIELD_dsp340050b49a6c_fld3749PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3750PQ_slot2", FIELD_dsp340050b49a6c_fld3750PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3751PQ_slot2", FIELD_dsp340050b49a6c_fld3751PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3752PQ_slot2", FIELD_dsp340050b49a6c_fld3752PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3753PQ_slot2", FIELD_dsp340050b49a6c_fld3753PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3754PQ_slot2", FIELD_dsp340050b49a6c_fld3754PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3756PQ_slot2", FIELD_dsp340050b49a6c_fld3756PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3757PQ_slot2", FIELD_dsp340050b49a6c_fld3757PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3758PQ_slot2", FIELD_dsp340050b49a6c_fld3758PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3759PQ_slot2", FIELD_dsp340050b49a6c_fld3759PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3760PQ_slot2", FIELD_dsp340050b49a6c_fld3760PQ_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s10", FIELD_op0_s10, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2825PQ_slot1", FIELD_dsp340050b49a6c_fld2825PQ_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2826PQ_slot1", FIELD_dsp340050b49a6c_fld2826PQ_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3761PQ_slot1", FIELD_dsp340050b49a6c_fld3761PQ_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s11", FIELD_op0_s11, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2059", FIELD_dsp340050b49a6c_fld2059, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2069", FIELD_dsp340050b49a6c_fld2069, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2827PQ_slot0", FIELD_dsp340050b49a6c_fld2827PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2829PQ_slot0", FIELD_dsp340050b49a6c_fld2829PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2830PQ_slot0", FIELD_dsp340050b49a6c_fld2830PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2831PQ_slot0", FIELD_dsp340050b49a6c_fld2831PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2832PQ_slot0", FIELD_dsp340050b49a6c_fld2832PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2833PQ_slot0", FIELD_dsp340050b49a6c_fld2833PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2835PQ_slot0", FIELD_dsp340050b49a6c_fld2835PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2836PQ_slot0", FIELD_dsp340050b49a6c_fld2836PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2837PQ_slot0", FIELD_dsp340050b49a6c_fld2837PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2838PQ_slot0", FIELD_dsp340050b49a6c_fld2838PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2839PQ_slot0", FIELD_dsp340050b49a6c_fld2839PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2840PQ_slot0", FIELD_dsp340050b49a6c_fld2840PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2842PQ_slot0", FIELD_dsp340050b49a6c_fld2842PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2843PQ_slot0", FIELD_dsp340050b49a6c_fld2843PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2844PQ_slot0", FIELD_dsp340050b49a6c_fld2844PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2845PQ_slot0", FIELD_dsp340050b49a6c_fld2845PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2846PQ_slot0", FIELD_dsp340050b49a6c_fld2846PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2847PQ_slot0", FIELD_dsp340050b49a6c_fld2847PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2849PQ_slot0", FIELD_dsp340050b49a6c_fld2849PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2850PQ_slot0", FIELD_dsp340050b49a6c_fld2850PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2851PQ_slot0", FIELD_dsp340050b49a6c_fld2851PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2852PQ_slot0", FIELD_dsp340050b49a6c_fld2852PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2853PQ_slot0", FIELD_dsp340050b49a6c_fld2853PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2854PQ_slot0", FIELD_dsp340050b49a6c_fld2854PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2855PQ_slot0", FIELD_dsp340050b49a6c_fld2855PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2856PQ_slot0", FIELD_dsp340050b49a6c_fld2856PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2857PQ_slot0", FIELD_dsp340050b49a6c_fld2857PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2858PQ_slot0", FIELD_dsp340050b49a6c_fld2858PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2859PQ_slot0", FIELD_dsp340050b49a6c_fld2859PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2860PQ_slot0", FIELD_dsp340050b49a6c_fld2860PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2861PQ_slot0", FIELD_dsp340050b49a6c_fld2861PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2863PQ_slot0", FIELD_dsp340050b49a6c_fld2863PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2864PQ_slot0", FIELD_dsp340050b49a6c_fld2864PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2865", FIELD_dsp340050b49a6c_fld2865, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2867PQ_slot0", FIELD_dsp340050b49a6c_fld2867PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2869PQ_slot0", FIELD_dsp340050b49a6c_fld2869PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2871PQ_slot0", FIELD_dsp340050b49a6c_fld2871PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2872PQ_slot0", FIELD_dsp340050b49a6c_fld2872PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2873PQ_slot0", FIELD_dsp340050b49a6c_fld2873PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2874PQ_slot0", FIELD_dsp340050b49a6c_fld2874PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2875PQ_slot0", FIELD_dsp340050b49a6c_fld2875PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2876PQ_slot0", FIELD_dsp340050b49a6c_fld2876PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2877PQ_slot0", FIELD_dsp340050b49a6c_fld2877PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2878PQ_slot0", FIELD_dsp340050b49a6c_fld2878PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2879PQ_slot0", FIELD_dsp340050b49a6c_fld2879PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2880PQ_slot0", FIELD_dsp340050b49a6c_fld2880PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2881PQ_slot0", FIELD_dsp340050b49a6c_fld2881PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2882", FIELD_dsp340050b49a6c_fld2882, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2883PQ_slot0", FIELD_dsp340050b49a6c_fld2883PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2884PQ_slot0", FIELD_dsp340050b49a6c_fld2884PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2885PQ_slot0", FIELD_dsp340050b49a6c_fld2885PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2886PQ_slot0", FIELD_dsp340050b49a6c_fld2886PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2887PQ_slot0", FIELD_dsp340050b49a6c_fld2887PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2888PQ_slot0", FIELD_dsp340050b49a6c_fld2888PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2890PQ_slot0", FIELD_dsp340050b49a6c_fld2890PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2891PQ_slot0", FIELD_dsp340050b49a6c_fld2891PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2892PQ_slot0", FIELD_dsp340050b49a6c_fld2892PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2893PQ_slot0", FIELD_dsp340050b49a6c_fld2893PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2894PQ_slot0", FIELD_dsp340050b49a6c_fld2894PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2895PQ_slot0", FIELD_dsp340050b49a6c_fld2895PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2897PQ_slot0", FIELD_dsp340050b49a6c_fld2897PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2899PQ_slot0", FIELD_dsp340050b49a6c_fld2899PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2900PQ_slot0", FIELD_dsp340050b49a6c_fld2900PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2901PQ_slot0", FIELD_dsp340050b49a6c_fld2901PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2902PQ_slot0", FIELD_dsp340050b49a6c_fld2902PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2903PQ_slot0", FIELD_dsp340050b49a6c_fld2903PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2904PQ_slot0", FIELD_dsp340050b49a6c_fld2904PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2905PQ_slot0", FIELD_dsp340050b49a6c_fld2905PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2906PQ_slot0", FIELD_dsp340050b49a6c_fld2906PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2907PQ_slot0", FIELD_dsp340050b49a6c_fld2907PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2908PQ_slot0", FIELD_dsp340050b49a6c_fld2908PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2909PQ_slot0", FIELD_dsp340050b49a6c_fld2909PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2910PQ_slot0", FIELD_dsp340050b49a6c_fld2910PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2911PQ_slot0", FIELD_dsp340050b49a6c_fld2911PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2912PQ_slot0", FIELD_dsp340050b49a6c_fld2912PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2913PQ_slot0", FIELD_dsp340050b49a6c_fld2913PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2914PQ_slot0", FIELD_dsp340050b49a6c_fld2914PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2915PQ_slot0", FIELD_dsp340050b49a6c_fld2915PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2916PQ_slot0", FIELD_dsp340050b49a6c_fld2916PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2917PQ_slot0", FIELD_dsp340050b49a6c_fld2917PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2918PQ_slot0", FIELD_dsp340050b49a6c_fld2918PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2919PQ_slot0", FIELD_dsp340050b49a6c_fld2919PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2920PQ_slot0", FIELD_dsp340050b49a6c_fld2920PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2921PQ_slot0", FIELD_dsp340050b49a6c_fld2921PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2922PQ_slot0", FIELD_dsp340050b49a6c_fld2922PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2923PQ_slot0", FIELD_dsp340050b49a6c_fld2923PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2924PQ_slot0", FIELD_dsp340050b49a6c_fld2924PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2925PQ_slot0", FIELD_dsp340050b49a6c_fld2925PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2926PQ_slot0", FIELD_dsp340050b49a6c_fld2926PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2927PQ_slot0", FIELD_dsp340050b49a6c_fld2927PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2928PQ_slot0", FIELD_dsp340050b49a6c_fld2928PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2929PQ_slot0", FIELD_dsp340050b49a6c_fld2929PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2930PQ_slot0", FIELD_dsp340050b49a6c_fld2930PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2932PQ_slot0", FIELD_dsp340050b49a6c_fld2932PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2934PQ_slot0", FIELD_dsp340050b49a6c_fld2934PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2935PQ_slot0", FIELD_dsp340050b49a6c_fld2935PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2936PQ_slot0", FIELD_dsp340050b49a6c_fld2936PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2937PQ_slot0", FIELD_dsp340050b49a6c_fld2937PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2939PQ_slot0", FIELD_dsp340050b49a6c_fld2939PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2940", FIELD_dsp340050b49a6c_fld2940, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2941PQ_slot0", FIELD_dsp340050b49a6c_fld2941PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2942PQ_slot0", FIELD_dsp340050b49a6c_fld2942PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2943PQ_slot0", FIELD_dsp340050b49a6c_fld2943PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2945PQ_slot0", FIELD_dsp340050b49a6c_fld2945PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2946PQ_slot0", FIELD_dsp340050b49a6c_fld2946PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2947PQ_slot0", FIELD_dsp340050b49a6c_fld2947PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2948PQ_slot0", FIELD_dsp340050b49a6c_fld2948PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2949PQ_slot0", FIELD_dsp340050b49a6c_fld2949PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2950PQ_slot0", FIELD_dsp340050b49a6c_fld2950PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3763PQ_slot0", FIELD_dsp340050b49a6c_fld3763PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3764PQ_slot0", FIELD_dsp340050b49a6c_fld3764PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3765PQ_slot0", FIELD_dsp340050b49a6c_fld3765PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3766PQ_slot0", FIELD_dsp340050b49a6c_fld3766PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3767PQ_slot0", FIELD_dsp340050b49a6c_fld3767PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3768PQ_slot0", FIELD_dsp340050b49a6c_fld3768PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3769PQ_slot0", FIELD_dsp340050b49a6c_fld3769PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3770PQ_slot0", FIELD_dsp340050b49a6c_fld3770PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3771PQ_slot0", FIELD_dsp340050b49a6c_fld3771PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3772", FIELD_dsp340050b49a6c_fld3772, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3773PQ_slot0", FIELD_dsp340050b49a6c_fld3773PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3775PQ_slot0", FIELD_dsp340050b49a6c_fld3775PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3776PQ_slot0", FIELD_dsp340050b49a6c_fld3776PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3777PQ_slot0", FIELD_dsp340050b49a6c_fld3777PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3778PQ_slot0", FIELD_dsp340050b49a6c_fld3778PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3779PQ_slot0", FIELD_dsp340050b49a6c_fld3779PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3780PQ_slot0", FIELD_dsp340050b49a6c_fld3780PQ_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s12", FIELD_op0_s12, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2953ACC2_slot2", FIELD_dsp340050b49a6c_fld2953ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2954ACC2_slot2", FIELD_dsp340050b49a6c_fld2954ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2955ACC2_slot2", FIELD_dsp340050b49a6c_fld2955ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2956ACC2_slot2", FIELD_dsp340050b49a6c_fld2956ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2957ACC2_slot2", FIELD_dsp340050b49a6c_fld2957ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2958ACC2_slot2", FIELD_dsp340050b49a6c_fld2958ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2959ACC2_slot2", FIELD_dsp340050b49a6c_fld2959ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2960ACC2_slot2", FIELD_dsp340050b49a6c_fld2960ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2963ACC2_slot2", FIELD_dsp340050b49a6c_fld2963ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2964ACC2_slot2", FIELD_dsp340050b49a6c_fld2964ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2966ACC2_slot2", FIELD_dsp340050b49a6c_fld2966ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2967ACC2_slot2", FIELD_dsp340050b49a6c_fld2967ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3782ACC2_slot2", FIELD_dsp340050b49a6c_fld3782ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3783ACC2_slot2", FIELD_dsp340050b49a6c_fld3783ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3784ACC2_slot2", FIELD_dsp340050b49a6c_fld3784ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3785ACC2_slot2", FIELD_dsp340050b49a6c_fld3785ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3786ACC2_slot2", FIELD_dsp340050b49a6c_fld3786ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3788ACC2_slot2", FIELD_dsp340050b49a6c_fld3788ACC2_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s13", FIELD_op0_s13, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2028", FIELD_dsp340050b49a6c_fld2028, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2075", FIELD_dsp340050b49a6c_fld2075, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2968ACC2_slot1", FIELD_dsp340050b49a6c_fld2968ACC2_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2969ACC2_slot1", FIELD_dsp340050b49a6c_fld2969ACC2_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3790ACC2_slot1", FIELD_dsp340050b49a6c_fld3790ACC2_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3793ACC2_slot1", FIELD_dsp340050b49a6c_fld3793ACC2_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s14", FIELD_op0_s14, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2973ACC2_slot0", FIELD_dsp340050b49a6c_fld2973ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2974ACC2_slot0", FIELD_dsp340050b49a6c_fld2974ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2975ACC2_slot0", FIELD_dsp340050b49a6c_fld2975ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2976ACC2_slot0", FIELD_dsp340050b49a6c_fld2976ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2977ACC2_slot0", FIELD_dsp340050b49a6c_fld2977ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2980ACC2_slot0", FIELD_dsp340050b49a6c_fld2980ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2981ACC2_slot0", FIELD_dsp340050b49a6c_fld2981ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2982ACC2_slot0", FIELD_dsp340050b49a6c_fld2982ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2984ACC2_slot0", FIELD_dsp340050b49a6c_fld2984ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2985ACC2_slot0", FIELD_dsp340050b49a6c_fld2985ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2987ACC2_slot0", FIELD_dsp340050b49a6c_fld2987ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2989ACC2_slot0", FIELD_dsp340050b49a6c_fld2989ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2990ACC2_slot0", FIELD_dsp340050b49a6c_fld2990ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3795ACC2_slot0", FIELD_dsp340050b49a6c_fld3795ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3796ACC2_slot0", FIELD_dsp340050b49a6c_fld3796ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3797", FIELD_dsp340050b49a6c_fld3797, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3798ACC2_slot0", FIELD_dsp340050b49a6c_fld3798ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3799ACC2_slot0", FIELD_dsp340050b49a6c_fld3799ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3800ACC2_slot0", FIELD_dsp340050b49a6c_fld3800ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3801ACC2_slot0", FIELD_dsp340050b49a6c_fld3801ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3802ACC2_slot0", FIELD_dsp340050b49a6c_fld3802ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3803ACC2_slot0", FIELD_dsp340050b49a6c_fld3803ACC2_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s15", FIELD_op0_s15, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2991SMOD_slot2", FIELD_dsp340050b49a6c_fld2991SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2992SMOD_slot2", FIELD_dsp340050b49a6c_fld2992SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2993SMOD_slot2", FIELD_dsp340050b49a6c_fld2993SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2994SMOD_slot2", FIELD_dsp340050b49a6c_fld2994SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2995SMOD_slot2", FIELD_dsp340050b49a6c_fld2995SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2996SMOD_slot2", FIELD_dsp340050b49a6c_fld2996SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2997SMOD_slot2", FIELD_dsp340050b49a6c_fld2997SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2998SMOD_slot2", FIELD_dsp340050b49a6c_fld2998SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2999SMOD_slot2", FIELD_dsp340050b49a6c_fld2999SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3000SMOD_slot2", FIELD_dsp340050b49a6c_fld3000SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3001SMOD_slot2", FIELD_dsp340050b49a6c_fld3001SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3002SMOD_slot2", FIELD_dsp340050b49a6c_fld3002SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3003SMOD_slot2", FIELD_dsp340050b49a6c_fld3003SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3004SMOD_slot2", FIELD_dsp340050b49a6c_fld3004SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3005SMOD_slot2", FIELD_dsp340050b49a6c_fld3005SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3006SMOD_slot2", FIELD_dsp340050b49a6c_fld3006SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3007SMOD_slot2", FIELD_dsp340050b49a6c_fld3007SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3008SMOD_slot2", FIELD_dsp340050b49a6c_fld3008SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3009SMOD_slot2", FIELD_dsp340050b49a6c_fld3009SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3010SMOD_slot2", FIELD_dsp340050b49a6c_fld3010SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3011SMOD_slot2", FIELD_dsp340050b49a6c_fld3011SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3012SMOD_slot2", FIELD_dsp340050b49a6c_fld3012SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3013SMOD_slot2", FIELD_dsp340050b49a6c_fld3013SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3014SMOD_slot2", FIELD_dsp340050b49a6c_fld3014SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3015SMOD_slot2", FIELD_dsp340050b49a6c_fld3015SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3016SMOD_slot2", FIELD_dsp340050b49a6c_fld3016SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3017SMOD_slot2", FIELD_dsp340050b49a6c_fld3017SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3018SMOD_slot2", FIELD_dsp340050b49a6c_fld3018SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3019SMOD_slot2", FIELD_dsp340050b49a6c_fld3019SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3020SMOD_slot2", FIELD_dsp340050b49a6c_fld3020SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3021SMOD_slot2", FIELD_dsp340050b49a6c_fld3021SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3022SMOD_slot2", FIELD_dsp340050b49a6c_fld3022SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3023SMOD_slot2", FIELD_dsp340050b49a6c_fld3023SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3024SMOD_slot2", FIELD_dsp340050b49a6c_fld3024SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3025SMOD_slot2", FIELD_dsp340050b49a6c_fld3025SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3026SMOD_slot2", FIELD_dsp340050b49a6c_fld3026SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3027SMOD_slot2", FIELD_dsp340050b49a6c_fld3027SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3028SMOD_slot2", FIELD_dsp340050b49a6c_fld3028SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3030SMOD_slot2", FIELD_dsp340050b49a6c_fld3030SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3031SMOD_slot2", FIELD_dsp340050b49a6c_fld3031SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3032SMOD_slot2", FIELD_dsp340050b49a6c_fld3032SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3033SMOD_slot2", FIELD_dsp340050b49a6c_fld3033SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3034SMOD_slot2", FIELD_dsp340050b49a6c_fld3034SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3035SMOD_slot2", FIELD_dsp340050b49a6c_fld3035SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3036SMOD_slot2", FIELD_dsp340050b49a6c_fld3036SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3038SMOD_slot2", FIELD_dsp340050b49a6c_fld3038SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3039SMOD_slot2", FIELD_dsp340050b49a6c_fld3039SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3040SMOD_slot2", FIELD_dsp340050b49a6c_fld3040SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3043SMOD_slot2", FIELD_dsp340050b49a6c_fld3043SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3044SMOD_slot2", FIELD_dsp340050b49a6c_fld3044SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3046SMOD_slot2", FIELD_dsp340050b49a6c_fld3046SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3047SMOD_slot2", FIELD_dsp340050b49a6c_fld3047SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3048", FIELD_dsp340050b49a6c_fld3048, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3049SMOD_slot2", FIELD_dsp340050b49a6c_fld3049SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3050SMOD_slot2", FIELD_dsp340050b49a6c_fld3050SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3051SMOD_slot2", FIELD_dsp340050b49a6c_fld3051SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3052SMOD_slot2", FIELD_dsp340050b49a6c_fld3052SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3053SMOD_slot2", FIELD_dsp340050b49a6c_fld3053SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3054SMOD_slot2", FIELD_dsp340050b49a6c_fld3054SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3055SMOD_slot2", FIELD_dsp340050b49a6c_fld3055SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3056SMOD_slot2", FIELD_dsp340050b49a6c_fld3056SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3058SMOD_slot2", FIELD_dsp340050b49a6c_fld3058SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3059SMOD_slot2", FIELD_dsp340050b49a6c_fld3059SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3061SMOD_slot2", FIELD_dsp340050b49a6c_fld3061SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3062", FIELD_dsp340050b49a6c_fld3062, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3063SMOD_slot2", FIELD_dsp340050b49a6c_fld3063SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3065SMOD_slot2", FIELD_dsp340050b49a6c_fld3065SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3066SMOD_slot2", FIELD_dsp340050b49a6c_fld3066SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3067SMOD_slot2", FIELD_dsp340050b49a6c_fld3067SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3068SMOD_slot2", FIELD_dsp340050b49a6c_fld3068SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3069SMOD_slot2", FIELD_dsp340050b49a6c_fld3069SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3070", FIELD_dsp340050b49a6c_fld3070, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3071SMOD_slot2", FIELD_dsp340050b49a6c_fld3071SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3072SMOD_slot2", FIELD_dsp340050b49a6c_fld3072SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3073SMOD_slot2", FIELD_dsp340050b49a6c_fld3073SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3074SMOD_slot2", FIELD_dsp340050b49a6c_fld3074SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3075SMOD_slot2", FIELD_dsp340050b49a6c_fld3075SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3076SMOD_slot2", FIELD_dsp340050b49a6c_fld3076SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3077SMOD_slot2", FIELD_dsp340050b49a6c_fld3077SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3078SMOD_slot2", FIELD_dsp340050b49a6c_fld3078SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3079SMOD_slot2", FIELD_dsp340050b49a6c_fld3079SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3080SMOD_slot2", FIELD_dsp340050b49a6c_fld3080SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3081SMOD_slot2", FIELD_dsp340050b49a6c_fld3081SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3082SMOD_slot2", FIELD_dsp340050b49a6c_fld3082SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3084SMOD_slot2", FIELD_dsp340050b49a6c_fld3084SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3085SMOD_slot2", FIELD_dsp340050b49a6c_fld3085SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3087SMOD_slot2", FIELD_dsp340050b49a6c_fld3087SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3088SMOD_slot2", FIELD_dsp340050b49a6c_fld3088SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3090SMOD_slot2", FIELD_dsp340050b49a6c_fld3090SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3091SMOD_slot2", FIELD_dsp340050b49a6c_fld3091SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3092SMOD_slot2", FIELD_dsp340050b49a6c_fld3092SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3093SMOD_slot2", FIELD_dsp340050b49a6c_fld3093SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3096SMOD_slot2", FIELD_dsp340050b49a6c_fld3096SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3097SMOD_slot2", FIELD_dsp340050b49a6c_fld3097SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3098SMOD_slot2", FIELD_dsp340050b49a6c_fld3098SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3099SMOD_slot2", FIELD_dsp340050b49a6c_fld3099SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3100SMOD_slot2", FIELD_dsp340050b49a6c_fld3100SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3101SMOD_slot2", FIELD_dsp340050b49a6c_fld3101SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3102SMOD_slot2", FIELD_dsp340050b49a6c_fld3102SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3104SMOD_slot2", FIELD_dsp340050b49a6c_fld3104SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3105SMOD_slot2", FIELD_dsp340050b49a6c_fld3105SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3106SMOD_slot2", FIELD_dsp340050b49a6c_fld3106SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3107SMOD_slot2", FIELD_dsp340050b49a6c_fld3107SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3108SMOD_slot2", FIELD_dsp340050b49a6c_fld3108SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3109SMOD_slot2", FIELD_dsp340050b49a6c_fld3109SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3110SMOD_slot2", FIELD_dsp340050b49a6c_fld3110SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3111SMOD_slot2", FIELD_dsp340050b49a6c_fld3111SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3113SMOD_slot2", FIELD_dsp340050b49a6c_fld3113SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3114SMOD_slot2", FIELD_dsp340050b49a6c_fld3114SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3115SMOD_slot2", FIELD_dsp340050b49a6c_fld3115SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3116SMOD_slot2", FIELD_dsp340050b49a6c_fld3116SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3805SMOD_slot2", FIELD_dsp340050b49a6c_fld3805SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3806SMOD_slot2", FIELD_dsp340050b49a6c_fld3806SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3807SMOD_slot2", FIELD_dsp340050b49a6c_fld3807SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3808", FIELD_dsp340050b49a6c_fld3808, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3809SMOD_slot2", FIELD_dsp340050b49a6c_fld3809SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3810SMOD_slot2", FIELD_dsp340050b49a6c_fld3810SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3812SMOD_slot2", FIELD_dsp340050b49a6c_fld3812SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3813SMOD_slot2", FIELD_dsp340050b49a6c_fld3813SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3814SMOD_slot2", FIELD_dsp340050b49a6c_fld3814SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3816SMOD_slot2", FIELD_dsp340050b49a6c_fld3816SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3817", FIELD_dsp340050b49a6c_fld3817, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3818SMOD_slot2", FIELD_dsp340050b49a6c_fld3818SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3819SMOD_slot2", FIELD_dsp340050b49a6c_fld3819SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3821SMOD_slot2", FIELD_dsp340050b49a6c_fld3821SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3822SMOD_slot2", FIELD_dsp340050b49a6c_fld3822SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3823SMOD_slot2", FIELD_dsp340050b49a6c_fld3823SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3824SMOD_slot2", FIELD_dsp340050b49a6c_fld3824SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3825SMOD_slot2", FIELD_dsp340050b49a6c_fld3825SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3826SMOD_slot2", FIELD_dsp340050b49a6c_fld3826SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3827SMOD_slot2", FIELD_dsp340050b49a6c_fld3827SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3828SMOD_slot2", FIELD_dsp340050b49a6c_fld3828SMOD_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s16", FIELD_op0_s16, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2033", FIELD_dsp340050b49a6c_fld2033, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2080", FIELD_dsp340050b49a6c_fld2080, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3117SMOD_slot1", FIELD_dsp340050b49a6c_fld3117SMOD_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3118SMOD_slot1", FIELD_dsp340050b49a6c_fld3118SMOD_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3829SMOD_slot1", FIELD_dsp340050b49a6c_fld3829SMOD_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s17", FIELD_op0_s17, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3119SMOD_slot0", FIELD_dsp340050b49a6c_fld3119SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3120SMOD_slot0", FIELD_dsp340050b49a6c_fld3120SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3121SMOD_slot0", FIELD_dsp340050b49a6c_fld3121SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3122SMOD_slot0", FIELD_dsp340050b49a6c_fld3122SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3123SMOD_slot0", FIELD_dsp340050b49a6c_fld3123SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3125SMOD_slot0", FIELD_dsp340050b49a6c_fld3125SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3126SMOD_slot0", FIELD_dsp340050b49a6c_fld3126SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3127SMOD_slot0", FIELD_dsp340050b49a6c_fld3127SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3128SMOD_slot0", FIELD_dsp340050b49a6c_fld3128SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3129SMOD_slot0", FIELD_dsp340050b49a6c_fld3129SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3130SMOD_slot0", FIELD_dsp340050b49a6c_fld3130SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3131SMOD_slot0", FIELD_dsp340050b49a6c_fld3131SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3132SMOD_slot0", FIELD_dsp340050b49a6c_fld3132SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3133SMOD_slot0", FIELD_dsp340050b49a6c_fld3133SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3134SMOD_slot0", FIELD_dsp340050b49a6c_fld3134SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3135SMOD_slot0", FIELD_dsp340050b49a6c_fld3135SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3136SMOD_slot0", FIELD_dsp340050b49a6c_fld3136SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3137SMOD_slot0", FIELD_dsp340050b49a6c_fld3137SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3138SMOD_slot0", FIELD_dsp340050b49a6c_fld3138SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3139SMOD_slot0", FIELD_dsp340050b49a6c_fld3139SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3140SMOD_slot0", FIELD_dsp340050b49a6c_fld3140SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3141SMOD_slot0", FIELD_dsp340050b49a6c_fld3141SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3142SMOD_slot0", FIELD_dsp340050b49a6c_fld3142SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3143SMOD_slot0", FIELD_dsp340050b49a6c_fld3143SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3144SMOD_slot0", FIELD_dsp340050b49a6c_fld3144SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3145SMOD_slot0", FIELD_dsp340050b49a6c_fld3145SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3146SMOD_slot0", FIELD_dsp340050b49a6c_fld3146SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3148SMOD_slot0", FIELD_dsp340050b49a6c_fld3148SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3149SMOD_slot0", FIELD_dsp340050b49a6c_fld3149SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3150", FIELD_dsp340050b49a6c_fld3150, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3152SMOD_slot0", FIELD_dsp340050b49a6c_fld3152SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3153SMOD_slot0", FIELD_dsp340050b49a6c_fld3153SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3155SMOD_slot0", FIELD_dsp340050b49a6c_fld3155SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3156SMOD_slot0", FIELD_dsp340050b49a6c_fld3156SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3157SMOD_slot0", FIELD_dsp340050b49a6c_fld3157SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3158SMOD_slot0", FIELD_dsp340050b49a6c_fld3158SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3159SMOD_slot0", FIELD_dsp340050b49a6c_fld3159SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3160SMOD_slot0", FIELD_dsp340050b49a6c_fld3160SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3161SMOD_slot0", FIELD_dsp340050b49a6c_fld3161SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3164SMOD_slot0", FIELD_dsp340050b49a6c_fld3164SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3165SMOD_slot0", FIELD_dsp340050b49a6c_fld3165SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3166SMOD_slot0", FIELD_dsp340050b49a6c_fld3166SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3168SMOD_slot0", FIELD_dsp340050b49a6c_fld3168SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3170SMOD_slot0", FIELD_dsp340050b49a6c_fld3170SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3171SMOD_slot0", FIELD_dsp340050b49a6c_fld3171SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3172SMOD_slot0", FIELD_dsp340050b49a6c_fld3172SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3173SMOD_slot0", FIELD_dsp340050b49a6c_fld3173SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3174SMOD_slot0", FIELD_dsp340050b49a6c_fld3174SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3175SMOD_slot0", FIELD_dsp340050b49a6c_fld3175SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3176SMOD_slot0", FIELD_dsp340050b49a6c_fld3176SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3177SMOD_slot0", FIELD_dsp340050b49a6c_fld3177SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3178SMOD_slot0", FIELD_dsp340050b49a6c_fld3178SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3179SMOD_slot0", FIELD_dsp340050b49a6c_fld3179SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3180SMOD_slot0", FIELD_dsp340050b49a6c_fld3180SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3181SMOD_slot0", FIELD_dsp340050b49a6c_fld3181SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3182SMOD_slot0", FIELD_dsp340050b49a6c_fld3182SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3184SMOD_slot0", FIELD_dsp340050b49a6c_fld3184SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3186SMOD_slot0", FIELD_dsp340050b49a6c_fld3186SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3188SMOD_slot0", FIELD_dsp340050b49a6c_fld3188SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3832SMOD_slot0", FIELD_dsp340050b49a6c_fld3832SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3833SMOD_slot0", FIELD_dsp340050b49a6c_fld3833SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3834", FIELD_dsp340050b49a6c_fld3834, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3836SMOD_slot0", FIELD_dsp340050b49a6c_fld3836SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3837SMOD_slot0", FIELD_dsp340050b49a6c_fld3837SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3838SMOD_slot0", FIELD_dsp340050b49a6c_fld3838SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3841SMOD_slot0", FIELD_dsp340050b49a6c_fld3841SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3842SMOD_slot0", FIELD_dsp340050b49a6c_fld3842SMOD_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s18", FIELD_op0_s18, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2074", FIELD_dsp340050b49a6c_fld2074, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3191LLR_slot2", FIELD_dsp340050b49a6c_fld3191LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3192LLR_slot2", FIELD_dsp340050b49a6c_fld3192LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3193LLR_slot2", FIELD_dsp340050b49a6c_fld3193LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3194LLR_slot2", FIELD_dsp340050b49a6c_fld3194LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3195LLR_slot2", FIELD_dsp340050b49a6c_fld3195LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3196LLR_slot2", FIELD_dsp340050b49a6c_fld3196LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3197LLR_slot2", FIELD_dsp340050b49a6c_fld3197LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3198LLR_slot2", FIELD_dsp340050b49a6c_fld3198LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3199LLR_slot2", FIELD_dsp340050b49a6c_fld3199LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3200LLR_slot2", FIELD_dsp340050b49a6c_fld3200LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3201LLR_slot2", FIELD_dsp340050b49a6c_fld3201LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3202LLR_slot2", FIELD_dsp340050b49a6c_fld3202LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3203LLR_slot2", FIELD_dsp340050b49a6c_fld3203LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3204LLR_slot2", FIELD_dsp340050b49a6c_fld3204LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3205", FIELD_dsp340050b49a6c_fld3205, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3206", FIELD_dsp340050b49a6c_fld3206, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3207LLR_slot2", FIELD_dsp340050b49a6c_fld3207LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3208LLR_slot2", FIELD_dsp340050b49a6c_fld3208LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3210LLR_slot2", FIELD_dsp340050b49a6c_fld3210LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3212", FIELD_dsp340050b49a6c_fld3212, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3213LLR_slot2", FIELD_dsp340050b49a6c_fld3213LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3214", FIELD_dsp340050b49a6c_fld3214, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3215LLR_slot2", FIELD_dsp340050b49a6c_fld3215LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3216LLR_slot2", FIELD_dsp340050b49a6c_fld3216LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3217", FIELD_dsp340050b49a6c_fld3217, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3218LLR_slot2", FIELD_dsp340050b49a6c_fld3218LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3220LLR_slot2", FIELD_dsp340050b49a6c_fld3220LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3221LLR_slot2", FIELD_dsp340050b49a6c_fld3221LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3222LLR_slot2", FIELD_dsp340050b49a6c_fld3222LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3224LLR_slot2", FIELD_dsp340050b49a6c_fld3224LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3225", FIELD_dsp340050b49a6c_fld3225, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3226LLR_slot2", FIELD_dsp340050b49a6c_fld3226LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3228LLR_slot2", FIELD_dsp340050b49a6c_fld3228LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3230", FIELD_dsp340050b49a6c_fld3230, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3231LLR_slot2", FIELD_dsp340050b49a6c_fld3231LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3232LLR_slot2", FIELD_dsp340050b49a6c_fld3232LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3233", FIELD_dsp340050b49a6c_fld3233, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3234LLR_slot2", FIELD_dsp340050b49a6c_fld3234LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3235LLR_slot2", FIELD_dsp340050b49a6c_fld3235LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3236", FIELD_dsp340050b49a6c_fld3236, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3237LLR_slot2", FIELD_dsp340050b49a6c_fld3237LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3238LLR_slot2", FIELD_dsp340050b49a6c_fld3238LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3240LLR_slot2", FIELD_dsp340050b49a6c_fld3240LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3241LLR_slot2", FIELD_dsp340050b49a6c_fld3241LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3242LLR_slot2", FIELD_dsp340050b49a6c_fld3242LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3243LLR_slot2", FIELD_dsp340050b49a6c_fld3243LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3244LLR_slot2", FIELD_dsp340050b49a6c_fld3244LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3245LLR_slot2", FIELD_dsp340050b49a6c_fld3245LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3246", FIELD_dsp340050b49a6c_fld3246, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3247LLR_slot2", FIELD_dsp340050b49a6c_fld3247LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3843LLR_slot2", FIELD_dsp340050b49a6c_fld3843LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3844", FIELD_dsp340050b49a6c_fld3844, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3845LLR_slot2", FIELD_dsp340050b49a6c_fld3845LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3847LLR_slot2", FIELD_dsp340050b49a6c_fld3847LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3848LLR_slot2", FIELD_dsp340050b49a6c_fld3848LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3849LLR_slot2", FIELD_dsp340050b49a6c_fld3849LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3850LLR_slot2", FIELD_dsp340050b49a6c_fld3850LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3851LLR_slot2", FIELD_dsp340050b49a6c_fld3851LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3853LLR_slot2", FIELD_dsp340050b49a6c_fld3853LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3855LLR_slot2", FIELD_dsp340050b49a6c_fld3855LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3856LLR_slot2", FIELD_dsp340050b49a6c_fld3856LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3857LLR_slot2", FIELD_dsp340050b49a6c_fld3857LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3859LLR_slot2", FIELD_dsp340050b49a6c_fld3859LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3860LLR_slot2", FIELD_dsp340050b49a6c_fld3860LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3861LLR_slot2", FIELD_dsp340050b49a6c_fld3861LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3862", FIELD_dsp340050b49a6c_fld3862, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3863LLR_slot2", FIELD_dsp340050b49a6c_fld3863LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3864LLR_slot2", FIELD_dsp340050b49a6c_fld3864LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3865LLR_slot2", FIELD_dsp340050b49a6c_fld3865LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3866LLR_slot2", FIELD_dsp340050b49a6c_fld3866LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3867LLR_slot2", FIELD_dsp340050b49a6c_fld3867LLR_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3868", FIELD_dsp340050b49a6c_fld3868, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s19", FIELD_op0_s19, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2034", FIELD_dsp340050b49a6c_fld2034, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3248LLR_slot1", FIELD_dsp340050b49a6c_fld3248LLR_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3250LLR_slot1", FIELD_dsp340050b49a6c_fld3250LLR_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3251LLR_slot1", FIELD_dsp340050b49a6c_fld3251LLR_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3252LLR_slot1", FIELD_dsp340050b49a6c_fld3252LLR_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3253LLR_slot1", FIELD_dsp340050b49a6c_fld3253LLR_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3254LLR_slot1", FIELD_dsp340050b49a6c_fld3254LLR_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3869LLR_slot1", FIELD_dsp340050b49a6c_fld3869LLR_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3870", FIELD_dsp340050b49a6c_fld3870, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3872LLR_slot1", FIELD_dsp340050b49a6c_fld3872LLR_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3875LLR_slot1", FIELD_dsp340050b49a6c_fld3875LLR_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3876LLR_slot1", FIELD_dsp340050b49a6c_fld3876LLR_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3878LLR_slot1", FIELD_dsp340050b49a6c_fld3878LLR_slot1, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s20", FIELD_op0_s20, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2071", FIELD_dsp340050b49a6c_fld2071, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3258LLR_slot0", FIELD_dsp340050b49a6c_fld3258LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3259LLR_slot0", FIELD_dsp340050b49a6c_fld3259LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3260LLR_slot0", FIELD_dsp340050b49a6c_fld3260LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3261LLR_slot0", FIELD_dsp340050b49a6c_fld3261LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3263LLR_slot0", FIELD_dsp340050b49a6c_fld3263LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3264LLR_slot0", FIELD_dsp340050b49a6c_fld3264LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3265LLR_slot0", FIELD_dsp340050b49a6c_fld3265LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3266LLR_slot0", FIELD_dsp340050b49a6c_fld3266LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3267LLR_slot0", FIELD_dsp340050b49a6c_fld3267LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3268LLR_slot0", FIELD_dsp340050b49a6c_fld3268LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3269LLR_slot0", FIELD_dsp340050b49a6c_fld3269LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3270LLR_slot0", FIELD_dsp340050b49a6c_fld3270LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3272LLR_slot0", FIELD_dsp340050b49a6c_fld3272LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3274LLR_slot0", FIELD_dsp340050b49a6c_fld3274LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3275LLR_slot0", FIELD_dsp340050b49a6c_fld3275LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3276LLR_slot0", FIELD_dsp340050b49a6c_fld3276LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3277LLR_slot0", FIELD_dsp340050b49a6c_fld3277LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3278LLR_slot0", FIELD_dsp340050b49a6c_fld3278LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3279LLR_slot0", FIELD_dsp340050b49a6c_fld3279LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3280LLR_slot0", FIELD_dsp340050b49a6c_fld3280LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3281LLR_slot0", FIELD_dsp340050b49a6c_fld3281LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3282LLR_slot0", FIELD_dsp340050b49a6c_fld3282LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3283LLR_slot0", FIELD_dsp340050b49a6c_fld3283LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3284LLR_slot0", FIELD_dsp340050b49a6c_fld3284LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3286LLR_slot0", FIELD_dsp340050b49a6c_fld3286LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3288LLR_slot0", FIELD_dsp340050b49a6c_fld3288LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3289LLR_slot0", FIELD_dsp340050b49a6c_fld3289LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3291LLR_slot0", FIELD_dsp340050b49a6c_fld3291LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3292LLR_slot0", FIELD_dsp340050b49a6c_fld3292LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3293LLR_slot0", FIELD_dsp340050b49a6c_fld3293LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3294LLR_slot0", FIELD_dsp340050b49a6c_fld3294LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3295LLR_slot0", FIELD_dsp340050b49a6c_fld3295LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3296LLR_slot0", FIELD_dsp340050b49a6c_fld3296LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3297LLR_slot0", FIELD_dsp340050b49a6c_fld3297LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3298LLR_slot0", FIELD_dsp340050b49a6c_fld3298LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3299LLR_slot0", FIELD_dsp340050b49a6c_fld3299LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3300LLR_slot0", FIELD_dsp340050b49a6c_fld3300LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3302LLR_slot0", FIELD_dsp340050b49a6c_fld3302LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3303LLR_slot0", FIELD_dsp340050b49a6c_fld3303LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3304LLR_slot0", FIELD_dsp340050b49a6c_fld3304LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3305LLR_slot0", FIELD_dsp340050b49a6c_fld3305LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3306LLR_slot0", FIELD_dsp340050b49a6c_fld3306LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3308LLR_slot0", FIELD_dsp340050b49a6c_fld3308LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3310LLR_slot0", FIELD_dsp340050b49a6c_fld3310LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3311LLR_slot0", FIELD_dsp340050b49a6c_fld3311LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3312LLR_slot0", FIELD_dsp340050b49a6c_fld3312LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3879LLR_slot0", FIELD_dsp340050b49a6c_fld3879LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3881LLR_slot0", FIELD_dsp340050b49a6c_fld3881LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3883LLR_slot0", FIELD_dsp340050b49a6c_fld3883LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3885LLR_slot0", FIELD_dsp340050b49a6c_fld3885LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3887LLR_slot0", FIELD_dsp340050b49a6c_fld3887LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3888LLR_slot0", FIELD_dsp340050b49a6c_fld3888LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3890LLR_slot0", FIELD_dsp340050b49a6c_fld3890LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3892LLR_slot0", FIELD_dsp340050b49a6c_fld3892LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3893LLR_slot0", FIELD_dsp340050b49a6c_fld3893LLR_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s21", FIELD_op0_s21, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3313DUAL_slot2", FIELD_dsp340050b49a6c_fld3313DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3314", FIELD_dsp340050b49a6c_fld3314, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3315DUAL_slot2", FIELD_dsp340050b49a6c_fld3315DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3316DUAL_slot2", FIELD_dsp340050b49a6c_fld3316DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3317DUAL_slot2", FIELD_dsp340050b49a6c_fld3317DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3318", FIELD_dsp340050b49a6c_fld3318, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3319DUAL_slot2", FIELD_dsp340050b49a6c_fld3319DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3320DUAL_slot2", FIELD_dsp340050b49a6c_fld3320DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3321DUAL_slot2", FIELD_dsp340050b49a6c_fld3321DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3322DUAL_slot2", FIELD_dsp340050b49a6c_fld3322DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3323DUAL_slot2", FIELD_dsp340050b49a6c_fld3323DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3324DUAL_slot2", FIELD_dsp340050b49a6c_fld3324DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3325DUAL_slot2", FIELD_dsp340050b49a6c_fld3325DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3326DUAL_slot2", FIELD_dsp340050b49a6c_fld3326DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3327DUAL_slot2", FIELD_dsp340050b49a6c_fld3327DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3328DUAL_slot2", FIELD_dsp340050b49a6c_fld3328DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3329DUAL_slot2", FIELD_dsp340050b49a6c_fld3329DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3330DUAL_slot2", FIELD_dsp340050b49a6c_fld3330DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3331DUAL_slot2", FIELD_dsp340050b49a6c_fld3331DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3332DUAL_slot2", FIELD_dsp340050b49a6c_fld3332DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3333DUAL_slot2", FIELD_dsp340050b49a6c_fld3333DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3334DUAL_slot2", FIELD_dsp340050b49a6c_fld3334DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3335DUAL_slot2", FIELD_dsp340050b49a6c_fld3335DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3336DUAL_slot2", FIELD_dsp340050b49a6c_fld3336DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3337DUAL_slot2", FIELD_dsp340050b49a6c_fld3337DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3339DUAL_slot2", FIELD_dsp340050b49a6c_fld3339DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3340DUAL_slot2", FIELD_dsp340050b49a6c_fld3340DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3341DUAL_slot2", FIELD_dsp340050b49a6c_fld3341DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3342DUAL_slot2", FIELD_dsp340050b49a6c_fld3342DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3345DUAL_slot2", FIELD_dsp340050b49a6c_fld3345DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3347DUAL_slot2", FIELD_dsp340050b49a6c_fld3347DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3348DUAL_slot2", FIELD_dsp340050b49a6c_fld3348DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3349DUAL_slot2", FIELD_dsp340050b49a6c_fld3349DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3350DUAL_slot2", FIELD_dsp340050b49a6c_fld3350DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3353DUAL_slot2", FIELD_dsp340050b49a6c_fld3353DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3354DUAL_slot2", FIELD_dsp340050b49a6c_fld3354DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3356DUAL_slot2", FIELD_dsp340050b49a6c_fld3356DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3358DUAL_slot2", FIELD_dsp340050b49a6c_fld3358DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3360DUAL_slot2", FIELD_dsp340050b49a6c_fld3360DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3361DUAL_slot2", FIELD_dsp340050b49a6c_fld3361DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3362DUAL_slot2", FIELD_dsp340050b49a6c_fld3362DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3363DUAL_slot2", FIELD_dsp340050b49a6c_fld3363DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3364", FIELD_dsp340050b49a6c_fld3364, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3365DUAL_slot2", FIELD_dsp340050b49a6c_fld3365DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3366DUAL_slot2", FIELD_dsp340050b49a6c_fld3366DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3367DUAL_slot2", FIELD_dsp340050b49a6c_fld3367DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3368DUAL_slot2", FIELD_dsp340050b49a6c_fld3368DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3369DUAL_slot2", FIELD_dsp340050b49a6c_fld3369DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3370DUAL_slot2", FIELD_dsp340050b49a6c_fld3370DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3371DUAL_slot2", FIELD_dsp340050b49a6c_fld3371DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3372DUAL_slot2", FIELD_dsp340050b49a6c_fld3372DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3373DUAL_slot2", FIELD_dsp340050b49a6c_fld3373DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3374DUAL_slot2", FIELD_dsp340050b49a6c_fld3374DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3375DUAL_slot2", FIELD_dsp340050b49a6c_fld3375DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3376DUAL_slot2", FIELD_dsp340050b49a6c_fld3376DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3377DUAL_slot2", FIELD_dsp340050b49a6c_fld3377DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3378DUAL_slot2", FIELD_dsp340050b49a6c_fld3378DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3379DUAL_slot2", FIELD_dsp340050b49a6c_fld3379DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3380DUAL_slot2", FIELD_dsp340050b49a6c_fld3380DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3381DUAL_slot2", FIELD_dsp340050b49a6c_fld3381DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3382DUAL_slot2", FIELD_dsp340050b49a6c_fld3382DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3384DUAL_slot2", FIELD_dsp340050b49a6c_fld3384DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3385DUAL_slot2", FIELD_dsp340050b49a6c_fld3385DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3386DUAL_slot2", FIELD_dsp340050b49a6c_fld3386DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3387DUAL_slot2", FIELD_dsp340050b49a6c_fld3387DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3388DUAL_slot2", FIELD_dsp340050b49a6c_fld3388DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3390DUAL_slot2", FIELD_dsp340050b49a6c_fld3390DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3392DUAL_slot2", FIELD_dsp340050b49a6c_fld3392DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3394DUAL_slot2", FIELD_dsp340050b49a6c_fld3394DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3396DUAL_slot2", FIELD_dsp340050b49a6c_fld3396DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3397DUAL_slot2", FIELD_dsp340050b49a6c_fld3397DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3399DUAL_slot2", FIELD_dsp340050b49a6c_fld3399DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3401DUAL_slot2", FIELD_dsp340050b49a6c_fld3401DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3403DUAL_slot2", FIELD_dsp340050b49a6c_fld3403DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3404DUAL_slot2", FIELD_dsp340050b49a6c_fld3404DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3406DUAL_slot2", FIELD_dsp340050b49a6c_fld3406DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3407", FIELD_dsp340050b49a6c_fld3407, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3408DUAL_slot2", FIELD_dsp340050b49a6c_fld3408DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3410", FIELD_dsp340050b49a6c_fld3410, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3411DUAL_slot2", FIELD_dsp340050b49a6c_fld3411DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3412DUAL_slot2", FIELD_dsp340050b49a6c_fld3412DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3413DUAL_slot2", FIELD_dsp340050b49a6c_fld3413DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3414DUAL_slot2", FIELD_dsp340050b49a6c_fld3414DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3415DUAL_slot2", FIELD_dsp340050b49a6c_fld3415DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3416DUAL_slot2", FIELD_dsp340050b49a6c_fld3416DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3417DUAL_slot2", FIELD_dsp340050b49a6c_fld3417DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3418DUAL_slot2", FIELD_dsp340050b49a6c_fld3418DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3419DUAL_slot2", FIELD_dsp340050b49a6c_fld3419DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3420DUAL_slot2", FIELD_dsp340050b49a6c_fld3420DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3421DUAL_slot2", FIELD_dsp340050b49a6c_fld3421DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3422DUAL_slot2", FIELD_dsp340050b49a6c_fld3422DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3423DUAL_slot2", FIELD_dsp340050b49a6c_fld3423DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3424DUAL_slot2", FIELD_dsp340050b49a6c_fld3424DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3425DUAL_slot2", FIELD_dsp340050b49a6c_fld3425DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3426DUAL_slot2", FIELD_dsp340050b49a6c_fld3426DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3427DUAL_slot2", FIELD_dsp340050b49a6c_fld3427DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3428DUAL_slot2", FIELD_dsp340050b49a6c_fld3428DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3429DUAL_slot2", FIELD_dsp340050b49a6c_fld3429DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3430DUAL_slot2", FIELD_dsp340050b49a6c_fld3430DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3431DUAL_slot2", FIELD_dsp340050b49a6c_fld3431DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3432DUAL_slot2", FIELD_dsp340050b49a6c_fld3432DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3433DUAL_slot2", FIELD_dsp340050b49a6c_fld3433DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3434DUAL_slot2", FIELD_dsp340050b49a6c_fld3434DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3435DUAL_slot2", FIELD_dsp340050b49a6c_fld3435DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3436DUAL_slot2", FIELD_dsp340050b49a6c_fld3436DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3437DUAL_slot2", FIELD_dsp340050b49a6c_fld3437DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3438DUAL_slot2", FIELD_dsp340050b49a6c_fld3438DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3439DUAL_slot2", FIELD_dsp340050b49a6c_fld3439DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3440DUAL_slot2", FIELD_dsp340050b49a6c_fld3440DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3441DUAL_slot2", FIELD_dsp340050b49a6c_fld3441DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3442DUAL_slot2", FIELD_dsp340050b49a6c_fld3442DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3443DUAL_slot2", FIELD_dsp340050b49a6c_fld3443DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3444DUAL_slot2", FIELD_dsp340050b49a6c_fld3444DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3445DUAL_slot2", FIELD_dsp340050b49a6c_fld3445DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3446DUAL_slot2", FIELD_dsp340050b49a6c_fld3446DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3448DUAL_slot2", FIELD_dsp340050b49a6c_fld3448DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3450DUAL_slot2", FIELD_dsp340050b49a6c_fld3450DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3451DUAL_slot2", FIELD_dsp340050b49a6c_fld3451DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3453DUAL_slot2", FIELD_dsp340050b49a6c_fld3453DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3454DUAL_slot2", FIELD_dsp340050b49a6c_fld3454DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3456DUAL_slot2", FIELD_dsp340050b49a6c_fld3456DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3457DUAL_slot2", FIELD_dsp340050b49a6c_fld3457DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3458DUAL_slot2", FIELD_dsp340050b49a6c_fld3458DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3459DUAL_slot2", FIELD_dsp340050b49a6c_fld3459DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3460DUAL_slot2", FIELD_dsp340050b49a6c_fld3460DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3461DUAL_slot2", FIELD_dsp340050b49a6c_fld3461DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3462DUAL_slot2", FIELD_dsp340050b49a6c_fld3462DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3464DUAL_slot2", FIELD_dsp340050b49a6c_fld3464DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3465DUAL_slot2", FIELD_dsp340050b49a6c_fld3465DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3466", FIELD_dsp340050b49a6c_fld3466, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3467DUAL_slot2", FIELD_dsp340050b49a6c_fld3467DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3468DUAL_slot2", FIELD_dsp340050b49a6c_fld3468DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3469DUAL_slot2", FIELD_dsp340050b49a6c_fld3469DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3470DUAL_slot2", FIELD_dsp340050b49a6c_fld3470DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3471DUAL_slot2", FIELD_dsp340050b49a6c_fld3471DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3472DUAL_slot2", FIELD_dsp340050b49a6c_fld3472DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3473DUAL_slot2", FIELD_dsp340050b49a6c_fld3473DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3474DUAL_slot2", FIELD_dsp340050b49a6c_fld3474DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3475DUAL_slot2", FIELD_dsp340050b49a6c_fld3475DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3477DUAL_slot2", FIELD_dsp340050b49a6c_fld3477DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3478DUAL_slot2", FIELD_dsp340050b49a6c_fld3478DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3479DUAL_slot2", FIELD_dsp340050b49a6c_fld3479DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3480DUAL_slot2", FIELD_dsp340050b49a6c_fld3480DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3481DUAL_slot2", FIELD_dsp340050b49a6c_fld3481DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3482DUAL_slot2", FIELD_dsp340050b49a6c_fld3482DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3484DUAL_slot2", FIELD_dsp340050b49a6c_fld3484DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3894DUAL_slot2", FIELD_dsp340050b49a6c_fld3894DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3895DUAL_slot2", FIELD_dsp340050b49a6c_fld3895DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3896DUAL_slot2", FIELD_dsp340050b49a6c_fld3896DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3897DUAL_slot2", FIELD_dsp340050b49a6c_fld3897DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3898DUAL_slot2", FIELD_dsp340050b49a6c_fld3898DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3899DUAL_slot2", FIELD_dsp340050b49a6c_fld3899DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3900", FIELD_dsp340050b49a6c_fld3900, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3901DUAL_slot2", FIELD_dsp340050b49a6c_fld3901DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3903DUAL_slot2", FIELD_dsp340050b49a6c_fld3903DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3904DUAL_slot2", FIELD_dsp340050b49a6c_fld3904DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3905DUAL_slot2", FIELD_dsp340050b49a6c_fld3905DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3906DUAL_slot2", FIELD_dsp340050b49a6c_fld3906DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3907DUAL_slot2", FIELD_dsp340050b49a6c_fld3907DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3908DUAL_slot2", FIELD_dsp340050b49a6c_fld3908DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3909DUAL_slot2", FIELD_dsp340050b49a6c_fld3909DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3910DUAL_slot2", FIELD_dsp340050b49a6c_fld3910DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3913DUAL_slot2", FIELD_dsp340050b49a6c_fld3913DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3914DUAL_slot2", FIELD_dsp340050b49a6c_fld3914DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3916DUAL_slot2", FIELD_dsp340050b49a6c_fld3916DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3917DUAL_slot2", FIELD_dsp340050b49a6c_fld3917DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3918DUAL_slot2", FIELD_dsp340050b49a6c_fld3918DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3919DUAL_slot2", FIELD_dsp340050b49a6c_fld3919DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3920DUAL_slot2", FIELD_dsp340050b49a6c_fld3920DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3921DUAL_slot2", FIELD_dsp340050b49a6c_fld3921DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3922DUAL_slot2", FIELD_dsp340050b49a6c_fld3922DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3923DUAL_slot2", FIELD_dsp340050b49a6c_fld3923DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3924DUAL_slot2", FIELD_dsp340050b49a6c_fld3924DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3925DUAL_slot2", FIELD_dsp340050b49a6c_fld3925DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3927DUAL_slot2", FIELD_dsp340050b49a6c_fld3927DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3928DUAL_slot2", FIELD_dsp340050b49a6c_fld3928DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3929DUAL_slot2", FIELD_dsp340050b49a6c_fld3929DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3930DUAL_slot2", FIELD_dsp340050b49a6c_fld3930DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3931DUAL_slot2", FIELD_dsp340050b49a6c_fld3931DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3933DUAL_slot2", FIELD_dsp340050b49a6c_fld3933DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3934DUAL_slot2", FIELD_dsp340050b49a6c_fld3934DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3935DUAL_slot2", FIELD_dsp340050b49a6c_fld3935DUAL_slot2, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s22", FIELD_op0_s22, -1, 0, 0, 0, 0, 0, 0 }, + { "op0_s23", FIELD_op0_s23, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2057", FIELD_dsp340050b49a6c_fld2057, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2060", FIELD_dsp340050b49a6c_fld2060, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2066", FIELD_dsp340050b49a6c_fld2066, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2072", FIELD_dsp340050b49a6c_fld2072, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld2079", FIELD_dsp340050b49a6c_fld2079, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3487DUAL_slot0", FIELD_dsp340050b49a6c_fld3487DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3488DUAL_slot0", FIELD_dsp340050b49a6c_fld3488DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3489DUAL_slot0", FIELD_dsp340050b49a6c_fld3489DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3490DUAL_slot0", FIELD_dsp340050b49a6c_fld3490DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3491DUAL_slot0", FIELD_dsp340050b49a6c_fld3491DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3492DUAL_slot0", FIELD_dsp340050b49a6c_fld3492DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3493DUAL_slot0", FIELD_dsp340050b49a6c_fld3493DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3494DUAL_slot0", FIELD_dsp340050b49a6c_fld3494DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3496DUAL_slot0", FIELD_dsp340050b49a6c_fld3496DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3497DUAL_slot0", FIELD_dsp340050b49a6c_fld3497DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3498DUAL_slot0", FIELD_dsp340050b49a6c_fld3498DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3499DUAL_slot0", FIELD_dsp340050b49a6c_fld3499DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3500DUAL_slot0", FIELD_dsp340050b49a6c_fld3500DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3502DUAL_slot0", FIELD_dsp340050b49a6c_fld3502DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3504DUAL_slot0", FIELD_dsp340050b49a6c_fld3504DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3505DUAL_slot0", FIELD_dsp340050b49a6c_fld3505DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3506DUAL_slot0", FIELD_dsp340050b49a6c_fld3506DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3507DUAL_slot0", FIELD_dsp340050b49a6c_fld3507DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3508DUAL_slot0", FIELD_dsp340050b49a6c_fld3508DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3509DUAL_slot0", FIELD_dsp340050b49a6c_fld3509DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3510DUAL_slot0", FIELD_dsp340050b49a6c_fld3510DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3511DUAL_slot0", FIELD_dsp340050b49a6c_fld3511DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3512DUAL_slot0", FIELD_dsp340050b49a6c_fld3512DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3513DUAL_slot0", FIELD_dsp340050b49a6c_fld3513DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3514DUAL_slot0", FIELD_dsp340050b49a6c_fld3514DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3515DUAL_slot0", FIELD_dsp340050b49a6c_fld3515DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3516DUAL_slot0", FIELD_dsp340050b49a6c_fld3516DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3517DUAL_slot0", FIELD_dsp340050b49a6c_fld3517DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3518DUAL_slot0", FIELD_dsp340050b49a6c_fld3518DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3519DUAL_slot0", FIELD_dsp340050b49a6c_fld3519DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3520DUAL_slot0", FIELD_dsp340050b49a6c_fld3520DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3522DUAL_slot0", FIELD_dsp340050b49a6c_fld3522DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3523DUAL_slot0", FIELD_dsp340050b49a6c_fld3523DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3524DUAL_slot0", FIELD_dsp340050b49a6c_fld3524DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3527DUAL_slot0", FIELD_dsp340050b49a6c_fld3527DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3529DUAL_slot0", FIELD_dsp340050b49a6c_fld3529DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3530DUAL_slot0", FIELD_dsp340050b49a6c_fld3530DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3531", FIELD_dsp340050b49a6c_fld3531, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3532DUAL_slot0", FIELD_dsp340050b49a6c_fld3532DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3533DUAL_slot0", FIELD_dsp340050b49a6c_fld3533DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3535DUAL_slot0", FIELD_dsp340050b49a6c_fld3535DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3536DUAL_slot0", FIELD_dsp340050b49a6c_fld3536DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3537DUAL_slot0", FIELD_dsp340050b49a6c_fld3537DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3538DUAL_slot0", FIELD_dsp340050b49a6c_fld3538DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3539DUAL_slot0", FIELD_dsp340050b49a6c_fld3539DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3541DUAL_slot0", FIELD_dsp340050b49a6c_fld3541DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3542DUAL_slot0", FIELD_dsp340050b49a6c_fld3542DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3543DUAL_slot0", FIELD_dsp340050b49a6c_fld3543DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3544DUAL_slot0", FIELD_dsp340050b49a6c_fld3544DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3545DUAL_slot0", FIELD_dsp340050b49a6c_fld3545DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3546DUAL_slot0", FIELD_dsp340050b49a6c_fld3546DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3547DUAL_slot0", FIELD_dsp340050b49a6c_fld3547DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3548DUAL_slot0", FIELD_dsp340050b49a6c_fld3548DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3549DUAL_slot0", FIELD_dsp340050b49a6c_fld3549DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3550DUAL_slot0", FIELD_dsp340050b49a6c_fld3550DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3551DUAL_slot0", FIELD_dsp340050b49a6c_fld3551DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3552", FIELD_dsp340050b49a6c_fld3552, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3553DUAL_slot0", FIELD_dsp340050b49a6c_fld3553DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3554DUAL_slot0", FIELD_dsp340050b49a6c_fld3554DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3555DUAL_slot0", FIELD_dsp340050b49a6c_fld3555DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3556DUAL_slot0", FIELD_dsp340050b49a6c_fld3556DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3557DUAL_slot0", FIELD_dsp340050b49a6c_fld3557DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3558DUAL_slot0", FIELD_dsp340050b49a6c_fld3558DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3559DUAL_slot0", FIELD_dsp340050b49a6c_fld3559DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3560DUAL_slot0", FIELD_dsp340050b49a6c_fld3560DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3562DUAL_slot0", FIELD_dsp340050b49a6c_fld3562DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3563DUAL_slot0", FIELD_dsp340050b49a6c_fld3563DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3564DUAL_slot0", FIELD_dsp340050b49a6c_fld3564DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3565DUAL_slot0", FIELD_dsp340050b49a6c_fld3565DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3566DUAL_slot0", FIELD_dsp340050b49a6c_fld3566DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3567DUAL_slot0", FIELD_dsp340050b49a6c_fld3567DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3568DUAL_slot0", FIELD_dsp340050b49a6c_fld3568DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3569DUAL_slot0", FIELD_dsp340050b49a6c_fld3569DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3570DUAL_slot0", FIELD_dsp340050b49a6c_fld3570DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3571DUAL_slot0", FIELD_dsp340050b49a6c_fld3571DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3572DUAL_slot0", FIELD_dsp340050b49a6c_fld3572DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3573DUAL_slot0", FIELD_dsp340050b49a6c_fld3573DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3574DUAL_slot0", FIELD_dsp340050b49a6c_fld3574DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3575DUAL_slot0", FIELD_dsp340050b49a6c_fld3575DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3576DUAL_slot0", FIELD_dsp340050b49a6c_fld3576DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3577DUAL_slot0", FIELD_dsp340050b49a6c_fld3577DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3578DUAL_slot0", FIELD_dsp340050b49a6c_fld3578DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3579DUAL_slot0", FIELD_dsp340050b49a6c_fld3579DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3580DUAL_slot0", FIELD_dsp340050b49a6c_fld3580DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3581DUAL_slot0", FIELD_dsp340050b49a6c_fld3581DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3582DUAL_slot0", FIELD_dsp340050b49a6c_fld3582DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3583DUAL_slot0", FIELD_dsp340050b49a6c_fld3583DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3584", FIELD_dsp340050b49a6c_fld3584, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3585DUAL_slot0", FIELD_dsp340050b49a6c_fld3585DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3587DUAL_slot0", FIELD_dsp340050b49a6c_fld3587DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3588DUAL_slot0", FIELD_dsp340050b49a6c_fld3588DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3589DUAL_slot0", FIELD_dsp340050b49a6c_fld3589DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3590DUAL_slot0", FIELD_dsp340050b49a6c_fld3590DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3591DUAL_slot0", FIELD_dsp340050b49a6c_fld3591DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3592DUAL_slot0", FIELD_dsp340050b49a6c_fld3592DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3593DUAL_slot0", FIELD_dsp340050b49a6c_fld3593DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3594DUAL_slot0", FIELD_dsp340050b49a6c_fld3594DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3595DUAL_slot0", FIELD_dsp340050b49a6c_fld3595DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3596DUAL_slot0", FIELD_dsp340050b49a6c_fld3596DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3597DUAL_slot0", FIELD_dsp340050b49a6c_fld3597DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3598DUAL_slot0", FIELD_dsp340050b49a6c_fld3598DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3599DUAL_slot0", FIELD_dsp340050b49a6c_fld3599DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3600DUAL_slot0", FIELD_dsp340050b49a6c_fld3600DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3601DUAL_slot0", FIELD_dsp340050b49a6c_fld3601DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3602", FIELD_dsp340050b49a6c_fld3602, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3603DUAL_slot0", FIELD_dsp340050b49a6c_fld3603DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3604DUAL_slot0", FIELD_dsp340050b49a6c_fld3604DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3606DUAL_slot0", FIELD_dsp340050b49a6c_fld3606DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3607DUAL_slot0", FIELD_dsp340050b49a6c_fld3607DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3608DUAL_slot0", FIELD_dsp340050b49a6c_fld3608DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3609DUAL_slot0", FIELD_dsp340050b49a6c_fld3609DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3610", FIELD_dsp340050b49a6c_fld3610, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3611DUAL_slot0", FIELD_dsp340050b49a6c_fld3611DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3612DUAL_slot0", FIELD_dsp340050b49a6c_fld3612DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3613DUAL_slot0", FIELD_dsp340050b49a6c_fld3613DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3614DUAL_slot0", FIELD_dsp340050b49a6c_fld3614DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3615DUAL_slot0", FIELD_dsp340050b49a6c_fld3615DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3616DUAL_slot0", FIELD_dsp340050b49a6c_fld3616DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3618DUAL_slot0", FIELD_dsp340050b49a6c_fld3618DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3619", FIELD_dsp340050b49a6c_fld3619, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3620DUAL_slot0", FIELD_dsp340050b49a6c_fld3620DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3621DUAL_slot0", FIELD_dsp340050b49a6c_fld3621DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3622DUAL_slot0", FIELD_dsp340050b49a6c_fld3622DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3623DUAL_slot0", FIELD_dsp340050b49a6c_fld3623DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3624DUAL_slot0", FIELD_dsp340050b49a6c_fld3624DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3625DUAL_slot0", FIELD_dsp340050b49a6c_fld3625DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3626DUAL_slot0", FIELD_dsp340050b49a6c_fld3626DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3936DUAL_slot0", FIELD_dsp340050b49a6c_fld3936DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3937DUAL_slot0", FIELD_dsp340050b49a6c_fld3937DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3938DUAL_slot0", FIELD_dsp340050b49a6c_fld3938DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3939DUAL_slot0", FIELD_dsp340050b49a6c_fld3939DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3940DUAL_slot0", FIELD_dsp340050b49a6c_fld3940DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3941DUAL_slot0", FIELD_dsp340050b49a6c_fld3941DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3943DUAL_slot0", FIELD_dsp340050b49a6c_fld3943DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3945DUAL_slot0", FIELD_dsp340050b49a6c_fld3945DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3946DUAL_slot0", FIELD_dsp340050b49a6c_fld3946DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3947DUAL_slot0", FIELD_dsp340050b49a6c_fld3947DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3949DUAL_slot0", FIELD_dsp340050b49a6c_fld3949DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3950DUAL_slot0", FIELD_dsp340050b49a6c_fld3950DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3951DUAL_slot0", FIELD_dsp340050b49a6c_fld3951DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3952DUAL_slot0", FIELD_dsp340050b49a6c_fld3952DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3954DUAL_slot0", FIELD_dsp340050b49a6c_fld3954DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3957DUAL_slot0", FIELD_dsp340050b49a6c_fld3957DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3958DUAL_slot0", FIELD_dsp340050b49a6c_fld3958DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3959DUAL_slot0", FIELD_dsp340050b49a6c_fld3959DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3960DUAL_slot0", FIELD_dsp340050b49a6c_fld3960DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 }, + { "dsp340050b49a6c_fld3961DUAL_slot0", FIELD_dsp340050b49a6c_fld3961DUAL_slot0, -1, 0, 0, 0, 0, 0, 0 } +}; + +enum xtensa_operand_id { + OPERAND_soffsetx4, + OPERAND_uimm12x8, + OPERAND_simm4, + OPERAND_arr, + OPERAND_ars, + OPERAND__ars_invisible, + OPERAND_art, + OPERAND_ar0, + OPERAND_ar4, + OPERAND_ar8, + OPERAND_ar12, + OPERAND_ars_entry, + OPERAND_immrx4, + OPERAND_lsi4x4, + OPERAND_simm7, + OPERAND_uimm6, + OPERAND_ai4const, + OPERAND_b4const, + OPERAND_b4constu, + OPERAND_uimm8, + OPERAND_uimm8x2, + OPERAND_uimm8x4, + OPERAND_uimm4x16, + OPERAND_simm8, + OPERAND_simm8x256, + OPERAND_simm12b, + OPERAND_msalp32, + OPERAND_op2p1, + OPERAND_label8, + OPERAND_ulabel8, + OPERAND_label12, + OPERAND_soffset, + OPERAND_uimm16x4, + OPERAND_immt, + OPERAND_imms, + OPERAND_bt, + OPERAND_bs, + OPERAND_br, + OPERAND_bt2, + OPERAND_bs2, + OPERAND_br2, + OPERAND_bt4, + OPERAND_bs4, + OPERAND_br4, + OPERAND_bt8, + OPERAND_bs8, + OPERAND_br8, + OPERAND_bt16, + OPERAND_bs16, + OPERAND_br16, + OPERAND_brall, + OPERAND_tp7, + OPERAND_xt_wbr15_label, + OPERAND_xt_wbr18_label, + OPERAND_cimm8x4, + OPERAND_frr, + OPERAND_frs, + OPERAND_frt, + OPERAND_dsp340050b49a6c_oper45_reg, + OPERAND_dsp340050b49a6c_oper46_reg, + OPERAND_dsp340050b49a6c_oper47_reg, + OPERAND_dsp340050b49a6c_oper48_imm, + OPERAND_dsp340050b49a6c_oper49_imm, + OPERAND_dsp340050b49a6c_oper50_reg, + OPERAND_dsp340050b49a6c_oper51_reg, + OPERAND_dsp340050b49a6c_oper52_imm, + OPERAND_dsp340050b49a6c_oper53_reg, + OPERAND_dsp340050b49a6c_oper54_reg, + OPERAND_dsp340050b49a6c_oper55_reg, + OPERAND_dsp340050b49a6c_oper56_reg, + OPERAND_dsp340050b49a6c_oper57_imm, + OPERAND_dsp340050b49a6c_oper58_imm, + OPERAND_dsp340050b49a6c_oper59_imm, + OPERAND_dsp340050b49a6c_oper60_imm, + OPERAND_dsp340050b49a6c_oper61_imm, + OPERAND_dsp340050b49a6c_oper62_reg, + OPERAND_dsp340050b49a6c_oper63_reg, + OPERAND_dsp340050b49a6c_oper64_imm, + OPERAND_dsp340050b49a6c_oper65_reg, + OPERAND_dsp340050b49a6c_oper66_reg, + OPERAND_dsp340050b49a6c_oper67_reg, + OPERAND_dsp340050b49a6c_oper68_imm, + OPERAND_dsp340050b49a6c_oper69_imm, + OPERAND_dsp340050b49a6c_oper70_imm, + OPERAND_dsp340050b49a6c_oper71_reg, + OPERAND_dsp340050b49a6c_oper72_imm, + OPERAND_dsp340050b49a6c_oper73_imm, + OPERAND_dsp340050b49a6c_oper74_imm, + OPERAND_dsp340050b49a6c_oper75_imm, + OPERAND_dsp340050b49a6c_oper76_imm, + OPERAND_dsp340050b49a6c_oper77_reg, + OPERAND_dsp340050b49a6c_oper78_imm, + OPERAND_dsp340050b49a6c_oper79_reg, + OPERAND_dsp340050b49a6c_oper80_reg, + OPERAND_dsp340050b49a6c_oper81_reg, + OPERAND_dsp340050b49a6c_oper82_reg, + OPERAND_dsp340050b49a6c_oper83_imm, + OPERAND_dsp340050b49a6c_oper84_imm, + OPERAND_dsp340050b49a6c_oper85_imm, + OPERAND_dsp340050b49a6c_oper86_imm, + OPERAND_dsp340050b49a6c_oper87_imm, + OPERAND_dsp340050b49a6c_oper88_imm, + OPERAND_dsp340050b49a6c_oper89_imm, + OPERAND_t, + OPERAND_bbi4, + OPERAND_bbi, + OPERAND_imm12, + OPERAND_imm8, + OPERAND_s, + OPERAND_imm12b, + OPERAND_imm16, + OPERAND_m, + OPERAND_n, + OPERAND_offset, + OPERAND_op0, + OPERAND_op1, + OPERAND_op2, + OPERAND_r, + OPERAND_sa4, + OPERAND_sae4, + OPERAND_sae, + OPERAND_sal, + OPERAND_sargt, + OPERAND_sas4, + OPERAND_sas, + OPERAND_sr, + OPERAND_st, + OPERAND_thi3, + OPERAND_imm4, + OPERAND_mn, + OPERAND_i, + OPERAND_imm6lo, + OPERAND_imm6hi, + OPERAND_imm7lo, + OPERAND_imm7hi, + OPERAND_z, + OPERAND_imm6, + OPERAND_imm7, + OPERAND_t2, + OPERAND_s2, + OPERAND_r2, + OPERAND_t4, + OPERAND_s4, + OPERAND_r4, + OPERAND_t8, + OPERAND_s8, + OPERAND_r8, + OPERAND_xt_wbr15_imm, + OPERAND_xt_wbr18_imm, + OPERAND_fimm8, + OPERAND_dsp340050b49a6c_fld2019, + OPERAND_dsp340050b49a6c_fld2021, + OPERAND_dsp340050b49a6c_fld2029, + OPERAND_dsp340050b49a6c_fld2030, + OPERAND_dsp340050b49a6c_fld2032, + OPERAND_dsp340050b49a6c_fld2035, + OPERAND_dsp340050b49a6c_fld2036, + OPERAND_dsp340050b49a6c_fld2037, + OPERAND_dsp340050b49a6c_fld2038, + OPERAND_dsp340050b49a6c_fld2039, + OPERAND_dsp340050b49a6c_fld2040, + OPERAND_dsp340050b49a6c_fld2041, + OPERAND_dsp340050b49a6c_fld2042, + OPERAND_dsp340050b49a6c_fld2043, + OPERAND_dsp340050b49a6c_fld2044, + OPERAND_dsp340050b49a6c_fld2045, + OPERAND_dsp340050b49a6c_fld2046, + OPERAND_dsp340050b49a6c_fld2047, + OPERAND_dsp340050b49a6c_fld2048, + OPERAND_dsp340050b49a6c_fld2049, + OPERAND_dsp340050b49a6c_fld2050, + OPERAND_dsp340050b49a6c_fld2051, + OPERAND_dsp340050b49a6c_fld2052, + OPERAND_dsp340050b49a6c_fld2053, + OPERAND_dsp340050b49a6c_fld2054, + OPERAND_dsp340050b49a6c_fld2055, + OPERAND_dsp340050b49a6c_fld2056, + OPERAND_dsp340050b49a6c_fld2082Inst, + OPERAND_dsp340050b49a6c_fld2083Inst, + OPERAND_dsp340050b49a6c_fld2084Inst, + OPERAND_dsp340050b49a6c_fld2085Inst, + OPERAND_dsp340050b49a6c_fld2086Inst, + OPERAND_dsp340050b49a6c_fld2088Inst, + OPERAND_dsp340050b49a6c_fld2089Inst, + OPERAND_dsp340050b49a6c_fld2090Inst, + OPERAND_dsp340050b49a6c_fld2091Inst, + OPERAND_dsp340050b49a6c_fld2092Inst, + OPERAND_dsp340050b49a6c_fld2094Inst, + OPERAND_dsp340050b49a6c_fld2095Inst, + OPERAND_dsp340050b49a6c_fld2096Inst, + OPERAND_dsp340050b49a6c_fld2098Inst, + OPERAND_dsp340050b49a6c_fld2099Inst, + OPERAND_dsp340050b49a6c_fld2100Inst, + OPERAND_dsp340050b49a6c_fld2101Inst, + OPERAND_dsp340050b49a6c_fld2102Inst, + OPERAND_dsp340050b49a6c_fld2103Inst, + OPERAND_dsp340050b49a6c_fld2104Inst, + OPERAND_dsp340050b49a6c_fld2105Inst, + OPERAND_dsp340050b49a6c_fld2106Inst, + OPERAND_dsp340050b49a6c_fld2107Inst, + OPERAND_dsp340050b49a6c_fld2108Inst, + OPERAND_dsp340050b49a6c_fld2109Inst, + OPERAND_dsp340050b49a6c_fld2110Inst, + OPERAND_dsp340050b49a6c_fld2111Inst, + OPERAND_dsp340050b49a6c_fld2112Inst, + OPERAND_dsp340050b49a6c_fld2113Inst, + OPERAND_dsp340050b49a6c_fld2114Inst, + OPERAND_dsp340050b49a6c_fld2115Inst, + OPERAND_dsp340050b49a6c_fld2116Inst, + OPERAND_dsp340050b49a6c_fld2117Inst, + OPERAND_dsp340050b49a6c_fld2118Inst, + OPERAND_dsp340050b49a6c_fld2119Inst, + OPERAND_dsp340050b49a6c_fld2120Inst, + OPERAND_dsp340050b49a6c_fld2122Inst, + OPERAND_dsp340050b49a6c_fld2123Inst, + OPERAND_dsp340050b49a6c_fld2124Inst, + OPERAND_dsp340050b49a6c_fld2125Inst, + OPERAND_dsp340050b49a6c_fld2126Inst, + OPERAND_dsp340050b49a6c_fld2127Inst, + OPERAND_dsp340050b49a6c_fld2128Inst, + OPERAND_dsp340050b49a6c_fld2129Inst, + OPERAND_dsp340050b49a6c_fld2131Inst, + OPERAND_dsp340050b49a6c_fld2132Inst, + OPERAND_dsp340050b49a6c_fld2133Inst, + OPERAND_dsp340050b49a6c_fld2134Inst, + OPERAND_dsp340050b49a6c_fld2136Inst, + OPERAND_dsp340050b49a6c_fld2137Inst, + OPERAND_dsp340050b49a6c_fld2138Inst, + OPERAND_dsp340050b49a6c_fld2139Inst, + OPERAND_dsp340050b49a6c_fld2140Inst, + OPERAND_dsp340050b49a6c_fld2141Inst, + OPERAND_dsp340050b49a6c_fld2142Inst, + OPERAND_dsp340050b49a6c_fld2143Inst, + OPERAND_dsp340050b49a6c_fld2144Inst, + OPERAND_dsp340050b49a6c_fld2145Inst, + OPERAND_dsp340050b49a6c_fld2146Inst, + OPERAND_dsp340050b49a6c_fld2147Inst, + OPERAND_dsp340050b49a6c_fld2149Inst, + OPERAND_dsp340050b49a6c_fld2151Inst, + OPERAND_dsp340050b49a6c_fld2153Inst, + OPERAND_dsp340050b49a6c_fld2154Inst, + OPERAND_dsp340050b49a6c_fld2155Inst, + OPERAND_dsp340050b49a6c_fld2156Inst, + OPERAND_dsp340050b49a6c_fld2157Inst, + OPERAND_dsp340050b49a6c_fld2158Inst, + OPERAND_dsp340050b49a6c_fld2159Inst, + OPERAND_dsp340050b49a6c_fld2160Inst, + OPERAND_dsp340050b49a6c_fld2161Inst, + OPERAND_dsp340050b49a6c_fld2162Inst, + OPERAND_dsp340050b49a6c_fld2163Inst, + OPERAND_dsp340050b49a6c_fld2164Inst, + OPERAND_dsp340050b49a6c_fld2165Inst, + OPERAND_dsp340050b49a6c_fld2166Inst, + OPERAND_dsp340050b49a6c_fld2167Inst, + OPERAND_dsp340050b49a6c_fld2168Inst, + OPERAND_dsp340050b49a6c_fld2169Inst, + OPERAND_dsp340050b49a6c_fld2171Inst, + OPERAND_dsp340050b49a6c_fld2172Inst, + OPERAND_dsp340050b49a6c_fld2173Inst, + OPERAND_dsp340050b49a6c_fld2174Inst, + OPERAND_dsp340050b49a6c_fld2175Inst, + OPERAND_dsp340050b49a6c_fld2177Inst, + OPERAND_dsp340050b49a6c_fld2178Inst, + OPERAND_dsp340050b49a6c_fld2179Inst, + OPERAND_dsp340050b49a6c_fld2180Inst, + OPERAND_dsp340050b49a6c_fld2181Inst, + OPERAND_dsp340050b49a6c_fld2182Inst, + OPERAND_dsp340050b49a6c_fld2183Inst, + OPERAND_dsp340050b49a6c_fld2184Inst, + OPERAND_dsp340050b49a6c_fld2185Inst, + OPERAND_dsp340050b49a6c_fld2186Inst, + OPERAND_dsp340050b49a6c_fld2187Inst, + OPERAND_dsp340050b49a6c_fld2188Inst, + OPERAND_dsp340050b49a6c_fld2189Inst, + OPERAND_dsp340050b49a6c_fld2190Inst, + OPERAND_dsp340050b49a6c_fld2191Inst, + OPERAND_dsp340050b49a6c_fld2192Inst, + OPERAND_dsp340050b49a6c_fld2193Inst, + OPERAND_dsp340050b49a6c_fld2194Inst, + OPERAND_dsp340050b49a6c_fld2195Inst, + OPERAND_dsp340050b49a6c_fld2196Inst, + OPERAND_dsp340050b49a6c_fld2197Inst, + OPERAND_dsp340050b49a6c_fld2198Inst, + OPERAND_dsp340050b49a6c_fld2199Inst, + OPERAND_dsp340050b49a6c_fld2200Inst, + OPERAND_dsp340050b49a6c_fld2201Inst, + OPERAND_dsp340050b49a6c_fld2202Inst, + OPERAND_dsp340050b49a6c_fld2203Inst, + OPERAND_dsp340050b49a6c_fld2204Inst, + OPERAND_dsp340050b49a6c_fld2205Inst, + OPERAND_dsp340050b49a6c_fld2206Inst, + OPERAND_dsp340050b49a6c_fld2207Inst, + OPERAND_dsp340050b49a6c_fld2208Inst, + OPERAND_dsp340050b49a6c_fld2209Inst, + OPERAND_dsp340050b49a6c_fld2210Inst, + OPERAND_dsp340050b49a6c_fld2211Inst, + OPERAND_dsp340050b49a6c_fld2212Inst, + OPERAND_dsp340050b49a6c_fld2213Inst, + OPERAND_dsp340050b49a6c_fld2214Inst, + OPERAND_dsp340050b49a6c_fld2215Inst, + OPERAND_dsp340050b49a6c_fld2216Inst, + OPERAND_dsp340050b49a6c_fld2217Inst, + OPERAND_dsp340050b49a6c_fld2218Inst, + OPERAND_dsp340050b49a6c_fld2219Inst, + OPERAND_dsp340050b49a6c_fld2220Inst, + OPERAND_dsp340050b49a6c_fld2221Inst, + OPERAND_dsp340050b49a6c_fld2222Inst, + OPERAND_dsp340050b49a6c_fld2223Inst, + OPERAND_dsp340050b49a6c_fld2224Inst, + OPERAND_dsp340050b49a6c_fld2225Inst, + OPERAND_dsp340050b49a6c_fld2226Inst, + OPERAND_dsp340050b49a6c_fld2227Inst, + OPERAND_dsp340050b49a6c_fld2228Inst, + OPERAND_dsp340050b49a6c_fld2229Inst, + OPERAND_dsp340050b49a6c_fld2230Inst, + OPERAND_dsp340050b49a6c_fld2231Inst, + OPERAND_dsp340050b49a6c_fld2232Inst, + OPERAND_dsp340050b49a6c_fld2234Inst, + OPERAND_dsp340050b49a6c_fld2235Inst, + OPERAND_dsp340050b49a6c_fld2236Inst, + OPERAND_dsp340050b49a6c_fld2237Inst, + OPERAND_dsp340050b49a6c_fld2238Inst, + OPERAND_dsp340050b49a6c_fld2239Inst, + OPERAND_dsp340050b49a6c_fld2240Inst, + OPERAND_dsp340050b49a6c_fld2241Inst, + OPERAND_dsp340050b49a6c_fld2242Inst, + OPERAND_dsp340050b49a6c_fld2243Inst, + OPERAND_dsp340050b49a6c_fld2244Inst, + OPERAND_dsp340050b49a6c_fld2245Inst, + OPERAND_dsp340050b49a6c_fld2246Inst, + OPERAND_dsp340050b49a6c_fld2247Inst, + OPERAND_dsp340050b49a6c_fld2248Inst, + OPERAND_dsp340050b49a6c_fld2249Inst, + OPERAND_dsp340050b49a6c_fld2250Inst, + OPERAND_dsp340050b49a6c_fld2251Inst, + OPERAND_dsp340050b49a6c_fld2252Inst, + OPERAND_dsp340050b49a6c_fld2253Inst, + OPERAND_dsp340050b49a6c_fld2254, + OPERAND_dsp340050b49a6c_fld2255Inst, + OPERAND_dsp340050b49a6c_fld2257Inst, + OPERAND_dsp340050b49a6c_fld3627Inst, + OPERAND_dsp340050b49a6c_fld3630Inst, + OPERAND_dsp340050b49a6c_fld3631Inst, + OPERAND_dsp340050b49a6c_fld3633Inst, + OPERAND_dsp340050b49a6c_fld3634, + OPERAND_dsp340050b49a6c_fld3635Inst, + OPERAND_dsp340050b49a6c_fld3636Inst, + OPERAND_dsp340050b49a6c_fld3637Inst, + OPERAND_dsp340050b49a6c_fld3638Inst, + OPERAND_dsp340050b49a6c_fld3639Inst, + OPERAND_dsp340050b49a6c_fld3640Inst, + OPERAND_dsp340050b49a6c_fld3642Inst, + OPERAND_dsp340050b49a6c_fld3643Inst, + OPERAND_dsp340050b49a6c_fld3644Inst, + OPERAND_dsp340050b49a6c_fld3645Inst, + OPERAND_dsp340050b49a6c_fld3647Inst, + OPERAND_dsp340050b49a6c_fld3648Inst, + OPERAND_dsp340050b49a6c_fld3649Inst, + OPERAND_dsp340050b49a6c_fld3650Inst, + OPERAND_dsp340050b49a6c_fld3651Inst, + OPERAND_dsp340050b49a6c_fld3653Inst, + OPERAND_dsp340050b49a6c_fld3654Inst, + OPERAND_dsp340050b49a6c_fld3655Inst, + OPERAND_dsp340050b49a6c_fld3656Inst, + OPERAND_dsp340050b49a6c_fld3657Inst, + OPERAND_dsp340050b49a6c_fld3658Inst, + OPERAND_dsp340050b49a6c_fld3659Inst, + OPERAND_dsp340050b49a6c_fld3660Inst, + OPERAND_dsp340050b49a6c_fld3661Inst, + OPERAND_dsp340050b49a6c_fld3662Inst, + OPERAND_op0_s3, + OPERAND_dsp340050b49a6c_fld2025, + OPERAND_dsp340050b49a6c_fld2027, + OPERAND_dsp340050b49a6c_fld2258GP_slot2, + OPERAND_dsp340050b49a6c_fld2259GP_slot2, + OPERAND_dsp340050b49a6c_fld2260GP_slot2, + OPERAND_dsp340050b49a6c_fld2261GP_slot2, + OPERAND_dsp340050b49a6c_fld2262GP_slot2, + OPERAND_dsp340050b49a6c_fld2263GP_slot2, + OPERAND_dsp340050b49a6c_fld2264GP_slot2, + OPERAND_dsp340050b49a6c_fld2266GP_slot2, + OPERAND_dsp340050b49a6c_fld2267GP_slot2, + OPERAND_dsp340050b49a6c_fld2268GP_slot2, + OPERAND_dsp340050b49a6c_fld2269GP_slot2, + OPERAND_dsp340050b49a6c_fld2270GP_slot2, + OPERAND_dsp340050b49a6c_fld2271GP_slot2, + OPERAND_dsp340050b49a6c_fld2272, + OPERAND_dsp340050b49a6c_fld2273GP_slot2, + OPERAND_dsp340050b49a6c_fld2274GP_slot2, + OPERAND_dsp340050b49a6c_fld2275GP_slot2, + OPERAND_dsp340050b49a6c_fld2277GP_slot2, + OPERAND_dsp340050b49a6c_fld2278GP_slot2, + OPERAND_dsp340050b49a6c_fld2279GP_slot2, + OPERAND_dsp340050b49a6c_fld2280GP_slot2, + OPERAND_dsp340050b49a6c_fld2281GP_slot2, + OPERAND_dsp340050b49a6c_fld2282GP_slot2, + OPERAND_dsp340050b49a6c_fld2283GP_slot2, + OPERAND_dsp340050b49a6c_fld2284GP_slot2, + OPERAND_dsp340050b49a6c_fld2286GP_slot2, + OPERAND_dsp340050b49a6c_fld2287GP_slot2, + OPERAND_dsp340050b49a6c_fld2288GP_slot2, + OPERAND_dsp340050b49a6c_fld2289GP_slot2, + OPERAND_dsp340050b49a6c_fld2290GP_slot2, + OPERAND_dsp340050b49a6c_fld2291GP_slot2, + OPERAND_dsp340050b49a6c_fld2292GP_slot2, + OPERAND_dsp340050b49a6c_fld2293GP_slot2, + OPERAND_dsp340050b49a6c_fld2294GP_slot2, + OPERAND_dsp340050b49a6c_fld2295GP_slot2, + OPERAND_dsp340050b49a6c_fld2296GP_slot2, + OPERAND_dsp340050b49a6c_fld2297GP_slot2, + OPERAND_dsp340050b49a6c_fld2298GP_slot2, + OPERAND_dsp340050b49a6c_fld2299GP_slot2, + OPERAND_dsp340050b49a6c_fld2300GP_slot2, + OPERAND_dsp340050b49a6c_fld2301GP_slot2, + OPERAND_dsp340050b49a6c_fld2302, + OPERAND_dsp340050b49a6c_fld2303GP_slot2, + OPERAND_dsp340050b49a6c_fld2304GP_slot2, + OPERAND_dsp340050b49a6c_fld2305, + OPERAND_dsp340050b49a6c_fld2306GP_slot2, + OPERAND_dsp340050b49a6c_fld2308GP_slot2, + OPERAND_dsp340050b49a6c_fld2309GP_slot2, + OPERAND_dsp340050b49a6c_fld2310GP_slot2, + OPERAND_dsp340050b49a6c_fld2312GP_slot2, + OPERAND_dsp340050b49a6c_fld2313, + OPERAND_dsp340050b49a6c_fld2314GP_slot2, + OPERAND_dsp340050b49a6c_fld2316GP_slot2, + OPERAND_dsp340050b49a6c_fld2317GP_slot2, + OPERAND_dsp340050b49a6c_fld2318GP_slot2, + OPERAND_dsp340050b49a6c_fld2319GP_slot2, + OPERAND_dsp340050b49a6c_fld2320GP_slot2, + OPERAND_dsp340050b49a6c_fld2321GP_slot2, + OPERAND_dsp340050b49a6c_fld2322GP_slot2, + OPERAND_dsp340050b49a6c_fld2323GP_slot2, + OPERAND_dsp340050b49a6c_fld2324GP_slot2, + OPERAND_dsp340050b49a6c_fld2325GP_slot2, + OPERAND_dsp340050b49a6c_fld2326GP_slot2, + OPERAND_dsp340050b49a6c_fld2327GP_slot2, + OPERAND_dsp340050b49a6c_fld2328GP_slot2, + OPERAND_dsp340050b49a6c_fld2329GP_slot2, + OPERAND_dsp340050b49a6c_fld2330GP_slot2, + OPERAND_dsp340050b49a6c_fld2331GP_slot2, + OPERAND_dsp340050b49a6c_fld2332GP_slot2, + OPERAND_dsp340050b49a6c_fld2333GP_slot2, + OPERAND_dsp340050b49a6c_fld2334GP_slot2, + OPERAND_dsp340050b49a6c_fld2335GP_slot2, + OPERAND_dsp340050b49a6c_fld2336GP_slot2, + OPERAND_dsp340050b49a6c_fld2337GP_slot2, + OPERAND_dsp340050b49a6c_fld2338GP_slot2, + OPERAND_dsp340050b49a6c_fld2339GP_slot2, + OPERAND_dsp340050b49a6c_fld2340GP_slot2, + OPERAND_dsp340050b49a6c_fld2341GP_slot2, + OPERAND_dsp340050b49a6c_fld2342GP_slot2, + OPERAND_dsp340050b49a6c_fld2343GP_slot2, + OPERAND_dsp340050b49a6c_fld2344GP_slot2, + OPERAND_dsp340050b49a6c_fld2345GP_slot2, + OPERAND_dsp340050b49a6c_fld2346GP_slot2, + OPERAND_dsp340050b49a6c_fld2347GP_slot2, + OPERAND_dsp340050b49a6c_fld2348GP_slot2, + OPERAND_dsp340050b49a6c_fld2349GP_slot2, + OPERAND_dsp340050b49a6c_fld2350GP_slot2, + OPERAND_dsp340050b49a6c_fld2351GP_slot2, + OPERAND_dsp340050b49a6c_fld2352GP_slot2, + OPERAND_dsp340050b49a6c_fld2353GP_slot2, + OPERAND_dsp340050b49a6c_fld2354GP_slot2, + OPERAND_dsp340050b49a6c_fld2355GP_slot2, + OPERAND_dsp340050b49a6c_fld2356GP_slot2, + OPERAND_dsp340050b49a6c_fld2357GP_slot2, + OPERAND_dsp340050b49a6c_fld2358GP_slot2, + OPERAND_dsp340050b49a6c_fld2359GP_slot2, + OPERAND_dsp340050b49a6c_fld2361GP_slot2, + OPERAND_dsp340050b49a6c_fld2362GP_slot2, + OPERAND_dsp340050b49a6c_fld2364GP_slot2, + OPERAND_dsp340050b49a6c_fld2366GP_slot2, + OPERAND_dsp340050b49a6c_fld2368GP_slot2, + OPERAND_dsp340050b49a6c_fld2369GP_slot2, + OPERAND_dsp340050b49a6c_fld2370GP_slot2, + OPERAND_dsp340050b49a6c_fld2371GP_slot2, + OPERAND_dsp340050b49a6c_fld2372GP_slot2, + OPERAND_dsp340050b49a6c_fld2373GP_slot2, + OPERAND_dsp340050b49a6c_fld2374GP_slot2, + OPERAND_dsp340050b49a6c_fld2375GP_slot2, + OPERAND_dsp340050b49a6c_fld2376GP_slot2, + OPERAND_dsp340050b49a6c_fld2378GP_slot2, + OPERAND_dsp340050b49a6c_fld2379GP_slot2, + OPERAND_dsp340050b49a6c_fld2381GP_slot2, + OPERAND_dsp340050b49a6c_fld2383GP_slot2, + OPERAND_dsp340050b49a6c_fld2384, + OPERAND_dsp340050b49a6c_fld2385GP_slot2, + OPERAND_dsp340050b49a6c_fld2386, + OPERAND_dsp340050b49a6c_fld2387GP_slot2, + OPERAND_dsp340050b49a6c_fld2388GP_slot2, + OPERAND_dsp340050b49a6c_fld2389GP_slot2, + OPERAND_dsp340050b49a6c_fld3663GP_slot2, + OPERAND_dsp340050b49a6c_fld3664GP_slot2, + OPERAND_dsp340050b49a6c_fld3665GP_slot2, + OPERAND_dsp340050b49a6c_fld3666, + OPERAND_dsp340050b49a6c_fld3667GP_slot2, + OPERAND_dsp340050b49a6c_fld3668GP_slot2, + OPERAND_dsp340050b49a6c_fld3669GP_slot2, + OPERAND_dsp340050b49a6c_fld3670GP_slot2, + OPERAND_dsp340050b49a6c_fld3671GP_slot2, + OPERAND_dsp340050b49a6c_fld3673GP_slot2, + OPERAND_dsp340050b49a6c_fld3674GP_slot2, + OPERAND_dsp340050b49a6c_fld3675GP_slot2, + OPERAND_dsp340050b49a6c_fld3676GP_slot2, + OPERAND_dsp340050b49a6c_fld3678GP_slot2, + OPERAND_dsp340050b49a6c_fld3679GP_slot2, + OPERAND_dsp340050b49a6c_fld3680GP_slot2, + OPERAND_op0_s4, + OPERAND_dsp340050b49a6c_fld2026, + OPERAND_dsp340050b49a6c_fld2031, + OPERAND_dsp340050b49a6c_fld2394GP_slot1, + OPERAND_dsp340050b49a6c_fld2395GP_slot1, + OPERAND_dsp340050b49a6c_fld2397GP_slot1, + OPERAND_dsp340050b49a6c_fld2398GP_slot1, + OPERAND_dsp340050b49a6c_fld2399GP_slot1, + OPERAND_dsp340050b49a6c_fld2400GP_slot1, + OPERAND_dsp340050b49a6c_fld2402GP_slot1, + OPERAND_dsp340050b49a6c_fld2403GP_slot1, + OPERAND_dsp340050b49a6c_fld2405GP_slot1, + OPERAND_dsp340050b49a6c_fld3681GP_slot1, + OPERAND_dsp340050b49a6c_fld3683GP_slot1, + OPERAND_dsp340050b49a6c_fld3684GP_slot1, + OPERAND_dsp340050b49a6c_fld3686GP_slot1, + OPERAND_op0_s5, + OPERAND_dsp340050b49a6c_fld2058, + OPERAND_dsp340050b49a6c_fld2067, + OPERAND_dsp340050b49a6c_fld2407GP_slot0, + OPERAND_dsp340050b49a6c_fld2409GP_slot0, + OPERAND_dsp340050b49a6c_fld2410GP_slot0, + OPERAND_dsp340050b49a6c_fld2411GP_slot0, + OPERAND_dsp340050b49a6c_fld2412GP_slot0, + OPERAND_dsp340050b49a6c_fld2413GP_slot0, + OPERAND_dsp340050b49a6c_fld2415GP_slot0, + OPERAND_dsp340050b49a6c_fld2416GP_slot0, + OPERAND_dsp340050b49a6c_fld2417GP_slot0, + OPERAND_dsp340050b49a6c_fld2418GP_slot0, + OPERAND_dsp340050b49a6c_fld2419GP_slot0, + OPERAND_dsp340050b49a6c_fld2420GP_slot0, + OPERAND_dsp340050b49a6c_fld2422GP_slot0, + OPERAND_dsp340050b49a6c_fld2423GP_slot0, + OPERAND_dsp340050b49a6c_fld2424GP_slot0, + OPERAND_dsp340050b49a6c_fld2425GP_slot0, + OPERAND_dsp340050b49a6c_fld2426GP_slot0, + OPERAND_dsp340050b49a6c_fld2427GP_slot0, + OPERAND_dsp340050b49a6c_fld2429GP_slot0, + OPERAND_dsp340050b49a6c_fld2430GP_slot0, + OPERAND_dsp340050b49a6c_fld2431GP_slot0, + OPERAND_dsp340050b49a6c_fld2432GP_slot0, + OPERAND_dsp340050b49a6c_fld2433GP_slot0, + OPERAND_dsp340050b49a6c_fld2434GP_slot0, + OPERAND_dsp340050b49a6c_fld2435GP_slot0, + OPERAND_dsp340050b49a6c_fld2436GP_slot0, + OPERAND_dsp340050b49a6c_fld2437GP_slot0, + OPERAND_dsp340050b49a6c_fld2438GP_slot0, + OPERAND_dsp340050b49a6c_fld2439GP_slot0, + OPERAND_dsp340050b49a6c_fld2440GP_slot0, + OPERAND_dsp340050b49a6c_fld2441GP_slot0, + OPERAND_dsp340050b49a6c_fld2443GP_slot0, + OPERAND_dsp340050b49a6c_fld2444GP_slot0, + OPERAND_dsp340050b49a6c_fld2445, + OPERAND_dsp340050b49a6c_fld2447GP_slot0, + OPERAND_dsp340050b49a6c_fld2448, + OPERAND_dsp340050b49a6c_fld2449GP_slot0, + OPERAND_dsp340050b49a6c_fld2451GP_slot0, + OPERAND_dsp340050b49a6c_fld2452GP_slot0, + OPERAND_dsp340050b49a6c_fld2453GP_slot0, + OPERAND_dsp340050b49a6c_fld2454GP_slot0, + OPERAND_dsp340050b49a6c_fld2455GP_slot0, + OPERAND_dsp340050b49a6c_fld2456GP_slot0, + OPERAND_dsp340050b49a6c_fld2457GP_slot0, + OPERAND_dsp340050b49a6c_fld2458GP_slot0, + OPERAND_dsp340050b49a6c_fld2459GP_slot0, + OPERAND_dsp340050b49a6c_fld2460GP_slot0, + OPERAND_dsp340050b49a6c_fld2461GP_slot0, + OPERAND_dsp340050b49a6c_fld2462, + OPERAND_dsp340050b49a6c_fld2463GP_slot0, + OPERAND_dsp340050b49a6c_fld2464GP_slot0, + OPERAND_dsp340050b49a6c_fld2465GP_slot0, + OPERAND_dsp340050b49a6c_fld2466GP_slot0, + OPERAND_dsp340050b49a6c_fld2467GP_slot0, + OPERAND_dsp340050b49a6c_fld2468GP_slot0, + OPERAND_dsp340050b49a6c_fld2470GP_slot0, + OPERAND_dsp340050b49a6c_fld2471GP_slot0, + OPERAND_dsp340050b49a6c_fld2472GP_slot0, + OPERAND_dsp340050b49a6c_fld2473GP_slot0, + OPERAND_dsp340050b49a6c_fld2474GP_slot0, + OPERAND_dsp340050b49a6c_fld2475GP_slot0, + OPERAND_dsp340050b49a6c_fld2477GP_slot0, + OPERAND_dsp340050b49a6c_fld2479GP_slot0, + OPERAND_dsp340050b49a6c_fld2480GP_slot0, + OPERAND_dsp340050b49a6c_fld2481GP_slot0, + OPERAND_dsp340050b49a6c_fld2482GP_slot0, + OPERAND_dsp340050b49a6c_fld2483GP_slot0, + OPERAND_dsp340050b49a6c_fld2484GP_slot0, + OPERAND_dsp340050b49a6c_fld2485GP_slot0, + OPERAND_dsp340050b49a6c_fld2486GP_slot0, + OPERAND_dsp340050b49a6c_fld2487GP_slot0, + OPERAND_dsp340050b49a6c_fld2488GP_slot0, + OPERAND_dsp340050b49a6c_fld2489GP_slot0, + OPERAND_dsp340050b49a6c_fld2490GP_slot0, + OPERAND_dsp340050b49a6c_fld2491GP_slot0, + OPERAND_dsp340050b49a6c_fld2492GP_slot0, + OPERAND_dsp340050b49a6c_fld2493GP_slot0, + OPERAND_dsp340050b49a6c_fld2494GP_slot0, + OPERAND_dsp340050b49a6c_fld2495GP_slot0, + OPERAND_dsp340050b49a6c_fld2496GP_slot0, + OPERAND_dsp340050b49a6c_fld2497GP_slot0, + OPERAND_dsp340050b49a6c_fld2498GP_slot0, + OPERAND_dsp340050b49a6c_fld2499GP_slot0, + OPERAND_dsp340050b49a6c_fld2500GP_slot0, + OPERAND_dsp340050b49a6c_fld2501GP_slot0, + OPERAND_dsp340050b49a6c_fld2502GP_slot0, + OPERAND_dsp340050b49a6c_fld2503GP_slot0, + OPERAND_dsp340050b49a6c_fld2504GP_slot0, + OPERAND_dsp340050b49a6c_fld2505GP_slot0, + OPERAND_dsp340050b49a6c_fld2506GP_slot0, + OPERAND_dsp340050b49a6c_fld2507GP_slot0, + OPERAND_dsp340050b49a6c_fld2508GP_slot0, + OPERAND_dsp340050b49a6c_fld2509GP_slot0, + OPERAND_dsp340050b49a6c_fld2510GP_slot0, + OPERAND_dsp340050b49a6c_fld2512GP_slot0, + OPERAND_dsp340050b49a6c_fld2514GP_slot0, + OPERAND_dsp340050b49a6c_fld2515GP_slot0, + OPERAND_dsp340050b49a6c_fld2516GP_slot0, + OPERAND_dsp340050b49a6c_fld2517GP_slot0, + OPERAND_dsp340050b49a6c_fld2518GP_slot0, + OPERAND_dsp340050b49a6c_fld2519GP_slot0, + OPERAND_dsp340050b49a6c_fld2520GP_slot0, + OPERAND_dsp340050b49a6c_fld2521GP_slot0, + OPERAND_dsp340050b49a6c_fld2523GP_slot0, + OPERAND_dsp340050b49a6c_fld2524GP_slot0, + OPERAND_dsp340050b49a6c_fld2526GP_slot0, + OPERAND_dsp340050b49a6c_fld2527GP_slot0, + OPERAND_dsp340050b49a6c_fld2528GP_slot0, + OPERAND_dsp340050b49a6c_fld2529GP_slot0, + OPERAND_dsp340050b49a6c_fld2530, + OPERAND_dsp340050b49a6c_fld2531GP_slot0, + OPERAND_dsp340050b49a6c_fld3688GP_slot0, + OPERAND_dsp340050b49a6c_fld3689GP_slot0, + OPERAND_dsp340050b49a6c_fld3690GP_slot0, + OPERAND_dsp340050b49a6c_fld3691GP_slot0, + OPERAND_dsp340050b49a6c_fld3692GP_slot0, + OPERAND_dsp340050b49a6c_fld3693GP_slot0, + OPERAND_dsp340050b49a6c_fld3695GP_slot0, + OPERAND_dsp340050b49a6c_fld3696GP_slot0, + OPERAND_dsp340050b49a6c_fld3697GP_slot0, + OPERAND_dsp340050b49a6c_fld3698GP_slot0, + OPERAND_dsp340050b49a6c_fld3699GP_slot0, + OPERAND_dsp340050b49a6c_fld3700GP_slot0, + OPERAND_dsp340050b49a6c_fld3702GP_slot0, + OPERAND_dsp340050b49a6c_fld3703GP_slot0, + OPERAND_dsp340050b49a6c_fld3705GP_slot0, + OPERAND_dsp340050b49a6c_fld3706GP_slot0, + OPERAND_op0_s6, + OPERAND_dsp340050b49a6c_fld2532DOT_slot2, + OPERAND_dsp340050b49a6c_fld2533DOT_slot2, + OPERAND_dsp340050b49a6c_fld2534DOT_slot2, + OPERAND_dsp340050b49a6c_fld2535DOT_slot2, + OPERAND_dsp340050b49a6c_fld2536DOT_slot2, + OPERAND_dsp340050b49a6c_fld2537DOT_slot2, + OPERAND_dsp340050b49a6c_fld2538DOT_slot2, + OPERAND_dsp340050b49a6c_fld2539DOT_slot2, + OPERAND_dsp340050b49a6c_fld2540DOT_slot2, + OPERAND_dsp340050b49a6c_fld2541DOT_slot2, + OPERAND_dsp340050b49a6c_fld2542DOT_slot2, + OPERAND_dsp340050b49a6c_fld2543DOT_slot2, + OPERAND_dsp340050b49a6c_fld2544DOT_slot2, + OPERAND_dsp340050b49a6c_fld2545DOT_slot2, + OPERAND_dsp340050b49a6c_fld2546DOT_slot2, + OPERAND_dsp340050b49a6c_fld2547DOT_slot2, + OPERAND_dsp340050b49a6c_fld2548DOT_slot2, + OPERAND_dsp340050b49a6c_fld2549DOT_slot2, + OPERAND_dsp340050b49a6c_fld2550DOT_slot2, + OPERAND_dsp340050b49a6c_fld2551DOT_slot2, + OPERAND_dsp340050b49a6c_fld2552DOT_slot2, + OPERAND_dsp340050b49a6c_fld2553DOT_slot2, + OPERAND_dsp340050b49a6c_fld2554DOT_slot2, + OPERAND_dsp340050b49a6c_fld2555DOT_slot2, + OPERAND_dsp340050b49a6c_fld2556DOT_slot2, + OPERAND_dsp340050b49a6c_fld2557DOT_slot2, + OPERAND_dsp340050b49a6c_fld2558DOT_slot2, + OPERAND_dsp340050b49a6c_fld2559DOT_slot2, + OPERAND_dsp340050b49a6c_fld2560DOT_slot2, + OPERAND_dsp340050b49a6c_fld2561DOT_slot2, + OPERAND_dsp340050b49a6c_fld2562DOT_slot2, + OPERAND_dsp340050b49a6c_fld2563DOT_slot2, + OPERAND_dsp340050b49a6c_fld2564DOT_slot2, + OPERAND_dsp340050b49a6c_fld2565DOT_slot2, + OPERAND_dsp340050b49a6c_fld2566DOT_slot2, + OPERAND_dsp340050b49a6c_fld2567DOT_slot2, + OPERAND_dsp340050b49a6c_fld2568DOT_slot2, + OPERAND_dsp340050b49a6c_fld2569DOT_slot2, + OPERAND_dsp340050b49a6c_fld2571DOT_slot2, + OPERAND_dsp340050b49a6c_fld2572DOT_slot2, + OPERAND_dsp340050b49a6c_fld2573DOT_slot2, + OPERAND_dsp340050b49a6c_fld2574DOT_slot2, + OPERAND_dsp340050b49a6c_fld2575DOT_slot2, + OPERAND_dsp340050b49a6c_fld2576DOT_slot2, + OPERAND_dsp340050b49a6c_fld2577DOT_slot2, + OPERAND_dsp340050b49a6c_fld2578, + OPERAND_dsp340050b49a6c_fld2579DOT_slot2, + OPERAND_dsp340050b49a6c_fld2580DOT_slot2, + OPERAND_dsp340050b49a6c_fld2581DOT_slot2, + OPERAND_dsp340050b49a6c_fld2582DOT_slot2, + OPERAND_dsp340050b49a6c_fld2583DOT_slot2, + OPERAND_dsp340050b49a6c_fld2584DOT_slot2, + OPERAND_dsp340050b49a6c_fld2585DOT_slot2, + OPERAND_dsp340050b49a6c_fld2586DOT_slot2, + OPERAND_dsp340050b49a6c_fld2587DOT_slot2, + OPERAND_dsp340050b49a6c_fld2588DOT_slot2, + OPERAND_dsp340050b49a6c_fld2589DOT_slot2, + OPERAND_dsp340050b49a6c_fld2590DOT_slot2, + OPERAND_dsp340050b49a6c_fld2591DOT_slot2, + OPERAND_dsp340050b49a6c_fld2592DOT_slot2, + OPERAND_dsp340050b49a6c_fld2595DOT_slot2, + OPERAND_dsp340050b49a6c_fld2596DOT_slot2, + OPERAND_dsp340050b49a6c_fld2598DOT_slot2, + OPERAND_dsp340050b49a6c_fld2599DOT_slot2, + OPERAND_dsp340050b49a6c_fld2601DOT_slot2, + OPERAND_dsp340050b49a6c_fld2602DOT_slot2, + OPERAND_dsp340050b49a6c_fld2604DOT_slot2, + OPERAND_dsp340050b49a6c_fld2605, + OPERAND_dsp340050b49a6c_fld2606DOT_slot2, + OPERAND_dsp340050b49a6c_fld2608DOT_slot2, + OPERAND_dsp340050b49a6c_fld2609DOT_slot2, + OPERAND_dsp340050b49a6c_fld2610DOT_slot2, + OPERAND_dsp340050b49a6c_fld2611DOT_slot2, + OPERAND_dsp340050b49a6c_fld2612, + OPERAND_dsp340050b49a6c_fld2613DOT_slot2, + OPERAND_dsp340050b49a6c_fld2614, + OPERAND_dsp340050b49a6c_fld2615DOT_slot2, + OPERAND_dsp340050b49a6c_fld2616DOT_slot2, + OPERAND_dsp340050b49a6c_fld2617DOT_slot2, + OPERAND_dsp340050b49a6c_fld2618DOT_slot2, + OPERAND_dsp340050b49a6c_fld2619DOT_slot2, + OPERAND_dsp340050b49a6c_fld2620DOT_slot2, + OPERAND_dsp340050b49a6c_fld2621DOT_slot2, + OPERAND_dsp340050b49a6c_fld2622DOT_slot2, + OPERAND_dsp340050b49a6c_fld2623DOT_slot2, + OPERAND_dsp340050b49a6c_fld2624DOT_slot2, + OPERAND_dsp340050b49a6c_fld2625, + OPERAND_dsp340050b49a6c_fld2626DOT_slot2, + OPERAND_dsp340050b49a6c_fld2628DOT_slot2, + OPERAND_dsp340050b49a6c_fld2630DOT_slot2, + OPERAND_dsp340050b49a6c_fld2632DOT_slot2, + OPERAND_dsp340050b49a6c_fld2633DOT_slot2, + OPERAND_dsp340050b49a6c_fld2635DOT_slot2, + OPERAND_dsp340050b49a6c_fld2636DOT_slot2, + OPERAND_dsp340050b49a6c_fld2637DOT_slot2, + OPERAND_dsp340050b49a6c_fld2640DOT_slot2, + OPERAND_dsp340050b49a6c_fld2641DOT_slot2, + OPERAND_dsp340050b49a6c_fld2642DOT_slot2, + OPERAND_dsp340050b49a6c_fld2643DOT_slot2, + OPERAND_dsp340050b49a6c_fld2644DOT_slot2, + OPERAND_dsp340050b49a6c_fld2645DOT_slot2, + OPERAND_dsp340050b49a6c_fld2646DOT_slot2, + OPERAND_dsp340050b49a6c_fld2647DOT_slot2, + OPERAND_dsp340050b49a6c_fld2648DOT_slot2, + OPERAND_dsp340050b49a6c_fld2649DOT_slot2, + OPERAND_dsp340050b49a6c_fld2650DOT_slot2, + OPERAND_dsp340050b49a6c_fld2651DOT_slot2, + OPERAND_dsp340050b49a6c_fld2652DOT_slot2, + OPERAND_dsp340050b49a6c_fld2654DOT_slot2, + OPERAND_dsp340050b49a6c_fld2655DOT_slot2, + OPERAND_dsp340050b49a6c_fld2656DOT_slot2, + OPERAND_dsp340050b49a6c_fld2657DOT_slot2, + OPERAND_dsp340050b49a6c_fld2658DOT_slot2, + OPERAND_dsp340050b49a6c_fld3708DOT_slot2, + OPERAND_dsp340050b49a6c_fld3709DOT_slot2, + OPERAND_dsp340050b49a6c_fld3710DOT_slot2, + OPERAND_dsp340050b49a6c_fld3711DOT_slot2, + OPERAND_dsp340050b49a6c_fld3712, + OPERAND_dsp340050b49a6c_fld3713DOT_slot2, + OPERAND_dsp340050b49a6c_fld3714DOT_slot2, + OPERAND_dsp340050b49a6c_fld3715, + OPERAND_dsp340050b49a6c_fld3716DOT_slot2, + OPERAND_dsp340050b49a6c_fld3717DOT_slot2, + OPERAND_dsp340050b49a6c_fld3718, + OPERAND_dsp340050b49a6c_fld3719DOT_slot2, + OPERAND_dsp340050b49a6c_fld3721DOT_slot2, + OPERAND_dsp340050b49a6c_fld3722, + OPERAND_dsp340050b49a6c_fld3723DOT_slot2, + OPERAND_dsp340050b49a6c_fld3724DOT_slot2, + OPERAND_dsp340050b49a6c_fld3725DOT_slot2, + OPERAND_dsp340050b49a6c_fld3726DOT_slot2, + OPERAND_dsp340050b49a6c_fld3727DOT_slot2, + OPERAND_dsp340050b49a6c_fld3728DOT_slot2, + OPERAND_dsp340050b49a6c_fld3729DOT_slot2, + OPERAND_dsp340050b49a6c_fld3731DOT_slot2, + OPERAND_dsp340050b49a6c_fld3732DOT_slot2, + OPERAND_dsp340050b49a6c_fld3733DOT_slot2, + OPERAND_op0_s7, + OPERAND_dsp340050b49a6c_fld3734DOT_slot1, + OPERAND_op0_s8, + OPERAND_dsp340050b49a6c_fld2068, + OPERAND_dsp340050b49a6c_fld2666DOT_slot0, + OPERAND_dsp340050b49a6c_fld2667DOT_slot0, + OPERAND_dsp340050b49a6c_fld2668DOT_slot0, + OPERAND_dsp340050b49a6c_fld2669DOT_slot0, + OPERAND_dsp340050b49a6c_fld2671DOT_slot0, + OPERAND_dsp340050b49a6c_fld2672DOT_slot0, + OPERAND_dsp340050b49a6c_fld2673DOT_slot0, + OPERAND_dsp340050b49a6c_fld2674DOT_slot0, + OPERAND_dsp340050b49a6c_fld2675DOT_slot0, + OPERAND_dsp340050b49a6c_fld2676DOT_slot0, + OPERAND_dsp340050b49a6c_fld2677DOT_slot0, + OPERAND_dsp340050b49a6c_fld2678DOT_slot0, + OPERAND_dsp340050b49a6c_fld2679DOT_slot0, + OPERAND_dsp340050b49a6c_fld2680DOT_slot0, + OPERAND_dsp340050b49a6c_fld2681DOT_slot0, + OPERAND_dsp340050b49a6c_fld2682DOT_slot0, + OPERAND_dsp340050b49a6c_fld2683DOT_slot0, + OPERAND_dsp340050b49a6c_fld2684DOT_slot0, + OPERAND_dsp340050b49a6c_fld2685DOT_slot0, + OPERAND_dsp340050b49a6c_fld2686DOT_slot0, + OPERAND_dsp340050b49a6c_fld2688DOT_slot0, + OPERAND_dsp340050b49a6c_fld2689DOT_slot0, + OPERAND_dsp340050b49a6c_fld2690DOT_slot0, + OPERAND_dsp340050b49a6c_fld2692DOT_slot0, + OPERAND_dsp340050b49a6c_fld2693DOT_slot0, + OPERAND_dsp340050b49a6c_fld2695DOT_slot0, + OPERAND_dsp340050b49a6c_fld2697DOT_slot0, + OPERAND_dsp340050b49a6c_fld2699DOT_slot0, + OPERAND_dsp340050b49a6c_fld2700DOT_slot0, + OPERAND_dsp340050b49a6c_fld2701DOT_slot0, + OPERAND_dsp340050b49a6c_fld2702DOT_slot0, + OPERAND_dsp340050b49a6c_fld2703DOT_slot0, + OPERAND_dsp340050b49a6c_fld2704DOT_slot0, + OPERAND_dsp340050b49a6c_fld2705DOT_slot0, + OPERAND_dsp340050b49a6c_fld3735DOT_slot0, + OPERAND_dsp340050b49a6c_fld3736, + OPERAND_dsp340050b49a6c_fld3737DOT_slot0, + OPERAND_dsp340050b49a6c_fld3738DOT_slot0, + OPERAND_dsp340050b49a6c_fld3739DOT_slot0, + OPERAND_dsp340050b49a6c_fld3740DOT_slot0, + OPERAND_dsp340050b49a6c_fld3741DOT_slot0, + OPERAND_dsp340050b49a6c_fld3742DOT_slot0, + OPERAND_op0_s9, + OPERAND_dsp340050b49a6c_fld2706PQ_slot2, + OPERAND_dsp340050b49a6c_fld2707PQ_slot2, + OPERAND_dsp340050b49a6c_fld2708PQ_slot2, + OPERAND_dsp340050b49a6c_fld2709PQ_slot2, + OPERAND_dsp340050b49a6c_fld2710PQ_slot2, + OPERAND_dsp340050b49a6c_fld2711PQ_slot2, + OPERAND_dsp340050b49a6c_fld2713PQ_slot2, + OPERAND_dsp340050b49a6c_fld2714PQ_slot2, + OPERAND_dsp340050b49a6c_fld2715PQ_slot2, + OPERAND_dsp340050b49a6c_fld2717PQ_slot2, + OPERAND_dsp340050b49a6c_fld2718PQ_slot2, + OPERAND_dsp340050b49a6c_fld2719PQ_slot2, + OPERAND_dsp340050b49a6c_fld2721PQ_slot2, + OPERAND_dsp340050b49a6c_fld2722PQ_slot2, + OPERAND_dsp340050b49a6c_fld2723PQ_slot2, + OPERAND_dsp340050b49a6c_fld2724PQ_slot2, + OPERAND_dsp340050b49a6c_fld2725PQ_slot2, + OPERAND_dsp340050b49a6c_fld2726PQ_slot2, + OPERAND_dsp340050b49a6c_fld2727PQ_slot2, + OPERAND_dsp340050b49a6c_fld2728PQ_slot2, + OPERAND_dsp340050b49a6c_fld2729PQ_slot2, + OPERAND_dsp340050b49a6c_fld2730PQ_slot2, + OPERAND_dsp340050b49a6c_fld2731PQ_slot2, + OPERAND_dsp340050b49a6c_fld2732PQ_slot2, + OPERAND_dsp340050b49a6c_fld2733PQ_slot2, + OPERAND_dsp340050b49a6c_fld2734PQ_slot2, + OPERAND_dsp340050b49a6c_fld2735PQ_slot2, + OPERAND_dsp340050b49a6c_fld2736PQ_slot2, + OPERAND_dsp340050b49a6c_fld2737, + OPERAND_dsp340050b49a6c_fld2738PQ_slot2, + OPERAND_dsp340050b49a6c_fld2739PQ_slot2, + OPERAND_dsp340050b49a6c_fld2741PQ_slot2, + OPERAND_dsp340050b49a6c_fld2742PQ_slot2, + OPERAND_dsp340050b49a6c_fld2743PQ_slot2, + OPERAND_dsp340050b49a6c_fld2746PQ_slot2, + OPERAND_dsp340050b49a6c_fld2747PQ_slot2, + OPERAND_dsp340050b49a6c_fld2748PQ_slot2, + OPERAND_dsp340050b49a6c_fld2750PQ_slot2, + OPERAND_dsp340050b49a6c_fld2751PQ_slot2, + OPERAND_dsp340050b49a6c_fld2752PQ_slot2, + OPERAND_dsp340050b49a6c_fld2753PQ_slot2, + OPERAND_dsp340050b49a6c_fld2754PQ_slot2, + OPERAND_dsp340050b49a6c_fld2755PQ_slot2, + OPERAND_dsp340050b49a6c_fld2756PQ_slot2, + OPERAND_dsp340050b49a6c_fld2757PQ_slot2, + OPERAND_dsp340050b49a6c_fld2758PQ_slot2, + OPERAND_dsp340050b49a6c_fld2759PQ_slot2, + OPERAND_dsp340050b49a6c_fld2760PQ_slot2, + OPERAND_dsp340050b49a6c_fld2761PQ_slot2, + OPERAND_dsp340050b49a6c_fld2762PQ_slot2, + OPERAND_dsp340050b49a6c_fld2763PQ_slot2, + OPERAND_dsp340050b49a6c_fld2764PQ_slot2, + OPERAND_dsp340050b49a6c_fld2765PQ_slot2, + OPERAND_dsp340050b49a6c_fld2766PQ_slot2, + OPERAND_dsp340050b49a6c_fld2767PQ_slot2, + OPERAND_dsp340050b49a6c_fld2768PQ_slot2, + OPERAND_dsp340050b49a6c_fld2769PQ_slot2, + OPERAND_dsp340050b49a6c_fld2770PQ_slot2, + OPERAND_dsp340050b49a6c_fld2771PQ_slot2, + OPERAND_dsp340050b49a6c_fld2772PQ_slot2, + OPERAND_dsp340050b49a6c_fld2773PQ_slot2, + OPERAND_dsp340050b49a6c_fld2774PQ_slot2, + OPERAND_dsp340050b49a6c_fld2775PQ_slot2, + OPERAND_dsp340050b49a6c_fld2776PQ_slot2, + OPERAND_dsp340050b49a6c_fld2777PQ_slot2, + OPERAND_dsp340050b49a6c_fld2778PQ_slot2, + OPERAND_dsp340050b49a6c_fld2779PQ_slot2, + OPERAND_dsp340050b49a6c_fld2780PQ_slot2, + OPERAND_dsp340050b49a6c_fld2781PQ_slot2, + OPERAND_dsp340050b49a6c_fld2782PQ_slot2, + OPERAND_dsp340050b49a6c_fld2783PQ_slot2, + OPERAND_dsp340050b49a6c_fld2784PQ_slot2, + OPERAND_dsp340050b49a6c_fld2785PQ_slot2, + OPERAND_dsp340050b49a6c_fld2786PQ_slot2, + OPERAND_dsp340050b49a6c_fld2787PQ_slot2, + OPERAND_dsp340050b49a6c_fld2788PQ_slot2, + OPERAND_dsp340050b49a6c_fld2789PQ_slot2, + OPERAND_dsp340050b49a6c_fld2790PQ_slot2, + OPERAND_dsp340050b49a6c_fld2791PQ_slot2, + OPERAND_dsp340050b49a6c_fld2792PQ_slot2, + OPERAND_dsp340050b49a6c_fld2793PQ_slot2, + OPERAND_dsp340050b49a6c_fld2795PQ_slot2, + OPERAND_dsp340050b49a6c_fld2796PQ_slot2, + OPERAND_dsp340050b49a6c_fld2798PQ_slot2, + OPERAND_dsp340050b49a6c_fld2801PQ_slot2, + OPERAND_dsp340050b49a6c_fld2803PQ_slot2, + OPERAND_dsp340050b49a6c_fld2805PQ_slot2, + OPERAND_dsp340050b49a6c_fld2806PQ_slot2, + OPERAND_dsp340050b49a6c_fld2807PQ_slot2, + OPERAND_dsp340050b49a6c_fld2808PQ_slot2, + OPERAND_dsp340050b49a6c_fld2809PQ_slot2, + OPERAND_dsp340050b49a6c_fld2810PQ_slot2, + OPERAND_dsp340050b49a6c_fld2811PQ_slot2, + OPERAND_dsp340050b49a6c_fld2812PQ_slot2, + OPERAND_dsp340050b49a6c_fld2814PQ_slot2, + OPERAND_dsp340050b49a6c_fld2816PQ_slot2, + OPERAND_dsp340050b49a6c_fld2817, + OPERAND_dsp340050b49a6c_fld2818PQ_slot2, + OPERAND_dsp340050b49a6c_fld2819, + OPERAND_dsp340050b49a6c_fld2820PQ_slot2, + OPERAND_dsp340050b49a6c_fld2821PQ_slot2, + OPERAND_dsp340050b49a6c_fld2823PQ_slot2, + OPERAND_dsp340050b49a6c_fld3744PQ_slot2, + OPERAND_dsp340050b49a6c_fld3745PQ_slot2, + OPERAND_dsp340050b49a6c_fld3746PQ_slot2, + OPERAND_dsp340050b49a6c_fld3747PQ_slot2, + OPERAND_dsp340050b49a6c_fld3748, + OPERAND_dsp340050b49a6c_fld3749PQ_slot2, + OPERAND_dsp340050b49a6c_fld3750PQ_slot2, + OPERAND_dsp340050b49a6c_fld3751PQ_slot2, + OPERAND_dsp340050b49a6c_fld3752PQ_slot2, + OPERAND_dsp340050b49a6c_fld3753PQ_slot2, + OPERAND_dsp340050b49a6c_fld3754PQ_slot2, + OPERAND_dsp340050b49a6c_fld3756PQ_slot2, + OPERAND_dsp340050b49a6c_fld3757PQ_slot2, + OPERAND_dsp340050b49a6c_fld3758PQ_slot2, + OPERAND_dsp340050b49a6c_fld3759PQ_slot2, + OPERAND_dsp340050b49a6c_fld3760PQ_slot2, + OPERAND_op0_s10, + OPERAND_dsp340050b49a6c_fld2825PQ_slot1, + OPERAND_dsp340050b49a6c_fld2826PQ_slot1, + OPERAND_dsp340050b49a6c_fld3761PQ_slot1, + OPERAND_op0_s11, + OPERAND_dsp340050b49a6c_fld2059, + OPERAND_dsp340050b49a6c_fld2069, + OPERAND_dsp340050b49a6c_fld2827PQ_slot0, + OPERAND_dsp340050b49a6c_fld2829PQ_slot0, + OPERAND_dsp340050b49a6c_fld2830PQ_slot0, + OPERAND_dsp340050b49a6c_fld2831PQ_slot0, + OPERAND_dsp340050b49a6c_fld2832PQ_slot0, + OPERAND_dsp340050b49a6c_fld2833PQ_slot0, + OPERAND_dsp340050b49a6c_fld2835PQ_slot0, + OPERAND_dsp340050b49a6c_fld2836PQ_slot0, + OPERAND_dsp340050b49a6c_fld2837PQ_slot0, + OPERAND_dsp340050b49a6c_fld2838PQ_slot0, + OPERAND_dsp340050b49a6c_fld2839PQ_slot0, + OPERAND_dsp340050b49a6c_fld2840PQ_slot0, + OPERAND_dsp340050b49a6c_fld2842PQ_slot0, + OPERAND_dsp340050b49a6c_fld2843PQ_slot0, + OPERAND_dsp340050b49a6c_fld2844PQ_slot0, + OPERAND_dsp340050b49a6c_fld2845PQ_slot0, + OPERAND_dsp340050b49a6c_fld2846PQ_slot0, + OPERAND_dsp340050b49a6c_fld2847PQ_slot0, + OPERAND_dsp340050b49a6c_fld2849PQ_slot0, + OPERAND_dsp340050b49a6c_fld2850PQ_slot0, + OPERAND_dsp340050b49a6c_fld2851PQ_slot0, + OPERAND_dsp340050b49a6c_fld2852PQ_slot0, + OPERAND_dsp340050b49a6c_fld2853PQ_slot0, + OPERAND_dsp340050b49a6c_fld2854PQ_slot0, + OPERAND_dsp340050b49a6c_fld2855PQ_slot0, + OPERAND_dsp340050b49a6c_fld2856PQ_slot0, + OPERAND_dsp340050b49a6c_fld2857PQ_slot0, + OPERAND_dsp340050b49a6c_fld2858PQ_slot0, + OPERAND_dsp340050b49a6c_fld2859PQ_slot0, + OPERAND_dsp340050b49a6c_fld2860PQ_slot0, + OPERAND_dsp340050b49a6c_fld2861PQ_slot0, + OPERAND_dsp340050b49a6c_fld2863PQ_slot0, + OPERAND_dsp340050b49a6c_fld2864PQ_slot0, + OPERAND_dsp340050b49a6c_fld2865, + OPERAND_dsp340050b49a6c_fld2867PQ_slot0, + OPERAND_dsp340050b49a6c_fld2869PQ_slot0, + OPERAND_dsp340050b49a6c_fld2871PQ_slot0, + OPERAND_dsp340050b49a6c_fld2872PQ_slot0, + OPERAND_dsp340050b49a6c_fld2873PQ_slot0, + OPERAND_dsp340050b49a6c_fld2874PQ_slot0, + OPERAND_dsp340050b49a6c_fld2875PQ_slot0, + OPERAND_dsp340050b49a6c_fld2876PQ_slot0, + OPERAND_dsp340050b49a6c_fld2877PQ_slot0, + OPERAND_dsp340050b49a6c_fld2878PQ_slot0, + OPERAND_dsp340050b49a6c_fld2879PQ_slot0, + OPERAND_dsp340050b49a6c_fld2880PQ_slot0, + OPERAND_dsp340050b49a6c_fld2881PQ_slot0, + OPERAND_dsp340050b49a6c_fld2882, + OPERAND_dsp340050b49a6c_fld2883PQ_slot0, + OPERAND_dsp340050b49a6c_fld2884PQ_slot0, + OPERAND_dsp340050b49a6c_fld2885PQ_slot0, + OPERAND_dsp340050b49a6c_fld2886PQ_slot0, + OPERAND_dsp340050b49a6c_fld2887PQ_slot0, + OPERAND_dsp340050b49a6c_fld2888PQ_slot0, + OPERAND_dsp340050b49a6c_fld2890PQ_slot0, + OPERAND_dsp340050b49a6c_fld2891PQ_slot0, + OPERAND_dsp340050b49a6c_fld2892PQ_slot0, + OPERAND_dsp340050b49a6c_fld2893PQ_slot0, + OPERAND_dsp340050b49a6c_fld2894PQ_slot0, + OPERAND_dsp340050b49a6c_fld2895PQ_slot0, + OPERAND_dsp340050b49a6c_fld2897PQ_slot0, + OPERAND_dsp340050b49a6c_fld2899PQ_slot0, + OPERAND_dsp340050b49a6c_fld2900PQ_slot0, + OPERAND_dsp340050b49a6c_fld2901PQ_slot0, + OPERAND_dsp340050b49a6c_fld2902PQ_slot0, + OPERAND_dsp340050b49a6c_fld2903PQ_slot0, + OPERAND_dsp340050b49a6c_fld2904PQ_slot0, + OPERAND_dsp340050b49a6c_fld2905PQ_slot0, + OPERAND_dsp340050b49a6c_fld2906PQ_slot0, + OPERAND_dsp340050b49a6c_fld2907PQ_slot0, + OPERAND_dsp340050b49a6c_fld2908PQ_slot0, + OPERAND_dsp340050b49a6c_fld2909PQ_slot0, + OPERAND_dsp340050b49a6c_fld2910PQ_slot0, + OPERAND_dsp340050b49a6c_fld2911PQ_slot0, + OPERAND_dsp340050b49a6c_fld2912PQ_slot0, + OPERAND_dsp340050b49a6c_fld2913PQ_slot0, + OPERAND_dsp340050b49a6c_fld2914PQ_slot0, + OPERAND_dsp340050b49a6c_fld2915PQ_slot0, + OPERAND_dsp340050b49a6c_fld2916PQ_slot0, + OPERAND_dsp340050b49a6c_fld2917PQ_slot0, + OPERAND_dsp340050b49a6c_fld2918PQ_slot0, + OPERAND_dsp340050b49a6c_fld2919PQ_slot0, + OPERAND_dsp340050b49a6c_fld2920PQ_slot0, + OPERAND_dsp340050b49a6c_fld2921PQ_slot0, + OPERAND_dsp340050b49a6c_fld2922PQ_slot0, + OPERAND_dsp340050b49a6c_fld2923PQ_slot0, + OPERAND_dsp340050b49a6c_fld2924PQ_slot0, + OPERAND_dsp340050b49a6c_fld2925PQ_slot0, + OPERAND_dsp340050b49a6c_fld2926PQ_slot0, + OPERAND_dsp340050b49a6c_fld2927PQ_slot0, + OPERAND_dsp340050b49a6c_fld2928PQ_slot0, + OPERAND_dsp340050b49a6c_fld2929PQ_slot0, + OPERAND_dsp340050b49a6c_fld2930PQ_slot0, + OPERAND_dsp340050b49a6c_fld2932PQ_slot0, + OPERAND_dsp340050b49a6c_fld2934PQ_slot0, + OPERAND_dsp340050b49a6c_fld2935PQ_slot0, + OPERAND_dsp340050b49a6c_fld2936PQ_slot0, + OPERAND_dsp340050b49a6c_fld2937PQ_slot0, + OPERAND_dsp340050b49a6c_fld2939PQ_slot0, + OPERAND_dsp340050b49a6c_fld2940, + OPERAND_dsp340050b49a6c_fld2941PQ_slot0, + OPERAND_dsp340050b49a6c_fld2942PQ_slot0, + OPERAND_dsp340050b49a6c_fld2943PQ_slot0, + OPERAND_dsp340050b49a6c_fld2945PQ_slot0, + OPERAND_dsp340050b49a6c_fld2946PQ_slot0, + OPERAND_dsp340050b49a6c_fld2947PQ_slot0, + OPERAND_dsp340050b49a6c_fld2948PQ_slot0, + OPERAND_dsp340050b49a6c_fld2949PQ_slot0, + OPERAND_dsp340050b49a6c_fld2950PQ_slot0, + OPERAND_dsp340050b49a6c_fld3763PQ_slot0, + OPERAND_dsp340050b49a6c_fld3764PQ_slot0, + OPERAND_dsp340050b49a6c_fld3765PQ_slot0, + OPERAND_dsp340050b49a6c_fld3766PQ_slot0, + OPERAND_dsp340050b49a6c_fld3767PQ_slot0, + OPERAND_dsp340050b49a6c_fld3768PQ_slot0, + OPERAND_dsp340050b49a6c_fld3769PQ_slot0, + OPERAND_dsp340050b49a6c_fld3770PQ_slot0, + OPERAND_dsp340050b49a6c_fld3771PQ_slot0, + OPERAND_dsp340050b49a6c_fld3772, + OPERAND_dsp340050b49a6c_fld3773PQ_slot0, + OPERAND_dsp340050b49a6c_fld3775PQ_slot0, + OPERAND_dsp340050b49a6c_fld3776PQ_slot0, + OPERAND_dsp340050b49a6c_fld3777PQ_slot0, + OPERAND_dsp340050b49a6c_fld3778PQ_slot0, + OPERAND_dsp340050b49a6c_fld3779PQ_slot0, + OPERAND_dsp340050b49a6c_fld3780PQ_slot0, + OPERAND_op0_s12, + OPERAND_dsp340050b49a6c_fld2953ACC2_slot2, + OPERAND_dsp340050b49a6c_fld2954ACC2_slot2, + OPERAND_dsp340050b49a6c_fld2955ACC2_slot2, + OPERAND_dsp340050b49a6c_fld2956ACC2_slot2, + OPERAND_dsp340050b49a6c_fld2957ACC2_slot2, + OPERAND_dsp340050b49a6c_fld2958ACC2_slot2, + OPERAND_dsp340050b49a6c_fld2959ACC2_slot2, + OPERAND_dsp340050b49a6c_fld2960ACC2_slot2, + OPERAND_dsp340050b49a6c_fld2963ACC2_slot2, + OPERAND_dsp340050b49a6c_fld2964ACC2_slot2, + OPERAND_dsp340050b49a6c_fld2966ACC2_slot2, + OPERAND_dsp340050b49a6c_fld2967ACC2_slot2, + OPERAND_dsp340050b49a6c_fld3782ACC2_slot2, + OPERAND_dsp340050b49a6c_fld3783ACC2_slot2, + OPERAND_dsp340050b49a6c_fld3784ACC2_slot2, + OPERAND_dsp340050b49a6c_fld3785ACC2_slot2, + OPERAND_dsp340050b49a6c_fld3786ACC2_slot2, + OPERAND_dsp340050b49a6c_fld3788ACC2_slot2, + OPERAND_op0_s13, + OPERAND_dsp340050b49a6c_fld2028, + OPERAND_dsp340050b49a6c_fld2075, + OPERAND_dsp340050b49a6c_fld2968ACC2_slot1, + OPERAND_dsp340050b49a6c_fld2969ACC2_slot1, + OPERAND_dsp340050b49a6c_fld3790ACC2_slot1, + OPERAND_dsp340050b49a6c_fld3793ACC2_slot1, + OPERAND_op0_s14, + OPERAND_dsp340050b49a6c_fld2973ACC2_slot0, + OPERAND_dsp340050b49a6c_fld2974ACC2_slot0, + OPERAND_dsp340050b49a6c_fld2975ACC2_slot0, + OPERAND_dsp340050b49a6c_fld2976ACC2_slot0, + OPERAND_dsp340050b49a6c_fld2977ACC2_slot0, + OPERAND_dsp340050b49a6c_fld2980ACC2_slot0, + OPERAND_dsp340050b49a6c_fld2981ACC2_slot0, + OPERAND_dsp340050b49a6c_fld2982ACC2_slot0, + OPERAND_dsp340050b49a6c_fld2984ACC2_slot0, + OPERAND_dsp340050b49a6c_fld2985ACC2_slot0, + OPERAND_dsp340050b49a6c_fld2987ACC2_slot0, + OPERAND_dsp340050b49a6c_fld2989ACC2_slot0, + OPERAND_dsp340050b49a6c_fld2990ACC2_slot0, + OPERAND_dsp340050b49a6c_fld3795ACC2_slot0, + OPERAND_dsp340050b49a6c_fld3796ACC2_slot0, + OPERAND_dsp340050b49a6c_fld3797, + OPERAND_dsp340050b49a6c_fld3798ACC2_slot0, + OPERAND_dsp340050b49a6c_fld3799ACC2_slot0, + OPERAND_dsp340050b49a6c_fld3800ACC2_slot0, + OPERAND_dsp340050b49a6c_fld3801ACC2_slot0, + OPERAND_dsp340050b49a6c_fld3802ACC2_slot0, + OPERAND_dsp340050b49a6c_fld3803ACC2_slot0, + OPERAND_op0_s15, + OPERAND_dsp340050b49a6c_fld2991SMOD_slot2, + OPERAND_dsp340050b49a6c_fld2992SMOD_slot2, + OPERAND_dsp340050b49a6c_fld2993SMOD_slot2, + OPERAND_dsp340050b49a6c_fld2994SMOD_slot2, + OPERAND_dsp340050b49a6c_fld2995SMOD_slot2, + OPERAND_dsp340050b49a6c_fld2996SMOD_slot2, + OPERAND_dsp340050b49a6c_fld2997SMOD_slot2, + OPERAND_dsp340050b49a6c_fld2998SMOD_slot2, + OPERAND_dsp340050b49a6c_fld2999SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3000SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3001SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3002SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3003SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3004SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3005SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3006SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3007SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3008SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3009SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3010SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3011SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3012SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3013SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3014SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3015SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3016SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3017SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3018SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3019SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3020SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3021SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3022SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3023SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3024SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3025SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3026SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3027SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3028SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3030SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3031SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3032SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3033SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3034SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3035SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3036SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3038SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3039SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3040SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3043SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3044SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3046SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3047SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3048, + OPERAND_dsp340050b49a6c_fld3049SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3050SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3051SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3052SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3053SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3054SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3055SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3056SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3058SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3059SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3061SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3062, + OPERAND_dsp340050b49a6c_fld3063SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3065SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3066SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3067SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3068SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3069SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3070, + OPERAND_dsp340050b49a6c_fld3071SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3072SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3073SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3074SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3075SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3076SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3077SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3078SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3079SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3080SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3081SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3082SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3084SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3085SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3087SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3088SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3090SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3091SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3092SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3093SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3096SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3097SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3098SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3099SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3100SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3101SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3102SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3104SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3105SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3106SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3107SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3108SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3109SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3110SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3111SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3113SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3114SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3115SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3116SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3805SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3806SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3807SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3808, + OPERAND_dsp340050b49a6c_fld3809SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3810SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3812SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3813SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3814SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3816SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3817, + OPERAND_dsp340050b49a6c_fld3818SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3819SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3821SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3822SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3823SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3824SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3825SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3826SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3827SMOD_slot2, + OPERAND_dsp340050b49a6c_fld3828SMOD_slot2, + OPERAND_op0_s16, + OPERAND_dsp340050b49a6c_fld2033, + OPERAND_dsp340050b49a6c_fld2080, + OPERAND_dsp340050b49a6c_fld3117SMOD_slot1, + OPERAND_dsp340050b49a6c_fld3118SMOD_slot1, + OPERAND_dsp340050b49a6c_fld3829SMOD_slot1, + OPERAND_op0_s17, + OPERAND_dsp340050b49a6c_fld3119SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3120SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3121SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3122SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3123SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3125SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3126SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3127SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3128SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3129SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3130SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3131SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3132SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3133SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3134SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3135SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3136SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3137SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3138SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3139SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3140SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3141SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3142SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3143SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3144SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3145SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3146SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3148SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3149SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3150, + OPERAND_dsp340050b49a6c_fld3152SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3153SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3155SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3156SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3157SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3158SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3159SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3160SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3161SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3164SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3165SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3166SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3168SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3170SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3171SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3172SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3173SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3174SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3175SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3176SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3177SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3178SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3179SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3180SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3181SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3182SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3184SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3186SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3188SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3832SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3833SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3834, + OPERAND_dsp340050b49a6c_fld3836SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3837SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3838SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3841SMOD_slot0, + OPERAND_dsp340050b49a6c_fld3842SMOD_slot0, + OPERAND_op0_s18, + OPERAND_dsp340050b49a6c_fld2074, + OPERAND_dsp340050b49a6c_fld3191LLR_slot2, + OPERAND_dsp340050b49a6c_fld3192LLR_slot2, + OPERAND_dsp340050b49a6c_fld3193LLR_slot2, + OPERAND_dsp340050b49a6c_fld3194LLR_slot2, + OPERAND_dsp340050b49a6c_fld3195LLR_slot2, + OPERAND_dsp340050b49a6c_fld3196LLR_slot2, + OPERAND_dsp340050b49a6c_fld3197LLR_slot2, + OPERAND_dsp340050b49a6c_fld3198LLR_slot2, + OPERAND_dsp340050b49a6c_fld3199LLR_slot2, + OPERAND_dsp340050b49a6c_fld3200LLR_slot2, + OPERAND_dsp340050b49a6c_fld3201LLR_slot2, + OPERAND_dsp340050b49a6c_fld3202LLR_slot2, + OPERAND_dsp340050b49a6c_fld3203LLR_slot2, + OPERAND_dsp340050b49a6c_fld3204LLR_slot2, + OPERAND_dsp340050b49a6c_fld3205, + OPERAND_dsp340050b49a6c_fld3206, + OPERAND_dsp340050b49a6c_fld3207LLR_slot2, + OPERAND_dsp340050b49a6c_fld3208LLR_slot2, + OPERAND_dsp340050b49a6c_fld3210LLR_slot2, + OPERAND_dsp340050b49a6c_fld3212, + OPERAND_dsp340050b49a6c_fld3213LLR_slot2, + OPERAND_dsp340050b49a6c_fld3214, + OPERAND_dsp340050b49a6c_fld3215LLR_slot2, + OPERAND_dsp340050b49a6c_fld3216LLR_slot2, + OPERAND_dsp340050b49a6c_fld3217, + OPERAND_dsp340050b49a6c_fld3218LLR_slot2, + OPERAND_dsp340050b49a6c_fld3220LLR_slot2, + OPERAND_dsp340050b49a6c_fld3221LLR_slot2, + OPERAND_dsp340050b49a6c_fld3222LLR_slot2, + OPERAND_dsp340050b49a6c_fld3224LLR_slot2, + OPERAND_dsp340050b49a6c_fld3225, + OPERAND_dsp340050b49a6c_fld3226LLR_slot2, + OPERAND_dsp340050b49a6c_fld3228LLR_slot2, + OPERAND_dsp340050b49a6c_fld3230, + OPERAND_dsp340050b49a6c_fld3231LLR_slot2, + OPERAND_dsp340050b49a6c_fld3232LLR_slot2, + OPERAND_dsp340050b49a6c_fld3233, + OPERAND_dsp340050b49a6c_fld3234LLR_slot2, + OPERAND_dsp340050b49a6c_fld3235LLR_slot2, + OPERAND_dsp340050b49a6c_fld3236, + OPERAND_dsp340050b49a6c_fld3237LLR_slot2, + OPERAND_dsp340050b49a6c_fld3238LLR_slot2, + OPERAND_dsp340050b49a6c_fld3240LLR_slot2, + OPERAND_dsp340050b49a6c_fld3241LLR_slot2, + OPERAND_dsp340050b49a6c_fld3242LLR_slot2, + OPERAND_dsp340050b49a6c_fld3243LLR_slot2, + OPERAND_dsp340050b49a6c_fld3244LLR_slot2, + OPERAND_dsp340050b49a6c_fld3245LLR_slot2, + OPERAND_dsp340050b49a6c_fld3246, + OPERAND_dsp340050b49a6c_fld3247LLR_slot2, + OPERAND_dsp340050b49a6c_fld3843LLR_slot2, + OPERAND_dsp340050b49a6c_fld3844, + OPERAND_dsp340050b49a6c_fld3845LLR_slot2, + OPERAND_dsp340050b49a6c_fld3847LLR_slot2, + OPERAND_dsp340050b49a6c_fld3848LLR_slot2, + OPERAND_dsp340050b49a6c_fld3849LLR_slot2, + OPERAND_dsp340050b49a6c_fld3850LLR_slot2, + OPERAND_dsp340050b49a6c_fld3851LLR_slot2, + OPERAND_dsp340050b49a6c_fld3853LLR_slot2, + OPERAND_dsp340050b49a6c_fld3855LLR_slot2, + OPERAND_dsp340050b49a6c_fld3856LLR_slot2, + OPERAND_dsp340050b49a6c_fld3857LLR_slot2, + OPERAND_dsp340050b49a6c_fld3859LLR_slot2, + OPERAND_dsp340050b49a6c_fld3860LLR_slot2, + OPERAND_dsp340050b49a6c_fld3861LLR_slot2, + OPERAND_dsp340050b49a6c_fld3862, + OPERAND_dsp340050b49a6c_fld3863LLR_slot2, + OPERAND_dsp340050b49a6c_fld3864LLR_slot2, + OPERAND_dsp340050b49a6c_fld3865LLR_slot2, + OPERAND_dsp340050b49a6c_fld3866LLR_slot2, + OPERAND_dsp340050b49a6c_fld3867LLR_slot2, + OPERAND_dsp340050b49a6c_fld3868, + OPERAND_op0_s19, + OPERAND_dsp340050b49a6c_fld2034, + OPERAND_dsp340050b49a6c_fld3248LLR_slot1, + OPERAND_dsp340050b49a6c_fld3250LLR_slot1, + OPERAND_dsp340050b49a6c_fld3251LLR_slot1, + OPERAND_dsp340050b49a6c_fld3252LLR_slot1, + OPERAND_dsp340050b49a6c_fld3253LLR_slot1, + OPERAND_dsp340050b49a6c_fld3254LLR_slot1, + OPERAND_dsp340050b49a6c_fld3869LLR_slot1, + OPERAND_dsp340050b49a6c_fld3870, + OPERAND_dsp340050b49a6c_fld3872LLR_slot1, + OPERAND_dsp340050b49a6c_fld3875LLR_slot1, + OPERAND_dsp340050b49a6c_fld3876LLR_slot1, + OPERAND_dsp340050b49a6c_fld3878LLR_slot1, + OPERAND_op0_s20, + OPERAND_dsp340050b49a6c_fld2071, + OPERAND_dsp340050b49a6c_fld3258LLR_slot0, + OPERAND_dsp340050b49a6c_fld3259LLR_slot0, + OPERAND_dsp340050b49a6c_fld3260LLR_slot0, + OPERAND_dsp340050b49a6c_fld3261LLR_slot0, + OPERAND_dsp340050b49a6c_fld3263LLR_slot0, + OPERAND_dsp340050b49a6c_fld3264LLR_slot0, + OPERAND_dsp340050b49a6c_fld3265LLR_slot0, + OPERAND_dsp340050b49a6c_fld3266LLR_slot0, + OPERAND_dsp340050b49a6c_fld3267LLR_slot0, + OPERAND_dsp340050b49a6c_fld3268LLR_slot0, + OPERAND_dsp340050b49a6c_fld3269LLR_slot0, + OPERAND_dsp340050b49a6c_fld3270LLR_slot0, + OPERAND_dsp340050b49a6c_fld3272LLR_slot0, + OPERAND_dsp340050b49a6c_fld3274LLR_slot0, + OPERAND_dsp340050b49a6c_fld3275LLR_slot0, + OPERAND_dsp340050b49a6c_fld3276LLR_slot0, + OPERAND_dsp340050b49a6c_fld3277LLR_slot0, + OPERAND_dsp340050b49a6c_fld3278LLR_slot0, + OPERAND_dsp340050b49a6c_fld3279LLR_slot0, + OPERAND_dsp340050b49a6c_fld3280LLR_slot0, + OPERAND_dsp340050b49a6c_fld3281LLR_slot0, + OPERAND_dsp340050b49a6c_fld3282LLR_slot0, + OPERAND_dsp340050b49a6c_fld3283LLR_slot0, + OPERAND_dsp340050b49a6c_fld3284LLR_slot0, + OPERAND_dsp340050b49a6c_fld3286LLR_slot0, + OPERAND_dsp340050b49a6c_fld3288LLR_slot0, + OPERAND_dsp340050b49a6c_fld3289LLR_slot0, + OPERAND_dsp340050b49a6c_fld3291LLR_slot0, + OPERAND_dsp340050b49a6c_fld3292LLR_slot0, + OPERAND_dsp340050b49a6c_fld3293LLR_slot0, + OPERAND_dsp340050b49a6c_fld3294LLR_slot0, + OPERAND_dsp340050b49a6c_fld3295LLR_slot0, + OPERAND_dsp340050b49a6c_fld3296LLR_slot0, + OPERAND_dsp340050b49a6c_fld3297LLR_slot0, + OPERAND_dsp340050b49a6c_fld3298LLR_slot0, + OPERAND_dsp340050b49a6c_fld3299LLR_slot0, + OPERAND_dsp340050b49a6c_fld3300LLR_slot0, + OPERAND_dsp340050b49a6c_fld3302LLR_slot0, + OPERAND_dsp340050b49a6c_fld3303LLR_slot0, + OPERAND_dsp340050b49a6c_fld3304LLR_slot0, + OPERAND_dsp340050b49a6c_fld3305LLR_slot0, + OPERAND_dsp340050b49a6c_fld3306LLR_slot0, + OPERAND_dsp340050b49a6c_fld3308LLR_slot0, + OPERAND_dsp340050b49a6c_fld3310LLR_slot0, + OPERAND_dsp340050b49a6c_fld3311LLR_slot0, + OPERAND_dsp340050b49a6c_fld3312LLR_slot0, + OPERAND_dsp340050b49a6c_fld3879LLR_slot0, + OPERAND_dsp340050b49a6c_fld3881LLR_slot0, + OPERAND_dsp340050b49a6c_fld3883LLR_slot0, + OPERAND_dsp340050b49a6c_fld3885LLR_slot0, + OPERAND_dsp340050b49a6c_fld3887LLR_slot0, + OPERAND_dsp340050b49a6c_fld3888LLR_slot0, + OPERAND_dsp340050b49a6c_fld3890LLR_slot0, + OPERAND_dsp340050b49a6c_fld3892LLR_slot0, + OPERAND_dsp340050b49a6c_fld3893LLR_slot0, + OPERAND_op0_s21, + OPERAND_dsp340050b49a6c_fld3313DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3314, + OPERAND_dsp340050b49a6c_fld3315DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3316DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3317DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3318, + OPERAND_dsp340050b49a6c_fld3319DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3320DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3321DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3322DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3323DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3324DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3325DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3326DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3327DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3328DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3329DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3330DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3331DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3332DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3333DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3334DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3335DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3336DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3337DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3339DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3340DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3341DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3342DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3345DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3347DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3348DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3349DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3350DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3353DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3354DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3356DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3358DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3360DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3361DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3362DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3363DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3364, + OPERAND_dsp340050b49a6c_fld3365DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3366DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3367DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3368DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3369DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3370DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3371DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3372DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3373DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3374DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3375DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3376DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3377DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3378DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3379DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3380DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3381DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3382DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3384DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3385DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3386DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3387DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3388DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3390DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3392DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3394DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3396DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3397DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3399DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3401DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3403DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3404DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3406DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3407, + OPERAND_dsp340050b49a6c_fld3408DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3410, + OPERAND_dsp340050b49a6c_fld3411DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3412DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3413DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3414DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3415DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3416DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3417DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3418DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3419DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3420DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3421DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3422DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3423DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3424DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3425DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3426DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3427DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3428DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3429DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3430DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3431DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3432DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3433DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3434DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3435DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3436DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3437DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3438DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3439DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3440DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3441DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3442DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3443DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3444DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3445DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3446DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3448DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3450DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3451DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3453DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3454DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3456DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3457DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3458DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3459DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3460DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3461DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3462DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3464DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3465DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3466, + OPERAND_dsp340050b49a6c_fld3467DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3468DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3469DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3470DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3471DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3472DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3473DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3474DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3475DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3477DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3478DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3479DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3480DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3481DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3482DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3484DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3894DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3895DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3896DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3897DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3898DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3899DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3900, + OPERAND_dsp340050b49a6c_fld3901DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3903DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3904DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3905DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3906DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3907DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3908DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3909DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3910DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3913DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3914DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3916DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3917DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3918DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3919DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3920DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3921DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3922DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3923DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3924DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3925DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3927DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3928DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3929DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3930DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3931DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3933DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3934DUAL_slot2, + OPERAND_dsp340050b49a6c_fld3935DUAL_slot2, + OPERAND_op0_s22, + OPERAND_op0_s23, + OPERAND_dsp340050b49a6c_fld2057, + OPERAND_dsp340050b49a6c_fld2060, + OPERAND_dsp340050b49a6c_fld2066, + OPERAND_dsp340050b49a6c_fld2072, + OPERAND_dsp340050b49a6c_fld2079, + OPERAND_dsp340050b49a6c_fld3487DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3488DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3489DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3490DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3491DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3492DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3493DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3494DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3496DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3497DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3498DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3499DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3500DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3502DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3504DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3505DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3506DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3507DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3508DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3509DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3510DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3511DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3512DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3513DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3514DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3515DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3516DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3517DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3518DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3519DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3520DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3522DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3523DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3524DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3527DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3529DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3530DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3531, + OPERAND_dsp340050b49a6c_fld3532DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3533DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3535DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3536DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3537DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3538DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3539DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3541DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3542DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3543DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3544DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3545DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3546DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3547DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3548DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3549DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3550DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3551DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3552, + OPERAND_dsp340050b49a6c_fld3553DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3554DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3555DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3556DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3557DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3558DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3559DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3560DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3562DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3563DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3564DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3565DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3566DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3567DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3568DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3569DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3570DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3571DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3572DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3573DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3574DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3575DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3576DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3577DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3578DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3579DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3580DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3581DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3582DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3583DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3584, + OPERAND_dsp340050b49a6c_fld3585DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3587DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3588DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3589DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3590DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3591DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3592DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3593DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3594DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3595DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3596DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3597DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3598DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3599DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3600DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3601DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3602, + OPERAND_dsp340050b49a6c_fld3603DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3604DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3606DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3607DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3608DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3609DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3610, + OPERAND_dsp340050b49a6c_fld3611DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3612DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3613DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3614DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3615DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3616DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3618DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3619, + OPERAND_dsp340050b49a6c_fld3620DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3621DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3622DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3623DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3624DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3625DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3626DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3936DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3937DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3938DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3939DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3940DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3941DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3943DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3945DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3946DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3947DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3949DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3950DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3951DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3952DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3954DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3957DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3958DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3959DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3960DUAL_slot0, + OPERAND_dsp340050b49a6c_fld3961DUAL_slot0 +}; + + +/* Iclass table. */ + +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { + { { STATE_PSEXCM }, 'o' }, + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar12 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar8 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { + { { STATE_PSCALLINC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { + { { OPERAND_ars_entry }, 's' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm12x8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { + { { STATE_WindowBase }, 'i' }, + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { + { { OPERAND_simm4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSWOE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { + { { STATE_EPC1 }, 'i' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_WindowBase }, 'm' }, + { { STATE_WindowStart }, 'm' }, + { { STATE_PSOWB }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_immrx4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_WindowBase }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_WindowStart }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_ai4const }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { + { { OPERAND_ars }, 'o' }, + { { OPERAND_simm7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_lsi4x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { + { { STATE_THREADPTR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_simm8x256 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4const }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_bbi }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_b4constu }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_label12 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { + { { OPERAND_soffsetx4 }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ar0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sae }, 'i' }, + { { OPERAND_op2p1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { + { { OPERAND_soffset }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_uimm16x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_ulabel8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { + { { STATE_LBEG }, 'o' }, + { { STATE_LEND }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_simm12b }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { + { { OPERAND__ars_invisible }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { + { { OPERAND_sas }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { + { { STATE_SAR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_msalp32 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_sargt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { + { { STATE_LEND }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { + { { STATE_LEND }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { + { { STATE_LEND }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { + { { STATE_LCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_LCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { + { { STATE_LBEG }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { + { { STATE_SAR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { + { { STATE_SAR }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { + { { STATE_SAR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'i' }, + { { STATE_LITBEN }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'o' }, + { { STATE_LITBEN }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { + { { STATE_LITBADDR }, 'm' }, + { { STATE_LITBEN }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'i' }, + { { STATE_PSCALLINC }, 'i' }, + { { STATE_PSOWB }, 'i' }, + { { STATE_PSUM }, 'i' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { + { { STATE_PSWOE }, 'm' }, + { { STATE_PSCALLINC }, 'm' }, + { { STATE_PSOWB }, 'm' }, + { { STATE_PSUM }, 'm' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSINTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_EPC1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_EXCSAVE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_EPC2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_EXCSAVE2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_EPC3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_EXCSAVE3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_EPC4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_EXCSAVE4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { + { { STATE_EPC5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { + { { STATE_EXCSAVE5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { + { { STATE_EPC6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { + { { STATE_EPC6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { + { { STATE_EPC6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { + { { STATE_EXCSAVE6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { + { { STATE_EXCSAVE6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { + { { STATE_EXCSAVE6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_EPS2 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_EPS3 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_EPS4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { + { { STATE_EPS5 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { + { { STATE_EPS6 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { + { { STATE_EPS6 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_EXCVADDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_DEPC }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'i' }, + { { STATE_XTSYNC }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_EXCCAUSE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { + { { STATE_VECBASE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_mul16_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPC1 }, 'i' }, + { { STATE_EPC2 }, 'i' }, + { { STATE_EPC3 }, 'i' }, + { { STATE_EPC4 }, 'i' }, + { { STATE_EPC5 }, 'i' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_EPS2 }, 'i' }, + { { STATE_EPS3 }, 'i' }, + { { STATE_EPS4 }, 'i' }, + { { STATE_EPS5 }, 'i' }, + { { STATE_EPS6 }, 'i' }, + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { + { { OPERAND_s }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSINTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_INTERRUPT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_INTENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { + { { OPERAND_imms }, 'i' }, + { { OPERAND_immt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSINTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_DBREAKA0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_DBREAKC0 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_DBREAKA1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_DBREAKC1 }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_IBREAKA0 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_IBREAKA1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_IBREAKENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'i' }, + { { STATE_DBNUM }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'o' }, + { { STATE_DBNUM }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_DEBUGCAUSE }, 'm' }, + { { STATE_DBNUM }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_ICOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_ICOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_ICOUNTLEVEL }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_DDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_DDR }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { + { { OPERAND_imms }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { + { { STATE_InOCDMode }, 'm' }, + { { STATE_EPC6 }, 'i' }, + { { STATE_PSWOE }, 'o' }, + { { STATE_PSCALLINC }, 'o' }, + { { STATE_PSOWB }, 'o' }, + { { STATE_PSUM }, 'o' }, + { { STATE_PSEXCM }, 'o' }, + { { STATE_PSINTLEVEL }, 'o' }, + { { STATE_EPS6 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { + { { STATE_InOCDMode }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_bs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { + { { OPERAND_bt }, 'o' }, + { { OPERAND_bs8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { + { { OPERAND_bs }, 'i' }, + { { OPERAND_label8 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { + { { OPERAND_arr }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_brall }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_brall }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_brall }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_CCOUNT }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_CCOUNT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_CCOMPARE0 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'o' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_CCOMPARE1 }, 'm' }, + { { STATE_INTERRUPT }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm4x16 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { + { { STATE_CPENABLE }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { + { { STATE_CPENABLE }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_tp7 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { + { { OPERAND_art }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_uimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' }, + { { STATE_XTSYNC }, 'i' }, + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { + { { STATE_SCOMPARE1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { + { { OPERAND_art }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { + { { OPERAND_art }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { + { { STATE_ATOMCTL }, 'm' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_InvalidEnable }, 'i' }, + { { STATE_DivZeroEnable }, 'i' }, + { { STATE_OverflowEnable }, 'i' }, + { { STATE_UnderflowEnable }, 'i' }, + { { STATE_InexactEnable }, 'i' }, + { { STATE_FPreserved20 }, 'i' }, + { { STATE_FPreserved5 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = { + { { STATE_RoundMode }, 'o' }, + { { STATE_InvalidEnable }, 'o' }, + { { STATE_DivZeroEnable }, 'o' }, + { { STATE_OverflowEnable }, 'o' }, + { { STATE_UnderflowEnable }, 'o' }, + { { STATE_InexactEnable }, 'o' }, + { { STATE_FPreserved20 }, 'o' }, + { { STATE_FPreserved5 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'i' }, + { { STATE_DivZeroFlag }, 'i' }, + { { STATE_OverflowFlag }, 'i' }, + { { STATE_UnderflowFlag }, 'i' }, + { { STATE_InexactFlag }, 'i' }, + { { STATE_FPreserved20a }, 'i' }, + { { STATE_FPreserved7 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = { + { { STATE_InvalidFlag }, 'o' }, + { { STATE_DivZeroFlag }, 'o' }, + { { STATE_OverflowFlag }, 'o' }, + { { STATE_UnderflowFlag }, 'o' }, + { { STATE_InexactFlag }, 'o' }, + { { STATE_FPreserved20a }, 'o' }, + { { STATE_FPreserved7 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_mac_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_cmov_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_bt }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_mov_args[] = { + { { OPERAND_frr }, 'm' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_mov2_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_cmp_args[] = { + { { OPERAND_br }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_frt }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_float_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_float_stateArgs[] = { + { { STATE_RoundMode }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_int_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' }, + { { OPERAND_t }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_int_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_rfr_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_frs }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_wfr_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_lsi_args[] = { + { { OPERAND_frt }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_cimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_lsiu_args[] = { + { { OPERAND_frt }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_cimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_lsx_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_lsxu_args[] = { + { { OPERAND_frr }, 'o' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_ssi_args[] = { + { { OPERAND_frt }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_cimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_ssiu_args[] = { + { { OPERAND_frt }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_cimm8x4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_ssx_args[] = { + { { OPERAND_frr }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_ssxu_args[] = { + { { OPERAND_frr }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_ARGMAX_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_ARGMAX_stateArgs[] = { + { { STATE_ARG_MAX_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_HSAR_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_HSAR_stateArgs[] = { + { { STATE_HSAR3 }, 'i' }, + { { STATE_HSAR2 }, 'i' }, + { { STATE_HSAR1 }, 'i' }, + { { STATE_HSAR0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_HSAR2SAR_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_HSAR2SAR_stateArgs[] = { + { { STATE_SAR3 }, 'o' }, + { { STATE_SAR2 }, 'o' }, + { { STATE_SAR1 }, 'o' }, + { { STATE_SAR0 }, 'o' }, + { { STATE_HSAR3 }, 'i' }, + { { STATE_HSAR2 }, 'i' }, + { { STATE_HSAR1 }, 'i' }, + { { STATE_HSAR0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_INTERP_EXT_N_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_INTERP_EXT_N_stateArgs[] = { + { { STATE_INTERP_EXT_N }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_INTERP_EXT_L_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_INTERP_EXT_L_stateArgs[] = { + { { STATE_INTERP_EXT_L }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_LLR_BUF_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper70_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_LLR_BUF_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_LLR_POS_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_LLR_POS_stateArgs[] = { + { { STATE_LLR_POS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_MAX_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_MAX_stateArgs[] = { + { { STATE_MAX_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_NCO_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_NCO_stateArgs[] = { + { { STATE_NCO_COUNTER }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_PERM_REG_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_PERM_REG_stateArgs[] = { + { { STATE_PERM_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_PHASOR_N_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_PHASOR_N_stateArgs[] = { + { { STATE_PHASOR_N }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_PHASOR_OFFSET_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_PHASOR_OFFSET_stateArgs[] = { + { { STATE_PHASOR_OFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_SAR_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_SAR_stateArgs[] = { + { { STATE_SAR3 }, 'i' }, + { { STATE_SAR2 }, 'i' }, + { { STATE_SAR1 }, 'i' }, + { { STATE_SAR0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_SCALE_REG_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_SCALE_REG_stateArgs[] = { + { { STATE_SCALE_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_SMOD_BUF_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_SMOD_BUF_stateArgs[] = { + { { STATE_SMOD_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_SMOD_OFFSET_TABLE_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_SMOD_OFFSET_TABLE_stateArgs[] = { + { { STATE_SMOD_OFFSET_TABLE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_SMOD_POS_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_SMOD_POS_stateArgs[] = { + { { STATE_SMOD_POS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_SOV_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_SOV_stateArgs[] = { + { { STATE_SOV }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_WGHT_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_GET_WGHT_stateArgs[] = { + { { STATE_WEIGHT_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_ARGMAX_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_ARGMAX_stateArgs[] = { + { { STATE_ARG_MAX_REG }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_EXT_REGS_args[] = { + { { OPERAND_dsp340050b49a6c_oper88_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper59_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_EXT_REGS_stateArgs[] = { + { { STATE_INTERP_EXT_N }, 'o' }, + { { STATE_INTERP_EXT_L }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_HSAR_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_HSAR_stateArgs[] = { + { { STATE_HSAR0 }, 'o' }, + { { STATE_HSAR1 }, 'o' }, + { { STATE_HSAR2 }, 'o' }, + { { STATE_HSAR3 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_LLR_BUF_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper78_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_LLR_BUF_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_LLR_POS_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_LLR_POS_stateArgs[] = { + { { STATE_LLR_POS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_MAX_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_MAX_stateArgs[] = { + { { STATE_MAX_REG }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_NCO_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_NCO_stateArgs[] = { + { { STATE_NCO_COUNTER }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_PERM_REG_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_PERM_REG_stateArgs[] = { + { { STATE_PERM_REG }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_PHASOR_N_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_PHASOR_N_stateArgs[] = { + { { STATE_PHASOR_N }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_PHASOR_OFFSET_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_PHASOR_OFFSET_stateArgs[] = { + { { STATE_PHASOR_OFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_SAR_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_SAR_stateArgs[] = { + { { STATE_SAR0 }, 'o' }, + { { STATE_SAR1 }, 'o' }, + { { STATE_SAR2 }, 'o' }, + { { STATE_SAR3 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_SCALE_REG_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_SCALE_REG_stateArgs[] = { + { { STATE_SCALE_REG }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_SMOD_BUF_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_SMOD_BUF_stateArgs[] = { + { { STATE_SMOD_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_SMOD_OFFSET_TABLE_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_SMOD_OFFSET_TABLE_stateArgs[] = { + { { STATE_SMOD_OFFSET_TABLE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_SMOD_POS_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_SMOD_POS_stateArgs[] = { + { { STATE_SMOD_POS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_SOV_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_SOV_stateArgs[] = { + { { STATE_SOV }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_WGHT_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SET_WGHT_stateArgs[] = { + { { STATE_WEIGHT_REG }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC2X32_args[] = { + { { OPERAND_dsp340050b49a6c_oper71_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper72_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper73_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC2X64_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper71_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper74_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC2X64_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC2X64_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper71_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper74_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC2X64_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC2X64_2_args[] = { + { { OPERAND_dsp340050b49a6c_oper71_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper74_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC2X64_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC2X64_3_args[] = { + { { OPERAND_dsp340050b49a6c_oper71_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper74_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC2X64_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC32_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper71_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper72_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper75_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC32_R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC_IH_args[] = { + { { OPERAND_dsp340050b49a6c_oper71_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper76_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC_IH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC_IL_args[] = { + { { OPERAND_dsp340050b49a6c_oper71_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper76_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC_IL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC_RH_args[] = { + { { OPERAND_dsp340050b49a6c_oper71_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper76_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC_RH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC_RL_args[] = { + { { OPERAND_dsp340050b49a6c_oper71_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper76_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LAC_RL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LCM_args[] = { + { { OPERAND_dsp340050b49a6c_oper77_reg }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper74_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LCM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LCM_PINC_args[] = { + { { OPERAND_dsp340050b49a6c_oper77_reg }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper76_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LCM_PINC_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LCM_PINC_X_args[] = { + { { OPERAND_dsp340050b49a6c_oper77_reg }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LCM_PINC_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LCM_U_args[] = { + { { OPERAND_dsp340050b49a6c_oper77_reg }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper76_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LCM_U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LCM_X_args[] = { + { { OPERAND_dsp340050b49a6c_oper77_reg }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LCM_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LCM_XU_args[] = { + { { OPERAND_dsp340050b49a6c_oper77_reg }, 'o' }, + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LCM_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LP_args[] = { + { { OPERAND_dsp340050b49a6c_oper79_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper76_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LP_X_args[] = { + { { OPERAND_dsp340050b49a6c_oper79_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LP_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LQ_args[] = { + { { OPERAND_dsp340050b49a6c_oper79_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper76_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LQ_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LQ_X_args[] = { + { { OPERAND_dsp340050b49a6c_oper79_reg }, 'm' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LQ_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT0_args[] = { + { { OPERAND_dsp340050b49a6c_oper77_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper80_reg }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT1_args[] = { + { { OPERAND_dsp340050b49a6c_oper77_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper80_reg }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT2_args[] = { + { { OPERAND_dsp340050b49a6c_oper77_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper80_reg }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT3_args[] = { + { { OPERAND_dsp340050b49a6c_oper77_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper80_reg }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC2X32_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper72_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper84_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC2X32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC2X64_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper85_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC2X64_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC2X64_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper85_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC2X64_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC2X64_2_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper85_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC2X64_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC2X64_3_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper85_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC2X64_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC32_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper72_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper86_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC32_R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC_IH_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper87_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC_IH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC_IL_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper87_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC_IL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC_RH_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper87_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC_RH_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC_RL_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper87_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SAC_RL_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SCM_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper85_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SCM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SCM_PINC_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper87_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SCM_PINC_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SCM_PINC_X_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SCM_PINC_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SCM_U_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper87_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SCM_U_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SCM_X_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SCM_X_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SCM_XU_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SCM_XU_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_STORE_P_args[] = { + { { OPERAND_dsp340050b49a6c_oper79_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper85_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_STORE_P_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_STORE_Q_args[] = { + { { OPERAND_dsp340050b49a6c_oper79_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper85_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_STORE_Q_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AR2CM_DUP_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AR2CM_DUP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AR2CM_LN_args[] = { + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper52_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AR2CM_LN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AR2CM_LN_I_args[] = { + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper52_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AR2CM_LN_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AR2CM_LN_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper52_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AR2CM_LN_R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AR2PQ_LN_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper52_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper57_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AR2PQ_LN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AR2SAR_DUP_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AR2SAR_DUP_stateArgs[] = { + { { STATE_SAR3 }, 'o' }, + { { STATE_SAR2 }, 'o' }, + { { STATE_SAR1 }, 'o' }, + { { STATE_SAR0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRAC_args[] = { + { { OPERAND_dsp340050b49a6c_oper63_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRAC_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRCM_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRCM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CM2AR_LN_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper64_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CM2AR_LN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CM2AR_LN_I_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper64_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CM2AR_LN_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CM2AR_LN_R_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper64_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CM2AR_LN_R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_COMB_AR_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CONJ_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CONJ_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOV2AC32_I_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper71_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MOV2AC32_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOV2AC32_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper71_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MOV2AC32_R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOV2CM2PQ_args[] = { + { { OPERAND_dsp340050b49a6c_oper65_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOV2CM2PQ_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVAC_args[] = { + { { OPERAND_dsp340050b49a6c_oper63_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVAC_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVAC_I_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper66_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVAC_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVAC_I2R_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper63_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVAC_I2R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVAC_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper66_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVAC_R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVAC_R2I_args[] = { + { { OPERAND_dsp340050b49a6c_oper63_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVAC_R2I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVAR2_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCM_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCM2PQ_args[] = { + { { OPERAND_dsp340050b49a6c_oper81_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCM2PQ_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_2_args[] = { + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_3_args[] = { + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_4_args[] = { + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_5_args[] = { + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_5_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_6_args[] = { + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_6_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_7_args[] = { + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND_7_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_2_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_3_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_4_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_5_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_5_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_6_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_6_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_7_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVCND8_7_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOV_I_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOV_I_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVPQ2PQ_args[] = { + { { OPERAND_dsp340050b49a6c_oper65_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOVPQ2PQ_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOV_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOV_R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_NEGCM_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_NEGCM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_POP16LLR_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper63_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_POP16LLR_1_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_LLR_POS }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_PQ2CM_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_PQ2CM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SWAPAC_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper54_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_SWAPAC_R_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SWAPAC_RI_args[] = { + { { OPERAND_dsp340050b49a6c_oper63_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SWAPAC_RI_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SWAPB_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADD2AC_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper52_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADD2AC_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAR0 }, 'i' }, + { { STATE_SAR1 }, 'i' }, + { { STATE_SAR2 }, 'i' }, + { { STATE_SAR3 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADDAC_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper54_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADDAC_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CDOT_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_CDOT_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CDOTAC_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CDOTAC_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CDOTACS_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CDOTACS_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMAC_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CMAC_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMACS_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CMACS_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMPY_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_CMPY_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMPY2CM_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMPY2CM_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMPY2PQ_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_CMPY2PQ_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMPYS_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_CMPYS_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMPYXP2PQ_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper52_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMPYXP2PQ_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_COMB32_args[] = { + { { OPERAND_dsp340050b49a6c_oper65_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper66_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper67_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_COMB32_stateArgs[] = { + { { STATE_WEIGHT_REG }, 'i' }, + { { STATE_SCALE_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_DOT_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_DOT_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_DOTAC_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_DOTAC_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_DOTACS_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_DOTACS_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LIN_INT_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LIN_INT_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_INTERP_EXT_L }, 'i' }, + { { STATE_INTERP_EXT_N }, 'i' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_SCALE_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LLRPRE1_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper54_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_LLRPRE1_stateArgs[] = { + { { STATE_PERM_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LLRPRE2_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper66_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper78_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LLRPRE2_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_LLR_POS }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MAC_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MAC_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MAC8_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MAC8_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MACD8_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MACD8_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MACPQXP_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MACPQXP_0_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MACPQXP_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MACPQXP_1_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MACPQXP_2_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MACPQXP_2_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MACPQXP_3_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MACPQXP_3_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MACS_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MACS_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MACXP2_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MACXP2_0_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MACXP2_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MACXP2_1_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MACXP_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MACXP_0_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MACXP_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MACXP_1_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MACXP_2_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MACXP_2_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MACXP_3_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MACXP_3_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOV2AC_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper52_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MOV2AC_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAR0 }, 'i' }, + { { STATE_SAR1 }, 'i' }, + { { STATE_SAR2 }, 'i' }, + { { STATE_SAR3 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPY_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPY_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPY2CM_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPY2CM_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPY2PQ_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_MPY2PQ_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPY8_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPY8_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYADD8_2CM_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYADD8_2CM_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYD8_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYD8_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYPQXP_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYPQXP_0_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYPQXP_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYPQXP_1_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYPQXP_2_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYPQXP_2_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYPQXP_3_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYPQXP_3_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYS_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYS_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP2PQ_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper52_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP2PQ_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP2_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP2_0_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP2_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP2_1_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP_0_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP_1_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP_2_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP_2_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP_3_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_MPYXP_3_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_NORMACD_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_NORMACD_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_NORMACPQ_I_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_NORMACPQ_I_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_NORMACPQ_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_NORMACPQ_R_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_NORMD_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_NORMD_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_NORMPYPQ_I_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_NORMPYPQ_I_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_NORMPYPQ_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_NORMPYPQ_R_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RCMAC_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_RCMAC_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RCMPY_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_RCMPY_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RCMPY2CM_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RCMPY2CM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RFIR_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper54_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper59_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RFIR_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RFIRA_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper54_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper59_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RFIRA_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RFIRD_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper54_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RFIRD_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RFIRDA_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper54_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RFIRDA_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RMAC_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_RMAC_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RMPY_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_RMPY_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RMPY2CM_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_RMPY2CM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SMOD_ALIGN_args[] = { + { { OPERAND_dsp340050b49a6c_oper63_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper78_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SMOD_ALIGN_stateArgs[] = { + { { STATE_SMOD_BUF }, 'm' }, + { { STATE_SMOD_POS }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SMOD_SCR_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper66_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SMOD_SCR_stateArgs[] = { + { { STATE_PERM_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SUB2AC_args[] = { + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper52_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SUB2AC_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAR0 }, 'i' }, + { { STATE_SAR1 }, 'i' }, + { { STATE_SAR2 }, 'i' }, + { { STATE_SAR3 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WGHT32_args[] = { + { { OPERAND_dsp340050b49a6c_oper65_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper50_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper62_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WGHT32_stateArgs[] = { + { { STATE_WEIGHT_REG }, 'i' }, + { { STATE_SCALE_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRTIEP_args[] = { + { { OPERAND_dsp340050b49a6c_oper61_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLRTIEP_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT_2FIFO_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT_2FIFO_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_EXT_2FIFO_0_intfArgs[] = { + INTERFACE_OUTQ0_128 +}; + +static xtensa_arg_internal Iclass_iclass_EXT_2FIFO_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT_2FIFO_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_EXT_2FIFO_1_intfArgs[] = { + INTERFACE_OUTQ1_128 +}; + +static xtensa_arg_internal Iclass_iclass_EXT_2FIFO_2_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT_2FIFO_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_EXT_2FIFO_2_intfArgs[] = { + INTERFACE_OUTQ2_128 +}; + +static xtensa_arg_internal Iclass_iclass_EXT_2FIFO_3_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT_2FIFO_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_EXT_2FIFO_3_intfArgs[] = { + INTERFACE_OUTQ3_128 +}; + +static xtensa_arg_internal Iclass_iclass_EXT_R2FIFO_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT_R2FIFO_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_EXT_R2FIFO_0_intfArgs[] = { + INTERFACE_OUTQ0_128 +}; + +static xtensa_arg_internal Iclass_iclass_EXT_R2FIFO_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT_R2FIFO_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_EXT_R2FIFO_1_intfArgs[] = { + INTERFACE_OUTQ1_128 +}; + +static xtensa_arg_internal Iclass_iclass_EXT_R2FIFO_2_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT_R2FIFO_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_EXT_R2FIFO_2_intfArgs[] = { + INTERFACE_OUTQ2_128 +}; + +static xtensa_arg_internal Iclass_iclass_EXT_R2FIFO_3_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT_R2FIFO_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_EXT_R2FIFO_3_intfArgs[] = { + INTERFACE_OUTQ3_128 +}; + +static xtensa_arg_internal Iclass_iclass_LUT_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_LUT_intfArgs[] = { + INTERFACE_LU128_Out, + INTERFACE_LU128_In +}; + +static xtensa_arg_internal Iclass_iclass_LUT_AR_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT_AR_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_LUT_AR_intfArgs[] = { + INTERFACE_LU128_Out, + INTERFACE_LU128_In +}; + +static xtensa_arg_internal Iclass_iclass_LUT_IEXT_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT_IEXT_stateArgs[] = { + { { STATE_INTERP_EXT_L }, 'i' }, + { { STATE_INTERP_EXT_N }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_LUT_IEXT_intfArgs[] = { + INTERFACE_LU128_Out, + INTERFACE_LU128_In +}; + +static xtensa_arg_internal Iclass_iclass_LUT_PHASOR_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT_PHASOR_stateArgs[] = { + { { STATE_PHASOR_N }, 'i' }, + { { STATE_PHASOR_OFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_LUT_PHASOR_intfArgs[] = { + INTERFACE_LU128_Out, + INTERFACE_LU128_In +}; + +static xtensa_arg_internal Iclass_iclass_LUT_REXT_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT_REXT_stateArgs[] = { + { { STATE_INTERP_EXT_L }, 'i' }, + { { STATE_INTERP_EXT_N }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_LUT_REXT_intfArgs[] = { + INTERFACE_LU128_Out, + INTERFACE_LU128_In +}; + +static xtensa_arg_internal Iclass_iclass_LUT_WRITE_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper64_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper52_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LUT_WRITE_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_LUT_WRITE_intfArgs[] = { + INTERFACE_LU128_Out, + INTERFACE_LU128_In +}; + +static xtensa_interface Iclass_iclass_MOVEQ128_0_intfArgs[] = { + INTERFACE_OUTQ0_128, + INTERFACE_INQ0_128 +}; + +static xtensa_interface Iclass_iclass_MOVEQ128_1_intfArgs[] = { + INTERFACE_OUTQ1_128, + INTERFACE_INQ1_128 +}; + +static xtensa_interface Iclass_iclass_MOVEQ128_2_intfArgs[] = { + INTERFACE_OUTQ2_128, + INTERFACE_INQ2_128 +}; + +static xtensa_interface Iclass_iclass_MOVEQ128_3_intfArgs[] = { + INTERFACE_OUTQ3_128, + INTERFACE_INQ3_128 +}; + +static xtensa_interface Iclass_iclass_MOVEQ128_4_intfArgs[] = { + INTERFACE_OUTQ4_128, + INTERFACE_INQ4_128 +}; + +static xtensa_interface Iclass_iclass_MOVEQ128_5_intfArgs[] = { + INTERFACE_OUTQ5_128, + INTERFACE_INQ5_128 +}; + +static xtensa_interface Iclass_iclass_MOVEQ32_0_intfArgs[] = { + INTERFACE_OUTQ0_32, + INTERFACE_INQ0_32 +}; + +static xtensa_interface Iclass_iclass_MOVEQ32_1_intfArgs[] = { + INTERFACE_OUTQ1_32, + INTERFACE_INQ1_32 +}; + +static xtensa_interface Iclass_iclass_MOVEQ32_2_intfArgs[] = { + INTERFACE_OUTQ2_32, + INTERFACE_INQ2_32 +}; + +static xtensa_interface Iclass_iclass_MOVEQ32_3_intfArgs[] = { + INTERFACE_OUTQ3_32, + INTERFACE_INQ3_32 +}; + +static xtensa_arg_internal Iclass_iclass_NCO_UPDATE_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_NCO_UPDATE_stateArgs[] = { + { { STATE_NCO_COUNTER }, 'm' }, + { { STATE_PHASOR_N }, 'i' }, + { { STATE_PHASOR_OFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_NCO_UPDATE_intfArgs[] = { + INTERFACE_LU128_Out, + INTERFACE_LU128_In +}; + +static xtensa_arg_internal Iclass_iclass_POP128_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_0_intfArgs[] = { + INTERFACE_INQ0_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_1_intfArgs[] = { + INTERFACE_INQ1_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2_intfArgs[] = { + INTERFACE_INQ2_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_3_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_3_intfArgs[] = { + INTERFACE_INQ3_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_4_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_4_intfArgs[] = { + INTERFACE_INQ4_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_5_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_5_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_5_intfArgs[] = { + INTERFACE_INQ5_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2CMPQ_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2CMPQ_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2CMPQ_0_intfArgs[] = { + INTERFACE_INQ0_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2CMPQ_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2CMPQ_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2CMPQ_1_intfArgs[] = { + INTERFACE_INQ1_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2CMPQ_2_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2CMPQ_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2CMPQ_2_intfArgs[] = { + INTERFACE_INQ2_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2CMPQ_3_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2CMPQ_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2CMPQ_3_intfArgs[] = { + INTERFACE_INQ3_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2M_0_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper83_imm }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2M_0_intfArgs[] = { + INTERFACE_INQ0_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2M_1_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper83_imm }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2M_1_intfArgs[] = { + INTERFACE_INQ1_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2M_2_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper83_imm }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2M_2_intfArgs[] = { + INTERFACE_INQ2_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2M_3_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper83_imm }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2M_3_intfArgs[] = { + INTERFACE_INQ3_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2PQ_0_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2PQ_0_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2PQ_0_intfArgs[] = { + INTERFACE_INQ0_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2PQ_1_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2PQ_1_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2PQ_1_intfArgs[] = { + INTERFACE_INQ1_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2PQ_2_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2PQ_2_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2PQ_2_intfArgs[] = { + INTERFACE_INQ2_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2PQ_3_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2PQ_3_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2PQ_3_intfArgs[] = { + INTERFACE_INQ3_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2PQ_4_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2PQ_4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2PQ_4_intfArgs[] = { + INTERFACE_INQ4_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2PQ_5_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_POP128_2PQ_5_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP128_2PQ_5_intfArgs[] = { + INTERFACE_INQ5_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP2X128_2PQ_01_args[] = { + { { OPERAND_dsp340050b49a6c_oper65_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_POP2X128_2PQ_01_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP2X128_2PQ_01_intfArgs[] = { + INTERFACE_INQ0_128, + INTERFACE_INQ1_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP2X128_2PQ_03_args[] = { + { { OPERAND_dsp340050b49a6c_oper65_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_POP2X128_2PQ_03_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP2X128_2PQ_03_intfArgs[] = { + INTERFACE_INQ0_128, + INTERFACE_INQ3_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP2X128_2PQ_21_args[] = { + { { OPERAND_dsp340050b49a6c_oper65_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_POP2X128_2PQ_21_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP2X128_2PQ_21_intfArgs[] = { + INTERFACE_INQ2_128, + INTERFACE_INQ1_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP2X128_2PQ_23_args[] = { + { { OPERAND_dsp340050b49a6c_oper65_reg }, 'o' } +}; + +static xtensa_arg_internal Iclass_iclass_POP2X128_2PQ_23_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_POP2X128_2PQ_23_intfArgs[] = { + INTERFACE_INQ2_128, + INTERFACE_INQ3_128 +}; + +static xtensa_arg_internal Iclass_iclass_POP32_0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_interface Iclass_iclass_POP32_0_intfArgs[] = { + INTERFACE_INQ0_32 +}; + +static xtensa_arg_internal Iclass_iclass_POP32_1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_interface Iclass_iclass_POP32_1_intfArgs[] = { + INTERFACE_INQ1_32 +}; + +static xtensa_arg_internal Iclass_iclass_POP32_2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_interface Iclass_iclass_POP32_2_intfArgs[] = { + INTERFACE_INQ2_32 +}; + +static xtensa_arg_internal Iclass_iclass_POP32_3_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_interface Iclass_iclass_POP32_3_intfArgs[] = { + INTERFACE_INQ3_32 +}; + +static xtensa_arg_internal Iclass_iclass_PUSH128_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper78_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_PUSH128_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_PUSH128_intfArgs[] = { + INTERFACE_OUTQ0_128, + INTERFACE_OUTQ0_128_KILL, + INTERFACE_OUTQ1_128, + INTERFACE_OUTQ1_128_KILL, + INTERFACE_OUTQ2_128, + INTERFACE_OUTQ2_128_KILL, + INTERFACE_OUTQ3_128, + INTERFACE_OUTQ3_128_KILL, + INTERFACE_OUTQ4_128, + INTERFACE_OUTQ4_128_KILL, + INTERFACE_OUTQ5_128, + INTERFACE_OUTQ5_128_KILL +}; + +static xtensa_arg_internal Iclass_iclass_PUSH128_M_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper52_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper83_imm }, 'i' } +}; + +static xtensa_interface Iclass_iclass_PUSH128_M_intfArgs[] = { + INTERFACE_OUTQ0_128, + INTERFACE_OUTQ0_128_KILL, + INTERFACE_OUTQ1_128, + INTERFACE_OUTQ1_128_KILL, + INTERFACE_OUTQ2_128, + INTERFACE_OUTQ2_128_KILL, + INTERFACE_OUTQ3_128, + INTERFACE_OUTQ3_128_KILL +}; + +static xtensa_arg_internal Iclass_iclass_PUSH128_PQ_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper78_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_PUSH128_PQ_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_PUSH128_PQ_intfArgs[] = { + INTERFACE_OUTQ0_128, + INTERFACE_OUTQ0_128_KILL, + INTERFACE_OUTQ1_128, + INTERFACE_OUTQ1_128_KILL, + INTERFACE_OUTQ2_128, + INTERFACE_OUTQ2_128_KILL, + INTERFACE_OUTQ3_128, + INTERFACE_OUTQ3_128_KILL, + INTERFACE_OUTQ4_128, + INTERFACE_OUTQ4_128_KILL, + INTERFACE_OUTQ5_128, + INTERFACE_OUTQ5_128_KILL +}; + +static xtensa_arg_internal Iclass_iclass_PUSH2X128_PQ_args[] = { + { { OPERAND_dsp340050b49a6c_oper56_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper57_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_PUSH2X128_PQ_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_PUSH2X128_PQ_intfArgs[] = { + INTERFACE_OUTQ0_128, + INTERFACE_OUTQ1_128, + INTERFACE_OUTQ2_128, + INTERFACE_OUTQ3_128, + INTERFACE_OUTQ0_128_KILL, + INTERFACE_OUTQ1_128_KILL, + INTERFACE_OUTQ2_128_KILL, + INTERFACE_OUTQ3_128_KILL +}; + +static xtensa_arg_internal Iclass_iclass_PUSH32_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper59_imm }, 'i' } +}; + +static xtensa_interface Iclass_iclass_PUSH32_intfArgs[] = { + INTERFACE_OUTQ0_32, + INTERFACE_OUTQ0_32_KILL, + INTERFACE_OUTQ1_32, + INTERFACE_OUTQ1_32_KILL, + INTERFACE_OUTQ2_32, + INTERFACE_OUTQ2_32_KILL, + INTERFACE_OUTQ3_32, + INTERFACE_OUTQ3_32_KILL, + INTERFACE_OUTQ4_32, + INTERFACE_OUTQ4_32_KILL, + INTERFACE_OUTQ5_32, + INTERFACE_OUTQ5_32_KILL +}; + +static xtensa_arg_internal Iclass_iclass_QREADY_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper61_imm }, 'i' } +}; + +static xtensa_interface Iclass_iclass_QREADY_intfArgs[] = { + INTERFACE_INQ0_32_NOTRDY, + INTERFACE_INQ1_32_NOTRDY, + INTERFACE_INQ2_32_NOTRDY, + INTERFACE_INQ3_32_NOTRDY, + INTERFACE_OUTQ0_32_NOTRDY, + INTERFACE_OUTQ1_32_NOTRDY, + INTERFACE_OUTQ2_32_NOTRDY, + INTERFACE_OUTQ3_32_NOTRDY, + INTERFACE_OUTQ4_32_NOTRDY, + INTERFACE_OUTQ5_32_NOTRDY, + INTERFACE_INQ0_128_NOTRDY, + INTERFACE_INQ1_128_NOTRDY, + INTERFACE_INQ2_128_NOTRDY, + INTERFACE_INQ3_128_NOTRDY, + INTERFACE_INQ4_128_NOTRDY, + INTERFACE_INQ5_128_NOTRDY, + INTERFACE_OUTQ0_128_NOTRDY, + INTERFACE_OUTQ1_128_NOTRDY, + INTERFACE_OUTQ2_128_NOTRDY, + INTERFACE_OUTQ3_128_NOTRDY, + INTERFACE_OUTQ4_128_NOTRDY, + INTERFACE_OUTQ5_128_NOTRDY, + INTERFACE_SIGNALQ_NOTRDY +}; + +static xtensa_arg_internal Iclass_iclass_RDTIEP_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_interface Iclass_iclass_RDTIEP_intfArgs[] = { + INTERFACE_IMPWIRE +}; + +static xtensa_arg_internal Iclass_iclass_SETTIEP_args[] = { + { { OPERAND_dsp340050b49a6c_oper61_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SETTIEP_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_SMOD_LUT_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper78_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper57_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SMOD_LUT_stateArgs[] = { + { { STATE_SMOD_OFFSET_TABLE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_interface Iclass_iclass_SMOD_LUT_intfArgs[] = { + INTERFACE_LU128_Out, + INTERFACE_LU128_In +}; + +static xtensa_arg_internal Iclass_iclass_WRTBSIGQ_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_interface Iclass_iclass_WRTBSIGQ_intfArgs[] = { + INTERFACE_SIGNALQ +}; + +static xtensa_arg_internal Iclass_iclass_WRTBSIGQM_args[] = { + { { OPERAND_dsp340050b49a6c_oper61_imm }, 'i' } +}; + +static xtensa_interface Iclass_iclass_WRTBSIGQM_intfArgs[] = { + INTERFACE_SIGNALQ +}; + +static xtensa_arg_internal Iclass_iclass_WRTIEP_args[] = { + { { OPERAND_art }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_WRTIEP_stateArgs[] = { + { { STATE_EXPSTATE }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_WRTSIGQ_args[] = { + { { OPERAND_ars }, 'i' } +}; + +static xtensa_interface Iclass_iclass_WRTSIGQ_intfArgs[] = { + INTERFACE_SIGNALQ +}; + +static xtensa_arg_internal Iclass_iclass_ABS8_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ABS8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADD16_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper49_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADD16_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADD32_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper53_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADD32_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADDAC_I2R_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_ADDAC_I2R_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADDAC_R2I_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_ADDAC_R2I_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADDAR2_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADDCM_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper53_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADDCM_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADDWRP_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper55_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ADDWRP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AND128_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper55_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_AND128_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ARGMAX8_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper53_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ARGMAX8_stateArgs[] = { + { { STATE_MAX_REG }, 'm' }, + { { STATE_ARG_MAX_REG }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASL_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper53_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASL_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASL32_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper55_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASL32_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASLACM_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper58_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASLACM_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASLM_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper59_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASLM_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASLM32_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper58_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASLM32_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASR_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper53_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASR_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASR32_args[] = { + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper55_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASR32_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASRAC_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper55_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASRAC_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASRM_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper59_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_ASRM_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_BITFEXT_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper60_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper61_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_BITFINS_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper61_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper60_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLB_C_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLB_C_stateArgs[] = { + { { STATE_SAR3 }, 'o' }, + { { STATE_SAR2 }, 'o' }, + { { STATE_SAR1 }, 'o' }, + { { STATE_SAR0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLB_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CLB_R_stateArgs[] = { + { { STATE_SAR3 }, 'o' }, + { { STATE_SAR2 }, 'o' }, + { { STATE_SAR1 }, 'o' }, + { { STATE_SAR0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMP8_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMP8_stateArgs[] = { + { { STATE_SOV }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMP_I_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMP_I_stateArgs[] = { + { { STATE_SOV }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMP_R_args[] = { + { { OPERAND_arr }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper47_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_CMP_R_stateArgs[] = { + { { STATE_SOV }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper68_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper69_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAR3 }, 'i' }, + { { STATE_SAR2 }, 'i' }, + { { STATE_SAR1 }, 'i' }, + { { STATE_SAR0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper68_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper69_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT_R_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAR3 }, 'i' }, + { { STATE_SAR2 }, 'i' }, + { { STATE_SAR1 }, 'i' }, + { { STATE_SAR0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT32_I_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT32_I_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT32_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper48_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXT32_R_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXTUI4_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_EXTUI4_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LSLM_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper59_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LSLM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LSRM_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper59_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_LSRM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MAX8_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper55_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MAX8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MEAN_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper55_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MEAN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MEAN32_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper53_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MEAN32_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MIN8_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper55_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MIN8_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MINCLB_C_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MINCLB_C_stateArgs[] = { + { { STATE_HSAR3 }, 'm' }, + { { STATE_HSAR2 }, 'm' }, + { { STATE_HSAR1 }, 'm' }, + { { STATE_HSAR0 }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MINCLB_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_MINCLB_R_stateArgs[] = { + { { STATE_HSAR3 }, 'm' }, + { { STATE_HSAR2 }, 'm' }, + { { STATE_HSAR1 }, 'm' }, + { { STATE_HSAR0 }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_NOT128_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_NOT128_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_OR128_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper55_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_OR128_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_PERM_args[] = { + { { OPERAND_dsp340050b49a6c_oper82_reg }, 'm' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_ars }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_PERM_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_REDAC_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_REDAC_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_REDAC2_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_REDAC2_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_REDAC4_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_REDAC4_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_REDACS_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_REDACS_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SMINCLB_C_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SMINCLB_C_stateArgs[] = { + { { STATE_HSAR3 }, 'o' }, + { { STATE_HSAR2 }, 'o' }, + { { STATE_HSAR1 }, 'o' }, + { { STATE_HSAR0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SMINCLB_R_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SMINCLB_R_stateArgs[] = { + { { STATE_HSAR3 }, 'o' }, + { { STATE_HSAR2 }, 'o' }, + { { STATE_HSAR1 }, 'o' }, + { { STATE_HSAR0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_STSWAPBM_args[] = { + { { OPERAND_ars }, 'i' }, + { { OPERAND_art }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper89_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_STSWAPBMU_args[] = { + { { OPERAND_art }, 'm' }, + { { OPERAND_ars }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper89_imm }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SUB32_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper53_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SUB32_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SUBAC_I2R_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_SUBAC_I2R_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SUBAC_R2I_args[] = { + { { OPERAND_dsp340050b49a6c_oper51_reg }, 'm' } +}; + +static xtensa_arg_internal Iclass_iclass_SUBAC_R2I_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SUBARX_args[] = { + { { OPERAND_ars }, 'm' }, + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SUBCM_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper55_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SUBCM_stateArgs[] = { + { { STATE_SOV }, 'm' }, + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SUBMEAN_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper55_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SUBMEAN_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SUBWRP_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper55_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_SUBWRP_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_TRANS_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_TRANS_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_XOR128_args[] = { + { { OPERAND_dsp340050b49a6c_oper45_reg }, 'o' }, + { { OPERAND_dsp340050b49a6c_oper55_reg }, 'i' }, + { { OPERAND_dsp340050b49a6c_oper46_reg }, 'i' } +}; + +static xtensa_arg_internal Iclass_iclass_XOR128_stateArgs[] = { + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { + { { STATE_EXPSTATE }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_sov_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_sov_stateArgs[] = { + { { STATE_SOV }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_sov_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_sov_stateArgs[] = { + { { STATE_SOV }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_sat_mode_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_sat_mode_stateArgs[] = { + { { STATE_SAT_MODE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_sat_mode_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_sat_mode_stateArgs[] = { + { { STATE_SAT_MODE }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_sar0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_sar0_stateArgs[] = { + { { STATE_SAR0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_sar0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_sar0_stateArgs[] = { + { { STATE_SAR0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_sar1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_sar1_stateArgs[] = { + { { STATE_SAR1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_sar1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_sar1_stateArgs[] = { + { { STATE_SAR1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_sar2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_sar2_stateArgs[] = { + { { STATE_SAR2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_sar2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_sar2_stateArgs[] = { + { { STATE_SAR2 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_sar3_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_sar3_stateArgs[] = { + { { STATE_SAR3 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_sar3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_sar3_stateArgs[] = { + { { STATE_SAR3 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_hsar0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_hsar0_stateArgs[] = { + { { STATE_HSAR0 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_hsar0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_hsar0_stateArgs[] = { + { { STATE_HSAR0 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_hsar1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_hsar1_stateArgs[] = { + { { STATE_HSAR1 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_hsar1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_hsar1_stateArgs[] = { + { { STATE_HSAR1 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_hsar2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_hsar2_stateArgs[] = { + { { STATE_HSAR2 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_hsar2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_hsar2_stateArgs[] = { + { { STATE_HSAR2 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_hsar3_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_hsar3_stateArgs[] = { + { { STATE_HSAR3 }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_hsar3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_hsar3_stateArgs[] = { + { { STATE_HSAR3 }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_max_reg_0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_max_reg_0_stateArgs[] = { + { { STATE_MAX_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_max_reg_0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_max_reg_0_stateArgs[] = { + { { STATE_MAX_REG }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_max_reg_1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_max_reg_1_stateArgs[] = { + { { STATE_MAX_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_max_reg_1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_max_reg_1_stateArgs[] = { + { { STATE_MAX_REG }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_max_reg_2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_max_reg_2_stateArgs[] = { + { { STATE_MAX_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_max_reg_2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_max_reg_2_stateArgs[] = { + { { STATE_MAX_REG }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_max_reg_3_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_max_reg_3_stateArgs[] = { + { { STATE_MAX_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_max_reg_3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_max_reg_3_stateArgs[] = { + { { STATE_MAX_REG }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_arg_max_reg_0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_arg_max_reg_0_stateArgs[] = { + { { STATE_ARG_MAX_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_arg_max_reg_0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_arg_max_reg_0_stateArgs[] = { + { { STATE_ARG_MAX_REG }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_arg_max_reg_1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_arg_max_reg_1_stateArgs[] = { + { { STATE_ARG_MAX_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_arg_max_reg_1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_arg_max_reg_1_stateArgs[] = { + { { STATE_ARG_MAX_REG }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_arg_max_reg_2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_arg_max_reg_2_stateArgs[] = { + { { STATE_ARG_MAX_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_arg_max_reg_2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_arg_max_reg_2_stateArgs[] = { + { { STATE_ARG_MAX_REG }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_arg_max_reg_3_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_arg_max_reg_3_stateArgs[] = { + { { STATE_ARG_MAX_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_arg_max_reg_3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_arg_max_reg_3_stateArgs[] = { + { { STATE_ARG_MAX_REG }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_nco_counter_0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_nco_counter_0_stateArgs[] = { + { { STATE_NCO_COUNTER }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_nco_counter_0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_nco_counter_0_stateArgs[] = { + { { STATE_NCO_COUNTER }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_nco_counter_1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_nco_counter_1_stateArgs[] = { + { { STATE_NCO_COUNTER }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_nco_counter_1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_nco_counter_1_stateArgs[] = { + { { STATE_NCO_COUNTER }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_nco_counter_2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_nco_counter_2_stateArgs[] = { + { { STATE_NCO_COUNTER }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_nco_counter_2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_nco_counter_2_stateArgs[] = { + { { STATE_NCO_COUNTER }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_nco_counter_3_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_nco_counter_3_stateArgs[] = { + { { STATE_NCO_COUNTER }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_nco_counter_3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_nco_counter_3_stateArgs[] = { + { { STATE_NCO_COUNTER }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_interp_ext_n_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_interp_ext_n_stateArgs[] = { + { { STATE_INTERP_EXT_N }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_interp_ext_n_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_interp_ext_n_stateArgs[] = { + { { STATE_INTERP_EXT_N }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_interp_ext_l_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_interp_ext_l_stateArgs[] = { + { { STATE_INTERP_EXT_L }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_interp_ext_l_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_interp_ext_l_stateArgs[] = { + { { STATE_INTERP_EXT_L }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_0_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_0_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_1_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_1_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_2_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_2_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_3_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_3_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_3_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_4_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_4_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_4_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_5_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_5_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_5_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_6_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_6_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_6_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_7_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_7_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_7_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_8_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_8_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_8_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_8_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_9_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_9_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_9_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_9_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_10_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_10_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_10_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_10_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_11_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_11_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_11_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_11_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_12_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_12_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_12_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_12_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_13_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_13_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_13_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_13_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_14_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_14_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_14_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_14_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_15_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_15_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_15_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_15_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_16_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_16_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_16_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_16_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_17_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_17_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_17_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_17_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_18_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_18_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_18_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_18_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_19_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_19_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_19_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_19_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_20_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_20_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_20_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_20_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_21_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_21_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_21_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_21_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_22_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_22_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_22_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_22_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_23_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_buf_23_stateArgs[] = { + { { STATE_LLR_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_23_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_buf_23_stateArgs[] = { + { { STATE_LLR_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_0_stateArgs[] = { + { { STATE_SMOD_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_0_stateArgs[] = { + { { STATE_SMOD_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_1_stateArgs[] = { + { { STATE_SMOD_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_1_stateArgs[] = { + { { STATE_SMOD_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_2_stateArgs[] = { + { { STATE_SMOD_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_2_stateArgs[] = { + { { STATE_SMOD_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_3_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_3_stateArgs[] = { + { { STATE_SMOD_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_3_stateArgs[] = { + { { STATE_SMOD_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_4_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_4_stateArgs[] = { + { { STATE_SMOD_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_4_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_4_stateArgs[] = { + { { STATE_SMOD_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_5_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_5_stateArgs[] = { + { { STATE_SMOD_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_5_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_5_stateArgs[] = { + { { STATE_SMOD_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_6_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_6_stateArgs[] = { + { { STATE_SMOD_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_6_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_6_stateArgs[] = { + { { STATE_SMOD_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_7_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_smod_buf_7_stateArgs[] = { + { { STATE_SMOD_BUF }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_7_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_buf_7_stateArgs[] = { + { { STATE_SMOD_BUF }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_weight_reg_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_weight_reg_stateArgs[] = { + { { STATE_WEIGHT_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_weight_reg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_weight_reg_stateArgs[] = { + { { STATE_WEIGHT_REG }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_scale_reg_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_scale_reg_stateArgs[] = { + { { STATE_SCALE_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_scale_reg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_scale_reg_stateArgs[] = { + { { STATE_SCALE_REG }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_llr_pos_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_llr_pos_stateArgs[] = { + { { STATE_LLR_POS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_pos_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_llr_pos_stateArgs[] = { + { { STATE_LLR_POS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_smod_pos_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_smod_pos_stateArgs[] = { + { { STATE_SMOD_POS }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_pos_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_pos_stateArgs[] = { + { { STATE_SMOD_POS }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_perm_reg_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_perm_reg_stateArgs[] = { + { { STATE_PERM_REG }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_perm_reg_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_perm_reg_stateArgs[] = { + { { STATE_PERM_REG }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_smod_offset_table_0_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_smod_offset_table_0_stateArgs[] = { + { { STATE_SMOD_OFFSET_TABLE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_offset_table_0_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_offset_table_0_stateArgs[] = { + { { STATE_SMOD_OFFSET_TABLE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_smod_offset_table_1_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_smod_offset_table_1_stateArgs[] = { + { { STATE_SMOD_OFFSET_TABLE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_offset_table_1_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_offset_table_1_stateArgs[] = { + { { STATE_SMOD_OFFSET_TABLE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_smod_offset_table_2_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_smod_offset_table_2_stateArgs[] = { + { { STATE_SMOD_OFFSET_TABLE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_offset_table_2_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_offset_table_2_stateArgs[] = { + { { STATE_SMOD_OFFSET_TABLE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_smod_offset_table_3_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_smod_offset_table_3_stateArgs[] = { + { { STATE_SMOD_OFFSET_TABLE }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_offset_table_3_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_smod_offset_table_3_stateArgs[] = { + { { STATE_SMOD_OFFSET_TABLE }, 'm' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_phasor_n_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_phasor_n_stateArgs[] = { + { { STATE_PHASOR_N }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_phasor_n_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_phasor_n_stateArgs[] = { + { { STATE_PHASOR_N }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_rur_phasor_offset_args[] = { + { { OPERAND_arr }, 'o' } +}; + +static xtensa_arg_internal Iclass_rur_phasor_offset_stateArgs[] = { + { { STATE_PHASOR_OFFSET }, 'i' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_phasor_offset_args[] = { + { { OPERAND_art }, 'i' } +}; + +static xtensa_arg_internal Iclass_wur_phasor_offset_stateArgs[] = { + { { STATE_PHASOR_OFFSET }, 'o' }, + { { STATE_CPENABLE }, 'i' } +}; + +static xtensa_iclass_internal iclasses[] = { + { 0, 0 /* xt_iclass_excw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_rfe */, + 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfde */, + 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_syscall */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_simcall */, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call12_args, + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call8_args, + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_call4_args, + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx12_args, + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx8_args, + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_callx4_args, + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_entry_args, + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movsp_args, + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rotw_args, + 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_retw_args, + 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfwou */, + 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l32e_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32e_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowbase_args, + 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowbase_args, + 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowbase_args, + 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_windowstart_args, + 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_windowstart_args, + 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_windowstart_args, + 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_add_n_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addi_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bz6_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill_n */, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_loadi4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_mov_n_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_movi_n_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nopn */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_retn_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_storei4_args, + 0, 0, 0, 0 }, + { 1, Iclass_rur_threadptr_args, + 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, + { 1, Iclass_wur_threadptr_args, + 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_addi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addmi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_addsub_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bit_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8b_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bsi8u_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bst8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bsz12_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_call0_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_callx0_args, + 0, 0, 0, 0 }, + { 4, Iclass_xt_iclass_exti_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_ill */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jump_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_jumpx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16ui_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l16si_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_l32r_args, + 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_l8i_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_loop_args, + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_loopz_args, + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_movi_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_movz_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_neg_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_nop */, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_return_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s16i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32i_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s8i_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_sar_args, + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_sari_args, + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shifts_args, + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_shiftst_args, + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_shiftt_args, + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_slli_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_srli_args, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_memw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_extw */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_isync */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_sync */, + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rsil_args, + 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lend_args, + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lend_args, + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lend_args, + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lcount_args, + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lcount_args, + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lcount_args, + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_lbeg_args, + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_lbeg_args, + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_lbeg_args, + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_sar_args, + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_sar_args, + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_sar_args, + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_litbase_args, + 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_litbase_args, + 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_litbase_args, + 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_176_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_176_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_208_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ps_args, + 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ps_args, + 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ps_args, + 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc1_args, + 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc1_args, + 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc1_args, + 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave1_args, + 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave1_args, + 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave1_args, + 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc2_args, + 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc2_args, + 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc2_args, + 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave2_args, + 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave2_args, + 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave2_args, + 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc3_args, + 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc3_args, + 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc3_args, + 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave3_args, + 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave3_args, + 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave3_args, + 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc4_args, + 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc4_args, + 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc4_args, + 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave4_args, + 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave4_args, + 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave4_args, + 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc5_args, + 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc5_args, + 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc5_args, + 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave5_args, + 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave5_args, + 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave5_args, + 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_epc6_args, + 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_epc6_args, + 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_epc6_args, + 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excsave6_args, + 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excsave6_args, + 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excsave6_args, + 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps2_args, + 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps2_args, + 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps2_args, + 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps3_args, + 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps3_args, + 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps3_args, + 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps4_args, + 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps4_args, + 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps4_args, + 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps5_args, + 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps5_args, + 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps5_args, + 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_eps6_args, + 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_eps6_args, + 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_eps6_args, + 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_excvaddr_args, + 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_excvaddr_args, + 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_excvaddr_args, + 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_depc_args, + 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_depc_args, + 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_depc_args, + 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_exccause_args, + 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_exccause_args, + 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_exccause_args, + 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_prid_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_vecbase_args, + 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_vecbase_args, + 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_vecbase_args, + 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, + { 3, Iclass_xt_mul16_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rfi_args, + 18, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wait_args, + 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_interrupt_args, + 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intset_args, + 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intclear_args, + 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_intenable_args, + 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_intenable_args, + 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_intenable_args, + 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_break_args, + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_break_n_args, + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka0_args, + 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka0_args, + 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka0_args, + 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc0_args, + 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc0_args, + 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc0_args, + 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreaka1_args, + 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreaka1_args, + 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreaka1_args, + 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dbreakc1_args, + 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dbreakc1_args, + 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dbreakc1_args, + 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka0_args, + 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka0_args, + 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka0_args, + 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreaka1_args, + 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreaka1_args, + 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreaka1_args, + 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ibreakenable_args, + 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ibreakenable_args, + 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ibreakenable_args, + 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_debugcause_args, + 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_debugcause_args, + 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_debugcause_args, + 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icount_args, + 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icount_args, + 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icount_args, + 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_icountlevel_args, + 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_icountlevel_args, + 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_icountlevel_args, + 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ddr_args, + 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ddr_args, + 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ddr_args, + 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rfdo_args, + 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rfdd */, + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_mmid_args, + 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_bbool1_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool4_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbool8_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_bbranch_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_bmove_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_RSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_WSR_BR_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_XSR_BR_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccount_args, + 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccount_args, + 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccount_args, + 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare0_args, + 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare0_args, + 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare0_args, + 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ccompare1_args, + 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ccompare1_args, + 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ccompare1_args, + 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_icache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_lock_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_icache_inv_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_licx_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_sicx_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_ind_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_inv_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dpf_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_dcache_lock_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_sdct_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_ldct_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_idtlb_args, + 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + { 2, Iclass_xt_iclass_rdtlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_wdtlb_args, + 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_iitlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_ritlb_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_witlb_args, + 0, 0, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_cpenable_args, + 1, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_cpenable_args, + 1, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_cpenable_args, + 1, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, + { 3, Iclass_xt_iclass_clamp_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_minmax_args, + 0, 0, 0, 0 }, + { 2, Iclass_xt_iclass_nsa_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_sx_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_l32ai_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32ri_args, + 0, 0, 0, 0 }, + { 3, Iclass_xt_iclass_s32c1i_args, + 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_scompare1_args, + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_scompare1_args, + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_scompare1_args, + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_atomctl_args, + 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_atomctl_args, + 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_atomctl_args, + 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_rer */, + 0, 0, 0, 0 }, + { 0, 0 /* xt_iclass_wer */, + 0, 0, 0, 0 }, + { 1, Iclass_rur_fcr_args, + 9, Iclass_rur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fcr_args, + 9, Iclass_wur_fcr_stateArgs, 0, 0 }, + { 1, Iclass_rur_fsr_args, + 8, Iclass_rur_fsr_stateArgs, 0, 0 }, + { 1, Iclass_wur_fsr_args, + 8, Iclass_wur_fsr_stateArgs, 0, 0 }, + { 3, Iclass_fp_args, + 2, Iclass_fp_stateArgs, 0, 0 }, + { 3, Iclass_fp_mac_args, + 2, Iclass_fp_mac_stateArgs, 0, 0 }, + { 3, Iclass_fp_cmov_args, + 1, Iclass_fp_cmov_stateArgs, 0, 0 }, + { 3, Iclass_fp_mov_args, + 1, Iclass_fp_mov_stateArgs, 0, 0 }, + { 2, Iclass_fp_mov2_args, + 1, Iclass_fp_mov2_stateArgs, 0, 0 }, + { 3, Iclass_fp_cmp_args, + 1, Iclass_fp_cmp_stateArgs, 0, 0 }, + { 3, Iclass_fp_float_args, + 2, Iclass_fp_float_stateArgs, 0, 0 }, + { 3, Iclass_fp_int_args, + 1, Iclass_fp_int_stateArgs, 0, 0 }, + { 2, Iclass_fp_rfr_args, + 1, Iclass_fp_rfr_stateArgs, 0, 0 }, + { 2, Iclass_fp_wfr_args, + 1, Iclass_fp_wfr_stateArgs, 0, 0 }, + { 3, Iclass_fp_lsi_args, + 1, Iclass_fp_lsi_stateArgs, 0, 0 }, + { 3, Iclass_fp_lsiu_args, + 1, Iclass_fp_lsiu_stateArgs, 0, 0 }, + { 3, Iclass_fp_lsx_args, + 1, Iclass_fp_lsx_stateArgs, 0, 0 }, + { 3, Iclass_fp_lsxu_args, + 1, Iclass_fp_lsxu_stateArgs, 0, 0 }, + { 3, Iclass_fp_ssi_args, + 1, Iclass_fp_ssi_stateArgs, 0, 0 }, + { 3, Iclass_fp_ssiu_args, + 1, Iclass_fp_ssiu_stateArgs, 0, 0 }, + { 3, Iclass_fp_ssx_args, + 1, Iclass_fp_ssx_stateArgs, 0, 0 }, + { 3, Iclass_fp_ssxu_args, + 1, Iclass_fp_ssxu_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_ARGMAX_args, + 2, Iclass_iclass_GET_ARGMAX_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_HSAR_args, + 5, Iclass_iclass_GET_HSAR_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_HSAR2SAR_args, + 9, Iclass_iclass_GET_HSAR2SAR_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_INTERP_EXT_N_args, + 2, Iclass_iclass_GET_INTERP_EXT_N_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_INTERP_EXT_L_args, + 2, Iclass_iclass_GET_INTERP_EXT_L_stateArgs, 0, 0 }, + { 2, Iclass_iclass_GET_LLR_BUF_args, + 2, Iclass_iclass_GET_LLR_BUF_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_LLR_POS_args, + 2, Iclass_iclass_GET_LLR_POS_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_MAX_args, + 2, Iclass_iclass_GET_MAX_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_NCO_args, + 2, Iclass_iclass_GET_NCO_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_PERM_REG_args, + 2, Iclass_iclass_GET_PERM_REG_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_PHASOR_N_args, + 2, Iclass_iclass_GET_PHASOR_N_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_PHASOR_OFFSET_args, + 2, Iclass_iclass_GET_PHASOR_OFFSET_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_SAR_args, + 5, Iclass_iclass_GET_SAR_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_SCALE_REG_args, + 2, Iclass_iclass_GET_SCALE_REG_stateArgs, 0, 0 }, + { 2, Iclass_iclass_GET_SMOD_BUF_args, + 2, Iclass_iclass_GET_SMOD_BUF_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_SMOD_OFFSET_TABLE_args, + 2, Iclass_iclass_GET_SMOD_OFFSET_TABLE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_SMOD_POS_args, + 2, Iclass_iclass_GET_SMOD_POS_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_SOV_args, + 2, Iclass_iclass_GET_SOV_stateArgs, 0, 0 }, + { 1, Iclass_iclass_GET_WGHT_args, + 2, Iclass_iclass_GET_WGHT_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_ARGMAX_args, + 2, Iclass_iclass_SET_ARGMAX_stateArgs, 0, 0 }, + { 2, Iclass_iclass_SET_EXT_REGS_args, + 3, Iclass_iclass_SET_EXT_REGS_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_HSAR_args, + 5, Iclass_iclass_SET_HSAR_stateArgs, 0, 0 }, + { 2, Iclass_iclass_SET_LLR_BUF_args, + 2, Iclass_iclass_SET_LLR_BUF_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_LLR_POS_args, + 2, Iclass_iclass_SET_LLR_POS_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_MAX_args, + 2, Iclass_iclass_SET_MAX_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_NCO_args, + 2, Iclass_iclass_SET_NCO_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_PERM_REG_args, + 2, Iclass_iclass_SET_PERM_REG_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_PHASOR_N_args, + 2, Iclass_iclass_SET_PHASOR_N_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_PHASOR_OFFSET_args, + 2, Iclass_iclass_SET_PHASOR_OFFSET_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_SAR_args, + 5, Iclass_iclass_SET_SAR_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_SCALE_REG_args, + 2, Iclass_iclass_SET_SCALE_REG_stateArgs, 0, 0 }, + { 2, Iclass_iclass_SET_SMOD_BUF_args, + 2, Iclass_iclass_SET_SMOD_BUF_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_SMOD_OFFSET_TABLE_args, + 2, Iclass_iclass_SET_SMOD_OFFSET_TABLE_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_SMOD_POS_args, + 2, Iclass_iclass_SET_SMOD_POS_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_SOV_args, + 2, Iclass_iclass_SET_SOV_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SET_WGHT_args, + 2, Iclass_iclass_SET_WGHT_stateArgs, 0, 0 }, + { 4, Iclass_iclass_LAC2X32_args, + 1, Iclass_iclass_LAC2X32_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LAC2X64_0_args, + 1, Iclass_iclass_LAC2X64_0_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LAC2X64_1_args, + 1, Iclass_iclass_LAC2X64_1_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LAC2X64_2_args, + 1, Iclass_iclass_LAC2X64_2_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LAC2X64_3_args, + 1, Iclass_iclass_LAC2X64_3_stateArgs, 0, 0 }, + { 4, Iclass_iclass_LAC32_R_args, + 1, Iclass_iclass_LAC32_R_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LAC_IH_args, + 1, Iclass_iclass_LAC_IH_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LAC_IL_args, + 1, Iclass_iclass_LAC_IL_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LAC_RH_args, + 1, Iclass_iclass_LAC_RH_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LAC_RL_args, + 1, Iclass_iclass_LAC_RL_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LCM_args, + 1, Iclass_iclass_LCM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LCM_PINC_args, + 1, Iclass_iclass_LCM_PINC_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LCM_PINC_X_args, + 1, Iclass_iclass_LCM_PINC_X_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LCM_U_args, + 1, Iclass_iclass_LCM_U_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LCM_X_args, + 1, Iclass_iclass_LCM_X_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LCM_XU_args, + 1, Iclass_iclass_LCM_XU_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LP_args, + 1, Iclass_iclass_LP_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LP_X_args, + 1, Iclass_iclass_LP_X_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LQ_args, + 1, Iclass_iclass_LQ_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LQ_X_args, + 1, Iclass_iclass_LQ_X_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LUT0_args, + 1, Iclass_iclass_LUT0_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LUT1_args, + 1, Iclass_iclass_LUT1_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LUT2_args, + 1, Iclass_iclass_LUT2_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LUT3_args, + 1, Iclass_iclass_LUT3_stateArgs, 0, 0 }, + { 4, Iclass_iclass_SAC2X32_args, + 1, Iclass_iclass_SAC2X32_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SAC2X64_0_args, + 1, Iclass_iclass_SAC2X64_0_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SAC2X64_1_args, + 1, Iclass_iclass_SAC2X64_1_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SAC2X64_2_args, + 1, Iclass_iclass_SAC2X64_2_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SAC2X64_3_args, + 1, Iclass_iclass_SAC2X64_3_stateArgs, 0, 0 }, + { 4, Iclass_iclass_SAC32_R_args, + 1, Iclass_iclass_SAC32_R_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SAC_IH_args, + 1, Iclass_iclass_SAC_IH_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SAC_IL_args, + 1, Iclass_iclass_SAC_IL_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SAC_RH_args, + 1, Iclass_iclass_SAC_RH_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SAC_RL_args, + 1, Iclass_iclass_SAC_RL_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SCM_args, + 1, Iclass_iclass_SCM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SCM_PINC_args, + 1, Iclass_iclass_SCM_PINC_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SCM_PINC_X_args, + 1, Iclass_iclass_SCM_PINC_X_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SCM_U_args, + 1, Iclass_iclass_SCM_U_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SCM_X_args, + 1, Iclass_iclass_SCM_X_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SCM_XU_args, + 1, Iclass_iclass_SCM_XU_stateArgs, 0, 0 }, + { 3, Iclass_iclass_STORE_P_args, + 1, Iclass_iclass_STORE_P_stateArgs, 0, 0 }, + { 3, Iclass_iclass_STORE_Q_args, + 1, Iclass_iclass_STORE_Q_stateArgs, 0, 0 }, + { 2, Iclass_iclass_AR2CM_DUP_args, + 1, Iclass_iclass_AR2CM_DUP_stateArgs, 0, 0 }, + { 3, Iclass_iclass_AR2CM_LN_args, + 1, Iclass_iclass_AR2CM_LN_stateArgs, 0, 0 }, + { 3, Iclass_iclass_AR2CM_LN_I_args, + 1, Iclass_iclass_AR2CM_LN_I_stateArgs, 0, 0 }, + { 3, Iclass_iclass_AR2CM_LN_R_args, + 1, Iclass_iclass_AR2CM_LN_R_stateArgs, 0, 0 }, + { 4, Iclass_iclass_AR2PQ_LN_args, + 1, Iclass_iclass_AR2PQ_LN_stateArgs, 0, 0 }, + { 1, Iclass_iclass_AR2SAR_DUP_args, + 5, Iclass_iclass_AR2SAR_DUP_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRAC_args, + 1, Iclass_iclass_CLRAC_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRCM_args, + 1, Iclass_iclass_CLRCM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_CM2AR_LN_args, + 1, Iclass_iclass_CM2AR_LN_stateArgs, 0, 0 }, + { 3, Iclass_iclass_CM2AR_LN_I_args, + 1, Iclass_iclass_CM2AR_LN_I_stateArgs, 0, 0 }, + { 3, Iclass_iclass_CM2AR_LN_R_args, + 1, Iclass_iclass_CM2AR_LN_R_stateArgs, 0, 0 }, + { 3, Iclass_iclass_COMB_AR_args, + 0, 0, 0, 0 }, + { 2, Iclass_iclass_CONJ_args, + 1, Iclass_iclass_CONJ_stateArgs, 0, 0 }, + { 2, Iclass_iclass_MOV2AC32_I_args, + 1, Iclass_iclass_MOV2AC32_I_stateArgs, 0, 0 }, + { 2, Iclass_iclass_MOV2AC32_R_args, + 1, Iclass_iclass_MOV2AC32_R_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOV2CM2PQ_args, + 1, Iclass_iclass_MOV2CM2PQ_stateArgs, 0, 0 }, + { 2, Iclass_iclass_MOVAC_args, + 1, Iclass_iclass_MOVAC_stateArgs, 0, 0 }, + { 2, Iclass_iclass_MOVAC_I_args, + 1, Iclass_iclass_MOVAC_I_stateArgs, 0, 0 }, + { 2, Iclass_iclass_MOVAC_I2R_args, + 1, Iclass_iclass_MOVAC_I2R_stateArgs, 0, 0 }, + { 2, Iclass_iclass_MOVAC_R_args, + 1, Iclass_iclass_MOVAC_R_stateArgs, 0, 0 }, + { 2, Iclass_iclass_MOVAC_R2I_args, + 1, Iclass_iclass_MOVAC_R2I_stateArgs, 0, 0 }, + { 2, Iclass_iclass_MOVAR2_args, + 0, 0, 0, 0 }, + { 2, Iclass_iclass_MOVCM_args, + 1, Iclass_iclass_MOVCM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCM2PQ_args, + 1, Iclass_iclass_MOVCM2PQ_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND_0_args, + 1, Iclass_iclass_MOVCND_0_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND_1_args, + 1, Iclass_iclass_MOVCND_1_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND_2_args, + 1, Iclass_iclass_MOVCND_2_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND_3_args, + 1, Iclass_iclass_MOVCND_3_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND_4_args, + 1, Iclass_iclass_MOVCND_4_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND_5_args, + 1, Iclass_iclass_MOVCND_5_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND_6_args, + 1, Iclass_iclass_MOVCND_6_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND_7_args, + 1, Iclass_iclass_MOVCND_7_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND8_0_args, + 1, Iclass_iclass_MOVCND8_0_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND8_1_args, + 1, Iclass_iclass_MOVCND8_1_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND8_2_args, + 1, Iclass_iclass_MOVCND8_2_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND8_3_args, + 1, Iclass_iclass_MOVCND8_3_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND8_4_args, + 1, Iclass_iclass_MOVCND8_4_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND8_5_args, + 1, Iclass_iclass_MOVCND8_5_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND8_6_args, + 1, Iclass_iclass_MOVCND8_6_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOVCND8_7_args, + 1, Iclass_iclass_MOVCND8_7_stateArgs, 0, 0 }, + { 2, Iclass_iclass_MOV_I_args, + 1, Iclass_iclass_MOV_I_stateArgs, 0, 0 }, + { 2, Iclass_iclass_MOVPQ2PQ_args, + 1, Iclass_iclass_MOVPQ2PQ_stateArgs, 0, 0 }, + { 2, Iclass_iclass_MOV_R_args, + 1, Iclass_iclass_MOV_R_stateArgs, 0, 0 }, + { 2, Iclass_iclass_NEGCM_args, + 1, Iclass_iclass_NEGCM_stateArgs, 0, 0 }, + { 1, Iclass_iclass_POP16LLR_1_args, + 3, Iclass_iclass_POP16LLR_1_stateArgs, 0, 0 }, + { 3, Iclass_iclass_PQ2CM_args, + 1, Iclass_iclass_PQ2CM_stateArgs, 0, 0 }, + { 2, Iclass_iclass_SWAPAC_R_args, + 1, Iclass_iclass_SWAPAC_R_stateArgs, 0, 0 }, + { 2, Iclass_iclass_SWAPAC_RI_args, + 1, Iclass_iclass_SWAPAC_RI_stateArgs, 0, 0 }, + { 2, Iclass_iclass_SWAPB_args, + 0, 0, 0, 0 }, + { 3, Iclass_iclass_ADD2AC_args, + 6, Iclass_iclass_ADD2AC_stateArgs, 0, 0 }, + { 3, Iclass_iclass_ADDAC_args, + 3, Iclass_iclass_ADDAC_stateArgs, 0, 0 }, + { 4, Iclass_iclass_CDOT_args, + 2, Iclass_iclass_CDOT_stateArgs, 0, 0 }, + { 4, Iclass_iclass_CDOTAC_args, + 3, Iclass_iclass_CDOTAC_stateArgs, 0, 0 }, + { 4, Iclass_iclass_CDOTACS_args, + 3, Iclass_iclass_CDOTACS_stateArgs, 0, 0 }, + { 3, Iclass_iclass_CMAC_args, + 3, Iclass_iclass_CMAC_stateArgs, 0, 0 }, + { 3, Iclass_iclass_CMACS_args, + 3, Iclass_iclass_CMACS_stateArgs, 0, 0 }, + { 3, Iclass_iclass_CMPY_args, + 2, Iclass_iclass_CMPY_stateArgs, 0, 0 }, + { 3, Iclass_iclass_CMPY2CM_args, + 3, Iclass_iclass_CMPY2CM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_CMPY2PQ_args, + 3, Iclass_iclass_CMPY2PQ_stateArgs, 0, 0 }, + { 3, Iclass_iclass_CMPYS_args, + 2, Iclass_iclass_CMPYS_stateArgs, 0, 0 }, + { 3, Iclass_iclass_CMPYXP2PQ_args, + 3, Iclass_iclass_CMPYXP2PQ_stateArgs, 0, 0 }, + { 5, Iclass_iclass_COMB32_args, + 3, Iclass_iclass_COMB32_stateArgs, 0, 0 }, + { 4, Iclass_iclass_DOT_args, + 2, Iclass_iclass_DOT_stateArgs, 0, 0 }, + { 4, Iclass_iclass_DOTAC_args, + 3, Iclass_iclass_DOTAC_stateArgs, 0, 0 }, + { 4, Iclass_iclass_DOTACS_args, + 3, Iclass_iclass_DOTACS_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LIN_INT_args, + 6, Iclass_iclass_LIN_INT_stateArgs, 0, 0 }, + { 6, Iclass_iclass_LLRPRE1_args, + 2, Iclass_iclass_LLRPRE1_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LLRPRE2_args, + 3, Iclass_iclass_LLRPRE2_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MAC_args, + 3, Iclass_iclass_MAC_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MAC8_args, + 3, Iclass_iclass_MAC8_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MACD8_args, + 3, Iclass_iclass_MACD8_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MACPQXP_0_args, + 3, Iclass_iclass_MACPQXP_0_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MACPQXP_1_args, + 3, Iclass_iclass_MACPQXP_1_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MACPQXP_2_args, + 3, Iclass_iclass_MACPQXP_2_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MACPQXP_3_args, + 3, Iclass_iclass_MACPQXP_3_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MACS_args, + 3, Iclass_iclass_MACS_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MACXP2_0_args, + 3, Iclass_iclass_MACXP2_0_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MACXP2_1_args, + 3, Iclass_iclass_MACXP2_1_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MACXP_0_args, + 3, Iclass_iclass_MACXP_0_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MACXP_1_args, + 3, Iclass_iclass_MACXP_1_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MACXP_2_args, + 3, Iclass_iclass_MACXP_2_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MACXP_3_args, + 3, Iclass_iclass_MACXP_3_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MOV2AC_args, + 6, Iclass_iclass_MOV2AC_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MPY_args, + 2, Iclass_iclass_MPY_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MPY2CM_args, + 3, Iclass_iclass_MPY2CM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MPY2PQ_args, + 3, Iclass_iclass_MPY2PQ_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MPY8_args, + 2, Iclass_iclass_MPY8_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MPYADD8_2CM_args, + 3, Iclass_iclass_MPYADD8_2CM_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MPYD8_args, + 2, Iclass_iclass_MPYD8_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MPYPQXP_0_args, + 2, Iclass_iclass_MPYPQXP_0_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MPYPQXP_1_args, + 2, Iclass_iclass_MPYPQXP_1_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MPYPQXP_2_args, + 2, Iclass_iclass_MPYPQXP_2_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MPYPQXP_3_args, + 2, Iclass_iclass_MPYPQXP_3_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MPYS_args, + 2, Iclass_iclass_MPYS_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MPYXP2PQ_args, + 3, Iclass_iclass_MPYXP2PQ_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MPYXP2_0_args, + 2, Iclass_iclass_MPYXP2_0_stateArgs, 0, 0 }, + { 4, Iclass_iclass_MPYXP2_1_args, + 2, Iclass_iclass_MPYXP2_1_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MPYXP_0_args, + 2, Iclass_iclass_MPYXP_0_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MPYXP_1_args, + 2, Iclass_iclass_MPYXP_1_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MPYXP_2_args, + 2, Iclass_iclass_MPYXP_2_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MPYXP_3_args, + 2, Iclass_iclass_MPYXP_3_stateArgs, 0, 0 }, + { 3, Iclass_iclass_NORMACD_args, + 3, Iclass_iclass_NORMACD_stateArgs, 0, 0 }, + { 2, Iclass_iclass_NORMACPQ_I_args, + 3, Iclass_iclass_NORMACPQ_I_stateArgs, 0, 0 }, + { 2, Iclass_iclass_NORMACPQ_R_args, + 3, Iclass_iclass_NORMACPQ_R_stateArgs, 0, 0 }, + { 3, Iclass_iclass_NORMD_args, + 2, Iclass_iclass_NORMD_stateArgs, 0, 0 }, + { 2, Iclass_iclass_NORMPYPQ_I_args, + 2, Iclass_iclass_NORMPYPQ_I_stateArgs, 0, 0 }, + { 2, Iclass_iclass_NORMPYPQ_R_args, + 2, Iclass_iclass_NORMPYPQ_R_stateArgs, 0, 0 }, + { 3, Iclass_iclass_RCMAC_args, + 3, Iclass_iclass_RCMAC_stateArgs, 0, 0 }, + { 3, Iclass_iclass_RCMPY_args, + 2, Iclass_iclass_RCMPY_stateArgs, 0, 0 }, + { 3, Iclass_iclass_RCMPY2CM_args, + 1, Iclass_iclass_RCMPY2CM_stateArgs, 0, 0 }, + { 6, Iclass_iclass_RFIR_args, + 3, Iclass_iclass_RFIR_stateArgs, 0, 0 }, + { 6, Iclass_iclass_RFIRA_args, + 3, Iclass_iclass_RFIRA_stateArgs, 0, 0 }, + { 5, Iclass_iclass_RFIRD_args, + 3, Iclass_iclass_RFIRD_stateArgs, 0, 0 }, + { 5, Iclass_iclass_RFIRDA_args, + 3, Iclass_iclass_RFIRDA_stateArgs, 0, 0 }, + { 3, Iclass_iclass_RMAC_args, + 3, Iclass_iclass_RMAC_stateArgs, 0, 0 }, + { 3, Iclass_iclass_RMPY_args, + 2, Iclass_iclass_RMPY_stateArgs, 0, 0 }, + { 3, Iclass_iclass_RMPY2CM_args, + 1, Iclass_iclass_RMPY2CM_stateArgs, 0, 0 }, + { 4, Iclass_iclass_SMOD_ALIGN_args, + 3, Iclass_iclass_SMOD_ALIGN_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SMOD_SCR_args, + 2, Iclass_iclass_SMOD_SCR_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SUB2AC_args, + 6, Iclass_iclass_SUB2AC_stateArgs, 0, 0 }, + { 3, Iclass_iclass_WGHT32_args, + 3, Iclass_iclass_WGHT32_stateArgs, 0, 0 }, + { 1, Iclass_iclass_CLRTIEP_args, + 1, Iclass_iclass_CLRTIEP_stateArgs, 0, 0 }, + { 3, Iclass_iclass_EXT_2FIFO_0_args, + 1, Iclass_iclass_EXT_2FIFO_0_stateArgs, 1, Iclass_iclass_EXT_2FIFO_0_intfArgs }, + { 3, Iclass_iclass_EXT_2FIFO_1_args, + 1, Iclass_iclass_EXT_2FIFO_1_stateArgs, 1, Iclass_iclass_EXT_2FIFO_1_intfArgs }, + { 3, Iclass_iclass_EXT_2FIFO_2_args, + 1, Iclass_iclass_EXT_2FIFO_2_stateArgs, 1, Iclass_iclass_EXT_2FIFO_2_intfArgs }, + { 3, Iclass_iclass_EXT_2FIFO_3_args, + 1, Iclass_iclass_EXT_2FIFO_3_stateArgs, 1, Iclass_iclass_EXT_2FIFO_3_intfArgs }, + { 3, Iclass_iclass_EXT_R2FIFO_0_args, + 1, Iclass_iclass_EXT_R2FIFO_0_stateArgs, 1, Iclass_iclass_EXT_R2FIFO_0_intfArgs }, + { 3, Iclass_iclass_EXT_R2FIFO_1_args, + 1, Iclass_iclass_EXT_R2FIFO_1_stateArgs, 1, Iclass_iclass_EXT_R2FIFO_1_intfArgs }, + { 3, Iclass_iclass_EXT_R2FIFO_2_args, + 1, Iclass_iclass_EXT_R2FIFO_2_stateArgs, 1, Iclass_iclass_EXT_R2FIFO_2_intfArgs }, + { 3, Iclass_iclass_EXT_R2FIFO_3_args, + 1, Iclass_iclass_EXT_R2FIFO_3_stateArgs, 1, Iclass_iclass_EXT_R2FIFO_3_intfArgs }, + { 3, Iclass_iclass_LUT_args, + 1, Iclass_iclass_LUT_stateArgs, 2, Iclass_iclass_LUT_intfArgs }, + { 3, Iclass_iclass_LUT_AR_args, + 1, Iclass_iclass_LUT_AR_stateArgs, 2, Iclass_iclass_LUT_AR_intfArgs }, + { 3, Iclass_iclass_LUT_IEXT_args, + 3, Iclass_iclass_LUT_IEXT_stateArgs, 2, Iclass_iclass_LUT_IEXT_intfArgs }, + { 2, Iclass_iclass_LUT_PHASOR_args, + 3, Iclass_iclass_LUT_PHASOR_stateArgs, 2, Iclass_iclass_LUT_PHASOR_intfArgs }, + { 3, Iclass_iclass_LUT_REXT_args, + 3, Iclass_iclass_LUT_REXT_stateArgs, 2, Iclass_iclass_LUT_REXT_intfArgs }, + { 3, Iclass_iclass_LUT_WRITE_args, + 1, Iclass_iclass_LUT_WRITE_stateArgs, 2, Iclass_iclass_LUT_WRITE_intfArgs }, + { 0, 0 /* iclass_MOVEQ128_0 */, + 0, 0, 2, Iclass_iclass_MOVEQ128_0_intfArgs }, + { 0, 0 /* iclass_MOVEQ128_1 */, + 0, 0, 2, Iclass_iclass_MOVEQ128_1_intfArgs }, + { 0, 0 /* iclass_MOVEQ128_2 */, + 0, 0, 2, Iclass_iclass_MOVEQ128_2_intfArgs }, + { 0, 0 /* iclass_MOVEQ128_3 */, + 0, 0, 2, Iclass_iclass_MOVEQ128_3_intfArgs }, + { 0, 0 /* iclass_MOVEQ128_4 */, + 0, 0, 2, Iclass_iclass_MOVEQ128_4_intfArgs }, + { 0, 0 /* iclass_MOVEQ128_5 */, + 0, 0, 2, Iclass_iclass_MOVEQ128_5_intfArgs }, + { 0, 0 /* iclass_MOVEQ32_0 */, + 0, 0, 2, Iclass_iclass_MOVEQ32_0_intfArgs }, + { 0, 0 /* iclass_MOVEQ32_1 */, + 0, 0, 2, Iclass_iclass_MOVEQ32_1_intfArgs }, + { 0, 0 /* iclass_MOVEQ32_2 */, + 0, 0, 2, Iclass_iclass_MOVEQ32_2_intfArgs }, + { 0, 0 /* iclass_MOVEQ32_3 */, + 0, 0, 2, Iclass_iclass_MOVEQ32_3_intfArgs }, + { 2, Iclass_iclass_NCO_UPDATE_args, + 4, Iclass_iclass_NCO_UPDATE_stateArgs, 2, Iclass_iclass_NCO_UPDATE_intfArgs }, + { 1, Iclass_iclass_POP128_0_args, + 1, Iclass_iclass_POP128_0_stateArgs, 1, Iclass_iclass_POP128_0_intfArgs }, + { 1, Iclass_iclass_POP128_1_args, + 1, Iclass_iclass_POP128_1_stateArgs, 1, Iclass_iclass_POP128_1_intfArgs }, + { 1, Iclass_iclass_POP128_2_args, + 1, Iclass_iclass_POP128_2_stateArgs, 1, Iclass_iclass_POP128_2_intfArgs }, + { 1, Iclass_iclass_POP128_3_args, + 1, Iclass_iclass_POP128_3_stateArgs, 1, Iclass_iclass_POP128_3_intfArgs }, + { 1, Iclass_iclass_POP128_4_args, + 1, Iclass_iclass_POP128_4_stateArgs, 1, Iclass_iclass_POP128_4_intfArgs }, + { 1, Iclass_iclass_POP128_5_args, + 1, Iclass_iclass_POP128_5_stateArgs, 1, Iclass_iclass_POP128_5_intfArgs }, + { 3, Iclass_iclass_POP128_2CMPQ_0_args, + 1, Iclass_iclass_POP128_2CMPQ_0_stateArgs, 1, Iclass_iclass_POP128_2CMPQ_0_intfArgs }, + { 3, Iclass_iclass_POP128_2CMPQ_1_args, + 1, Iclass_iclass_POP128_2CMPQ_1_stateArgs, 1, Iclass_iclass_POP128_2CMPQ_1_intfArgs }, + { 3, Iclass_iclass_POP128_2CMPQ_2_args, + 1, Iclass_iclass_POP128_2CMPQ_2_stateArgs, 1, Iclass_iclass_POP128_2CMPQ_2_intfArgs }, + { 3, Iclass_iclass_POP128_2CMPQ_3_args, + 1, Iclass_iclass_POP128_2CMPQ_3_stateArgs, 1, Iclass_iclass_POP128_2CMPQ_3_intfArgs }, + { 2, Iclass_iclass_POP128_2M_0_args, + 0, 0, 1, Iclass_iclass_POP128_2M_0_intfArgs }, + { 2, Iclass_iclass_POP128_2M_1_args, + 0, 0, 1, Iclass_iclass_POP128_2M_1_intfArgs }, + { 2, Iclass_iclass_POP128_2M_2_args, + 0, 0, 1, Iclass_iclass_POP128_2M_2_intfArgs }, + { 2, Iclass_iclass_POP128_2M_3_args, + 0, 0, 1, Iclass_iclass_POP128_2M_3_intfArgs }, + { 2, Iclass_iclass_POP128_2PQ_0_args, + 1, Iclass_iclass_POP128_2PQ_0_stateArgs, 1, Iclass_iclass_POP128_2PQ_0_intfArgs }, + { 2, Iclass_iclass_POP128_2PQ_1_args, + 1, Iclass_iclass_POP128_2PQ_1_stateArgs, 1, Iclass_iclass_POP128_2PQ_1_intfArgs }, + { 2, Iclass_iclass_POP128_2PQ_2_args, + 1, Iclass_iclass_POP128_2PQ_2_stateArgs, 1, Iclass_iclass_POP128_2PQ_2_intfArgs }, + { 2, Iclass_iclass_POP128_2PQ_3_args, + 1, Iclass_iclass_POP128_2PQ_3_stateArgs, 1, Iclass_iclass_POP128_2PQ_3_intfArgs }, + { 2, Iclass_iclass_POP128_2PQ_4_args, + 1, Iclass_iclass_POP128_2PQ_4_stateArgs, 1, Iclass_iclass_POP128_2PQ_4_intfArgs }, + { 2, Iclass_iclass_POP128_2PQ_5_args, + 1, Iclass_iclass_POP128_2PQ_5_stateArgs, 1, Iclass_iclass_POP128_2PQ_5_intfArgs }, + { 1, Iclass_iclass_POP2X128_2PQ_01_args, + 1, Iclass_iclass_POP2X128_2PQ_01_stateArgs, 2, Iclass_iclass_POP2X128_2PQ_01_intfArgs }, + { 1, Iclass_iclass_POP2X128_2PQ_03_args, + 1, Iclass_iclass_POP2X128_2PQ_03_stateArgs, 2, Iclass_iclass_POP2X128_2PQ_03_intfArgs }, + { 1, Iclass_iclass_POP2X128_2PQ_21_args, + 1, Iclass_iclass_POP2X128_2PQ_21_stateArgs, 2, Iclass_iclass_POP2X128_2PQ_21_intfArgs }, + { 1, Iclass_iclass_POP2X128_2PQ_23_args, + 1, Iclass_iclass_POP2X128_2PQ_23_stateArgs, 2, Iclass_iclass_POP2X128_2PQ_23_intfArgs }, + { 1, Iclass_iclass_POP32_0_args, + 0, 0, 1, Iclass_iclass_POP32_0_intfArgs }, + { 1, Iclass_iclass_POP32_1_args, + 0, 0, 1, Iclass_iclass_POP32_1_intfArgs }, + { 1, Iclass_iclass_POP32_2_args, + 0, 0, 1, Iclass_iclass_POP32_2_intfArgs }, + { 1, Iclass_iclass_POP32_3_args, + 0, 0, 1, Iclass_iclass_POP32_3_intfArgs }, + { 2, Iclass_iclass_PUSH128_args, + 1, Iclass_iclass_PUSH128_stateArgs, 12, Iclass_iclass_PUSH128_intfArgs }, + { 3, Iclass_iclass_PUSH128_M_args, + 0, 0, 8, Iclass_iclass_PUSH128_M_intfArgs }, + { 3, Iclass_iclass_PUSH128_PQ_args, + 1, Iclass_iclass_PUSH128_PQ_stateArgs, 12, Iclass_iclass_PUSH128_PQ_intfArgs }, + { 3, Iclass_iclass_PUSH2X128_PQ_args, + 1, Iclass_iclass_PUSH2X128_PQ_stateArgs, 8, Iclass_iclass_PUSH2X128_PQ_intfArgs }, + { 2, Iclass_iclass_PUSH32_args, + 0, 0, 12, Iclass_iclass_PUSH32_intfArgs }, + { 2, Iclass_iclass_QREADY_args, + 0, 0, 23, Iclass_iclass_QREADY_intfArgs }, + { 1, Iclass_iclass_RDTIEP_args, + 0, 0, 1, Iclass_iclass_RDTIEP_intfArgs }, + { 1, Iclass_iclass_SETTIEP_args, + 1, Iclass_iclass_SETTIEP_stateArgs, 0, 0 }, + { 5, Iclass_iclass_SMOD_LUT_args, + 2, Iclass_iclass_SMOD_LUT_stateArgs, 2, Iclass_iclass_SMOD_LUT_intfArgs }, + { 1, Iclass_iclass_WRTBSIGQ_args, + 0, 0, 1, Iclass_iclass_WRTBSIGQ_intfArgs }, + { 1, Iclass_iclass_WRTBSIGQM_args, + 0, 0, 1, Iclass_iclass_WRTBSIGQM_intfArgs }, + { 2, Iclass_iclass_WRTIEP_args, + 1, Iclass_iclass_WRTIEP_stateArgs, 0, 0 }, + { 1, Iclass_iclass_WRTSIGQ_args, + 0, 0, 1, Iclass_iclass_WRTSIGQ_intfArgs }, + { 2, Iclass_iclass_ABS8_args, + 1, Iclass_iclass_ABS8_stateArgs, 0, 0 }, + { 4, Iclass_iclass_ADD16_args, + 3, Iclass_iclass_ADD16_stateArgs, 0, 0 }, + { 3, Iclass_iclass_ADD32_args, + 3, Iclass_iclass_ADD32_stateArgs, 0, 0 }, + { 1, Iclass_iclass_ADDAC_I2R_args, + 3, Iclass_iclass_ADDAC_I2R_stateArgs, 0, 0 }, + { 1, Iclass_iclass_ADDAC_R2I_args, + 3, Iclass_iclass_ADDAC_R2I_stateArgs, 0, 0 }, + { 2, Iclass_iclass_ADDAR2_args, + 0, 0, 0, 0 }, + { 3, Iclass_iclass_ADDCM_args, + 3, Iclass_iclass_ADDCM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_ADDWRP_args, + 1, Iclass_iclass_ADDWRP_stateArgs, 0, 0 }, + { 3, Iclass_iclass_AND128_args, + 1, Iclass_iclass_AND128_stateArgs, 0, 0 }, + { 2, Iclass_iclass_ARGMAX8_args, + 3, Iclass_iclass_ARGMAX8_stateArgs, 0, 0 }, + { 3, Iclass_iclass_ASL_args, + 3, Iclass_iclass_ASL_stateArgs, 0, 0 }, + { 3, Iclass_iclass_ASL32_args, + 3, Iclass_iclass_ASL32_stateArgs, 0, 0 }, + { 2, Iclass_iclass_ASLACM_args, + 3, Iclass_iclass_ASLACM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_ASLM_args, + 3, Iclass_iclass_ASLM_stateArgs, 0, 0 }, + { 2, Iclass_iclass_ASLM32_args, + 3, Iclass_iclass_ASLM32_stateArgs, 0, 0 }, + { 3, Iclass_iclass_ASR_args, + 3, Iclass_iclass_ASR_stateArgs, 0, 0 }, + { 3, Iclass_iclass_ASR32_args, + 3, Iclass_iclass_ASR32_stateArgs, 0, 0 }, + { 2, Iclass_iclass_ASRAC_args, + 3, Iclass_iclass_ASRAC_stateArgs, 0, 0 }, + { 3, Iclass_iclass_ASRM_args, + 3, Iclass_iclass_ASRM_stateArgs, 0, 0 }, + { 4, Iclass_iclass_BITFEXT_args, + 0, 0, 0, 0 }, + { 4, Iclass_iclass_BITFINS_args, + 0, 0, 0, 0 }, + { 2, Iclass_iclass_CLB_C_args, + 5, Iclass_iclass_CLB_C_stateArgs, 0, 0 }, + { 2, Iclass_iclass_CLB_R_args, + 5, Iclass_iclass_CLB_R_stateArgs, 0, 0 }, + { 3, Iclass_iclass_CMP8_args, + 2, Iclass_iclass_CMP8_stateArgs, 0, 0 }, + { 3, Iclass_iclass_CMP_I_args, + 2, Iclass_iclass_CMP_I_stateArgs, 0, 0 }, + { 3, Iclass_iclass_CMP_R_args, + 2, Iclass_iclass_CMP_R_stateArgs, 0, 0 }, + { 5, Iclass_iclass_EXT_args, + 6, Iclass_iclass_EXT_stateArgs, 0, 0 }, + { 5, Iclass_iclass_EXT_R_args, + 6, Iclass_iclass_EXT_R_stateArgs, 0, 0 }, + { 3, Iclass_iclass_EXT32_I_args, + 2, Iclass_iclass_EXT32_I_stateArgs, 0, 0 }, + { 3, Iclass_iclass_EXT32_R_args, + 2, Iclass_iclass_EXT32_R_stateArgs, 0, 0 }, + { 3, Iclass_iclass_EXTUI4_args, + 1, Iclass_iclass_EXTUI4_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LSLM_args, + 1, Iclass_iclass_LSLM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_LSRM_args, + 1, Iclass_iclass_LSRM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MAX8_args, + 1, Iclass_iclass_MAX8_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MEAN_args, + 1, Iclass_iclass_MEAN_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MEAN32_args, + 1, Iclass_iclass_MEAN32_stateArgs, 0, 0 }, + { 3, Iclass_iclass_MIN8_args, + 1, Iclass_iclass_MIN8_stateArgs, 0, 0 }, + { 2, Iclass_iclass_MINCLB_C_args, + 5, Iclass_iclass_MINCLB_C_stateArgs, 0, 0 }, + { 2, Iclass_iclass_MINCLB_R_args, + 5, Iclass_iclass_MINCLB_R_stateArgs, 0, 0 }, + { 2, Iclass_iclass_NOT128_args, + 1, Iclass_iclass_NOT128_stateArgs, 0, 0 }, + { 3, Iclass_iclass_OR128_args, + 1, Iclass_iclass_OR128_stateArgs, 0, 0 }, + { 3, Iclass_iclass_PERM_args, + 1, Iclass_iclass_PERM_stateArgs, 0, 0 }, + { 1, Iclass_iclass_REDAC_args, + 3, Iclass_iclass_REDAC_stateArgs, 0, 0 }, + { 1, Iclass_iclass_REDAC2_args, + 3, Iclass_iclass_REDAC2_stateArgs, 0, 0 }, + { 1, Iclass_iclass_REDAC4_args, + 3, Iclass_iclass_REDAC4_stateArgs, 0, 0 }, + { 1, Iclass_iclass_REDACS_args, + 3, Iclass_iclass_REDACS_stateArgs, 0, 0 }, + { 2, Iclass_iclass_SMINCLB_C_args, + 5, Iclass_iclass_SMINCLB_C_stateArgs, 0, 0 }, + { 2, Iclass_iclass_SMINCLB_R_args, + 5, Iclass_iclass_SMINCLB_R_stateArgs, 0, 0 }, + { 3, Iclass_iclass_STSWAPBM_args, + 0, 0, 0, 0 }, + { 3, Iclass_iclass_STSWAPBMU_args, + 0, 0, 0, 0 }, + { 3, Iclass_iclass_SUB32_args, + 3, Iclass_iclass_SUB32_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SUBAC_I2R_args, + 3, Iclass_iclass_SUBAC_I2R_stateArgs, 0, 0 }, + { 1, Iclass_iclass_SUBAC_R2I_args, + 3, Iclass_iclass_SUBAC_R2I_stateArgs, 0, 0 }, + { 2, Iclass_iclass_SUBARX_args, + 0, 0, 0, 0 }, + { 3, Iclass_iclass_SUBCM_args, + 3, Iclass_iclass_SUBCM_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SUBMEAN_args, + 1, Iclass_iclass_SUBMEAN_stateArgs, 0, 0 }, + { 3, Iclass_iclass_SUBWRP_args, + 1, Iclass_iclass_SUBWRP_stateArgs, 0, 0 }, + { 2, Iclass_iclass_TRANS_args, + 1, Iclass_iclass_TRANS_stateArgs, 0, 0 }, + { 3, Iclass_iclass_XOR128_args, + 1, Iclass_iclass_XOR128_stateArgs, 0, 0 }, + { 1, Iclass_rur_expstate_args, + 1, Iclass_rur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_wur_expstate_args, + 1, Iclass_wur_expstate_stateArgs, 0, 0 }, + { 1, Iclass_rur_sov_args, + 2, Iclass_rur_sov_stateArgs, 0, 0 }, + { 1, Iclass_wur_sov_args, + 2, Iclass_wur_sov_stateArgs, 0, 0 }, + { 1, Iclass_rur_sat_mode_args, + 2, Iclass_rur_sat_mode_stateArgs, 0, 0 }, + { 1, Iclass_wur_sat_mode_args, + 2, Iclass_wur_sat_mode_stateArgs, 0, 0 }, + { 1, Iclass_rur_sar0_args, + 2, Iclass_rur_sar0_stateArgs, 0, 0 }, + { 1, Iclass_wur_sar0_args, + 2, Iclass_wur_sar0_stateArgs, 0, 0 }, + { 1, Iclass_rur_sar1_args, + 2, Iclass_rur_sar1_stateArgs, 0, 0 }, + { 1, Iclass_wur_sar1_args, + 2, Iclass_wur_sar1_stateArgs, 0, 0 }, + { 1, Iclass_rur_sar2_args, + 2, Iclass_rur_sar2_stateArgs, 0, 0 }, + { 1, Iclass_wur_sar2_args, + 2, Iclass_wur_sar2_stateArgs, 0, 0 }, + { 1, Iclass_rur_sar3_args, + 2, Iclass_rur_sar3_stateArgs, 0, 0 }, + { 1, Iclass_wur_sar3_args, + 2, Iclass_wur_sar3_stateArgs, 0, 0 }, + { 1, Iclass_rur_hsar0_args, + 2, Iclass_rur_hsar0_stateArgs, 0, 0 }, + { 1, Iclass_wur_hsar0_args, + 2, Iclass_wur_hsar0_stateArgs, 0, 0 }, + { 1, Iclass_rur_hsar1_args, + 2, Iclass_rur_hsar1_stateArgs, 0, 0 }, + { 1, Iclass_wur_hsar1_args, + 2, Iclass_wur_hsar1_stateArgs, 0, 0 }, + { 1, Iclass_rur_hsar2_args, + 2, Iclass_rur_hsar2_stateArgs, 0, 0 }, + { 1, Iclass_wur_hsar2_args, + 2, Iclass_wur_hsar2_stateArgs, 0, 0 }, + { 1, Iclass_rur_hsar3_args, + 2, Iclass_rur_hsar3_stateArgs, 0, 0 }, + { 1, Iclass_wur_hsar3_args, + 2, Iclass_wur_hsar3_stateArgs, 0, 0 }, + { 1, Iclass_rur_max_reg_0_args, + 2, Iclass_rur_max_reg_0_stateArgs, 0, 0 }, + { 1, Iclass_wur_max_reg_0_args, + 2, Iclass_wur_max_reg_0_stateArgs, 0, 0 }, + { 1, Iclass_rur_max_reg_1_args, + 2, Iclass_rur_max_reg_1_stateArgs, 0, 0 }, + { 1, Iclass_wur_max_reg_1_args, + 2, Iclass_wur_max_reg_1_stateArgs, 0, 0 }, + { 1, Iclass_rur_max_reg_2_args, + 2, Iclass_rur_max_reg_2_stateArgs, 0, 0 }, + { 1, Iclass_wur_max_reg_2_args, + 2, Iclass_wur_max_reg_2_stateArgs, 0, 0 }, + { 1, Iclass_rur_max_reg_3_args, + 2, Iclass_rur_max_reg_3_stateArgs, 0, 0 }, + { 1, Iclass_wur_max_reg_3_args, + 2, Iclass_wur_max_reg_3_stateArgs, 0, 0 }, + { 1, Iclass_rur_arg_max_reg_0_args, + 2, Iclass_rur_arg_max_reg_0_stateArgs, 0, 0 }, + { 1, Iclass_wur_arg_max_reg_0_args, + 2, Iclass_wur_arg_max_reg_0_stateArgs, 0, 0 }, + { 1, Iclass_rur_arg_max_reg_1_args, + 2, Iclass_rur_arg_max_reg_1_stateArgs, 0, 0 }, + { 1, Iclass_wur_arg_max_reg_1_args, + 2, Iclass_wur_arg_max_reg_1_stateArgs, 0, 0 }, + { 1, Iclass_rur_arg_max_reg_2_args, + 2, Iclass_rur_arg_max_reg_2_stateArgs, 0, 0 }, + { 1, Iclass_wur_arg_max_reg_2_args, + 2, Iclass_wur_arg_max_reg_2_stateArgs, 0, 0 }, + { 1, Iclass_rur_arg_max_reg_3_args, + 2, Iclass_rur_arg_max_reg_3_stateArgs, 0, 0 }, + { 1, Iclass_wur_arg_max_reg_3_args, + 2, Iclass_wur_arg_max_reg_3_stateArgs, 0, 0 }, + { 1, Iclass_rur_nco_counter_0_args, + 2, Iclass_rur_nco_counter_0_stateArgs, 0, 0 }, + { 1, Iclass_wur_nco_counter_0_args, + 2, Iclass_wur_nco_counter_0_stateArgs, 0, 0 }, + { 1, Iclass_rur_nco_counter_1_args, + 2, Iclass_rur_nco_counter_1_stateArgs, 0, 0 }, + { 1, Iclass_wur_nco_counter_1_args, + 2, Iclass_wur_nco_counter_1_stateArgs, 0, 0 }, + { 1, Iclass_rur_nco_counter_2_args, + 2, Iclass_rur_nco_counter_2_stateArgs, 0, 0 }, + { 1, Iclass_wur_nco_counter_2_args, + 2, Iclass_wur_nco_counter_2_stateArgs, 0, 0 }, + { 1, Iclass_rur_nco_counter_3_args, + 2, Iclass_rur_nco_counter_3_stateArgs, 0, 0 }, + { 1, Iclass_wur_nco_counter_3_args, + 2, Iclass_wur_nco_counter_3_stateArgs, 0, 0 }, + { 1, Iclass_rur_interp_ext_n_args, + 2, Iclass_rur_interp_ext_n_stateArgs, 0, 0 }, + { 1, Iclass_wur_interp_ext_n_args, + 2, Iclass_wur_interp_ext_n_stateArgs, 0, 0 }, + { 1, Iclass_rur_interp_ext_l_args, + 2, Iclass_rur_interp_ext_l_stateArgs, 0, 0 }, + { 1, Iclass_wur_interp_ext_l_args, + 2, Iclass_wur_interp_ext_l_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_0_args, + 2, Iclass_rur_llr_buf_0_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_0_args, + 2, Iclass_wur_llr_buf_0_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_1_args, + 2, Iclass_rur_llr_buf_1_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_1_args, + 2, Iclass_wur_llr_buf_1_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_2_args, + 2, Iclass_rur_llr_buf_2_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_2_args, + 2, Iclass_wur_llr_buf_2_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_3_args, + 2, Iclass_rur_llr_buf_3_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_3_args, + 2, Iclass_wur_llr_buf_3_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_4_args, + 2, Iclass_rur_llr_buf_4_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_4_args, + 2, Iclass_wur_llr_buf_4_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_5_args, + 2, Iclass_rur_llr_buf_5_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_5_args, + 2, Iclass_wur_llr_buf_5_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_6_args, + 2, Iclass_rur_llr_buf_6_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_6_args, + 2, Iclass_wur_llr_buf_6_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_7_args, + 2, Iclass_rur_llr_buf_7_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_7_args, + 2, Iclass_wur_llr_buf_7_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_8_args, + 2, Iclass_rur_llr_buf_8_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_8_args, + 2, Iclass_wur_llr_buf_8_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_9_args, + 2, Iclass_rur_llr_buf_9_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_9_args, + 2, Iclass_wur_llr_buf_9_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_10_args, + 2, Iclass_rur_llr_buf_10_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_10_args, + 2, Iclass_wur_llr_buf_10_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_11_args, + 2, Iclass_rur_llr_buf_11_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_11_args, + 2, Iclass_wur_llr_buf_11_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_12_args, + 2, Iclass_rur_llr_buf_12_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_12_args, + 2, Iclass_wur_llr_buf_12_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_13_args, + 2, Iclass_rur_llr_buf_13_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_13_args, + 2, Iclass_wur_llr_buf_13_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_14_args, + 2, Iclass_rur_llr_buf_14_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_14_args, + 2, Iclass_wur_llr_buf_14_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_15_args, + 2, Iclass_rur_llr_buf_15_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_15_args, + 2, Iclass_wur_llr_buf_15_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_16_args, + 2, Iclass_rur_llr_buf_16_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_16_args, + 2, Iclass_wur_llr_buf_16_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_17_args, + 2, Iclass_rur_llr_buf_17_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_17_args, + 2, Iclass_wur_llr_buf_17_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_18_args, + 2, Iclass_rur_llr_buf_18_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_18_args, + 2, Iclass_wur_llr_buf_18_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_19_args, + 2, Iclass_rur_llr_buf_19_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_19_args, + 2, Iclass_wur_llr_buf_19_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_20_args, + 2, Iclass_rur_llr_buf_20_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_20_args, + 2, Iclass_wur_llr_buf_20_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_21_args, + 2, Iclass_rur_llr_buf_21_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_21_args, + 2, Iclass_wur_llr_buf_21_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_22_args, + 2, Iclass_rur_llr_buf_22_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_22_args, + 2, Iclass_wur_llr_buf_22_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_buf_23_args, + 2, Iclass_rur_llr_buf_23_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_buf_23_args, + 2, Iclass_wur_llr_buf_23_stateArgs, 0, 0 }, + { 1, Iclass_rur_smod_buf_0_args, + 2, Iclass_rur_smod_buf_0_stateArgs, 0, 0 }, + { 1, Iclass_wur_smod_buf_0_args, + 2, Iclass_wur_smod_buf_0_stateArgs, 0, 0 }, + { 1, Iclass_rur_smod_buf_1_args, + 2, Iclass_rur_smod_buf_1_stateArgs, 0, 0 }, + { 1, Iclass_wur_smod_buf_1_args, + 2, Iclass_wur_smod_buf_1_stateArgs, 0, 0 }, + { 1, Iclass_rur_smod_buf_2_args, + 2, Iclass_rur_smod_buf_2_stateArgs, 0, 0 }, + { 1, Iclass_wur_smod_buf_2_args, + 2, Iclass_wur_smod_buf_2_stateArgs, 0, 0 }, + { 1, Iclass_rur_smod_buf_3_args, + 2, Iclass_rur_smod_buf_3_stateArgs, 0, 0 }, + { 1, Iclass_wur_smod_buf_3_args, + 2, Iclass_wur_smod_buf_3_stateArgs, 0, 0 }, + { 1, Iclass_rur_smod_buf_4_args, + 2, Iclass_rur_smod_buf_4_stateArgs, 0, 0 }, + { 1, Iclass_wur_smod_buf_4_args, + 2, Iclass_wur_smod_buf_4_stateArgs, 0, 0 }, + { 1, Iclass_rur_smod_buf_5_args, + 2, Iclass_rur_smod_buf_5_stateArgs, 0, 0 }, + { 1, Iclass_wur_smod_buf_5_args, + 2, Iclass_wur_smod_buf_5_stateArgs, 0, 0 }, + { 1, Iclass_rur_smod_buf_6_args, + 2, Iclass_rur_smod_buf_6_stateArgs, 0, 0 }, + { 1, Iclass_wur_smod_buf_6_args, + 2, Iclass_wur_smod_buf_6_stateArgs, 0, 0 }, + { 1, Iclass_rur_smod_buf_7_args, + 2, Iclass_rur_smod_buf_7_stateArgs, 0, 0 }, + { 1, Iclass_wur_smod_buf_7_args, + 2, Iclass_wur_smod_buf_7_stateArgs, 0, 0 }, + { 1, Iclass_rur_weight_reg_args, + 2, Iclass_rur_weight_reg_stateArgs, 0, 0 }, + { 1, Iclass_wur_weight_reg_args, + 2, Iclass_wur_weight_reg_stateArgs, 0, 0 }, + { 1, Iclass_rur_scale_reg_args, + 2, Iclass_rur_scale_reg_stateArgs, 0, 0 }, + { 1, Iclass_wur_scale_reg_args, + 2, Iclass_wur_scale_reg_stateArgs, 0, 0 }, + { 1, Iclass_rur_llr_pos_args, + 2, Iclass_rur_llr_pos_stateArgs, 0, 0 }, + { 1, Iclass_wur_llr_pos_args, + 2, Iclass_wur_llr_pos_stateArgs, 0, 0 }, + { 1, Iclass_rur_smod_pos_args, + 2, Iclass_rur_smod_pos_stateArgs, 0, 0 }, + { 1, Iclass_wur_smod_pos_args, + 2, Iclass_wur_smod_pos_stateArgs, 0, 0 }, + { 1, Iclass_rur_perm_reg_args, + 2, Iclass_rur_perm_reg_stateArgs, 0, 0 }, + { 1, Iclass_wur_perm_reg_args, + 2, Iclass_wur_perm_reg_stateArgs, 0, 0 }, + { 1, Iclass_rur_smod_offset_table_0_args, + 2, Iclass_rur_smod_offset_table_0_stateArgs, 0, 0 }, + { 1, Iclass_wur_smod_offset_table_0_args, + 2, Iclass_wur_smod_offset_table_0_stateArgs, 0, 0 }, + { 1, Iclass_rur_smod_offset_table_1_args, + 2, Iclass_rur_smod_offset_table_1_stateArgs, 0, 0 }, + { 1, Iclass_wur_smod_offset_table_1_args, + 2, Iclass_wur_smod_offset_table_1_stateArgs, 0, 0 }, + { 1, Iclass_rur_smod_offset_table_2_args, + 2, Iclass_rur_smod_offset_table_2_stateArgs, 0, 0 }, + { 1, Iclass_wur_smod_offset_table_2_args, + 2, Iclass_wur_smod_offset_table_2_stateArgs, 0, 0 }, + { 1, Iclass_rur_smod_offset_table_3_args, + 2, Iclass_rur_smod_offset_table_3_stateArgs, 0, 0 }, + { 1, Iclass_wur_smod_offset_table_3_args, + 2, Iclass_wur_smod_offset_table_3_stateArgs, 0, 0 }, + { 1, Iclass_rur_phasor_n_args, + 2, Iclass_rur_phasor_n_stateArgs, 0, 0 }, + { 1, Iclass_wur_phasor_n_args, + 2, Iclass_wur_phasor_n_stateArgs, 0, 0 }, + { 1, Iclass_rur_phasor_offset_args, + 2, Iclass_rur_phasor_offset_stateArgs, 0, 0 }, + { 1, Iclass_wur_phasor_offset_args, + 2, Iclass_wur_phasor_offset_stateArgs, 0, 0 } +}; + +enum xtensa_iclass_id { + ICLASS_xt_iclass_excw, + ICLASS_xt_iclass_rfe, + ICLASS_xt_iclass_rfde, + ICLASS_xt_iclass_syscall, + ICLASS_xt_iclass_simcall, + ICLASS_xt_iclass_call12, + ICLASS_xt_iclass_call8, + ICLASS_xt_iclass_call4, + ICLASS_xt_iclass_callx12, + ICLASS_xt_iclass_callx8, + ICLASS_xt_iclass_callx4, + ICLASS_xt_iclass_entry, + ICLASS_xt_iclass_movsp, + ICLASS_xt_iclass_rotw, + ICLASS_xt_iclass_retw, + ICLASS_xt_iclass_rfwou, + ICLASS_xt_iclass_l32e, + ICLASS_xt_iclass_s32e, + ICLASS_xt_iclass_rsr_windowbase, + ICLASS_xt_iclass_wsr_windowbase, + ICLASS_xt_iclass_xsr_windowbase, + ICLASS_xt_iclass_rsr_windowstart, + ICLASS_xt_iclass_wsr_windowstart, + ICLASS_xt_iclass_xsr_windowstart, + ICLASS_xt_iclass_add_n, + ICLASS_xt_iclass_addi_n, + ICLASS_xt_iclass_bz6, + ICLASS_xt_iclass_ill_n, + ICLASS_xt_iclass_loadi4, + ICLASS_xt_iclass_mov_n, + ICLASS_xt_iclass_movi_n, + ICLASS_xt_iclass_nopn, + ICLASS_xt_iclass_retn, + ICLASS_xt_iclass_storei4, + ICLASS_rur_threadptr, + ICLASS_wur_threadptr, + ICLASS_xt_iclass_addi, + ICLASS_xt_iclass_addmi, + ICLASS_xt_iclass_addsub, + ICLASS_xt_iclass_bit, + ICLASS_xt_iclass_bsi8, + ICLASS_xt_iclass_bsi8b, + ICLASS_xt_iclass_bsi8u, + ICLASS_xt_iclass_bst8, + ICLASS_xt_iclass_bsz12, + ICLASS_xt_iclass_call0, + ICLASS_xt_iclass_callx0, + ICLASS_xt_iclass_exti, + ICLASS_xt_iclass_ill, + ICLASS_xt_iclass_jump, + ICLASS_xt_iclass_jumpx, + ICLASS_xt_iclass_l16ui, + ICLASS_xt_iclass_l16si, + ICLASS_xt_iclass_l32i, + ICLASS_xt_iclass_l32r, + ICLASS_xt_iclass_l8i, + ICLASS_xt_iclass_loop, + ICLASS_xt_iclass_loopz, + ICLASS_xt_iclass_movi, + ICLASS_xt_iclass_movz, + ICLASS_xt_iclass_neg, + ICLASS_xt_iclass_nop, + ICLASS_xt_iclass_return, + ICLASS_xt_iclass_s16i, + ICLASS_xt_iclass_s32i, + ICLASS_xt_iclass_s8i, + ICLASS_xt_iclass_sar, + ICLASS_xt_iclass_sari, + ICLASS_xt_iclass_shifts, + ICLASS_xt_iclass_shiftst, + ICLASS_xt_iclass_shiftt, + ICLASS_xt_iclass_slli, + ICLASS_xt_iclass_srai, + ICLASS_xt_iclass_srli, + ICLASS_xt_iclass_memw, + ICLASS_xt_iclass_extw, + ICLASS_xt_iclass_isync, + ICLASS_xt_iclass_sync, + ICLASS_xt_iclass_rsil, + ICLASS_xt_iclass_rsr_lend, + ICLASS_xt_iclass_wsr_lend, + ICLASS_xt_iclass_xsr_lend, + ICLASS_xt_iclass_rsr_lcount, + ICLASS_xt_iclass_wsr_lcount, + ICLASS_xt_iclass_xsr_lcount, + ICLASS_xt_iclass_rsr_lbeg, + ICLASS_xt_iclass_wsr_lbeg, + ICLASS_xt_iclass_xsr_lbeg, + ICLASS_xt_iclass_rsr_sar, + ICLASS_xt_iclass_wsr_sar, + ICLASS_xt_iclass_xsr_sar, + ICLASS_xt_iclass_rsr_litbase, + ICLASS_xt_iclass_wsr_litbase, + ICLASS_xt_iclass_xsr_litbase, + ICLASS_xt_iclass_rsr_176, + ICLASS_xt_iclass_wsr_176, + ICLASS_xt_iclass_rsr_208, + ICLASS_xt_iclass_rsr_ps, + ICLASS_xt_iclass_wsr_ps, + ICLASS_xt_iclass_xsr_ps, + ICLASS_xt_iclass_rsr_epc1, + ICLASS_xt_iclass_wsr_epc1, + ICLASS_xt_iclass_xsr_epc1, + ICLASS_xt_iclass_rsr_excsave1, + ICLASS_xt_iclass_wsr_excsave1, + ICLASS_xt_iclass_xsr_excsave1, + ICLASS_xt_iclass_rsr_epc2, + ICLASS_xt_iclass_wsr_epc2, + ICLASS_xt_iclass_xsr_epc2, + ICLASS_xt_iclass_rsr_excsave2, + ICLASS_xt_iclass_wsr_excsave2, + ICLASS_xt_iclass_xsr_excsave2, + ICLASS_xt_iclass_rsr_epc3, + ICLASS_xt_iclass_wsr_epc3, + ICLASS_xt_iclass_xsr_epc3, + ICLASS_xt_iclass_rsr_excsave3, + ICLASS_xt_iclass_wsr_excsave3, + ICLASS_xt_iclass_xsr_excsave3, + ICLASS_xt_iclass_rsr_epc4, + ICLASS_xt_iclass_wsr_epc4, + ICLASS_xt_iclass_xsr_epc4, + ICLASS_xt_iclass_rsr_excsave4, + ICLASS_xt_iclass_wsr_excsave4, + ICLASS_xt_iclass_xsr_excsave4, + ICLASS_xt_iclass_rsr_epc5, + ICLASS_xt_iclass_wsr_epc5, + ICLASS_xt_iclass_xsr_epc5, + ICLASS_xt_iclass_rsr_excsave5, + ICLASS_xt_iclass_wsr_excsave5, + ICLASS_xt_iclass_xsr_excsave5, + ICLASS_xt_iclass_rsr_epc6, + ICLASS_xt_iclass_wsr_epc6, + ICLASS_xt_iclass_xsr_epc6, + ICLASS_xt_iclass_rsr_excsave6, + ICLASS_xt_iclass_wsr_excsave6, + ICLASS_xt_iclass_xsr_excsave6, + ICLASS_xt_iclass_rsr_eps2, + ICLASS_xt_iclass_wsr_eps2, + ICLASS_xt_iclass_xsr_eps2, + ICLASS_xt_iclass_rsr_eps3, + ICLASS_xt_iclass_wsr_eps3, + ICLASS_xt_iclass_xsr_eps3, + ICLASS_xt_iclass_rsr_eps4, + ICLASS_xt_iclass_wsr_eps4, + ICLASS_xt_iclass_xsr_eps4, + ICLASS_xt_iclass_rsr_eps5, + ICLASS_xt_iclass_wsr_eps5, + ICLASS_xt_iclass_xsr_eps5, + ICLASS_xt_iclass_rsr_eps6, + ICLASS_xt_iclass_wsr_eps6, + ICLASS_xt_iclass_xsr_eps6, + ICLASS_xt_iclass_rsr_excvaddr, + ICLASS_xt_iclass_wsr_excvaddr, + ICLASS_xt_iclass_xsr_excvaddr, + ICLASS_xt_iclass_rsr_depc, + ICLASS_xt_iclass_wsr_depc, + ICLASS_xt_iclass_xsr_depc, + ICLASS_xt_iclass_rsr_exccause, + ICLASS_xt_iclass_wsr_exccause, + ICLASS_xt_iclass_xsr_exccause, + ICLASS_xt_iclass_rsr_prid, + ICLASS_xt_iclass_rsr_vecbase, + ICLASS_xt_iclass_wsr_vecbase, + ICLASS_xt_iclass_xsr_vecbase, + ICLASS_xt_mul16, + ICLASS_xt_iclass_rfi, + ICLASS_xt_iclass_wait, + ICLASS_xt_iclass_rsr_interrupt, + ICLASS_xt_iclass_wsr_intset, + ICLASS_xt_iclass_wsr_intclear, + ICLASS_xt_iclass_rsr_intenable, + ICLASS_xt_iclass_wsr_intenable, + ICLASS_xt_iclass_xsr_intenable, + ICLASS_xt_iclass_break, + ICLASS_xt_iclass_break_n, + ICLASS_xt_iclass_rsr_dbreaka0, + ICLASS_xt_iclass_wsr_dbreaka0, + ICLASS_xt_iclass_xsr_dbreaka0, + ICLASS_xt_iclass_rsr_dbreakc0, + ICLASS_xt_iclass_wsr_dbreakc0, + ICLASS_xt_iclass_xsr_dbreakc0, + ICLASS_xt_iclass_rsr_dbreaka1, + ICLASS_xt_iclass_wsr_dbreaka1, + ICLASS_xt_iclass_xsr_dbreaka1, + ICLASS_xt_iclass_rsr_dbreakc1, + ICLASS_xt_iclass_wsr_dbreakc1, + ICLASS_xt_iclass_xsr_dbreakc1, + ICLASS_xt_iclass_rsr_ibreaka0, + ICLASS_xt_iclass_wsr_ibreaka0, + ICLASS_xt_iclass_xsr_ibreaka0, + ICLASS_xt_iclass_rsr_ibreaka1, + ICLASS_xt_iclass_wsr_ibreaka1, + ICLASS_xt_iclass_xsr_ibreaka1, + ICLASS_xt_iclass_rsr_ibreakenable, + ICLASS_xt_iclass_wsr_ibreakenable, + ICLASS_xt_iclass_xsr_ibreakenable, + ICLASS_xt_iclass_rsr_debugcause, + ICLASS_xt_iclass_wsr_debugcause, + ICLASS_xt_iclass_xsr_debugcause, + ICLASS_xt_iclass_rsr_icount, + ICLASS_xt_iclass_wsr_icount, + ICLASS_xt_iclass_xsr_icount, + ICLASS_xt_iclass_rsr_icountlevel, + ICLASS_xt_iclass_wsr_icountlevel, + ICLASS_xt_iclass_xsr_icountlevel, + ICLASS_xt_iclass_rsr_ddr, + ICLASS_xt_iclass_wsr_ddr, + ICLASS_xt_iclass_xsr_ddr, + ICLASS_xt_iclass_rfdo, + ICLASS_xt_iclass_rfdd, + ICLASS_xt_iclass_wsr_mmid, + ICLASS_xt_iclass_bbool1, + ICLASS_xt_iclass_bbool4, + ICLASS_xt_iclass_bbool8, + ICLASS_xt_iclass_bbranch, + ICLASS_xt_iclass_bmove, + ICLASS_xt_iclass_RSR_BR, + ICLASS_xt_iclass_WSR_BR, + ICLASS_xt_iclass_XSR_BR, + ICLASS_xt_iclass_rsr_ccount, + ICLASS_xt_iclass_wsr_ccount, + ICLASS_xt_iclass_xsr_ccount, + ICLASS_xt_iclass_rsr_ccompare0, + ICLASS_xt_iclass_wsr_ccompare0, + ICLASS_xt_iclass_xsr_ccompare0, + ICLASS_xt_iclass_rsr_ccompare1, + ICLASS_xt_iclass_wsr_ccompare1, + ICLASS_xt_iclass_xsr_ccompare1, + ICLASS_xt_iclass_icache, + ICLASS_xt_iclass_icache_lock, + ICLASS_xt_iclass_icache_inv, + ICLASS_xt_iclass_licx, + ICLASS_xt_iclass_sicx, + ICLASS_xt_iclass_dcache, + ICLASS_xt_iclass_dcache_ind, + ICLASS_xt_iclass_dcache_inv, + ICLASS_xt_iclass_dpf, + ICLASS_xt_iclass_dcache_lock, + ICLASS_xt_iclass_sdct, + ICLASS_xt_iclass_ldct, + ICLASS_xt_iclass_idtlb, + ICLASS_xt_iclass_rdtlb, + ICLASS_xt_iclass_wdtlb, + ICLASS_xt_iclass_iitlb, + ICLASS_xt_iclass_ritlb, + ICLASS_xt_iclass_witlb, + ICLASS_xt_iclass_rsr_cpenable, + ICLASS_xt_iclass_wsr_cpenable, + ICLASS_xt_iclass_xsr_cpenable, + ICLASS_xt_iclass_clamp, + ICLASS_xt_iclass_minmax, + ICLASS_xt_iclass_nsa, + ICLASS_xt_iclass_sx, + ICLASS_xt_iclass_l32ai, + ICLASS_xt_iclass_s32ri, + ICLASS_xt_iclass_s32c1i, + ICLASS_xt_iclass_rsr_scompare1, + ICLASS_xt_iclass_wsr_scompare1, + ICLASS_xt_iclass_xsr_scompare1, + ICLASS_xt_iclass_rsr_atomctl, + ICLASS_xt_iclass_wsr_atomctl, + ICLASS_xt_iclass_xsr_atomctl, + ICLASS_xt_iclass_rer, + ICLASS_xt_iclass_wer, + ICLASS_rur_fcr, + ICLASS_wur_fcr, + ICLASS_rur_fsr, + ICLASS_wur_fsr, + ICLASS_fp, + ICLASS_fp_mac, + ICLASS_fp_cmov, + ICLASS_fp_mov, + ICLASS_fp_mov2, + ICLASS_fp_cmp, + ICLASS_fp_float, + ICLASS_fp_int, + ICLASS_fp_rfr, + ICLASS_fp_wfr, + ICLASS_fp_lsi, + ICLASS_fp_lsiu, + ICLASS_fp_lsx, + ICLASS_fp_lsxu, + ICLASS_fp_ssi, + ICLASS_fp_ssiu, + ICLASS_fp_ssx, + ICLASS_fp_ssxu, + ICLASS_iclass_GET_ARGMAX, + ICLASS_iclass_GET_HSAR, + ICLASS_iclass_GET_HSAR2SAR, + ICLASS_iclass_GET_INTERP_EXT_N, + ICLASS_iclass_GET_INTERP_EXT_L, + ICLASS_iclass_GET_LLR_BUF, + ICLASS_iclass_GET_LLR_POS, + ICLASS_iclass_GET_MAX, + ICLASS_iclass_GET_NCO, + ICLASS_iclass_GET_PERM_REG, + ICLASS_iclass_GET_PHASOR_N, + ICLASS_iclass_GET_PHASOR_OFFSET, + ICLASS_iclass_GET_SAR, + ICLASS_iclass_GET_SCALE_REG, + ICLASS_iclass_GET_SMOD_BUF, + ICLASS_iclass_GET_SMOD_OFFSET_TABLE, + ICLASS_iclass_GET_SMOD_POS, + ICLASS_iclass_GET_SOV, + ICLASS_iclass_GET_WGHT, + ICLASS_iclass_SET_ARGMAX, + ICLASS_iclass_SET_EXT_REGS, + ICLASS_iclass_SET_HSAR, + ICLASS_iclass_SET_LLR_BUF, + ICLASS_iclass_SET_LLR_POS, + ICLASS_iclass_SET_MAX, + ICLASS_iclass_SET_NCO, + ICLASS_iclass_SET_PERM_REG, + ICLASS_iclass_SET_PHASOR_N, + ICLASS_iclass_SET_PHASOR_OFFSET, + ICLASS_iclass_SET_SAR, + ICLASS_iclass_SET_SCALE_REG, + ICLASS_iclass_SET_SMOD_BUF, + ICLASS_iclass_SET_SMOD_OFFSET_TABLE, + ICLASS_iclass_SET_SMOD_POS, + ICLASS_iclass_SET_SOV, + ICLASS_iclass_SET_WGHT, + ICLASS_iclass_LAC2X32, + ICLASS_iclass_LAC2X64_0, + ICLASS_iclass_LAC2X64_1, + ICLASS_iclass_LAC2X64_2, + ICLASS_iclass_LAC2X64_3, + ICLASS_iclass_LAC32_R, + ICLASS_iclass_LAC_IH, + ICLASS_iclass_LAC_IL, + ICLASS_iclass_LAC_RH, + ICLASS_iclass_LAC_RL, + ICLASS_iclass_LCM, + ICLASS_iclass_LCM_PINC, + ICLASS_iclass_LCM_PINC_X, + ICLASS_iclass_LCM_U, + ICLASS_iclass_LCM_X, + ICLASS_iclass_LCM_XU, + ICLASS_iclass_LP, + ICLASS_iclass_LP_X, + ICLASS_iclass_LQ, + ICLASS_iclass_LQ_X, + ICLASS_iclass_LUT0, + ICLASS_iclass_LUT1, + ICLASS_iclass_LUT2, + ICLASS_iclass_LUT3, + ICLASS_iclass_SAC2X32, + ICLASS_iclass_SAC2X64_0, + ICLASS_iclass_SAC2X64_1, + ICLASS_iclass_SAC2X64_2, + ICLASS_iclass_SAC2X64_3, + ICLASS_iclass_SAC32_R, + ICLASS_iclass_SAC_IH, + ICLASS_iclass_SAC_IL, + ICLASS_iclass_SAC_RH, + ICLASS_iclass_SAC_RL, + ICLASS_iclass_SCM, + ICLASS_iclass_SCM_PINC, + ICLASS_iclass_SCM_PINC_X, + ICLASS_iclass_SCM_U, + ICLASS_iclass_SCM_X, + ICLASS_iclass_SCM_XU, + ICLASS_iclass_STORE_P, + ICLASS_iclass_STORE_Q, + ICLASS_iclass_AR2CM_DUP, + ICLASS_iclass_AR2CM_LN, + ICLASS_iclass_AR2CM_LN_I, + ICLASS_iclass_AR2CM_LN_R, + ICLASS_iclass_AR2PQ_LN, + ICLASS_iclass_AR2SAR_DUP, + ICLASS_iclass_CLRAC, + ICLASS_iclass_CLRCM, + ICLASS_iclass_CM2AR_LN, + ICLASS_iclass_CM2AR_LN_I, + ICLASS_iclass_CM2AR_LN_R, + ICLASS_iclass_COMB_AR, + ICLASS_iclass_CONJ, + ICLASS_iclass_MOV2AC32_I, + ICLASS_iclass_MOV2AC32_R, + ICLASS_iclass_MOV2CM2PQ, + ICLASS_iclass_MOVAC, + ICLASS_iclass_MOVAC_I, + ICLASS_iclass_MOVAC_I2R, + ICLASS_iclass_MOVAC_R, + ICLASS_iclass_MOVAC_R2I, + ICLASS_iclass_MOVAR2, + ICLASS_iclass_MOVCM, + ICLASS_iclass_MOVCM2PQ, + ICLASS_iclass_MOVCND_0, + ICLASS_iclass_MOVCND_1, + ICLASS_iclass_MOVCND_2, + ICLASS_iclass_MOVCND_3, + ICLASS_iclass_MOVCND_4, + ICLASS_iclass_MOVCND_5, + ICLASS_iclass_MOVCND_6, + ICLASS_iclass_MOVCND_7, + ICLASS_iclass_MOVCND8_0, + ICLASS_iclass_MOVCND8_1, + ICLASS_iclass_MOVCND8_2, + ICLASS_iclass_MOVCND8_3, + ICLASS_iclass_MOVCND8_4, + ICLASS_iclass_MOVCND8_5, + ICLASS_iclass_MOVCND8_6, + ICLASS_iclass_MOVCND8_7, + ICLASS_iclass_MOV_I, + ICLASS_iclass_MOVPQ2PQ, + ICLASS_iclass_MOV_R, + ICLASS_iclass_NEGCM, + ICLASS_iclass_POP16LLR_1, + ICLASS_iclass_PQ2CM, + ICLASS_iclass_SWAPAC_R, + ICLASS_iclass_SWAPAC_RI, + ICLASS_iclass_SWAPB, + ICLASS_iclass_ADD2AC, + ICLASS_iclass_ADDAC, + ICLASS_iclass_CDOT, + ICLASS_iclass_CDOTAC, + ICLASS_iclass_CDOTACS, + ICLASS_iclass_CMAC, + ICLASS_iclass_CMACS, + ICLASS_iclass_CMPY, + ICLASS_iclass_CMPY2CM, + ICLASS_iclass_CMPY2PQ, + ICLASS_iclass_CMPYS, + ICLASS_iclass_CMPYXP2PQ, + ICLASS_iclass_COMB32, + ICLASS_iclass_DOT, + ICLASS_iclass_DOTAC, + ICLASS_iclass_DOTACS, + ICLASS_iclass_LIN_INT, + ICLASS_iclass_LLRPRE1, + ICLASS_iclass_LLRPRE2, + ICLASS_iclass_MAC, + ICLASS_iclass_MAC8, + ICLASS_iclass_MACD8, + ICLASS_iclass_MACPQXP_0, + ICLASS_iclass_MACPQXP_1, + ICLASS_iclass_MACPQXP_2, + ICLASS_iclass_MACPQXP_3, + ICLASS_iclass_MACS, + ICLASS_iclass_MACXP2_0, + ICLASS_iclass_MACXP2_1, + ICLASS_iclass_MACXP_0, + ICLASS_iclass_MACXP_1, + ICLASS_iclass_MACXP_2, + ICLASS_iclass_MACXP_3, + ICLASS_iclass_MOV2AC, + ICLASS_iclass_MPY, + ICLASS_iclass_MPY2CM, + ICLASS_iclass_MPY2PQ, + ICLASS_iclass_MPY8, + ICLASS_iclass_MPYADD8_2CM, + ICLASS_iclass_MPYD8, + ICLASS_iclass_MPYPQXP_0, + ICLASS_iclass_MPYPQXP_1, + ICLASS_iclass_MPYPQXP_2, + ICLASS_iclass_MPYPQXP_3, + ICLASS_iclass_MPYS, + ICLASS_iclass_MPYXP2PQ, + ICLASS_iclass_MPYXP2_0, + ICLASS_iclass_MPYXP2_1, + ICLASS_iclass_MPYXP_0, + ICLASS_iclass_MPYXP_1, + ICLASS_iclass_MPYXP_2, + ICLASS_iclass_MPYXP_3, + ICLASS_iclass_NORMACD, + ICLASS_iclass_NORMACPQ_I, + ICLASS_iclass_NORMACPQ_R, + ICLASS_iclass_NORMD, + ICLASS_iclass_NORMPYPQ_I, + ICLASS_iclass_NORMPYPQ_R, + ICLASS_iclass_RCMAC, + ICLASS_iclass_RCMPY, + ICLASS_iclass_RCMPY2CM, + ICLASS_iclass_RFIR, + ICLASS_iclass_RFIRA, + ICLASS_iclass_RFIRD, + ICLASS_iclass_RFIRDA, + ICLASS_iclass_RMAC, + ICLASS_iclass_RMPY, + ICLASS_iclass_RMPY2CM, + ICLASS_iclass_SMOD_ALIGN, + ICLASS_iclass_SMOD_SCR, + ICLASS_iclass_SUB2AC, + ICLASS_iclass_WGHT32, + ICLASS_iclass_CLRTIEP, + ICLASS_iclass_EXT_2FIFO_0, + ICLASS_iclass_EXT_2FIFO_1, + ICLASS_iclass_EXT_2FIFO_2, + ICLASS_iclass_EXT_2FIFO_3, + ICLASS_iclass_EXT_R2FIFO_0, + ICLASS_iclass_EXT_R2FIFO_1, + ICLASS_iclass_EXT_R2FIFO_2, + ICLASS_iclass_EXT_R2FIFO_3, + ICLASS_iclass_LUT, + ICLASS_iclass_LUT_AR, + ICLASS_iclass_LUT_IEXT, + ICLASS_iclass_LUT_PHASOR, + ICLASS_iclass_LUT_REXT, + ICLASS_iclass_LUT_WRITE, + ICLASS_iclass_MOVEQ128_0, + ICLASS_iclass_MOVEQ128_1, + ICLASS_iclass_MOVEQ128_2, + ICLASS_iclass_MOVEQ128_3, + ICLASS_iclass_MOVEQ128_4, + ICLASS_iclass_MOVEQ128_5, + ICLASS_iclass_MOVEQ32_0, + ICLASS_iclass_MOVEQ32_1, + ICLASS_iclass_MOVEQ32_2, + ICLASS_iclass_MOVEQ32_3, + ICLASS_iclass_NCO_UPDATE, + ICLASS_iclass_POP128_0, + ICLASS_iclass_POP128_1, + ICLASS_iclass_POP128_2, + ICLASS_iclass_POP128_3, + ICLASS_iclass_POP128_4, + ICLASS_iclass_POP128_5, + ICLASS_iclass_POP128_2CMPQ_0, + ICLASS_iclass_POP128_2CMPQ_1, + ICLASS_iclass_POP128_2CMPQ_2, + ICLASS_iclass_POP128_2CMPQ_3, + ICLASS_iclass_POP128_2M_0, + ICLASS_iclass_POP128_2M_1, + ICLASS_iclass_POP128_2M_2, + ICLASS_iclass_POP128_2M_3, + ICLASS_iclass_POP128_2PQ_0, + ICLASS_iclass_POP128_2PQ_1, + ICLASS_iclass_POP128_2PQ_2, + ICLASS_iclass_POP128_2PQ_3, + ICLASS_iclass_POP128_2PQ_4, + ICLASS_iclass_POP128_2PQ_5, + ICLASS_iclass_POP2X128_2PQ_01, + ICLASS_iclass_POP2X128_2PQ_03, + ICLASS_iclass_POP2X128_2PQ_21, + ICLASS_iclass_POP2X128_2PQ_23, + ICLASS_iclass_POP32_0, + ICLASS_iclass_POP32_1, + ICLASS_iclass_POP32_2, + ICLASS_iclass_POP32_3, + ICLASS_iclass_PUSH128, + ICLASS_iclass_PUSH128_M, + ICLASS_iclass_PUSH128_PQ, + ICLASS_iclass_PUSH2X128_PQ, + ICLASS_iclass_PUSH32, + ICLASS_iclass_QREADY, + ICLASS_iclass_RDTIEP, + ICLASS_iclass_SETTIEP, + ICLASS_iclass_SMOD_LUT, + ICLASS_iclass_WRTBSIGQ, + ICLASS_iclass_WRTBSIGQM, + ICLASS_iclass_WRTIEP, + ICLASS_iclass_WRTSIGQ, + ICLASS_iclass_ABS8, + ICLASS_iclass_ADD16, + ICLASS_iclass_ADD32, + ICLASS_iclass_ADDAC_I2R, + ICLASS_iclass_ADDAC_R2I, + ICLASS_iclass_ADDAR2, + ICLASS_iclass_ADDCM, + ICLASS_iclass_ADDWRP, + ICLASS_iclass_AND128, + ICLASS_iclass_ARGMAX8, + ICLASS_iclass_ASL, + ICLASS_iclass_ASL32, + ICLASS_iclass_ASLACM, + ICLASS_iclass_ASLM, + ICLASS_iclass_ASLM32, + ICLASS_iclass_ASR, + ICLASS_iclass_ASR32, + ICLASS_iclass_ASRAC, + ICLASS_iclass_ASRM, + ICLASS_iclass_BITFEXT, + ICLASS_iclass_BITFINS, + ICLASS_iclass_CLB_C, + ICLASS_iclass_CLB_R, + ICLASS_iclass_CMP8, + ICLASS_iclass_CMP_I, + ICLASS_iclass_CMP_R, + ICLASS_iclass_EXT, + ICLASS_iclass_EXT_R, + ICLASS_iclass_EXT32_I, + ICLASS_iclass_EXT32_R, + ICLASS_iclass_EXTUI4, + ICLASS_iclass_LSLM, + ICLASS_iclass_LSRM, + ICLASS_iclass_MAX8, + ICLASS_iclass_MEAN, + ICLASS_iclass_MEAN32, + ICLASS_iclass_MIN8, + ICLASS_iclass_MINCLB_C, + ICLASS_iclass_MINCLB_R, + ICLASS_iclass_NOT128, + ICLASS_iclass_OR128, + ICLASS_iclass_PERM, + ICLASS_iclass_REDAC, + ICLASS_iclass_REDAC2, + ICLASS_iclass_REDAC4, + ICLASS_iclass_REDACS, + ICLASS_iclass_SMINCLB_C, + ICLASS_iclass_SMINCLB_R, + ICLASS_iclass_STSWAPBM, + ICLASS_iclass_STSWAPBMU, + ICLASS_iclass_SUB32, + ICLASS_iclass_SUBAC_I2R, + ICLASS_iclass_SUBAC_R2I, + ICLASS_iclass_SUBARX, + ICLASS_iclass_SUBCM, + ICLASS_iclass_SUBMEAN, + ICLASS_iclass_SUBWRP, + ICLASS_iclass_TRANS, + ICLASS_iclass_XOR128, + ICLASS_rur_expstate, + ICLASS_wur_expstate, + ICLASS_rur_sov, + ICLASS_wur_sov, + ICLASS_rur_sat_mode, + ICLASS_wur_sat_mode, + ICLASS_rur_sar0, + ICLASS_wur_sar0, + ICLASS_rur_sar1, + ICLASS_wur_sar1, + ICLASS_rur_sar2, + ICLASS_wur_sar2, + ICLASS_rur_sar3, + ICLASS_wur_sar3, + ICLASS_rur_hsar0, + ICLASS_wur_hsar0, + ICLASS_rur_hsar1, + ICLASS_wur_hsar1, + ICLASS_rur_hsar2, + ICLASS_wur_hsar2, + ICLASS_rur_hsar3, + ICLASS_wur_hsar3, + ICLASS_rur_max_reg_0, + ICLASS_wur_max_reg_0, + ICLASS_rur_max_reg_1, + ICLASS_wur_max_reg_1, + ICLASS_rur_max_reg_2, + ICLASS_wur_max_reg_2, + ICLASS_rur_max_reg_3, + ICLASS_wur_max_reg_3, + ICLASS_rur_arg_max_reg_0, + ICLASS_wur_arg_max_reg_0, + ICLASS_rur_arg_max_reg_1, + ICLASS_wur_arg_max_reg_1, + ICLASS_rur_arg_max_reg_2, + ICLASS_wur_arg_max_reg_2, + ICLASS_rur_arg_max_reg_3, + ICLASS_wur_arg_max_reg_3, + ICLASS_rur_nco_counter_0, + ICLASS_wur_nco_counter_0, + ICLASS_rur_nco_counter_1, + ICLASS_wur_nco_counter_1, + ICLASS_rur_nco_counter_2, + ICLASS_wur_nco_counter_2, + ICLASS_rur_nco_counter_3, + ICLASS_wur_nco_counter_3, + ICLASS_rur_interp_ext_n, + ICLASS_wur_interp_ext_n, + ICLASS_rur_interp_ext_l, + ICLASS_wur_interp_ext_l, + ICLASS_rur_llr_buf_0, + ICLASS_wur_llr_buf_0, + ICLASS_rur_llr_buf_1, + ICLASS_wur_llr_buf_1, + ICLASS_rur_llr_buf_2, + ICLASS_wur_llr_buf_2, + ICLASS_rur_llr_buf_3, + ICLASS_wur_llr_buf_3, + ICLASS_rur_llr_buf_4, + ICLASS_wur_llr_buf_4, + ICLASS_rur_llr_buf_5, + ICLASS_wur_llr_buf_5, + ICLASS_rur_llr_buf_6, + ICLASS_wur_llr_buf_6, + ICLASS_rur_llr_buf_7, + ICLASS_wur_llr_buf_7, + ICLASS_rur_llr_buf_8, + ICLASS_wur_llr_buf_8, + ICLASS_rur_llr_buf_9, + ICLASS_wur_llr_buf_9, + ICLASS_rur_llr_buf_10, + ICLASS_wur_llr_buf_10, + ICLASS_rur_llr_buf_11, + ICLASS_wur_llr_buf_11, + ICLASS_rur_llr_buf_12, + ICLASS_wur_llr_buf_12, + ICLASS_rur_llr_buf_13, + ICLASS_wur_llr_buf_13, + ICLASS_rur_llr_buf_14, + ICLASS_wur_llr_buf_14, + ICLASS_rur_llr_buf_15, + ICLASS_wur_llr_buf_15, + ICLASS_rur_llr_buf_16, + ICLASS_wur_llr_buf_16, + ICLASS_rur_llr_buf_17, + ICLASS_wur_llr_buf_17, + ICLASS_rur_llr_buf_18, + ICLASS_wur_llr_buf_18, + ICLASS_rur_llr_buf_19, + ICLASS_wur_llr_buf_19, + ICLASS_rur_llr_buf_20, + ICLASS_wur_llr_buf_20, + ICLASS_rur_llr_buf_21, + ICLASS_wur_llr_buf_21, + ICLASS_rur_llr_buf_22, + ICLASS_wur_llr_buf_22, + ICLASS_rur_llr_buf_23, + ICLASS_wur_llr_buf_23, + ICLASS_rur_smod_buf_0, + ICLASS_wur_smod_buf_0, + ICLASS_rur_smod_buf_1, + ICLASS_wur_smod_buf_1, + ICLASS_rur_smod_buf_2, + ICLASS_wur_smod_buf_2, + ICLASS_rur_smod_buf_3, + ICLASS_wur_smod_buf_3, + ICLASS_rur_smod_buf_4, + ICLASS_wur_smod_buf_4, + ICLASS_rur_smod_buf_5, + ICLASS_wur_smod_buf_5, + ICLASS_rur_smod_buf_6, + ICLASS_wur_smod_buf_6, + ICLASS_rur_smod_buf_7, + ICLASS_wur_smod_buf_7, + ICLASS_rur_weight_reg, + ICLASS_wur_weight_reg, + ICLASS_rur_scale_reg, + ICLASS_wur_scale_reg, + ICLASS_rur_llr_pos, + ICLASS_wur_llr_pos, + ICLASS_rur_smod_pos, + ICLASS_wur_smod_pos, + ICLASS_rur_perm_reg, + ICLASS_wur_perm_reg, + ICLASS_rur_smod_offset_table_0, + ICLASS_wur_smod_offset_table_0, + ICLASS_rur_smod_offset_table_1, + ICLASS_wur_smod_offset_table_1, + ICLASS_rur_smod_offset_table_2, + ICLASS_wur_smod_offset_table_2, + ICLASS_rur_smod_offset_table_3, + ICLASS_wur_smod_offset_table_3, + ICLASS_rur_phasor_n, + ICLASS_wur_phasor_n, + ICLASS_rur_phasor_offset, + ICLASS_wur_phasor_offset +}; + + +/* Opcode encodings. */ + +static void +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2080; +} + +static void +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3200; +} + +static void +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000; +} + +static void +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5100; +} + +static void +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35; +} + +static void +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0; +} + +static void +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0; +} + +static void +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0; +} + +static void +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36; +} + +static void +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90; +} + +static void +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf01d; +} + +static void +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3500; +} + +static void +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x90000; +} + +static void +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800; +} + +static void +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134800; +} + +static void +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614800; +} + +static void +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34900; +} + +static void +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x134900; +} + +static void +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x614900; +} + +static void +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa; +} + +static void +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb; +} + +static void +Opcode_addi_n_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_addi_n_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001; +} + +static void +Opcode_addi_n_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_addi_n_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_addi_n_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001; +} + +static void +Opcode_addi_n_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_addi_n_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_addi_n_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_addi_n_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe0002; +} + +static void +Opcode_addi_n_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f8001; +} + +static void +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c; +} + +static void +Opcode_beqz_n_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000; +} + +static void +Opcode_beqz_n_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13000; +} + +static void +Opcode_beqz_n_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f001; +} + +static void +Opcode_beqz_n_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc05001; +} + +static void +Opcode_beqz_n_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d3001; +} + +static void +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc; +} + +static void +Opcode_bnez_n_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23000; +} + +static void +Opcode_bnez_n_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x23000; +} + +static void +Opcode_bnez_n_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x52001; +} + +static void +Opcode_bnez_n_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc09001; +} + +static void +Opcode_bnez_n_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e3001; +} + +static void +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf06d; +} + +static void +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8; +} + +static void +Opcode_l32i_n_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c001; +} + +static void +Opcode_l32i_n_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c001; +} + +static void +Opcode_l32i_n_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c000; +} + +static void +Opcode_l32i_n_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001; +} + +static void +Opcode_l32i_n_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40c000; +} + +static void +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_mov_n_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ec00; +} + +static void +Opcode_mov_n_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd400; +} + +static void +Opcode_mov_n_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd803; +} + +static void +Opcode_mov_n_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e000; +} + +static void +Opcode_mov_n_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd400; +} + +static void +Opcode_mov_n_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_mov_n_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x53401; +} + +static void +Opcode_mov_n_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb403; +} + +static void +Opcode_mov_n_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x601401; +} + +static void +Opcode_mov_n_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c6c01; +} + +static void +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc; +} + +static void +Opcode_movi_n_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000; +} + +static void +Opcode_movi_n_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42002; +} + +static void +Opcode_movi_n_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_movi_n_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_movi_n_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42002; +} + +static void +Opcode_movi_n_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_movi_n_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50001; +} + +static void +Opcode_movi_n_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8003; +} + +static void +Opcode_movi_n_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402001; +} + +static void +Opcode_movi_n_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf03d; +} + +static void +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00d; +} + +static void +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_s32i_n_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20002; +} + +static void +Opcode_s32i_n_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20002; +} + +static void +Opcode_s32i_n_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40001; +} + +static void +Opcode_s32i_n_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_s32i_n_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a4000; +} + +static void +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e70; +} + +static void +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e700; +} + +static void +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addi_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2001; +} + +static void +Opcode_addi_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_addmi_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401; +} + +static void +Opcode_addmi_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800000; +} + +static void +Opcode_add_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_add_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001; +} + +static void +Opcode_add_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_add_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_add_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001; +} + +static void +Opcode_add_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_add_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000; +} + +static void +Opcode_add_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_add_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0002; +} + +static void +Opcode_add_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f0001; +} + +static void +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00000; +} + +static void +Opcode_sub_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000; +} + +static void +Opcode_sub_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48002; +} + +static void +Opcode_sub_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8001; +} + +static void +Opcode_sub_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24000; +} + +static void +Opcode_sub_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002; +} + +static void +Opcode_sub_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8001; +} + +static void +Opcode_sub_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c001; +} + +static void +Opcode_sub_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8002; +} + +static void +Opcode_sub_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f0002; +} + +static void +Opcode_sub_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4ec000; +} + +static void +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900000; +} + +static void +Opcode_addx2_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c001; +} + +static void +Opcode_addx2_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c001; +} + +static void +Opcode_addx2_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000; +} + +static void +Opcode_addx2_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd4002; +} + +static void +Opcode_addx2_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3fc001; +} + +static void +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00000; +} + +static void +Opcode_addx4_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34001; +} + +static void +Opcode_addx4_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34001; +} + +static void +Opcode_addx4_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34000; +} + +static void +Opcode_addx4_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8002; +} + +static void +Opcode_addx4_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00000; +} + +static void +Opcode_addx8_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38001; +} + +static void +Opcode_addx8_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38001; +} + +static void +Opcode_addx8_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_addx8_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc002; +} + +static void +Opcode_addx8_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00000; +} + +static void +Opcode_subx2_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50002; +} + +static void +Opcode_subx2_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c002; +} + +static void +Opcode_subx2_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34001; +} + +static void +Opcode_subx2_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1ec002; +} + +static void +Opcode_subx2_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f8000; +} + +static void +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00000; +} + +static void +Opcode_subx4_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002; +} + +static void +Opcode_subx4_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54002; +} + +static void +Opcode_subx4_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38001; +} + +static void +Opcode_subx4_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f4002; +} + +static void +Opcode_subx4_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4fc000; +} + +static void +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00000; +} + +static void +Opcode_subx8_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c002; +} + +static void +Opcode_subx8_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58002; +} + +static void +Opcode_subx8_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c001; +} + +static void +Opcode_subx8_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1f8002; +} + +static void +Opcode_subx8_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x504000; +} + +static void +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100000; +} + +static void +Opcode_and_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_and_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c001; +} + +static void +Opcode_and_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_and_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_and_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c001; +} + +static void +Opcode_and_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_and_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_and_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe4002; +} + +static void +Opcode_and_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408000; +} + +static void +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200000; +} + +static void +Opcode_or_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000; +} + +static void +Opcode_or_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8002; +} + +static void +Opcode_or_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_or_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c000; +} + +static void +Opcode_or_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8002; +} + +static void +Opcode_or_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001; +} + +static void +Opcode_or_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4003; +} + +static void +Opcode_or_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d4002; +} + +static void +Opcode_or_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x494000; +} + +static void +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300000; +} + +static void +Opcode_xor_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000; +} + +static void +Opcode_xor_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54002; +} + +static void +Opcode_xor_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc001; +} + +static void +Opcode_xor_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28000; +} + +static void +Opcode_xor_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c002; +} + +static void +Opcode_xor_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44001; +} + +static void +Opcode_xor_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_xor_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1fc002; +} + +static void +Opcode_xor_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x518000; +} + +static void +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26; +} + +static void +Opcode_beqi_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; +} + +static void +Opcode_beqi_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66; +} + +static void +Opcode_bnei_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800040; +} + +static void +Opcode_bnei_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2; +} + +static void +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe6; +} + +static void +Opcode_bgei_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_bgei_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42; +} + +static void +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa6; +} + +static void +Opcode_blti_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_blti_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x102; +} + +static void +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6007; +} + +static void +Opcode_bbci_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x801; +} + +static void +Opcode_bbci_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe007; +} + +static void +Opcode_bbsi_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1001; +} + +static void +Opcode_bbsi_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; +} + +static void +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf6; +} + +static void +Opcode_bgeui_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; +} + +static void +Opcode_bgeui_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82; +} + +static void +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb6; +} + +static void +Opcode_bltui_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400040; +} + +static void +Opcode_bltui_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x202; +} + +static void +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1007; +} + +static void +Opcode_beq_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800801; +} + +static void +Opcode_beq_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800; +} + +static void +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9007; +} + +static void +Opcode_bne_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401001; +} + +static void +Opcode_bne_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa007; +} + +static void +Opcode_bge_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c01; +} + +static void +Opcode_bge_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2007; +} + +static void +Opcode_blt_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00801; +} + +static void +Opcode_blt_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3400; +} + +static void +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb007; +} + +static void +Opcode_bgeu_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800c01; +} + +static void +Opcode_bgeu_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c00; +} + +static void +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3007; +} + +static void +Opcode_bltu_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00c01; +} + +static void +Opcode_bltu_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3800; +} + +static void +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8007; +} + +static void +Opcode_bany_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800401; +} + +static void +Opcode_bany_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; +} + +static void +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7; +} + +static void +Opcode_bnone_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x801001; +} + +static void +Opcode_bnone_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403; +} + +static void +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4007; +} + +static void +Opcode_ball_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400401; +} + +static void +Opcode_ball_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; +} + +static void +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc007; +} + +static void +Opcode_bnall_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1801; +} + +static void +Opcode_bnall_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c00; +} + +static void +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5007; +} + +static void +Opcode_bbc_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00401; +} + +static void +Opcode_bbc_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c00; +} + +static void +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd007; +} + +static void +Opcode_bbs_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400801; +} + +static void +Opcode_bbs_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; +} + +static void +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16; +} + +static void +Opcode_beqz_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002; +} + +static void +Opcode_beqz_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001; +} + +static void +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56; +} + +static void +Opcode_bnez_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400002; +} + +static void +Opcode_bnez_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0001; +} + +static void +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd6; +} + +static void +Opcode_bgez_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100002; +} + +static void +Opcode_bgez_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100001; +} + +static void +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x96; +} + +static void +Opcode_bltz_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200002; +} + +static void +Opcode_bltz_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200001; +} + +static void +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_extui_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_extui_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_extui_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_extui_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_extui_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_extui_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_extui_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0; +} + +static void +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_l16ui_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1003; +} + +static void +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9002; +} + +static void +Opcode_l16si_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x803; +} + +static void +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_l32i_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2003; +} + +static void +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_l32r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400001; +} + +static void +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_l8ui_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc03; +} + +static void +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8076; +} + +static void +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9076; +} + +static void +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa076; +} + +static void +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_movi_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800002; +} + +static void +Opcode_movi_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0001; +} + +static void +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x830000; +} + +static void +Opcode_moveqz_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_moveqz_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001; +} + +static void +Opcode_moveqz_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_moveqz_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74001; +} + +static void +Opcode_moveqz_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78000; +} + +static void +Opcode_moveqz_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c4002; +} + +static void +Opcode_moveqz_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x454000; +} + +static void +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x930000; +} + +static void +Opcode_movnez_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000; +} + +static void +Opcode_movnez_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_movnez_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000; +} + +static void +Opcode_movnez_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_movnez_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001; +} + +static void +Opcode_movnez_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e0002; +} + +static void +Opcode_movnez_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x474000; +} + +static void +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa30000; +} + +static void +Opcode_movltz_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000; +} + +static void +Opcode_movltz_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001; +} + +static void +Opcode_movltz_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000; +} + +static void +Opcode_movltz_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c001; +} + +static void +Opcode_movltz_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_movltz_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d0002; +} + +static void +Opcode_movltz_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x470000; +} + +static void +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb30000; +} + +static void +Opcode_movgez_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_movgez_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001; +} + +static void +Opcode_movgez_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_movgez_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78001; +} + +static void +Opcode_movgez_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c000; +} + +static void +Opcode_movgez_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c8002; +} + +static void +Opcode_movgez_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x464000; +} + +static void +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_neg_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34034; +} + +static void +Opcode_neg_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000c; +} + +static void +Opcode_neg_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x801f; +} + +static void +Opcode_neg_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34020; +} + +static void +Opcode_neg_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000c; +} + +static void +Opcode_neg_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_neg_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54035; +} + +static void +Opcode_neg_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01f; +} + +static void +Opcode_neg_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001a; +} + +static void +Opcode_neg_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000d; +} + +static void +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600100; +} + +static void +Opcode_abs_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34030; +} + +static void +Opcode_abs_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000c; +} + +static void +Opcode_abs_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34010; +} + +static void +Opcode_abs_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000c; +} + +static void +Opcode_abs_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54021; +} + +static void +Opcode_abs_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140016; +} + +static void +Opcode_abs_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34000d; +} + +static void +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20f0; +} + +static void +Opcode_nop_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32f64; +} + +static void +Opcode_nop_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc030; +} + +static void +Opcode_nop_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35430; +} + +static void +Opcode_nop_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda5d4; +} + +static void +Opcode_nop_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_nop_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa42f; +} + +static void +Opcode_nop_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2eda4; +} + +static void +Opcode_nop_Slot_pq_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_nop_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35430; +} + +static void +Opcode_nop_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60; +} + +static void +Opcode_nop_Slot_acc2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_nop_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e40; +} + +static void +Opcode_nop_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9add4; +} + +static void +Opcode_nop_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x202; +} + +static void +Opcode_nop_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b015; +} + +static void +Opcode_nop_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x168dd; +} + +static void +Opcode_nop_Slot_llr_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_nop_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc237; +} + +static void +Opcode_nop_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa50dc; +} + +static void +Opcode_nop_Slot_dual_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_nop_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dec31; +} + +static void +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002; +} + +static void +Opcode_s16i_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1403; +} + +static void +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_s32i_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1803; +} + +static void +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_s8i_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c03; +} + +static void +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400000; +} + +static void +Opcode_ssr_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d740; +} + +static void +Opcode_ssr_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d740; +} + +static void +Opcode_ssr_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5df41; +} + +static void +Opcode_ssr_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc8c0; +} + +static void +Opcode_ssr_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ee801; +} + +static void +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401000; +} + +static void +Opcode_ssl_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d6c0; +} + +static void +Opcode_ssl_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d6c0; +} + +static void +Opcode_ssl_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5dec1; +} + +static void +Opcode_ssl_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc4c0; +} + +static void +Opcode_ssl_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e6c01; +} + +static void +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402000; +} + +static void +Opcode_ssa8l_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d700; +} + +static void +Opcode_ssa8l_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d700; +} + +static void +Opcode_ssa8l_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5df01; +} + +static void +Opcode_ssa8l_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0c0; +} + +static void +Opcode_ssa8l_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2debc1; +} + +static void +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403000; +} + +static void +Opcode_ssa8b_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d680; +} + +static void +Opcode_ssa8b_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d680; +} + +static void +Opcode_ssa8b_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5de81; +} + +static void +Opcode_ssa8b_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00c0; +} + +static void +Opcode_ssa8b_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2deb81; +} + +static void +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404000; +} + +static void +Opcode_ssai_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_ssai_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_ssai_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5dc01; +} + +static void +Opcode_ssai_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480080; +} + +static void +Opcode_ssai_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d6f81; +} + +static void +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10000; +} + +static void +Opcode_sll_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_sll_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c002; +} + +static void +Opcode_sll_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_sll_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_sll_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c002; +} + +static void +Opcode_sll_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001; +} + +static void +Opcode_sll_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_sll_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40c0; +} + +static void +Opcode_sll_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40142; +} + +static void +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810000; +} + +static void +Opcode_src_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38002; +} + +static void +Opcode_src_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38002; +} + +static void +Opcode_src_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28001; +} + +static void +Opcode_src_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e4002; +} + +static void +Opcode_src_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e0000; +} + +static void +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910000; +} + +static void +Opcode_srl_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5800c; +} + +static void +Opcode_srl_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5800c; +} + +static void +Opcode_srl_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58011; +} + +static void +Opcode_srl_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148016; +} + +static void +Opcode_srl_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34c00d; +} + +static void +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb10000; +} + +static void +Opcode_sra_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34038; +} + +static void +Opcode_sra_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002c; +} + +static void +Opcode_sra_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x802b; +} + +static void +Opcode_sra_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34014; +} + +static void +Opcode_sra_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5002c; +} + +static void +Opcode_sra_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5403d; +} + +static void +Opcode_sra_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc02b; +} + +static void +Opcode_sra_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144016; +} + +static void +Opcode_sra_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34802d; +} + +static void +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_slli_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40001; +} + +static void +Opcode_slli_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003; +} + +static void +Opcode_slli_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40001; +} + +static void +Opcode_slli_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_slli_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10003; +} + +static void +Opcode_slli_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0002; +} + +static void +Opcode_slli_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d8001; +} + +static void +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x210000; +} + +static void +Opcode_srai_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18001; +} + +static void +Opcode_srai_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000; +} + +static void +Opcode_srai_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18001; +} + +static void +Opcode_srai_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000; +} + +static void +Opcode_srai_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18000; +} + +static void +Opcode_srai_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc8002; +} + +static void +Opcode_srai_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e8001; +} + +static void +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_srli_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c002; +} + +static void +Opcode_srli_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c002; +} + +static void +Opcode_srli_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30001; +} + +static void +Opcode_srli_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1e8002; +} + +static void +Opcode_srli_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4cc000; +} + +static void +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20c0; +} + +static void +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20d0; +} + +static void +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2010; +} + +static void +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2030; +} + +static void +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30100; +} + +static void +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130100; +} + +static void +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610100; +} + +static void +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30200; +} + +static void +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130200; +} + +static void +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610200; +} + +static void +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130000; +} + +static void +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610000; +} + +static void +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30300; +} + +static void +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130300; +} + +static void +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610300; +} + +static void +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30500; +} + +static void +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130500; +} + +static void +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610500; +} + +static void +Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b000; +} + +static void +Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b000; +} + +static void +Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d000; +} + +static void +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e600; +} + +static void +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e600; +} + +static void +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e600; +} + +static void +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b100; +} + +static void +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b100; +} + +static void +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b100; +} + +static void +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d100; +} + +static void +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d100; +} + +static void +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d100; +} + +static void +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b200; +} + +static void +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b200; +} + +static void +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b200; +} + +static void +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d200; +} + +static void +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d200; +} + +static void +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d200; +} + +static void +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b300; +} + +static void +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b300; +} + +static void +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b300; +} + +static void +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d300; +} + +static void +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d300; +} + +static void +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d300; +} + +static void +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b400; +} + +static void +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b400; +} + +static void +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b400; +} + +static void +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d400; +} + +static void +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d400; +} + +static void +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d400; +} + +static void +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b500; +} + +static void +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b500; +} + +static void +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b500; +} + +static void +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d500; +} + +static void +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d500; +} + +static void +Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b600; +} + +static void +Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13b600; +} + +static void +Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61b600; +} + +static void +Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13d600; +} + +static void +Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61d600; +} + +static void +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c200; +} + +static void +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c200; +} + +static void +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c200; +} + +static void +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c300; +} + +static void +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c300; +} + +static void +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c300; +} + +static void +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c400; +} + +static void +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c400; +} + +static void +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c400; +} + +static void +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c500; +} + +static void +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c500; +} + +static void +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c500; +} + +static void +Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c600; +} + +static void +Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c600; +} + +static void +Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c600; +} + +static void +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ee00; +} + +static void +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ee00; +} + +static void +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ee00; +} + +static void +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13c000; +} + +static void +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61c000; +} + +static void +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e800; +} + +static void +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e800; +} + +static void +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e800; +} + +static void +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3eb00; +} + +static void +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e700; +} + +static void +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e700; +} + +static void +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e700; +} + +static void +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc10000; +} + +static void +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd10000; +} + +static void +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3010; +} + +static void +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e200; +} + +static void +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e200; +} + +static void +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e300; +} + +static void +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e400; +} + +static void +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e400; +} + +static void +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e400; +} + +static void +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf02d; +} + +static void +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39000; +} + +static void +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139000; +} + +static void +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619000; +} + +static void +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a000; +} + +static void +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a000; +} + +static void +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a000; +} + +static void +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39100; +} + +static void +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x139100; +} + +static void +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x619100; +} + +static void +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a100; +} + +static void +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13a100; +} + +static void +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61a100; +} + +static void +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138000; +} + +static void +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618000; +} + +static void +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x138100; +} + +static void +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x618100; +} + +static void +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36000; +} + +static void +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136000; +} + +static void +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616000; +} + +static void +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e900; +} + +static void +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e900; +} + +static void +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e900; +} + +static void +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ec00; +} + +static void +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ec00; +} + +static void +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ec00; +} + +static void +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ed00; +} + +static void +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ed00; +} + +static void +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ed00; +} + +static void +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36800; +} + +static void +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136800; +} + +static void +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616800; +} + +static void +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e000; +} + +static void +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1e010; +} + +static void +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x135900; +} + +static void +Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_andb_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48001; +} + +static void +Opcode_andb_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48001; +} + +static void +Opcode_andb_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48000; +} + +static void +Opcode_andb_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe8002; +} + +static void +Opcode_andb_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410000; +} + +static void +Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x120000; +} + +static void +Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x220000; +} + +static void +Opcode_orb_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002; +} + +static void +Opcode_orb_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002; +} + +static void +Opcode_orb_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20001; +} + +static void +Opcode_orb_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d8002; +} + +static void +Opcode_orb_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x498000; +} + +static void +Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x320000; +} + +static void +Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_xorb_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58002; +} + +static void +Opcode_xorb_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002; +} + +static void +Opcode_xorb_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48001; +} + +static void +Opcode_xorb_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240002; +} + +static void +Opcode_xorb_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x51c000; +} + +static void +Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_any4_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35400; +} + +static void +Opcode_any4_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35400; +} + +static void +Opcode_any4_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58421; +} + +static void +Opcode_any4_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x481421; +} + +static void +Opcode_any4_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2cec21; +} + +static void +Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9000; +} + +static void +Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_any8_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d420; +} + +static void +Opcode_any8_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d420; +} + +static void +Opcode_any8_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58019; +} + +static void +Opcode_any8_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x481419; +} + +static void +Opcode_any8_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2cec31; +} + +static void +Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x76; +} + +static void +Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1076; +} + +static void +Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc30000; +} + +static void +Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd30000; +} + +static void +Opcode_movt_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_movt_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_movt_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8001; +} + +static void +Opcode_movt_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1cc002; +} + +static void +Opcode_movt_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47c000; +} + +static void +Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30400; +} + +static void +Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130400; +} + +static void +Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610400; +} + +static void +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ea00; +} + +static void +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13ea00; +} + +static void +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61ea00; +} + +static void +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f000; +} + +static void +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f000; +} + +static void +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f000; +} + +static void +Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f100; +} + +static void +Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13f100; +} + +static void +Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61f100; +} + +static void +Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70c2; +} + +static void +Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e2; +} + +static void +Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70d2; +} + +static void +Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270d2; +} + +static void +Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370d2; +} + +static void +Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70f2; +} + +static void +Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf10000; +} + +static void +Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf12000; +} + +static void +Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf11000; +} + +static void +Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf13000; +} + +static void +Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7042; +} + +static void +Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7052; +} + +static void +Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x47082; +} + +static void +Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x57082; +} + +static void +Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7062; +} + +static void +Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7072; +} + +static void +Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7002; +} + +static void +Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7012; +} + +static void +Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7022; +} + +static void +Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7032; +} + +static void +Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7082; +} + +static void +Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x27082; +} + +static void +Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x37082; +} + +static void +Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf19000; +} + +static void +Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf18000; +} + +static void +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50c000; +} + +static void +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50d000; +} + +static void +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50b000; +} + +static void +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50f000; +} + +static void +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50e000; +} + +static void +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x504000; +} + +static void +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x505000; +} + +static void +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x503000; +} + +static void +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x507000; +} + +static void +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x506000; +} + +static void +Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e000; +} + +static void +Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13e000; +} + +static void +Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61e000; +} + +static void +Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x330000; +} + +static void +Opcode_clamps_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50001; +} + +static void +Opcode_clamps_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50001; +} + +static void +Opcode_clamps_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50000; +} + +static void +Opcode_clamps_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf0002; +} + +static void +Opcode_clamps_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440000; +} + +static void +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_min_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001; +} + +static void +Opcode_min_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001; +} + +static void +Opcode_min_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c000; +} + +static void +Opcode_min_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc002; +} + +static void +Opcode_min_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x460000; +} + +static void +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x530000; +} + +static void +Opcode_max_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001; +} + +static void +Opcode_max_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64001; +} + +static void +Opcode_max_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68000; +} + +static void +Opcode_max_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf4002; +} + +static void +Opcode_max_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x448000; +} + +static void +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x630000; +} + +static void +Opcode_minu_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001; +} + +static void +Opcode_minu_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c001; +} + +static void +Opcode_minu_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74000; +} + +static void +Opcode_minu_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0002; +} + +static void +Opcode_minu_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44c000; +} + +static void +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x730000; +} + +static void +Opcode_maxu_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001; +} + +static void +Opcode_maxu_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001; +} + +static void +Opcode_maxu_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_maxu_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf8002; +} + +static void +Opcode_maxu_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x450000; +} + +static void +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40e000; +} + +static void +Opcode_nsa_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15400; +} + +static void +Opcode_nsa_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15400; +} + +static void +Opcode_nsa_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x53801; +} + +static void +Opcode_nsa_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c1401; +} + +static void +Opcode_nsa_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ce801; +} + +static void +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40f000; +} + +static void +Opcode_nsau_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400; +} + +static void +Opcode_nsau_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25400; +} + +static void +Opcode_nsau_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x53c01; +} + +static void +Opcode_nsau_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c5401; +} + +static void +Opcode_nsau_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d6801; +} + +static void +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x230000; +} + +static void +Opcode_sext_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34002; +} + +static void +Opcode_sext_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34002; +} + +static void +Opcode_sext_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24001; +} + +static void +Opcode_sext_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1dc002; +} + +static void +Opcode_sext_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d0000; +} + +static void +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb002; +} + +static void +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30c00; +} + +static void +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x130c00; +} + +static void +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x610c00; +} + +static void +Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x36300; +} + +static void +Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x136300; +} + +static void +Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x616300; +} + +static void +Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x406000; +} + +static void +Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x407000; +} + +static void +Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e80; +} + +static void +Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e800; +} + +static void +Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30e90; +} + +static void +Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf3e900; +} + +static void +Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa0000; +} + +static void +Opcode_add_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3f4001; +} + +static void +Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a0000; +} + +static void +Opcode_sub_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f4000; +} + +static void +Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a0000; +} + +static void +Opcode_mul_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x490000; +} + +static void +Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_madd_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x444000; +} + +static void +Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a0000; +} + +static void +Opcode_msub_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x488000; +} + +static void +Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcb0000; +} + +static void +Opcode_movf_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x45c000; +} + +static void +Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdb0000; +} + +static void +Opcode_movt_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x484000; +} + +static void +Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8b0000; +} + +static void +Opcode_moveqz_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x458000; +} + +static void +Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9b0000; +} + +static void +Opcode_movnez_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x478000; +} + +static void +Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xab0000; +} + +static void +Opcode_movltz_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46c000; +} + +static void +Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbb0000; +} + +static void +Opcode_movgez_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x468000; +} + +static void +Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0010; +} + +static void +Opcode_abs_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x142; +} + +static void +Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0000; +} + +static void +Opcode_mov_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4142; +} + +static void +Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0060; +} + +static void +Opcode_neg_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8142; +} + +static void +Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1b0000; +} + +static void +Opcode_un_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50c000; +} + +static void +Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b0000; +} + +static void +Opcode_oeq_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a0000; +} + +static void +Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b0000; +} + +static void +Opcode_ueq_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x510000; +} + +static void +Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0000; +} + +static void +Opcode_olt_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48c000; +} + +static void +Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b0000; +} + +static void +Opcode_ult_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b0000; +} + +static void +Opcode_ole_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7b0000; +} + +static void +Opcode_ule_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x540000; +} + +static void +Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xca0000; +} + +static void +Opcode_float_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x500000; +} + +static void +Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda0000; +} + +static void +Opcode_ufloat_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x520000; +} + +static void +Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a0000; +} + +static void +Opcode_round_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x49c000; +} + +static void +Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xba0000; +} + +static void +Opcode_ceil_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x420000; +} + +static void +Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xaa0000; +} + +static void +Opcode_floor_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x600000; +} + +static void +Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9a0000; +} + +static void +Opcode_trunc_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x508000; +} + +static void +Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xea0000; +} + +static void +Opcode_utrunc_s_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x514000; +} + +static void +Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0040; +} + +static void +Opcode_rfr_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20142; +} + +static void +Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfa0050; +} + +static void +Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_lsi_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140001; +} + +static void +Opcode_lsiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8003; +} + +static void +Opcode_lsiu_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180001; +} + +static void +Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_lsxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180000; +} + +static void +Opcode_lsxu_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x430000; +} + +static void +Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4003; +} + +static void +Opcode_ssi_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240001; +} + +static void +Opcode_ssiu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc003; +} + +static void +Opcode_ssiu_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280001; +} + +static void +Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_ssx_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d4000; +} + +static void +Opcode_ssxu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x580000; +} + +static void +Opcode_ssxu_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d8000; +} + +static void +Opcode_get_argmax_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b700; +} + +static void +Opcode_get_argmax_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3407c; +} + +static void +Opcode_get_argmax_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x181d4; +} + +static void +Opcode_get_argmax_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3401c; +} + +static void +Opcode_get_argmax_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8294; +} + +static void +Opcode_get_argmax_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd; +} + +static void +Opcode_get_argmax_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x840ec; +} + +static void +Opcode_get_hsar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6ba00; +} + +static void +Opcode_get_hsar_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340bc; +} + +static void +Opcode_get_hsar_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d434; +} + +static void +Opcode_get_hsar_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x281d4; +} + +static void +Opcode_get_hsar_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x802f; +} + +static void +Opcode_get_hsar_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34058; +} + +static void +Opcode_get_hsar_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d434; +} + +static void +Opcode_get_hsar_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8314; +} + +static void +Opcode_get_hsar_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58415; +} + +static void +Opcode_get_hsar_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40d9; +} + +static void +Opcode_get_hsar_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc83b; +} + +static void +Opcode_get_hsar_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880ec; +} + +static void +Opcode_get_hsar_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dec05; +} + +static void +Opcode_get_hsar2sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6bc00; +} + +static void +Opcode_get_hsar2sar_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3413c; +} + +static void +Opcode_get_hsar2sar_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d438; +} + +static void +Opcode_get_hsar2sar_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x481d4; +} + +static void +Opcode_get_hsar2sar_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x842f; +} + +static void +Opcode_get_hsar2sar_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34098; +} + +static void +Opcode_get_hsar2sar_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d438; +} + +static void +Opcode_get_hsar2sar_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18254; +} + +static void +Opcode_get_hsar2sar_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58815; +} + +static void +Opcode_get_hsar2sar_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d9; +} + +static void +Opcode_get_hsar2sar_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd03b; +} + +static void +Opcode_get_hsar2sar_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x900ec; +} + +static void +Opcode_get_hsar2sar_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dec09; +} + +static void +Opcode_get_interp_ext_n_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70b90; +} + +static void +Opcode_get_interp_ext_n_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6806c; +} + +static void +Opcode_get_interp_ext_n_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6806c; +} + +static void +Opcode_get_interp_ext_n_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64101; +} + +static void +Opcode_get_interp_ext_n_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3540ed; +} + +static void +Opcode_get_interp_ext_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70b80; +} + +static void +Opcode_get_interp_ext_l_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6802c; +} + +static void +Opcode_get_interp_ext_l_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6802c; +} + +static void +Opcode_get_interp_ext_l_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64081; +} + +static void +Opcode_get_interp_ext_l_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35406d; +} + +static void +Opcode_get_llr_buf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x462000; +} + +static void +Opcode_get_llr_buf_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d400; +} + +static void +Opcode_get_llr_buf_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d400; +} + +static void +Opcode_get_llr_buf_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58021; +} + +static void +Opcode_get_llr_buf_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000; +} + +static void +Opcode_get_llr_buf_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2cec01; +} + +static void +Opcode_get_llr_pos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70ba0; +} + +static void +Opcode_get_llr_pos_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680ac; +} + +static void +Opcode_get_llr_pos_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680ac; +} + +static void +Opcode_get_llr_pos_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64201; +} + +static void +Opcode_get_llr_pos_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc06f; +} + +static void +Opcode_get_llr_pos_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35416d; +} + +static void +Opcode_get_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6bb00; +} + +static void +Opcode_get_max_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3423c; +} + +static void +Opcode_get_max_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x881d4; +} + +static void +Opcode_get_max_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34118; +} + +static void +Opcode_get_max_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28254; +} + +static void +Opcode_get_max_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100d9; +} + +static void +Opcode_get_max_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa00ec; +} + +static void +Opcode_get_nco_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6bd00; +} + +static void +Opcode_get_nco_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340fc; +} + +static void +Opcode_get_nco_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x381d4; +} + +static void +Opcode_get_nco_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34218; +} + +static void +Opcode_get_nco_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48254; +} + +static void +Opcode_get_nco_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200d9; +} + +static void +Opcode_get_nco_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0ec; +} + +static void +Opcode_get_perm_reg_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6812c; +} + +static void +Opcode_get_perm_reg_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8037; +} + +static void +Opcode_get_perm_reg_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6812c; +} + +static void +Opcode_get_perm_reg_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64049; +} + +static void +Opcode_get_perm_reg_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0ef; +} + +static void +Opcode_get_perm_reg_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35426d; +} + +static void +Opcode_get_phasor_n_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70bc0; +} + +static void +Opcode_get_phasor_n_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6822c; +} + +static void +Opcode_get_phasor_n_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6822c; +} + +static void +Opcode_get_phasor_n_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64051; +} + +static void +Opcode_get_phasor_n_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3541ed; +} + +static void +Opcode_get_phasor_offset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70bb0; +} + +static void +Opcode_get_phasor_offset_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680ec; +} + +static void +Opcode_get_phasor_offset_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680ec; +} + +static void +Opcode_get_phasor_offset_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64061; +} + +static void +Opcode_get_phasor_offset_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3542ed; +} + +static void +Opcode_get_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6be00; +} + +static void +Opcode_get_sar_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3417c; +} + +static void +Opcode_get_sar_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d43c; +} + +static void +Opcode_get_sar_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x581d4; +} + +static void +Opcode_get_sar_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x882f; +} + +static void +Opcode_get_sar_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3405c; +} + +static void +Opcode_get_sar_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d43c; +} + +static void +Opcode_get_sar_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88254; +} + +static void +Opcode_get_sar_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59015; +} + +static void +Opcode_get_sar_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40dd; +} + +static void +Opcode_get_sar_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe03b; +} + +static void +Opcode_get_sar_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x940ec; +} + +static void +Opcode_get_sar_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dec11; +} + +static void +Opcode_get_scale_reg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70bd0; +} + +static void +Opcode_get_scale_reg_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6816c; +} + +static void +Opcode_get_scale_reg_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6816c; +} + +static void +Opcode_get_scale_reg_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6404d; +} + +static void +Opcode_get_scale_reg_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc16f; +} + +static void +Opcode_get_scale_reg_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35436d; +} + +static void +Opcode_get_smod_buf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b200; +} + +static void +Opcode_get_smod_buf_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d428; +} + +static void +Opcode_get_smod_buf_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d428; +} + +static void +Opcode_get_smod_buf_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58419; +} + +static void +Opcode_get_smod_buf_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc03b; +} + +static void +Opcode_get_smod_buf_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2cec39; +} + +static void +Opcode_get_smod_offset_table_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6bf00; +} + +static void +Opcode_get_smod_offset_table_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35410; +} + +static void +Opcode_get_smod_offset_table_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35410; +} + +static void +Opcode_get_smod_offset_table_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a015; +} + +static void +Opcode_get_smod_offset_table_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc43f; +} + +static void +Opcode_get_smod_offset_table_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dec21; +} + +static void +Opcode_get_smod_pos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70be0; +} + +static void +Opcode_get_smod_pos_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x681ac; +} + +static void +Opcode_get_smod_pos_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x681ac; +} + +static void +Opcode_get_smod_pos_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64055; +} + +static void +Opcode_get_smod_pos_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc26f; +} + +static void +Opcode_get_smod_pos_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3543ed; +} + +static void +Opcode_get_sov_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70bf0; +} + +static void +Opcode_get_sov_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x681ec; +} + +static void +Opcode_get_sov_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x681ec; +} + +static void +Opcode_get_sov_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64059; +} + +static void +Opcode_get_sov_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35802d; +} + +static void +Opcode_get_wght_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70b00; +} + +static void +Opcode_get_wght_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6826c; +} + +static void +Opcode_get_wght_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6826c; +} + +static void +Opcode_get_wght_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6405d; +} + +static void +Opcode_get_wght_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1ef; +} + +static void +Opcode_get_wght_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35804d; +} + +static void +Opcode_set_argmax_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70b30; +} + +static void +Opcode_set_argmax_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d9; +} + +static void +Opcode_set_argmax_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8254; +} + +static void +Opcode_set_argmax_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400d9; +} + +static void +Opcode_set_argmax_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x85d4; +} + +static void +Opcode_set_argmax_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d; +} + +static void +Opcode_set_argmax_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810d0; +} + +static void +Opcode_set_ext_regs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370b00; +} + +static void +Opcode_set_ext_regs_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32400; +} + +static void +Opcode_set_ext_regs_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c01; +} + +static void +Opcode_set_ext_regs_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dc00; +} + +static void +Opcode_set_ext_regs_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001; +} + +static void +Opcode_set_ext_regs_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_set_ext_regs_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e1401; +} + +static void +Opcode_set_hsar_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400dd; +} + +static void +Opcode_set_hsar_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8294; +} + +static void +Opcode_set_hsar_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400dd; +} + +static void +Opcode_set_hsar_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8dd4; +} + +static void +Opcode_set_hsar_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x159; +} + +static void +Opcode_set_hsar_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x820d0; +} + +static void +Opcode_set_llr_buf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70300; +} + +static void +Opcode_set_llr_buf_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c202; +} + +static void +Opcode_set_llr_buf_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c202; +} + +static void +Opcode_set_llr_buf_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70001; +} + +static void +Opcode_set_llr_buf_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc02f; +} + +static void +Opcode_set_llr_buf_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35402d; +} + +static void +Opcode_set_llr_pos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1620d0; +} + +static void +Opcode_set_llr_pos_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d480; +} + +static void +Opcode_set_llr_pos_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d480; +} + +static void +Opcode_set_llr_pos_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5dc81; +} + +static void +Opcode_set_llr_pos_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10200; +} + +static void +Opcode_set_llr_pos_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2de941; +} + +static void +Opcode_set_max_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70b50; +} + +static void +Opcode_set_max_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404d9; +} + +static void +Opcode_set_max_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8314; +} + +static void +Opcode_set_max_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x404d9; +} + +static void +Opcode_set_max_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x95d4; +} + +static void +Opcode_set_max_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x199; +} + +static void +Opcode_set_max_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810d4; +} + +static void +Opcode_set_nco_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70b60; +} + +static void +Opcode_set_nco_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408d9; +} + +static void +Opcode_set_nco_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8654; +} + +static void +Opcode_set_nco_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x408d9; +} + +static void +Opcode_set_nco_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa5d4; +} + +static void +Opcode_set_nco_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x51d; +} + +static void +Opcode_set_nco_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810d8; +} + +static void +Opcode_set_perm_reg_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_set_perm_reg_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf403; +} + +static void +Opcode_set_perm_reg_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d500; +} + +static void +Opcode_set_perm_reg_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5dd01; +} + +static void +Opcode_set_perm_reg_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10040; +} + +static void +Opcode_set_perm_reg_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2de981; +} + +static void +Opcode_set_phasor_n_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1620e0; +} + +static void +Opcode_set_phasor_n_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_set_phasor_n_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d600; +} + +static void +Opcode_set_phasor_n_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5de01; +} + +static void +Opcode_set_phasor_n_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2de9c1; +} + +static void +Opcode_set_phasor_offset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1630d0; +} + +static void +Opcode_set_phasor_offset_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d4c0; +} + +static void +Opcode_set_phasor_offset_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d4c0; +} + +static void +Opcode_set_phasor_offset_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5dcc1; +} + +static void +Opcode_set_phasor_offset_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dea41; +} + +static void +Opcode_set_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70b70; +} + +static void +Opcode_set_sar_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410d9; +} + +static void +Opcode_set_sar_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x683ac; +} + +static void +Opcode_set_sar_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8a54; +} + +static void +Opcode_set_sar_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8237; +} + +static void +Opcode_set_sar_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x410d9; +} + +static void +Opcode_set_sar_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x683ac; +} + +static void +Opcode_set_sar_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9dd4; +} + +static void +Opcode_set_sar_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64075; +} + +static void +Opcode_set_sar_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x91d; +} + +static void +Opcode_set_sar_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0b7; +} + +static void +Opcode_set_sar_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x814d0; +} + +static void +Opcode_set_sar_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3581ad; +} + +static void +Opcode_set_scale_reg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1620f0; +} + +static void +Opcode_set_scale_reg_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d540; +} + +static void +Opcode_set_scale_reg_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d540; +} + +static void +Opcode_set_scale_reg_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5dd41; +} + +static void +Opcode_set_scale_reg_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10080; +} + +static void +Opcode_set_scale_reg_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dea81; +} + +static void +Opcode_set_smod_buf_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370e00; +} + +static void +Opcode_set_smod_buf_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c008; +} + +static void +Opcode_set_smod_buf_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c008; +} + +static void +Opcode_set_smod_buf_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64041; +} + +static void +Opcode_set_smod_buf_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc073; +} + +static void +Opcode_set_smod_buf_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350039; +} + +static void +Opcode_set_smod_offset_table_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70b90; +} + +static void +Opcode_set_smod_offset_table_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x683ec; +} + +static void +Opcode_set_smod_offset_table_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x683ec; +} + +static void +Opcode_set_smod_offset_table_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64079; +} + +static void +Opcode_set_smod_offset_table_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc137; +} + +static void +Opcode_set_smod_offset_table_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3582ad; +} + +static void +Opcode_set_smod_pos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1630e0; +} + +static void +Opcode_set_smod_pos_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d580; +} + +static void +Opcode_set_smod_pos_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d580; +} + +static void +Opcode_set_smod_pos_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5dd81; +} + +static void +Opcode_set_smod_pos_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10440; +} + +static void +Opcode_set_smod_pos_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2deb01; +} + +static void +Opcode_set_sov_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1630f0; +} + +static void +Opcode_set_sov_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d5c0; +} + +static void +Opcode_set_sov_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d5c0; +} + +static void +Opcode_set_sov_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5ddc1; +} + +static void +Opcode_set_sov_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2deac1; +} + +static void +Opcode_set_wght_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a010; +} + +static void +Opcode_set_wght_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d640; +} + +static void +Opcode_set_wght_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d640; +} + +static void +Opcode_set_wght_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5de41; +} + +static void +Opcode_set_wght_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10840; +} + +static void +Opcode_set_wght_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2deb41; +} + +static void +Opcode_lac2x32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_lac2x32_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_lac2x32_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_lac2x32_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300001; +} + +static void +Opcode_lac2x64_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x82003; +} + +static void +Opcode_lac2x64_0_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c00; +} + +static void +Opcode_lac2x64_0_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c00; +} + +static void +Opcode_lac2x64_0_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0c01; +} + +static void +Opcode_lac2x64_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32003; +} + +static void +Opcode_lac2x64_1_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c00; +} + +static void +Opcode_lac2x64_1_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c00; +} + +static void +Opcode_lac2x64_1_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c2801; +} + +static void +Opcode_lac2x64_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x132003; +} + +static void +Opcode_lac2x64_2_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; +} + +static void +Opcode_lac2x64_2_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1400; +} + +static void +Opcode_lac2x64_2_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c4c01; +} + +static void +Opcode_lac2x64_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x52003; +} + +static void +Opcode_lac2x64_3_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; +} + +static void +Opcode_lac2x64_3_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1800; +} + +static void +Opcode_lac2x64_3_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c2c01; +} + +static void +Opcode_lac32_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x61000; +} + +static void +Opcode_lac32_r_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_lac32_r_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400; +} + +static void +Opcode_lac32_r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0001; +} + +static void +Opcode_lac_ih_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2003; +} + +static void +Opcode_lac_ih_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; +} + +static void +Opcode_lac_ih_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800; +} + +static void +Opcode_lac_ih_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0401; +} + +static void +Opcode_lac_il_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12003; +} + +static void +Opcode_lac_il_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_lac_il_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000; +} + +static void +Opcode_lac_il_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0801; +} + +static void +Opcode_lac_rh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x22003; +} + +static void +Opcode_lac_rh_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; +} + +static void +Opcode_lac_rh_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00; +} + +static void +Opcode_lac_rh_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c1001; +} + +static void +Opcode_lac_rl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42003; +} + +static void +Opcode_lac_rl_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800; +} + +static void +Opcode_lac_rl_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800; +} + +static void +Opcode_lac_rl_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c2401; +} + +static void +Opcode_lcm_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70300; +} + +static void +Opcode_lcm_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40008; +} + +static void +Opcode_lcm_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001; +} + +static void +Opcode_lcm_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40008; +} + +static void +Opcode_lcm_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54000; +} + +static void +Opcode_lcm_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_lcm_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340011; +} + +static void +Opcode_lcm_pinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70000; +} + +static void +Opcode_lcm_pinc_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_lcm_pinc_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_lcm_pinc_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_lcm_pinc_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340001; +} + +static void +Opcode_lcm_pinc_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x680000; +} + +static void +Opcode_lcm_pinc_x_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54001; +} + +static void +Opcode_lcm_pinc_x_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54001; +} + +static void +Opcode_lcm_pinc_x_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58000; +} + +static void +Opcode_lcm_pinc_x_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x414000; +} + +static void +Opcode_lcm_u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70100; +} + +static void +Opcode_lcm_u_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40004; +} + +static void +Opcode_lcm_u_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001; +} + +static void +Opcode_lcm_u_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40004; +} + +static void +Opcode_lcm_u_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_lcm_u_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001; +} + +static void +Opcode_lcm_u_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380001; +} + +static void +Opcode_lcm_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x880000; +} + +static void +Opcode_lcm_x_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58001; +} + +static void +Opcode_lcm_x_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_lcm_x_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58001; +} + +static void +Opcode_lcm_x_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001; +} + +static void +Opcode_lcm_x_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c000; +} + +static void +Opcode_lcm_x_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_lcm_x_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x418000; +} + +static void +Opcode_lcm_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80000; +} + +static void +Opcode_lcm_xu_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c001; +} + +static void +Opcode_lcm_xu_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_lcm_xu_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c001; +} + +static void +Opcode_lcm_xu_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_lcm_xu_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000; +} + +static void +Opcode_lcm_xu_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_lcm_xu_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41c000; +} + +static void +Opcode_lp_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70200; +} + +static void +Opcode_lp_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340005; +} + +static void +Opcode_lp_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80000; +} + +static void +Opcode_lp_x_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x424000; +} + +static void +Opcode_lq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70400; +} + +static void +Opcode_lq_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340009; +} + +static void +Opcode_lq_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80000; +} + +static void +Opcode_lq_x_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x428000; +} + +static void +Opcode_lut0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d0000; +} + +static void +Opcode_lut0_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42c000; +} + +static void +Opcode_lut1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0000; +} + +static void +Opcode_lut1_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x434000; +} + +static void +Opcode_lut2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d0000; +} + +static void +Opcode_lut2_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x438000; +} + +static void +Opcode_lut3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c0000; +} + +static void +Opcode_lut3_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x43c000; +} + +static void +Opcode_sac2x32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0000; +} + +static void +Opcode_sac2x32_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_sac2x32_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_sac2x32_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0001; +} + +static void +Opcode_sac2x64_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf88000; +} + +static void +Opcode_sac2x64_0_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c002; +} + +static void +Opcode_sac2x64_0_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002; +} + +static void +Opcode_sac2x64_0_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x52a000; +} + +static void +Opcode_sac2x64_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d8000; +} + +static void +Opcode_sac2x64_1_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e002; +} + +static void +Opcode_sac2x64_1_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70002; +} + +static void +Opcode_sac2x64_1_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x52c000; +} + +static void +Opcode_sac2x64_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d8000; +} + +static void +Opcode_sac2x64_2_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64002; +} + +static void +Opcode_sac2x64_2_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a002; +} + +static void +Opcode_sac2x64_2_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x52e000; +} + +static void +Opcode_sac2x64_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac8000; +} + +static void +Opcode_sac2x64_3_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68002; +} + +static void +Opcode_sac2x64_3_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c002; +} + +static void +Opcode_sac2x64_3_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x532000; +} + +static void +Opcode_sac32_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd0000; +} + +static void +Opcode_sac32_r_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8001; +} + +static void +Opcode_sac32_r_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8001; +} + +static void +Opcode_sac32_r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c8001; +} + +static void +Opcode_sac_ih_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d0000; +} + +static void +Opcode_sac_ih_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002; +} + +static void +Opcode_sac_ih_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002; +} + +static void +Opcode_sac_ih_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4a8000; +} + +static void +Opcode_sac_il_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6d8000; +} + +static void +Opcode_sac_il_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18002; +} + +static void +Opcode_sac_il_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18002; +} + +static void +Opcode_sac_il_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b0000; +} + +static void +Opcode_sac_rh_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d0000; +} + +static void +Opcode_sac_rh_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a002; +} + +static void +Opcode_sac_rh_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1a002; +} + +static void +Opcode_sac_rh_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4aa000; +} + +static void +Opcode_sac_rl_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac0000; +} + +static void +Opcode_sac_rl_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28002; +} + +static void +Opcode_sac_rl_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28002; +} + +static void +Opcode_sac_rl_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b2000; +} + +static void +Opcode_scm_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d0000; +} + +static void +Opcode_scm_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_scm_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4003; +} + +static void +Opcode_scm_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_scm_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc001; +} + +static void +Opcode_scm_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_scm_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4b8000; +} + +static void +Opcode_scm_pinc_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0000; +} + +static void +Opcode_scm_pinc_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001; +} + +static void +Opcode_scm_pinc_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001; +} + +static void +Opcode_scm_pinc_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_scm_pinc_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d0001; +} + +static void +Opcode_scm_pinc_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x780000; +} + +static void +Opcode_scm_pinc_x_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002; +} + +static void +Opcode_scm_pinc_x_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14002; +} + +static void +Opcode_scm_pinc_x_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14001; +} + +static void +Opcode_scm_pinc_x_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4bc000; +} + +static void +Opcode_scm_u_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c0000; +} + +static void +Opcode_scm_u_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20001; +} + +static void +Opcode_scm_u_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002; +} + +static void +Opcode_scm_u_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20001; +} + +static void +Opcode_scm_u_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_scm_u_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002; +} + +static void +Opcode_scm_u_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3e0001; +} + +static void +Opcode_scm_x_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980000; +} + +static void +Opcode_scm_x_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30002; +} + +static void +Opcode_scm_x_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_scm_x_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30002; +} + +static void +Opcode_scm_x_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4003; +} + +static void +Opcode_scm_x_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18001; +} + +static void +Opcode_scm_x_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8001; +} + +static void +Opcode_scm_x_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c4000; +} + +static void +Opcode_scm_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb80000; +} + +static void +Opcode_scm_xu_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24002; +} + +static void +Opcode_scm_xu_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_scm_xu_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x24002; +} + +static void +Opcode_scm_xu_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_scm_xu_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c001; +} + +static void +Opcode_scm_xu_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc001; +} + +static void +Opcode_scm_xu_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c8000; +} + +static void +Opcode_store_p_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c0000; +} + +static void +Opcode_store_p_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48002; +} + +static void +Opcode_store_p_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4dc000; +} + +static void +Opcode_store_q_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0000; +} + +static void +Opcode_store_q_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x50002; +} + +static void +Opcode_store_q_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e4000; +} + +static void +Opcode_ar2cm_dup_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a000; +} + +static void +Opcode_ar2cm_dup_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c080; +} + +static void +Opcode_ar2cm_dup_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5400; +} + +static void +Opcode_ar2cm_dup_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40001; +} + +static void +Opcode_ar2cm_dup_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf002; +} + +static void +Opcode_ar2cm_dup_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38100; +} + +static void +Opcode_ar2cm_dup_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5400; +} + +static void +Opcode_ar2cm_dup_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40001; +} + +static void +Opcode_ar2cm_dup_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x53001; +} + +static void +Opcode_ar2cm_dup_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4102; +} + +static void +Opcode_ar2cm_dup_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb003; +} + +static void +Opcode_ar2cm_dup_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1000c0; +} + +static void +Opcode_ar2cm_dup_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c6801; +} + +static void +Opcode_ar2cm_ln_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64000; +} + +static void +Opcode_ar2cm_ln_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e000; +} + +static void +Opcode_ar2cm_ln_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ar2cm_ln_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002; +} + +static void +Opcode_ar2cm_ln_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe002; +} + +static void +Opcode_ar2cm_ln_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c000; +} + +static void +Opcode_ar2cm_ln_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_ar2cm_ln_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002; +} + +static void +Opcode_ar2cm_ln_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c001; +} + +static void +Opcode_ar2cm_ln_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_ar2cm_ln_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa003; +} + +static void +Opcode_ar2cm_ln_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01001; +} + +static void +Opcode_ar2cm_ln_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c3001; +} + +static void +Opcode_ar2cm_ln_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c000; +} + +static void +Opcode_ar2cm_ln_i_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_ar2cm_ln_i_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000; +} + +static void +Opcode_ar2cm_ln_i_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d001; +} + +static void +Opcode_ar2cm_ln_i_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c7001; +} + +static void +Opcode_ar2cm_ln_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164000; +} + +static void +Opcode_ar2cm_ln_r_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_ar2cm_ln_r_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb000; +} + +static void +Opcode_ar2cm_ln_r_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e001; +} + +static void +Opcode_ar2cm_ln_r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2cb001; +} + +static void +Opcode_ar2pq_ln_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x30000; +} + +static void +Opcode_ar2pq_ln_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_ar2pq_ln_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_ar2sar_dup_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32e00; +} + +static void +Opcode_ar2sar_dup_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12401; +} + +static void +Opcode_ar2sar_dup_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ed00; +} + +static void +Opcode_ar2sar_dup_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c01; +} + +static void +Opcode_ar2sar_dup_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4942; +} + +static void +Opcode_ar2sar_dup_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00c0; +} + +static void +Opcode_clrac_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a080; +} + +static void +Opcode_clrac_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d780; +} + +static void +Opcode_clrac_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf803; +} + +static void +Opcode_clrac_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d780; +} + +static void +Opcode_clrac_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f6801; +} + +static void +Opcode_clrcm_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b600; +} + +static void +Opcode_clrcm_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3403c; +} + +static void +Opcode_clrcm_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d430; +} + +static void +Opcode_clrcm_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81d4; +} + +static void +Opcode_clrcm_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8033; +} + +static void +Opcode_clrcm_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34018; +} + +static void +Opcode_clrcm_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d430; +} + +static void +Opcode_clrcm_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_clrcm_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b00; +} + +static void +Opcode_clrcm_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8254; +} + +static void +Opcode_clrcm_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58015; +} + +static void +Opcode_clrcm_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9; +} + +static void +Opcode_clrcm_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc43b; +} + +static void +Opcode_clrcm_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800ec; +} + +static void +Opcode_clrcm_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dec01; +} + +static void +Opcode_cm2ar_ln_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd0000; +} + +static void +Opcode_cm2ar_ln_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34000; +} + +static void +Opcode_cm2ar_ln_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40010; +} + +static void +Opcode_cm2ar_ln_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc010; +} + +static void +Opcode_cm2ar_ln_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8003; +} + +static void +Opcode_cm2ar_ln_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34000; +} + +static void +Opcode_cm2ar_ln_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40010; +} + +static void +Opcode_cm2ar_ln_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc010; +} + +static void +Opcode_cm2ar_ln_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54001; +} + +static void +Opcode_cm2ar_ln_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8002; +} + +static void +Opcode_cm2ar_ln_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc003; +} + +static void +Opcode_cm2ar_ln_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140032; +} + +static void +Opcode_cm2ar_ln_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x344011; +} + +static void +Opcode_cm2ar_ln_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd0400; +} + +static void +Opcode_cm2ar_ln_i_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40030; +} + +static void +Opcode_cm2ar_ln_i_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40030; +} + +static void +Opcode_cm2ar_ln_i_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58001; +} + +static void +Opcode_cm2ar_ln_i_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x344031; +} + +static void +Opcode_cm2ar_ln_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbd0800; +} + +static void +Opcode_cm2ar_ln_r_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44010; +} + +static void +Opcode_cm2ar_ln_r_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44010; +} + +static void +Opcode_cm2ar_ln_r_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54011; +} + +static void +Opcode_cm2ar_ln_r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34c011; +} + +static void +Opcode_comb_ar_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c0000; +} + +static void +Opcode_comb_ar_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001; +} + +static void +Opcode_comb_ar_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001; +} + +static void +Opcode_comb_ar_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_comb_ar_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x480000; +} + +static void +Opcode_conj_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170300; +} + +static void +Opcode_conj_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001d; +} + +static void +Opcode_conj_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44008; +} + +static void +Opcode_conj_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8054; +} + +static void +Opcode_conj_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8013; +} + +static void +Opcode_conj_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001d; +} + +static void +Opcode_conj_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44008; +} + +static void +Opcode_conj_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_conj_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81; +} + +static void +Opcode_conj_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8054; +} + +static void +Opcode_conj_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54025; +} + +static void +Opcode_conj_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d; +} + +static void +Opcode_conj_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc013; +} + +static void +Opcode_conj_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800c4; +} + +static void +Opcode_conj_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34002d; +} + +static void +Opcode_mov2ac32_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd0020; +} + +static void +Opcode_mov2ac32_i_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c042; +} + +static void +Opcode_mov2ac32_i_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c042; +} + +static void +Opcode_mov2ac32_i_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100142; +} + +static void +Opcode_mov2ac32_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd0040; +} + +static void +Opcode_mov2ac32_r_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c082; +} + +static void +Opcode_mov2ac32_r_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c082; +} + +static void +Opcode_mov2ac32_r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200142; +} + +static void +Opcode_mov2cm2pq_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x801; +} + +static void +Opcode_mov2cm2pq_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0; +} + +static void +Opcode_mov2cm2pq_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0; +} + +static void +Opcode_movac_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970b80; +} + +static void +Opcode_movac_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a042; +} + +static void +Opcode_movac_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e202; +} + +static void +Opcode_movac_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc142; +} + +static void +Opcode_movac_i_Slot_llr_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_movac_i2r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x978b80; +} + +static void +Opcode_movac_r_Slot_llr_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2020; +} + +static void +Opcode_movac_r2i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70380; +} + +static void +Opcode_movar2_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c100; +} + +static void +Opcode_movar2_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001; +} + +static void +Opcode_movar2_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38200; +} + +static void +Opcode_movar2_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001; +} + +static void +Opcode_movar2_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc402; +} + +static void +Opcode_movar2_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00c0; +} + +static void +Opcode_movcm_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170b00; +} + +static void +Opcode_movcm_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40099; +} + +static void +Opcode_movcm_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002c; +} + +static void +Opcode_movcm_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8114; +} + +static void +Opcode_movcm_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8023; +} + +static void +Opcode_movcm_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40099; +} + +static void +Opcode_movcm_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002c; +} + +static void +Opcode_movcm_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_movcm_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101; +} + +static void +Opcode_movcm_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8114; +} + +static void +Opcode_movcm_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54029; +} + +static void +Opcode_movcm_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x99; +} + +static void +Opcode_movcm_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc023; +} + +static void +Opcode_movcm_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800e0; +} + +static void +Opcode_movcm_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34400d; +} + +static void +Opcode_movcm2pq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70600; +} + +static void +Opcode_movcm2pq_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc02; +} + +static void +Opcode_movcm2pq_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4181; +} + +static void +Opcode_movcm2pq_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_movcm2pq_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4181; +} + +static void +Opcode_movcm2pq_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x182; +} + +static void +Opcode_movcnd_0_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001; +} + +static void +Opcode_movcnd_0_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4240; +} + +static void +Opcode_movcnd_0_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2801; +} + +static void +Opcode_movcnd_0_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4240; +} + +static void +Opcode_movcnd_0_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c3; +} + +static void +Opcode_movcnd_0_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x281c01; +} + +static void +Opcode_movcnd_1_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c01; +} + +static void +Opcode_movcnd_1_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4280; +} + +static void +Opcode_movcnd_1_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3001; +} + +static void +Opcode_movcnd_1_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4280; +} + +static void +Opcode_movcnd_1_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x243; +} + +static void +Opcode_movcnd_1_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x301c01; +} + +static void +Opcode_movcnd_2_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3401; +} + +static void +Opcode_movcnd_2_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4300; +} + +static void +Opcode_movcnd_2_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c01; +} + +static void +Opcode_movcnd_2_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4300; +} + +static void +Opcode_movcnd_2_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x283; +} + +static void +Opcode_movcnd_2_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c1c01; +} + +static void +Opcode_movcnd_3_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801; +} + +static void +Opcode_movcnd_3_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42c0; +} + +static void +Opcode_movcnd_3_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3401; +} + +static void +Opcode_movcnd_3_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x42c0; +} + +static void +Opcode_movcnd_3_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x303; +} + +static void +Opcode_movcnd_3_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x341c01; +} + +static void +Opcode_movcnd_4_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c01; +} + +static void +Opcode_movcnd_4_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4340; +} + +static void +Opcode_movcnd_4_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3801; +} + +static void +Opcode_movcnd_4_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4340; +} + +static void +Opcode_movcnd_4_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c3; +} + +static void +Opcode_movcnd_4_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x381c01; +} + +static void +Opcode_movcnd_5_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_movcnd_5_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4380; +} + +static void +Opcode_movcnd_5_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c01; +} + +static void +Opcode_movcnd_5_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4380; +} + +static void +Opcode_movcnd_5_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x343; +} + +static void +Opcode_movcnd_5_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c1c01; +} + +static void +Opcode_movcnd_6_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402; +} + +static void +Opcode_movcnd_6_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x43c0; +} + +static void +Opcode_movcnd_6_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_movcnd_6_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x43c0; +} + +static void +Opcode_movcnd_6_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x383; +} + +static void +Opcode_movcnd_6_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401401; +} + +static void +Opcode_movcnd_7_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x802; +} + +static void +Opcode_movcnd_7_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001; +} + +static void +Opcode_movcnd_7_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402; +} + +static void +Opcode_movcnd_7_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001; +} + +static void +Opcode_movcnd_7_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c3; +} + +static void +Opcode_movcnd_7_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401801; +} + +static void +Opcode_movcnd8_0_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1001; +} + +static void +Opcode_movcnd8_0_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4040; +} + +static void +Opcode_movcnd8_0_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x801; +} + +static void +Opcode_movcnd8_0_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4040; +} + +static void +Opcode_movcnd8_0_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_movcnd8_0_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81c01; +} + +static void +Opcode_movcnd8_1_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2001; +} + +static void +Opcode_movcnd8_1_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4080; +} + +static void +Opcode_movcnd8_1_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1001; +} + +static void +Opcode_movcnd8_1_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4080; +} + +static void +Opcode_movcnd8_1_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x43; +} + +static void +Opcode_movcnd8_1_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x101c01; +} + +static void +Opcode_movcnd8_2_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01; +} + +static void +Opcode_movcnd8_2_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100; +} + +static void +Opcode_movcnd8_2_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2001; +} + +static void +Opcode_movcnd8_2_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4100; +} + +static void +Opcode_movcnd8_2_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x83; +} + +static void +Opcode_movcnd8_2_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x201c01; +} + +static void +Opcode_movcnd8_3_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1401; +} + +static void +Opcode_movcnd8_3_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4200; +} + +static void +Opcode_movcnd8_3_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01; +} + +static void +Opcode_movcnd8_3_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4200; +} + +static void +Opcode_movcnd8_3_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x103; +} + +static void +Opcode_movcnd8_3_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1c01; +} + +static void +Opcode_movcnd8_4_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1801; +} + +static void +Opcode_movcnd8_4_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40c0; +} + +static void +Opcode_movcnd8_4_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1401; +} + +static void +Opcode_movcnd8_4_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40c0; +} + +static void +Opcode_movcnd8_4_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x203; +} + +static void +Opcode_movcnd8_4_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x141c01; +} + +static void +Opcode_movcnd8_5_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01; +} + +static void +Opcode_movcnd8_5_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4140; +} + +static void +Opcode_movcnd8_5_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1801; +} + +static void +Opcode_movcnd8_5_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4140; +} + +static void +Opcode_movcnd8_5_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3; +} + +static void +Opcode_movcnd8_5_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x181c01; +} + +static void +Opcode_movcnd8_6_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2401; +} + +static void +Opcode_movcnd8_6_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4180; +} + +static void +Opcode_movcnd8_6_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01; +} + +static void +Opcode_movcnd8_6_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4180; +} + +static void +Opcode_movcnd8_6_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x143; +} + +static void +Opcode_movcnd8_6_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c1c01; +} + +static void +Opcode_movcnd8_7_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2801; +} + +static void +Opcode_movcnd8_7_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41c0; +} + +static void +Opcode_movcnd8_7_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2401; +} + +static void +Opcode_movcnd8_7_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41c0; +} + +static void +Opcode_movcnd8_7_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x183; +} + +static void +Opcode_movcnd8_7_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x241c01; +} + +static void +Opcode_mov_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370300; +} + +static void +Opcode_mov_i_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4800c; +} + +static void +Opcode_mov_i_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8017; +} + +static void +Opcode_mov_i_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4800c; +} + +static void +Opcode_mov_i_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54031; +} + +static void +Opcode_mov_i_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc017; +} + +static void +Opcode_mov_i_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34800d; +} + +static void +Opcode_movpq2pq_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f400; +} + +static void +Opcode_movpq2pq_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10801; +} + +static void +Opcode_movpq2pq_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10801; +} + +static void +Opcode_mov_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x570300; +} + +static void +Opcode_mov_r_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000c; +} + +static void +Opcode_mov_r_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x801b; +} + +static void +Opcode_mov_r_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5000c; +} + +static void +Opcode_mov_r_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5402d; +} + +static void +Opcode_mov_r_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc01b; +} + +static void +Opcode_mov_r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35000d; +} + +static void +Opcode_negcm_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970300; +} + +static void +Opcode_negcm_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40219; +} + +static void +Opcode_negcm_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4802c; +} + +static void +Opcode_negcm_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d4; +} + +static void +Opcode_negcm_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8027; +} + +static void +Opcode_negcm_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40219; +} + +static void +Opcode_negcm_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4802c; +} + +static void +Opcode_negcm_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21; +} + +static void +Opcode_negcm_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x201; +} + +static void +Opcode_negcm_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d4; +} + +static void +Opcode_negcm_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54039; +} + +static void +Opcode_negcm_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x219; +} + +static void +Opcode_negcm_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc027; +} + +static void +Opcode_negcm_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800e4; +} + +static void +Opcode_negcm_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34402d; +} + +static void +Opcode_pop16llr_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a180; +} + +static void +Opcode_pop16llr_1_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d7a0; +} + +static void +Opcode_pop16llr_1_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3d7a0; +} + +static void +Opcode_pop16llr_1_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11040; +} + +static void +Opcode_pop16llr_1_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e6c41; +} + +static void +Opcode_pq2cm_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x62000; +} + +static void +Opcode_pq2cm_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34028; +} + +static void +Opcode_pq2cm_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88018; +} + +static void +Opcode_pq2cm_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_pq2cm_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x88018; +} + +static void +Opcode_pq2cm_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002; +} + +static void +Opcode_pq2cm_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x440080; +} + +static void +Opcode_swapac_r_Slot_acc2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; +} + +static void +Opcode_swapac_ri_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb70b00; +} + +static void +Opcode_swapac_ri_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a082; +} + +static void +Opcode_swapac_ri_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e142; +} + +static void +Opcode_swapac_ri_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc162; +} + +static void +Opcode_swapb_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd0010; +} + +static void +Opcode_swapb_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0c0; +} + +static void +Opcode_swapb_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11801; +} + +static void +Opcode_swapb_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38140; +} + +static void +Opcode_swapb_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11401; +} + +static void +Opcode_swapb_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd402; +} + +static void +Opcode_swapb_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80c0; +} + +static void +Opcode_add2ac_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_addac_Slot_llr_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_cdot_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_cdotac_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_cdotacs_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_cmac_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_cmac_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001; +} + +static void +Opcode_cmacs_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_cmpy_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_cmpy_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8001; +} + +static void +Opcode_cmpy2cm_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc001; +} + +static void +Opcode_cmpy2cm_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_cmpy2pq_Slot_pq_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_cmpys_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2001; +} + +static void +Opcode_cmpyxp2pq_Slot_pq_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_comb32_Slot_llr_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_dot_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_dotac_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20000; +} + +static void +Opcode_dotacs_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20001; +} + +static void +Opcode_lin_int_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_llrpre1_Slot_acc2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_llrpre2_Slot_llr_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000; +} + +static void +Opcode_mac_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_mac_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6001; +} + +static void +Opcode_mac8_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_macd8_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20002; +} + +static void +Opcode_macpqxp_0_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20003; +} + +static void +Opcode_macpqxp_1_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_macpqxp_2_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40001; +} + +static void +Opcode_macpqxp_3_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002; +} + +static void +Opcode_macs_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_macxp2_0_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40003; +} + +static void +Opcode_macxp2_1_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60000; +} + +static void +Opcode_macxp_0_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2003; +} + +static void +Opcode_macxp_1_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_macxp_2_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6000; +} + +static void +Opcode_macxp_3_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001; +} + +static void +Opcode_mov2ac_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc010; +} + +static void +Opcode_mpy_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6001; +} + +static void +Opcode_mpy_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa001; +} + +static void +Opcode_mpy2cm_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc003; +} + +static void +Opcode_mpy2cm_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_mpy2pq_Slot_pq_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_mpy8_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_mpyadd8_2cm_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_mpyadd8_2cm_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_mpyd8_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001; +} + +static void +Opcode_mpypqxp_0_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60002; +} + +static void +Opcode_mpypqxp_1_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60003; +} + +static void +Opcode_mpypqxp_2_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80000; +} + +static void +Opcode_mpypqxp_3_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80001; +} + +static void +Opcode_mpys_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002; +} + +static void +Opcode_mpyxp2pq_Slot_pq_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; +} + +static void +Opcode_mpyxp2_0_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80002; +} + +static void +Opcode_mpyxp2_1_Slot_dot_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80003; +} + +static void +Opcode_mpyxp_0_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4003; +} + +static void +Opcode_mpyxp_1_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6003; +} + +static void +Opcode_mpyxp_2_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_mpyxp_3_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa000; +} + +static void +Opcode_normacd_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8001; +} + +static void +Opcode_normacd_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc001; +} + +static void +Opcode_normacpq_i_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe000; +} + +static void +Opcode_normacpq_r_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe040; +} + +static void +Opcode_normd_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa001; +} + +static void +Opcode_normd_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe001; +} + +static void +Opcode_normpypq_i_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe080; +} + +static void +Opcode_normpypq_r_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe100; +} + +static void +Opcode_rcmac_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8002; +} + +static void +Opcode_rcmpy_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_rcmpy2cm_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001; +} + +static void +Opcode_rcmpy2cm_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_rfir_Slot_acc2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_rfira_Slot_acc2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_rfird_Slot_acc2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_rfirda_Slot_acc2_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_rmac_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8003; +} + +static void +Opcode_rmpy_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa003; +} + +static void +Opcode_rmpy2cm_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10002; +} + +static void +Opcode_rmpy2cm_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_smod_align_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_smod_scr_Slot_smod_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_sub2ac_Slot_gp_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc020; +} + +static void +Opcode_wght32_Slot_llr_slot1_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_clrtiep_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b000; +} + +static void +Opcode_clrtiep_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32c00; +} + +static void +Opcode_clrtiep_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12801; +} + +static void +Opcode_clrtiep_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2f000; +} + +static void +Opcode_clrtiep_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12801; +} + +static void +Opcode_clrtiep_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4202; +} + +static void +Opcode_clrtiep_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280; +} + +static void +Opcode_ext_2fifo_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x470600; +} + +static void +Opcode_ext_2fifo_0_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54008; +} + +static void +Opcode_ext_2fifo_0_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc02; +} + +static void +Opcode_ext_2fifo_0_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54008; +} + +static void +Opcode_ext_2fifo_0_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x342019; +} + +static void +Opcode_ext_2fifo_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x870600; +} + +static void +Opcode_ext_2fifo_1_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64008; +} + +static void +Opcode_ext_2fifo_1_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc003; +} + +static void +Opcode_ext_2fifo_1_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64008; +} + +static void +Opcode_ext_2fifo_1_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x348019; +} + +static void +Opcode_ext_2fifo_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170e00; +} + +static void +Opcode_ext_2fifo_2_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46028; +} + +static void +Opcode_ext_2fifo_2_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc403; +} + +static void +Opcode_ext_2fifo_2_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46028; +} + +static void +Opcode_ext_2fifo_2_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x350019; +} + +static void +Opcode_ext_2fifo_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178600; +} + +static void +Opcode_ext_2fifo_3_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c028; +} + +static void +Opcode_ext_2fifo_3_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc803; +} + +static void +Opcode_ext_2fifo_3_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c028; +} + +static void +Opcode_ext_2fifo_3_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x360019; +} + +static void +Opcode_ext_r2fifo_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x178e00; +} + +static void +Opcode_ext_r2fifo_0_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e008; +} + +static void +Opcode_ext_r2fifo_0_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd003; +} + +static void +Opcode_ext_r2fifo_0_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e008; +} + +static void +Opcode_ext_r2fifo_0_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x342039; +} + +static void +Opcode_ext_r2fifo_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270e00; +} + +static void +Opcode_ext_r2fifo_1_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e028; +} + +static void +Opcode_ext_r2fifo_1_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe003; +} + +static void +Opcode_ext_r2fifo_1_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e028; +} + +static void +Opcode_ext_r2fifo_1_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x348039; +} + +static void +Opcode_ext_r2fifo_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x278600; +} + +static void +Opcode_ext_r2fifo_2_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54028; +} + +static void +Opcode_ext_r2fifo_2_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc03; +} + +static void +Opcode_ext_r2fifo_2_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x54028; +} + +static void +Opcode_ext_r2fifo_2_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34a019; +} + +static void +Opcode_ext_r2fifo_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x370600; +} + +static void +Opcode_ext_r2fifo_3_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56008; +} + +static void +Opcode_ext_r2fifo_3_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd403; +} + +static void +Opcode_ext_r2fifo_3_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x56008; +} + +static void +Opcode_ext_r2fifo_3_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34a039; +} + +static void +Opcode_lut_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40180; +} + +static void +Opcode_lut_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0; +} + +static void +Opcode_lut_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40180; +} + +static void +Opcode_lut_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0; +} + +static void +Opcode_lut_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240; +} + +static void +Opcode_lut_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80040; +} + +static void +Opcode_lut_ar_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_lut_ar_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_lut_ar_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10000; +} + +static void +Opcode_lut_ar_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_lut_ar_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_lut_ar_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec002; +} + +static void +Opcode_lut_iext_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401c0; +} + +static void +Opcode_lut_iext_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240; +} + +static void +Opcode_lut_iext_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401c0; +} + +static void +Opcode_lut_iext_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4002; +} + +static void +Opcode_lut_iext_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240; +} + +static void +Opcode_lut_iext_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280; +} + +static void +Opcode_lut_iext_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0040; +} + +static void +Opcode_lut_phasor_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40059; +} + +static void +Opcode_lut_phasor_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8094; +} + +static void +Opcode_lut_phasor_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40059; +} + +static void +Opcode_lut_phasor_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_lut_phasor_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8094; +} + +static void +Opcode_lut_phasor_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59; +} + +static void +Opcode_lut_phasor_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800c8; +} + +static void +Opcode_lut_rext_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40240; +} + +static void +Opcode_lut_rext_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280; +} + +static void +Opcode_lut_rext_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40240; +} + +static void +Opcode_lut_rext_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x280; +} + +static void +Opcode_lut_rext_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; +} + +static void +Opcode_lut_rext_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe40040; +} + +static void +Opcode_lut_write_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40431; +} + +static void +Opcode_lut_write_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_lut_write_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41031; +} + +static void +Opcode_lut_write_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_lut_write_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x131; +} + +static void +Opcode_lut_write_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800d0; +} + +static void +Opcode_moveq128_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b010; +} + +static void +Opcode_moveq128_0_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32f40; +} + +static void +Opcode_moveq128_0_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd81d4; +} + +static void +Opcode_moveq128_0_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ed80; +} + +static void +Opcode_moveq128_0_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xadd4; +} + +static void +Opcode_moveq128_0_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140dd; +} + +static void +Opcode_moveq128_0_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x818d0; +} + +static void +Opcode_moveq128_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b110; +} + +static void +Opcode_moveq128_1_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32f80; +} + +static void +Opcode_moveq128_1_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe81d4; +} + +static void +Opcode_moveq128_1_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ed84; +} + +static void +Opcode_moveq128_1_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb5d4; +} + +static void +Opcode_moveq128_1_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x144dd; +} + +static void +Opcode_moveq128_1_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x810dc; +} + +static void +Opcode_moveq128_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b210; +} + +static void +Opcode_moveq128_2_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32f44; +} + +static void +Opcode_moveq128_2_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd85d4; +} + +static void +Opcode_moveq128_2_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ed88; +} + +static void +Opcode_moveq128_2_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1add4; +} + +static void +Opcode_moveq128_2_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x148dd; +} + +static void +Opcode_moveq128_2_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x850dc; +} + +static void +Opcode_moveq128_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b410; +} + +static void +Opcode_moveq128_3_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32f48; +} + +static void +Opcode_moveq128_3_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd89d4; +} + +static void +Opcode_moveq128_3_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ed90; +} + +static void +Opcode_moveq128_3_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2add4; +} + +static void +Opcode_moveq128_3_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x150dd; +} + +static void +Opcode_moveq128_3_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x890dc; +} + +static void +Opcode_moveq128_4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b810; +} + +static void +Opcode_moveq128_4_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32f50; +} + +static void +Opcode_moveq128_4_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd91d4; +} + +static void +Opcode_moveq128_4_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2eda0; +} + +static void +Opcode_moveq128_4_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4add4; +} + +static void +Opcode_moveq128_4_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x160dd; +} + +static void +Opcode_moveq128_4_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x910dc; +} + +static void +Opcode_moveq128_5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b310; +} + +static void +Opcode_moveq128_5_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32f60; +} + +static void +Opcode_moveq128_5_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xda1d4; +} + +static void +Opcode_moveq128_5_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2edc0; +} + +static void +Opcode_moveq128_5_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8add4; +} + +static void +Opcode_moveq128_5_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14cdd; +} + +static void +Opcode_moveq128_5_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa10dc; +} + +static void +Opcode_moveq32_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b510; +} + +static void +Opcode_moveq32_0_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32f4c; +} + +static void +Opcode_moveq32_0_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd8dd4; +} + +static void +Opcode_moveq32_0_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ed8c; +} + +static void +Opcode_moveq32_0_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3add4; +} + +static void +Opcode_moveq32_0_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x154dd; +} + +static void +Opcode_moveq32_0_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8d0dc; +} + +static void +Opcode_moveq32_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b610; +} + +static void +Opcode_moveq32_1_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32f54; +} + +static void +Opcode_moveq32_1_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd95d4; +} + +static void +Opcode_moveq32_1_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ed94; +} + +static void +Opcode_moveq32_1_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5add4; +} + +static void +Opcode_moveq32_1_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x158dd; +} + +static void +Opcode_moveq32_1_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x950dc; +} + +static void +Opcode_moveq32_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b710; +} + +static void +Opcode_moveq32_2_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32f58; +} + +static void +Opcode_moveq32_2_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd99d4; +} + +static void +Opcode_moveq32_2_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ed98; +} + +static void +Opcode_moveq32_2_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6add4; +} + +static void +Opcode_moveq32_2_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15cdd; +} + +static void +Opcode_moveq32_2_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x990dc; +} + +static void +Opcode_moveq32_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16b910; +} + +static void +Opcode_moveq32_3_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32f5c; +} + +static void +Opcode_moveq32_3_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd9dd4; +} + +static void +Opcode_moveq32_3_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ed9c; +} + +static void +Opcode_moveq32_3_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7add4; +} + +static void +Opcode_moveq32_3_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x164dd; +} + +static void +Opcode_moveq32_3_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d0dc; +} + +static void +Opcode_nco_update_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40119; +} + +static void +Opcode_nco_update_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8214; +} + +static void +Opcode_nco_update_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40119; +} + +static void +Opcode_nco_update_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11; +} + +static void +Opcode_nco_update_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8214; +} + +static void +Opcode_nco_update_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x119; +} + +static void +Opcode_nco_update_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800cc; +} + +static void +Opcode_pop128_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263000; +} + +static void +Opcode_pop128_0_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x341bc; +} + +static void +Opcode_pop128_0_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35420; +} + +static void +Opcode_pop128_0_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x681d4; +} + +static void +Opcode_pop128_0_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x902f; +} + +static void +Opcode_pop128_0_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3409c; +} + +static void +Opcode_pop128_0_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35420; +} + +static void +Opcode_pop128_0_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40d; +} + +static void +Opcode_pop128_0_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b40; +} + +static void +Opcode_pop128_0_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38254; +} + +static void +Opcode_pop128_0_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58c15; +} + +static void +Opcode_pop128_0_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80dd; +} + +static void +Opcode_pop128_0_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc83f; +} + +static void +Opcode_pop128_0_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x980ec; +} + +static void +Opcode_pop128_0_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dec0d; +} + +static void +Opcode_pop128_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x26a000; +} + +static void +Opcode_pop128_1_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x341fc; +} + +static void +Opcode_pop128_1_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35414; +} + +static void +Opcode_pop128_1_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x781d4; +} + +static void +Opcode_pop128_1_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa02f; +} + +static void +Opcode_pop128_1_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340d8; +} + +static void +Opcode_pop128_1_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35414; +} + +static void +Opcode_pop128_1_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80d; +} + +static void +Opcode_pop128_1_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2b80; +} + +static void +Opcode_pop128_1_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58254; +} + +static void +Opcode_pop128_1_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59415; +} + +static void +Opcode_pop128_1_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0d9; +} + +static void +Opcode_pop128_1_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc3b; +} + +static void +Opcode_pop128_1_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0ec; +} + +static void +Opcode_pop128_1_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dec15; +} + +static void +Opcode_pop128_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x362000; +} + +static void +Opcode_pop128_2_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3427c; +} + +static void +Opcode_pop128_2_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35418; +} + +static void +Opcode_pop128_2_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x981d4; +} + +static void +Opcode_pop128_2_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8c2f; +} + +static void +Opcode_pop128_2_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340dc; +} + +static void +Opcode_pop128_2_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35418; +} + +static void +Opcode_pop128_2_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100d; +} + +static void +Opcode_pop128_2_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2bc0; +} + +static void +Opcode_pop128_2_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68254; +} + +static void +Opcode_pop128_2_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59815; +} + +static void +Opcode_pop128_2_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0dd; +} + +static void +Opcode_pop128_2_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc3f; +} + +static void +Opcode_pop128_2_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa40ec; +} + +static void +Opcode_pop128_2_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dec19; +} + +static void +Opcode_pop128_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263100; +} + +static void +Opcode_pop128_3_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x342bc; +} + +static void +Opcode_pop128_3_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3541c; +} + +static void +Opcode_pop128_3_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa81d4; +} + +static void +Opcode_pop128_3_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x942f; +} + +static void +Opcode_pop128_3_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3411c; +} + +static void +Opcode_pop128_3_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3541c; +} + +static void +Opcode_pop128_3_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200d; +} + +static void +Opcode_pop128_3_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c80; +} + +static void +Opcode_pop128_3_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78254; +} + +static void +Opcode_pop128_3_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x59c15; +} + +static void +Opcode_pop128_3_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100dd; +} + +static void +Opcode_pop128_3_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd03f; +} + +static void +Opcode_pop128_3_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa80ec; +} + +static void +Opcode_pop128_3_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dec1d; +} + +static void +Opcode_pop128_4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263200; +} + +static void +Opcode_pop128_4_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3433c; +} + +static void +Opcode_pop128_4_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35424; +} + +static void +Opcode_pop128_4_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc81d4; +} + +static void +Opcode_pop128_4_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x982f; +} + +static void +Opcode_pop128_4_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34158; +} + +static void +Opcode_pop128_4_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35424; +} + +static void +Opcode_pop128_4_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0d; +} + +static void +Opcode_pop128_4_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d00; +} + +static void +Opcode_pop128_4_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x98254; +} + +static void +Opcode_pop128_4_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a415; +} + +static void +Opcode_pop128_4_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140d9; +} + +static void +Opcode_pop128_4_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd43b; +} + +static void +Opcode_pop128_4_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb00ec; +} + +static void +Opcode_pop128_4_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dec25; +} + +static void +Opcode_pop128_5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263400; +} + +static void +Opcode_pop128_5_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x342fc; +} + +static void +Opcode_pop128_5_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35428; +} + +static void +Opcode_pop128_5_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb81d4; +} + +static void +Opcode_pop128_5_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c2f; +} + +static void +Opcode_pop128_5_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34198; +} + +static void +Opcode_pop128_5_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35428; +} + +static void +Opcode_pop128_5_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140d; +} + +static void +Opcode_pop128_5_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e00; +} + +static void +Opcode_pop128_5_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa8254; +} + +static void +Opcode_pop128_5_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a815; +} + +static void +Opcode_pop128_5_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180d9; +} + +static void +Opcode_pop128_5_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd83b; +} + +static void +Opcode_pop128_5_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xac0ec; +} + +static void +Opcode_pop128_5_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dec29; +} + +static void +Opcode_pop128_2cmpq_0_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38000; +} + +static void +Opcode_pop128_2cmpq_0_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8018; +} + +static void +Opcode_pop128_2cmpq_0_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8018; +} + +static void +Opcode_pop128_2cmpq_1_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34010; +} + +static void +Opcode_pop128_2cmpq_1_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18018; +} + +static void +Opcode_pop128_2cmpq_1_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x18018; +} + +static void +Opcode_pop128_2cmpq_2_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34020; +} + +static void +Opcode_pop128_2cmpq_2_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28018; +} + +static void +Opcode_pop128_2cmpq_2_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x28018; +} + +static void +Opcode_pop128_2cmpq_3_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34018; +} + +static void +Opcode_pop128_2cmpq_3_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48018; +} + +static void +Opcode_pop128_2cmpq_3_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x48018; +} + +static void +Opcode_pop128_2m_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0000; +} + +static void +Opcode_pop128_2m_0_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66002; +} + +static void +Opcode_pop128_2m_0_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72002; +} + +static void +Opcode_pop128_2m_0_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c001; +} + +static void +Opcode_pop128_2m_0_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300401; +} + +static void +Opcode_pop128_2m_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc0000; +} + +static void +Opcode_pop128_2m_1_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66402; +} + +static void +Opcode_pop128_2m_1_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x74002; +} + +static void +Opcode_pop128_2m_1_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c401; +} + +static void +Opcode_pop128_2m_1_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300801; +} + +static void +Opcode_pop128_2m_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0000; +} + +static void +Opcode_pop128_2m_2_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66802; +} + +static void +Opcode_pop128_2m_2_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x78002; +} + +static void +Opcode_pop128_2m_2_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c801; +} + +static void +Opcode_pop128_2m_2_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x302401; +} + +static void +Opcode_pop128_2m_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd1000; +} + +static void +Opcode_pop128_2m_3_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x66c02; +} + +static void +Opcode_pop128_2m_3_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x72402; +} + +static void +Opcode_pop128_2m_3_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5e001; +} + +static void +Opcode_pop128_2m_3_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x304401; +} + +static void +Opcode_pop128_2pq_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162080; +} + +static void +Opcode_pop128_2pq_0_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x33400; +} + +static void +Opcode_pop128_2pq_0_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38818; +} + +static void +Opcode_pop128_2pq_0_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3000; +} + +static void +Opcode_pop128_2pq_0_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38418; +} + +static void +Opcode_pop128_2pq_0_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2de801; +} + +static void +Opcode_pop128_2pq_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a000; +} + +static void +Opcode_pop128_2pq_1_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x33408; +} + +static void +Opcode_pop128_2pq_1_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39018; +} + +static void +Opcode_pop128_2pq_1_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2900; +} + +static void +Opcode_pop128_2pq_1_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38c18; +} + +static void +Opcode_pop128_2pq_1_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d6d01; +} + +static void +Opcode_pop128_2pq_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162090; +} + +static void +Opcode_pop128_2pq_2_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x33410; +} + +static void +Opcode_pop128_2pq_2_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a018; +} + +static void +Opcode_pop128_2pq_2_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a00; +} + +static void +Opcode_pop128_2pq_2_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39418; +} + +static void +Opcode_pop128_2pq_2_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d6e01; +} + +static void +Opcode_pop128_2pq_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1620a0; +} + +static void +Opcode_pop128_2pq_3_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x33420; +} + +static void +Opcode_pop128_2pq_3_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38c18; +} + +static void +Opcode_pop128_2pq_3_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c00; +} + +static void +Opcode_pop128_2pq_3_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a418; +} + +static void +Opcode_pop128_2pq_3_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d6d81; +} + +static void +Opcode_pop128_2pq_4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1620c0; +} + +static void +Opcode_pop128_2pq_4_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x33418; +} + +static void +Opcode_pop128_2pq_4_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39418; +} + +static void +Opcode_pop128_2pq_4_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2980; +} + +static void +Opcode_pop128_2pq_4_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39c18; +} + +static void +Opcode_pop128_2pq_4_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d6e81; +} + +static void +Opcode_pop128_2pq_5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1620b0; +} + +static void +Opcode_pop128_2pq_5_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x33428; +} + +static void +Opcode_pop128_2pq_5_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39818; +} + +static void +Opcode_pop128_2pq_5_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a80; +} + +static void +Opcode_pop128_2pq_5_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3ac18; +} + +static void +Opcode_pop128_2pq_5_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d6f01; +} + +static void +Opcode_pop2x128_2pq_01_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263800; +} + +static void +Opcode_pop2x128_2pq_01_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32d80; +} + +static void +Opcode_pop2x128_2pq_01_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12441; +} + +static void +Opcode_pop2x128_2pq_01_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2cc0; +} + +static void +Opcode_pop2x128_2pq_01_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c41; +} + +static void +Opcode_pop2x128_2pq_01_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2de881; +} + +static void +Opcode_pop2x128_2pq_03_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263300; +} + +static void +Opcode_pop2x128_2pq_03_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32dc0; +} + +static void +Opcode_pop2x128_2pq_03_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12481; +} + +static void +Opcode_pop2x128_2pq_03_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d40; +} + +static void +Opcode_pop2x128_2pq_03_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c81; +} + +static void +Opcode_pop2x128_2pq_03_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2de901; +} + +static void +Opcode_pop2x128_2pq_21_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263500; +} + +static void +Opcode_pop2x128_2pq_21_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32e40; +} + +static void +Opcode_pop2x128_2pq_21_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12501; +} + +static void +Opcode_pop2x128_2pq_21_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d80; +} + +static void +Opcode_pop2x128_2pq_21_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d01; +} + +static void +Opcode_pop2x128_2pq_21_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dea01; +} + +static void +Opcode_pop2x128_2pq_23_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x263600; +} + +static void +Opcode_pop2x128_2pq_23_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32e80; +} + +static void +Opcode_pop2x128_2pq_23_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12601; +} + +static void +Opcode_pop2x128_2pq_23_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2dc0; +} + +static void +Opcode_pop2x128_2pq_23_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11e01; +} + +static void +Opcode_pop2x128_2pq_23_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2de8c1; +} + +static void +Opcode_pop32_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf70300; +} + +static void +Opcode_pop32_0_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3437c; +} + +static void +Opcode_pop32_0_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x682ac; +} + +static void +Opcode_pop32_0_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39c18; +} + +static void +Opcode_pop32_0_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x803b; +} + +static void +Opcode_pop32_0_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3415c; +} + +static void +Opcode_pop32_0_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x682ac; +} + +static void +Opcode_pop32_0_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_pop32_0_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc1; +} + +static void +Opcode_pop32_0_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b418; +} + +static void +Opcode_pop32_0_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64065; +} + +static void +Opcode_pop32_0_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x29; +} + +static void +Opcode_pop32_0_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc2ef; +} + +static void +Opcode_pop32_0_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb40ec; +} + +static void +Opcode_pop32_0_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35c00d; +} + +static void +Opcode_pop32_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70b10; +} + +static void +Opcode_pop32_1_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x343bc; +} + +static void +Opcode_pop32_1_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6832c; +} + +static void +Opcode_pop32_1_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x39c1c; +} + +static void +Opcode_pop32_1_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8077; +} + +static void +Opcode_pop32_1_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3419c; +} + +static void +Opcode_pop32_1_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6832c; +} + +static void +Opcode_pop32_1_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; +} + +static void +Opcode_pop32_1_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc5; +} + +static void +Opcode_pop32_1_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b41c; +} + +static void +Opcode_pop32_1_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64069; +} + +static void +Opcode_pop32_1_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x425; +} + +static void +Opcode_pop32_1_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc36f; +} + +static void +Opcode_pop32_1_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb80ec; +} + +static void +Opcode_pop32_1_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3580ad; +} + +static void +Opcode_pop32_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70b20; +} + +static void +Opcode_pop32_2_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x343fc; +} + +static void +Opcode_pop32_2_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x682ec; +} + +static void +Opcode_pop32_2_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a418; +} + +static void +Opcode_pop32_2_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80b7; +} + +static void +Opcode_pop32_2_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x341d8; +} + +static void +Opcode_pop32_2_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x682ec; +} + +static void +Opcode_pop32_2_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_pop32_2_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc9; +} + +static void +Opcode_pop32_2_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3bc18; +} + +static void +Opcode_pop32_2_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x64071; +} + +static void +Opcode_pop32_2_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x825; +} + +static void +Opcode_pop32_2_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc3ef; +} + +static void +Opcode_pop32_2_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc0ec; +} + +static void +Opcode_pop32_2_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35812d; +} + +static void +Opcode_pop32_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70b40; +} + +static void +Opcode_pop32_3_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38008; +} + +static void +Opcode_pop32_3_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6836c; +} + +static void +Opcode_pop32_3_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3a818; +} + +static void +Opcode_pop32_3_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8137; +} + +static void +Opcode_pop32_3_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x341dc; +} + +static void +Opcode_pop32_3_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6836c; +} + +static void +Opcode_pop32_3_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_pop32_3_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd1; +} + +static void +Opcode_pop32_3_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3bc1c; +} + +static void +Opcode_pop32_3_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6406d; +} + +static void +Opcode_pop32_3_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1025; +} + +static void +Opcode_pop32_3_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc037; +} + +static void +Opcode_pop32_3_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800f4; +} + +static void +Opcode_pop32_3_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35822d; +} + +static void +Opcode_push128_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x970b00; +} + +static void +Opcode_push128_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd02; +} + +static void +Opcode_push128_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6c102; +} + +static void +Opcode_push128_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4541; +} + +static void +Opcode_push128_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10040; +} + +static void +Opcode_push128_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40025; +} + +static void +Opcode_push128_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7c102; +} + +static void +Opcode_push128_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; +} + +static void +Opcode_push128_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6; +} + +static void +Opcode_push128_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x81d4; +} + +static void +Opcode_push128_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68001; +} + +static void +Opcode_push128_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x25; +} + +static void +Opcode_push128_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc033; +} + +static void +Opcode_push128_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x481411; +} + +static void +Opcode_push128_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35800d; +} + +static void +Opcode_push128_m_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80000; +} + +static void +Opcode_push128_m_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46002; +} + +static void +Opcode_push128_m_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x46002; +} + +static void +Opcode_push128_m_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x60001; +} + +static void +Opcode_push128_m_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x526000; +} + +static void +Opcode_push128_pq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x162000; +} + +static void +Opcode_push128_pq_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2fc00; +} + +static void +Opcode_push128_pq_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001; +} + +static void +Opcode_push128_pq_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d400; +} + +static void +Opcode_push128_pq_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2400; +} + +static void +Opcode_push128_pq_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38018; +} + +static void +Opcode_push128_pq_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc802; +} + +static void +Opcode_push128_pq_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb803; +} + +static void +Opcode_push128_pq_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c9401; +} + +static void +Opcode_push128_pq_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e6801; +} + +static void +Opcode_push2x128_pq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x862000; +} + +static void +Opcode_push2x128_pq_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x33800; +} + +static void +Opcode_push2x128_pq_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38018; +} + +static void +Opcode_push2x128_pq_Slot_acc2_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2800; +} + +static void +Opcode_push2x128_pq_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x58018; +} + +static void +Opcode_push2x128_pq_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10100; +} + +static void +Opcode_push2x128_pq_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d6c01; +} + +static void +Opcode_push32_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdd0000; +} + +static void +Opcode_push32_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32000; +} + +static void +Opcode_push32_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d400; +} + +static void +Opcode_push32_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12001; +} + +static void +Opcode_push32_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xdc03; +} + +static void +Opcode_push32_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d800; +} + +static void +Opcode_push32_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1d400; +} + +static void +Opcode_push32_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2; +} + +static void +Opcode_push32_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11001; +} + +static void +Opcode_push32_Slot_smod_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5cc01; +} + +static void +Opcode_push32_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd002; +} + +static void +Opcode_push32_Slot_llr_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc03; +} + +static void +Opcode_push32_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d1401; +} + +static void +Opcode_push32_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10142; +} + +static void +Opcode_qready_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70e00; +} + +static void +Opcode_qready_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c000; +} + +static void +Opcode_qready_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001; +} + +static void +Opcode_qready_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38080; +} + +static void +Opcode_qready_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10001; +} + +static void +Opcode_qready_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20002; +} + +static void +Opcode_qready_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x240; +} + +static void +Opcode_rdtiep_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70b80; +} + +static void +Opcode_rdtiep_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x38010; +} + +static void +Opcode_rdtiep_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3b018; +} + +static void +Opcode_rdtiep_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3421c; +} + +static void +Opcode_rdtiep_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x68018; +} + +static void +Opcode_rdtiep_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2025; +} + +static void +Opcode_rdtiep_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800f8; +} + +static void +Opcode_settiep_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b400; +} + +static void +Opcode_settiep_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32c80; +} + +static void +Opcode_settiep_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001; +} + +static void +Opcode_settiep_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ec00; +} + +static void +Opcode_settiep_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x13001; +} + +static void +Opcode_settiep_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4142; +} + +static void +Opcode_settiep_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; +} + +static void +Opcode_smod_lut_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4041; +} + +static void +Opcode_wrtbsigq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a020; +} + +static void +Opcode_wrtbsigq_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32f00; +} + +static void +Opcode_wrtbsigq_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x124c1; +} + +static void +Opcode_wrtbsigq_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ee00; +} + +static void +Opcode_wrtbsigq_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11cc1; +} + +static void +Opcode_wrtbsigq_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5142; +} + +static void +Opcode_wrtbsigq_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcd0c0; +} + +static void +Opcode_wrtbsigqm_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6b800; +} + +static void +Opcode_wrtbsigqm_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32d00; +} + +static void +Opcode_wrtbsigqm_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12841; +} + +static void +Opcode_wrtbsigqm_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ec80; +} + +static void +Opcode_wrtbsigqm_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12841; +} + +static void +Opcode_wrtbsigqm_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4182; +} + +static void +Opcode_wrtbsigqm_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x244; +} + +static void +Opcode_wrtiep_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x262000; +} + +static void +Opcode_wrtiep_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x33000; +} + +static void +Opcode_wrtiep_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11c01; +} + +static void +Opcode_wrtiep_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e800; +} + +static void +Opcode_wrtiep_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11801; +} + +static void +Opcode_wrtiep_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd802; +} + +static void +Opcode_wrtiep_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4d5401; +} + +static void +Opcode_wrtsigq_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x16a040; +} + +static void +Opcode_wrtsigq_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32ec0; +} + +static void +Opcode_wrtsigq_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x12541; +} + +static void +Opcode_wrtsigq_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2ed40; +} + +static void +Opcode_wrtsigq_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11d41; +} + +static void +Opcode_wrtsigq_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6142; +} + +static void +Opcode_wrtsigq_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xce0c0; +} + +static void +Opcode_abs8_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40019; +} + +static void +Opcode_abs8_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8014; +} + +static void +Opcode_abs8_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40019; +} + +static void +Opcode_abs8_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8014; +} + +static void +Opcode_abs8_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x19; +} + +static void +Opcode_abs8_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800c0; +} + +static void +Opcode_add16_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40031; +} + +static void +Opcode_add16_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8030; +} + +static void +Opcode_add16_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40031; +} + +static void +Opcode_add16_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8030; +} + +static void +Opcode_add16_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x31; +} + +static void +Opcode_add16_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x481401; +} + +static void +Opcode_add32_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_add32_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_add32_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_add32_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3; +} + +static void +Opcode_add32_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_add32_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_add32_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc00040; +} + +static void +Opcode_addac_i2r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb78380; +} + +static void +Opcode_addac_i2r_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a00c; +} + +static void +Opcode_addac_i2r_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a00c; +} + +static void +Opcode_addac_i2r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35832d; +} + +static void +Opcode_addac_r2i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb78390; +} + +static void +Opcode_addac_r2i_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a04c; +} + +static void +Opcode_addac_r2i_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a04c; +} + +static void +Opcode_addac_r2i_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3583ad; +} + +static void +Opcode_addar2_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e400; +} + +static void +Opcode_addar2_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20001; +} + +static void +Opcode_addar2_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2d000; +} + +static void +Opcode_addar2_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x20001; +} + +static void +Opcode_addar2_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc002; +} + +static void +Opcode_addar2_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x501401; +} + +static void +Opcode_addcm_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40040; +} + +static void +Opcode_addcm_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; +} + +static void +Opcode_addcm_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40040; +} + +static void +Opcode_addcm_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_addcm_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; +} + +static void +Opcode_addcm_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40; +} + +static void +Opcode_addcm_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc40040; +} + +static void +Opcode_addwrp_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080; +} + +static void +Opcode_addwrp_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_addwrp_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080; +} + +static void +Opcode_addwrp_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_addwrp_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80; +} + +static void +Opcode_addwrp_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc80040; +} + +static void +Opcode_and128_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40100; +} + +static void +Opcode_and128_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; +} + +static void +Opcode_and128_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40100; +} + +static void +Opcode_and128_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; +} + +static void +Opcode_and128_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x100; +} + +static void +Opcode_and128_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd00040; +} + +static void +Opcode_argmax8_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc82; +} + +static void +Opcode_argmax8_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4141; +} + +static void +Opcode_argmax8_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_argmax8_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_argmax8_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4581; +} + +static void +Opcode_argmax8_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40140; +} + +static void +Opcode_argmax8_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2000c0; +} + +static void +Opcode_asl_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40200; +} + +static void +Opcode_asl_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_asl_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40200; +} + +static void +Opcode_asl_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_asl_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x200; +} + +static void +Opcode_asl_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe00040; +} + +static void +Opcode_asl32_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_asl32_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_asl32_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_asl32_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000; +} + +static void +Opcode_asl32_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_asl32_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c01; +} + +static void +Opcode_aslacm_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xbc8000; +} + +static void +Opcode_aslacm_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x70002; +} + +static void +Opcode_aslacm_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e002; +} + +static void +Opcode_aslacm_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x302; +} + +static void +Opcode_aslm_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40001; +} + +static void +Opcode_aslm_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_aslm_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40001; +} + +static void +Opcode_aslm_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8000; +} + +static void +Opcode_aslm_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_aslm_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140002; +} + +static void +Opcode_aslm32_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2002; +} + +static void +Opcode_aslm32_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4301; +} + +static void +Opcode_aslm32_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_aslm32_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4301; +} + +static void +Opcode_aslm32_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40300; +} + +static void +Opcode_aslm32_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400100; +} + +static void +Opcode_asr_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0; +} + +static void +Opcode_asr_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_asr_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0; +} + +static void +Opcode_asr_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4001; +} + +static void +Opcode_asr_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_asr_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140; +} + +static void +Opcode_asr_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc0040; +} + +static void +Opcode_asr32_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401; +} + +static void +Opcode_asr32_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140; +} + +static void +Opcode_asr32_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x401; +} + +static void +Opcode_asr32_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140; +} + +static void +Opcode_asr32_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180; +} + +static void +Opcode_asr32_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x41c01; +} + +static void +Opcode_asrac_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x570b00; +} + +static void +Opcode_asrac_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a002; +} + +static void +Opcode_asrac_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6e102; +} + +static void +Opcode_asrac_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x80142; +} + +static void +Opcode_asrm_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40005; +} + +static void +Opcode_asrm_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8004; +} + +static void +Opcode_asrm_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40005; +} + +static void +Opcode_asrm_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8004; +} + +static void +Opcode_asrm_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5; +} + +static void +Opcode_asrm_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180002; +} + +static void +Opcode_bitfext_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0; +} + +static void +Opcode_bitfins_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1; +} + +static void +Opcode_clb_c_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770300; +} + +static void +Opcode_clb_c_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5802c; +} + +static void +Opcode_clb_c_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe403; +} + +static void +Opcode_clb_c_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5802c; +} + +static void +Opcode_clb_c_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34c02d; +} + +static void +Opcode_clb_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x578b00; +} + +static void +Opcode_clb_r_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a02c; +} + +static void +Opcode_clb_r_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe803; +} + +static void +Opcode_clb_r_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a02c; +} + +static void +Opcode_clb_r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x34e02d; +} + +static void +Opcode_cmp8_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40009; +} + +static void +Opcode_cmp8_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8008; +} + +static void +Opcode_cmp8_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40009; +} + +static void +Opcode_cmp8_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8008; +} + +static void +Opcode_cmp8_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9; +} + +static void +Opcode_cmp8_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140006; +} + +static void +Opcode_cmp_i_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40011; +} + +static void +Opcode_cmp_i_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010; +} + +static void +Opcode_cmp_i_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40011; +} + +static void +Opcode_cmp_i_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8010; +} + +static void +Opcode_cmp_i_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11; +} + +static void +Opcode_cmp_i_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000a; +} + +static void +Opcode_cmp_r_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40021; +} + +static void +Opcode_cmp_r_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8020; +} + +static void +Opcode_cmp_r_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40021; +} + +static void +Opcode_cmp_r_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8020; +} + +static void +Opcode_cmp_r_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x21; +} + +static void +Opcode_cmp_r_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140012; +} + +static void +Opcode_ext_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd80000; +} + +static void +Opcode_ext_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a002; +} + +static void +Opcode_ext_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8002; +} + +static void +Opcode_ext_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2a002; +} + +static void +Opcode_ext_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x524000; +} + +static void +Opcode_ext_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd88000; +} + +static void +Opcode_ext_r_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e002; +} + +static void +Opcode_ext_r_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xa002; +} + +static void +Opcode_ext_r_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e002; +} + +static void +Opcode_ext_r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x528000; +} + +static void +Opcode_ext32_i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x170600; +} + +static void +Opcode_ext32_i_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44028; +} + +static void +Opcode_ext32_i_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf402; +} + +static void +Opcode_ext32_i_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x44028; +} + +static void +Opcode_ext32_i_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340019; +} + +static void +Opcode_ext32_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x270600; +} + +static void +Opcode_ext32_r_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c008; +} + +static void +Opcode_ext32_r_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf802; +} + +static void +Opcode_ext32_r_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4c008; +} + +static void +Opcode_ext32_r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340039; +} + +static void +Opcode_extui4_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40140; +} + +static void +Opcode_extui4_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180; +} + +static void +Opcode_extui4_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40140; +} + +static void +Opcode_extui4_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x180; +} + +static void +Opcode_extui4_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1c0; +} + +static void +Opcode_extui4_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd40040; +} + +static void +Opcode_lslm_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000d; +} + +static void +Opcode_lslm_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_lslm_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4000d; +} + +static void +Opcode_lslm_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc000; +} + +static void +Opcode_lslm_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd; +} + +static void +Opcode_lslm_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x140022; +} + +static void +Opcode_lsrm_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40015; +} + +static void +Opcode_lsrm_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800c; +} + +static void +Opcode_lsrm_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40015; +} + +static void +Opcode_lsrm_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800c; +} + +static void +Opcode_lsrm_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x15; +} + +static void +Opcode_lsrm_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x14000e; +} + +static void +Opcode_max8_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40280; +} + +static void +Opcode_max8_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; +} + +static void +Opcode_max8_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40280; +} + +static void +Opcode_max8_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x300; +} + +static void +Opcode_max8_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0; +} + +static void +Opcode_max8_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe80040; +} + +static void +Opcode_mean_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40300; +} + +static void +Opcode_mean_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0; +} + +static void +Opcode_mean_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40300; +} + +static void +Opcode_mean_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2c0; +} + +static void +Opcode_mean_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340; +} + +static void +Opcode_mean_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf00040; +} + +static void +Opcode_mean32_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402c0; +} + +static void +Opcode_mean32_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340; +} + +static void +Opcode_mean32_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x402c0; +} + +static void +Opcode_mean32_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x340; +} + +static void +Opcode_mean32_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380; +} + +static void +Opcode_mean32_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec0040; +} + +static void +Opcode_min8_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40340; +} + +static void +Opcode_min8_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380; +} + +static void +Opcode_min8_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40340; +} + +static void +Opcode_min8_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x380; +} + +static void +Opcode_min8_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3c0; +} + +static void +Opcode_min8_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf40040; +} + +static void +Opcode_minclb_c_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x770b00; +} + +static void +Opcode_minclb_c_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002c; +} + +static void +Opcode_minclb_c_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf003; +} + +static void +Opcode_minclb_c_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6002c; +} + +static void +Opcode_minclb_c_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35002d; +} + +static void +Opcode_minclb_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x778300; +} + +static void +Opcode_minclb_r_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800c; +} + +static void +Opcode_minclb_r_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe407; +} + +static void +Opcode_minclb_r_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6800c; +} + +static void +Opcode_minclb_r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35400d; +} + +static void +Opcode_not128_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4005d; +} + +static void +Opcode_not128_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8154; +} + +static void +Opcode_not128_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4005d; +} + +static void +Opcode_not128_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8154; +} + +static void +Opcode_not128_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5d; +} + +static void +Opcode_not128_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800e8; +} + +static void +Opcode_or128_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40380; +} + +static void +Opcode_or128_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8001; +} + +static void +Opcode_or128_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40380; +} + +static void +Opcode_or128_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8001; +} + +static void +Opcode_or128_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40000; +} + +static void +Opcode_or128_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf80040; +} + +static void +Opcode_perm_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x1002; +} + +static void +Opcode_perm_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc001; +} + +static void +Opcode_perm_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x802; +} + +static void +Opcode_perm_Slot_acc2_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4003; +} + +static void +Opcode_perm_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc001; +} + +static void +Opcode_perm_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40001; +} + +static void +Opcode_perm_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x441401; +} + +static void +Opcode_redac_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb783a0; +} + +static void +Opcode_redac_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a08c; +} + +static void +Opcode_redac_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a08c; +} + +static void +Opcode_redac_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a32d; +} + +static void +Opcode_redac2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb783c0; +} + +static void +Opcode_redac2_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a10c; +} + +static void +Opcode_redac2_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a10c; +} + +static void +Opcode_redac2_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35a3ad; +} + +static void +Opcode_redac4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb783b0; +} + +static void +Opcode_redac4_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a20c; +} + +static void +Opcode_redac4_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a20c; +} + +static void +Opcode_redac4_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35806d; +} + +static void +Opcode_redacs_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb783d0; +} + +static void +Opcode_redacs_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0cc; +} + +static void +Opcode_redacs_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a0cc; +} + +static void +Opcode_redacs_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x3580cd; +} + +static void +Opcode_sminclb_c_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x778b00; +} + +static void +Opcode_sminclb_c_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000c; +} + +static void +Opcode_sminclb_c_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe807; +} + +static void +Opcode_sminclb_c_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x7000c; +} + +static void +Opcode_sminclb_c_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35202d; +} + +static void +Opcode_sminclb_r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xd70300; +} + +static void +Opcode_sminclb_r_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6202c; +} + +static void +Opcode_sminclb_r_Slot_dot_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xec03; +} + +static void +Opcode_sminclb_r_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6202c; +} + +static void +Opcode_sminclb_r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35600d; +} + +static void +Opcode_stswapbm_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9c0000; +} + +static void +Opcode_stswapbm_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4e8000; +} + +static void +Opcode_stswapbmu_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xad0000; +} + +static void +Opcode_stswapbmu_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4f0000; +} + +static void +Opcode_sub32_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403c0; +} + +static void +Opcode_sub32_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4041; +} + +static void +Opcode_sub32_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x403c0; +} + +static void +Opcode_sub32_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4081; +} + +static void +Opcode_sub32_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40040; +} + +static void +Opcode_sub32_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xfc0040; +} + +static void +Opcode_subac_i2r_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb783e0; +} + +static void +Opcode_subac_i2r_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a14c; +} + +static void +Opcode_subac_i2r_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a14c; +} + +static void +Opcode_subac_i2r_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35814d; +} + +static void +Opcode_subac_r2i_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xb783f0; +} + +static void +Opcode_subac_r2i_Slot_gp_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a18c; +} + +static void +Opcode_subac_r2i_Slot_pq_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x6a18c; +} + +static void +Opcode_subac_r2i_Slot_dual_slot0_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x35824d; +} + +static void +Opcode_subarx_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x32800; +} + +static void +Opcode_subarx_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x11401; +} + +static void +Opcode_subarx_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x2e400; +} + +static void +Opcode_subarx_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x10c01; +} + +static void +Opcode_subarx_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xcc02; +} + +static void +Opcode_subarx_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4cd401; +} + +static void +Opcode_subcm_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002; +} + +static void +Opcode_subcm_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4081; +} + +static void +Opcode_subcm_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40002; +} + +static void +Opcode_subcm_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4101; +} + +static void +Opcode_subcm_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40080; +} + +static void +Opcode_subcm_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xc0; +} + +static void +Opcode_submean_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40042; +} + +static void +Opcode_submean_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4101; +} + +static void +Opcode_submean_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40042; +} + +static void +Opcode_submean_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4201; +} + +static void +Opcode_submean_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40100; +} + +static void +Opcode_submean_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400080; +} + +static void +Opcode_subwrp_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40082; +} + +static void +Opcode_subwrp_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4201; +} + +static void +Opcode_subwrp_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40082; +} + +static void +Opcode_subwrp_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40c1; +} + +static void +Opcode_subwrp_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40200; +} + +static void +Opcode_subwrp_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800080; +} + +static void +Opcode_trans_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4009d; +} + +static void +Opcode_trans_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8194; +} + +static void +Opcode_trans_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4009d; +} + +static void +Opcode_trans_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x8194; +} + +static void +Opcode_trans_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x9d; +} + +static void +Opcode_trans_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x800f0; +} + +static void +Opcode_xor128_Slot_gp_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40102; +} + +static void +Opcode_xor128_Slot_dot_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40c1; +} + +static void +Opcode_xor128_Slot_pq_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x40102; +} + +static void +Opcode_xor128_Slot_smod_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x4141; +} + +static void +Opcode_xor128_Slot_llr_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0; +} + +static void +Opcode_xor128_Slot_dual_slot2_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x400c0; +} + +static void +Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30000; +} + +static void +Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30000; +} + +static void +Opcode_rur_sov_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30010; +} + +static void +Opcode_wur_sov_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30100; +} + +static void +Opcode_rur_sat_mode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30020; +} + +static void +Opcode_wur_sat_mode_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30200; +} + +static void +Opcode_rur_sar0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30030; +} + +static void +Opcode_wur_sar0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30300; +} + +static void +Opcode_rur_sar1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30040; +} + +static void +Opcode_wur_sar1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30400; +} + +static void +Opcode_rur_sar2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30050; +} + +static void +Opcode_wur_sar2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30500; +} + +static void +Opcode_rur_sar3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30060; +} + +static void +Opcode_wur_sar3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30600; +} + +static void +Opcode_rur_hsar0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30070; +} + +static void +Opcode_wur_hsar0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30700; +} + +static void +Opcode_rur_hsar1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30080; +} + +static void +Opcode_wur_hsar1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30800; +} + +static void +Opcode_rur_hsar2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30090; +} + +static void +Opcode_wur_hsar2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30900; +} + +static void +Opcode_rur_hsar3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe300a0; +} + +static void +Opcode_wur_hsar3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30a00; +} + +static void +Opcode_rur_max_reg_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe300b0; +} + +static void +Opcode_wur_max_reg_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30b00; +} + +static void +Opcode_rur_max_reg_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe300c0; +} + +static void +Opcode_wur_max_reg_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30c00; +} + +static void +Opcode_rur_max_reg_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe300d0; +} + +static void +Opcode_wur_max_reg_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30d00; +} + +static void +Opcode_rur_max_reg_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe300e0; +} + +static void +Opcode_wur_max_reg_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30e00; +} + +static void +Opcode_rur_arg_max_reg_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe300f0; +} + +static void +Opcode_wur_arg_max_reg_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf30f00; +} + +static void +Opcode_rur_arg_max_reg_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30100; +} + +static void +Opcode_wur_arg_max_reg_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31000; +} + +static void +Opcode_rur_arg_max_reg_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30110; +} + +static void +Opcode_wur_arg_max_reg_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31100; +} + +static void +Opcode_rur_arg_max_reg_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30120; +} + +static void +Opcode_wur_arg_max_reg_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31200; +} + +static void +Opcode_rur_nco_counter_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30130; +} + +static void +Opcode_wur_nco_counter_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31300; +} + +static void +Opcode_rur_nco_counter_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30140; +} + +static void +Opcode_wur_nco_counter_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31400; +} + +static void +Opcode_rur_nco_counter_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30150; +} + +static void +Opcode_wur_nco_counter_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31500; +} + +static void +Opcode_rur_nco_counter_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30160; +} + +static void +Opcode_wur_nco_counter_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31600; +} + +static void +Opcode_rur_interp_ext_n_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30170; +} + +static void +Opcode_wur_interp_ext_n_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31700; +} + +static void +Opcode_rur_interp_ext_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30180; +} + +static void +Opcode_wur_interp_ext_l_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31800; +} + +static void +Opcode_rur_llr_buf_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30190; +} + +static void +Opcode_wur_llr_buf_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31900; +} + +static void +Opcode_rur_llr_buf_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe301a0; +} + +static void +Opcode_wur_llr_buf_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31a00; +} + +static void +Opcode_rur_llr_buf_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe301b0; +} + +static void +Opcode_wur_llr_buf_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31b00; +} + +static void +Opcode_rur_llr_buf_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe301c0; +} + +static void +Opcode_wur_llr_buf_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31c00; +} + +static void +Opcode_rur_llr_buf_4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe301d0; +} + +static void +Opcode_wur_llr_buf_4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31d00; +} + +static void +Opcode_rur_llr_buf_5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe301e0; +} + +static void +Opcode_wur_llr_buf_5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31e00; +} + +static void +Opcode_rur_llr_buf_6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe301f0; +} + +static void +Opcode_wur_llr_buf_6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf31f00; +} + +static void +Opcode_rur_llr_buf_7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30200; +} + +static void +Opcode_wur_llr_buf_7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32000; +} + +static void +Opcode_rur_llr_buf_8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30210; +} + +static void +Opcode_wur_llr_buf_8_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32100; +} + +static void +Opcode_rur_llr_buf_9_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30220; +} + +static void +Opcode_wur_llr_buf_9_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32200; +} + +static void +Opcode_rur_llr_buf_10_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30230; +} + +static void +Opcode_wur_llr_buf_10_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32300; +} + +static void +Opcode_rur_llr_buf_11_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30240; +} + +static void +Opcode_wur_llr_buf_11_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32400; +} + +static void +Opcode_rur_llr_buf_12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30250; +} + +static void +Opcode_wur_llr_buf_12_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32500; +} + +static void +Opcode_rur_llr_buf_13_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30260; +} + +static void +Opcode_wur_llr_buf_13_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32600; +} + +static void +Opcode_rur_llr_buf_14_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30270; +} + +static void +Opcode_wur_llr_buf_14_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32700; +} + +static void +Opcode_rur_llr_buf_15_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30280; +} + +static void +Opcode_wur_llr_buf_15_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32800; +} + +static void +Opcode_rur_llr_buf_16_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30290; +} + +static void +Opcode_wur_llr_buf_16_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32900; +} + +static void +Opcode_rur_llr_buf_17_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe302a0; +} + +static void +Opcode_wur_llr_buf_17_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32a00; +} + +static void +Opcode_rur_llr_buf_18_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe302b0; +} + +static void +Opcode_wur_llr_buf_18_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32b00; +} + +static void +Opcode_rur_llr_buf_19_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe302c0; +} + +static void +Opcode_wur_llr_buf_19_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32c00; +} + +static void +Opcode_rur_llr_buf_20_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe302d0; +} + +static void +Opcode_wur_llr_buf_20_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32d00; +} + +static void +Opcode_rur_llr_buf_21_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe302e0; +} + +static void +Opcode_wur_llr_buf_21_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32e00; +} + +static void +Opcode_rur_llr_buf_22_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe302f0; +} + +static void +Opcode_wur_llr_buf_22_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf32f00; +} + +static void +Opcode_rur_llr_buf_23_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30300; +} + +static void +Opcode_wur_llr_buf_23_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33000; +} + +static void +Opcode_rur_smod_buf_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30310; +} + +static void +Opcode_wur_smod_buf_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33100; +} + +static void +Opcode_rur_smod_buf_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30320; +} + +static void +Opcode_wur_smod_buf_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33200; +} + +static void +Opcode_rur_smod_buf_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30330; +} + +static void +Opcode_wur_smod_buf_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33300; +} + +static void +Opcode_rur_smod_buf_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30340; +} + +static void +Opcode_wur_smod_buf_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33400; +} + +static void +Opcode_rur_smod_buf_4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30350; +} + +static void +Opcode_wur_smod_buf_4_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33500; +} + +static void +Opcode_rur_smod_buf_5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30360; +} + +static void +Opcode_wur_smod_buf_5_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33600; +} + +static void +Opcode_rur_smod_buf_6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30370; +} + +static void +Opcode_wur_smod_buf_6_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33700; +} + +static void +Opcode_rur_smod_buf_7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30380; +} + +static void +Opcode_wur_smod_buf_7_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33800; +} + +static void +Opcode_rur_weight_reg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30390; +} + +static void +Opcode_wur_weight_reg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33900; +} + +static void +Opcode_rur_scale_reg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe303a0; +} + +static void +Opcode_wur_scale_reg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33a00; +} + +static void +Opcode_rur_llr_pos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe303b0; +} + +static void +Opcode_wur_llr_pos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33b00; +} + +static void +Opcode_rur_smod_pos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe303c0; +} + +static void +Opcode_wur_smod_pos_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33c00; +} + +static void +Opcode_rur_perm_reg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe303d0; +} + +static void +Opcode_wur_perm_reg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33d00; +} + +static void +Opcode_rur_smod_offset_table_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe303e0; +} + +static void +Opcode_wur_smod_offset_table_0_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33e00; +} + +static void +Opcode_rur_smod_offset_table_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe303f0; +} + +static void +Opcode_wur_smod_offset_table_1_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf33f00; +} + +static void +Opcode_rur_smod_offset_table_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30400; +} + +static void +Opcode_wur_smod_offset_table_2_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf34000; +} + +static void +Opcode_rur_smod_offset_table_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30410; +} + +static void +Opcode_wur_smod_offset_table_3_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf34100; +} + +static void +Opcode_rur_phasor_n_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30420; +} + +static void +Opcode_wur_phasor_n_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf34200; +} + +static void +Opcode_rur_phasor_offset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xe30430; +} + +static void +Opcode_wur_phasor_offset_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf34300; +} + +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { + Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { + Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { + Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { + Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { + Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { + Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { + Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { + Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { + Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { + Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { + Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { + Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { + Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { + Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { + Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { + 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { + Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { + Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { + Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { + Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { + 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { + 0, Opcode_addi_n_Slot_inst16a_encode, 0, Opcode_addi_n_Slot_gp_slot2_encode, 0, Opcode_addi_n_Slot_gp_slot0_encode, 0, 0, Opcode_addi_n_Slot_dot_slot0_encode, Opcode_addi_n_Slot_pq_slot2_encode, 0, Opcode_addi_n_Slot_pq_slot0_encode, 0, 0, Opcode_addi_n_Slot_acc2_slot0_encode, 0, 0, Opcode_addi_n_Slot_smod_slot0_encode, 0, 0, Opcode_addi_n_Slot_llr_slot0_encode, Opcode_addi_n_Slot_dual_slot2_encode, 0, Opcode_addi_n_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { + 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, Opcode_beqz_n_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_beqz_n_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_beqz_n_Slot_smod_slot0_encode, 0, 0, 0, Opcode_beqz_n_Slot_dual_slot2_encode, 0, Opcode_beqz_n_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { + 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, Opcode_bnez_n_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_bnez_n_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_bnez_n_Slot_smod_slot0_encode, 0, 0, 0, Opcode_bnez_n_Slot_dual_slot2_encode, 0, Opcode_bnez_n_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { + 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { + 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, Opcode_l32i_n_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_l32i_n_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_l32i_n_Slot_smod_slot0_encode, 0, 0, Opcode_l32i_n_Slot_llr_slot0_encode, 0, 0, Opcode_l32i_n_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { + 0, 0, Opcode_mov_n_Slot_inst16b_encode, Opcode_mov_n_Slot_gp_slot2_encode, 0, Opcode_mov_n_Slot_gp_slot0_encode, 0, 0, Opcode_mov_n_Slot_dot_slot0_encode, Opcode_mov_n_Slot_pq_slot2_encode, 0, Opcode_mov_n_Slot_pq_slot0_encode, 0, 0, Opcode_mov_n_Slot_acc2_slot0_encode, 0, 0, Opcode_mov_n_Slot_smod_slot0_encode, 0, 0, Opcode_mov_n_Slot_llr_slot0_encode, Opcode_mov_n_Slot_dual_slot2_encode, 0, Opcode_mov_n_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { + 0, 0, Opcode_movi_n_Slot_inst16b_encode, Opcode_movi_n_Slot_gp_slot2_encode, 0, Opcode_movi_n_Slot_gp_slot0_encode, 0, 0, Opcode_movi_n_Slot_dot_slot0_encode, Opcode_movi_n_Slot_pq_slot2_encode, 0, Opcode_movi_n_Slot_pq_slot0_encode, 0, 0, Opcode_movi_n_Slot_acc2_slot0_encode, 0, 0, Opcode_movi_n_Slot_smod_slot0_encode, 0, 0, Opcode_movi_n_Slot_llr_slot0_encode, Opcode_movi_n_Slot_dual_slot2_encode, 0, Opcode_movi_n_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { + 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { + 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { + 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, Opcode_s32i_n_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_s32i_n_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_s32i_n_Slot_smod_slot0_encode, 0, 0, Opcode_s32i_n_Slot_llr_slot0_encode, 0, 0, Opcode_s32i_n_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { + Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { + Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { + Opcode_addi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addi_Slot_dual_slot2_encode, 0, Opcode_addi_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { + Opcode_addmi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addmi_Slot_dual_slot2_encode, 0, Opcode_addmi_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { + Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_gp_slot2_encode, 0, Opcode_add_Slot_gp_slot0_encode, 0, 0, Opcode_add_Slot_dot_slot0_encode, Opcode_add_Slot_pq_slot2_encode, 0, Opcode_add_Slot_pq_slot0_encode, 0, 0, Opcode_add_Slot_acc2_slot0_encode, 0, 0, Opcode_add_Slot_smod_slot0_encode, 0, 0, Opcode_add_Slot_llr_slot0_encode, Opcode_add_Slot_dual_slot2_encode, 0, Opcode_add_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { + Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_gp_slot2_encode, 0, Opcode_sub_Slot_gp_slot0_encode, 0, 0, Opcode_sub_Slot_dot_slot0_encode, Opcode_sub_Slot_pq_slot2_encode, 0, Opcode_sub_Slot_pq_slot0_encode, 0, 0, Opcode_sub_Slot_acc2_slot0_encode, 0, 0, Opcode_sub_Slot_smod_slot0_encode, 0, 0, Opcode_sub_Slot_llr_slot0_encode, Opcode_sub_Slot_dual_slot2_encode, 0, Opcode_sub_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { + Opcode_addx2_Slot_inst_encode, 0, 0, 0, 0, Opcode_addx2_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_addx2_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_addx2_Slot_smod_slot0_encode, 0, 0, 0, Opcode_addx2_Slot_dual_slot2_encode, 0, Opcode_addx2_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { + Opcode_addx4_Slot_inst_encode, 0, 0, 0, 0, Opcode_addx4_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_addx4_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_addx4_Slot_smod_slot0_encode, 0, 0, 0, Opcode_addx4_Slot_dual_slot2_encode, 0, Opcode_addx4_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { + Opcode_addx8_Slot_inst_encode, 0, 0, 0, 0, Opcode_addx8_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_addx8_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_addx8_Slot_smod_slot0_encode, 0, 0, 0, Opcode_addx8_Slot_dual_slot2_encode, 0, Opcode_addx8_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { + Opcode_subx2_Slot_inst_encode, 0, 0, 0, 0, Opcode_subx2_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_subx2_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_subx2_Slot_smod_slot0_encode, 0, 0, 0, Opcode_subx2_Slot_dual_slot2_encode, 0, Opcode_subx2_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { + Opcode_subx4_Slot_inst_encode, 0, 0, 0, 0, Opcode_subx4_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_subx4_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_subx4_Slot_smod_slot0_encode, 0, 0, 0, Opcode_subx4_Slot_dual_slot2_encode, 0, Opcode_subx4_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { + Opcode_subx8_Slot_inst_encode, 0, 0, 0, 0, Opcode_subx8_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_subx8_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_subx8_Slot_smod_slot0_encode, 0, 0, 0, Opcode_subx8_Slot_dual_slot2_encode, 0, Opcode_subx8_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { + Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_gp_slot2_encode, 0, Opcode_and_Slot_gp_slot0_encode, 0, 0, Opcode_and_Slot_dot_slot0_encode, Opcode_and_Slot_pq_slot2_encode, 0, Opcode_and_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_and_Slot_smod_slot0_encode, 0, 0, Opcode_and_Slot_llr_slot0_encode, Opcode_and_Slot_dual_slot2_encode, 0, Opcode_and_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { + Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_gp_slot2_encode, 0, Opcode_or_Slot_gp_slot0_encode, 0, 0, Opcode_or_Slot_dot_slot0_encode, Opcode_or_Slot_pq_slot2_encode, 0, Opcode_or_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_or_Slot_smod_slot0_encode, 0, 0, Opcode_or_Slot_llr_slot0_encode, Opcode_or_Slot_dual_slot2_encode, 0, Opcode_or_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { + Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_gp_slot2_encode, 0, Opcode_xor_Slot_gp_slot0_encode, 0, 0, Opcode_xor_Slot_dot_slot0_encode, Opcode_xor_Slot_pq_slot2_encode, 0, Opcode_xor_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_xor_Slot_smod_slot0_encode, 0, 0, Opcode_xor_Slot_llr_slot0_encode, Opcode_xor_Slot_dual_slot2_encode, 0, Opcode_xor_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { + Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_Slot_dual_slot2_encode, 0, Opcode_beqi_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { + Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_Slot_dual_slot2_encode, 0, Opcode_bnei_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { + Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_Slot_dual_slot2_encode, 0, Opcode_bgei_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { + Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_blti_Slot_dual_slot2_encode, 0, Opcode_blti_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { + Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_Slot_dual_slot2_encode, 0, Opcode_bbci_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { + Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_Slot_dual_slot2_encode, 0, Opcode_bbsi_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { + Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_Slot_dual_slot2_encode, 0, Opcode_bgeui_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { + Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_Slot_dual_slot2_encode, 0, Opcode_bltui_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { + Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beq_Slot_dual_slot2_encode, 0, Opcode_beq_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { + Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bne_Slot_dual_slot2_encode, 0, Opcode_bne_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { + Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bge_Slot_dual_slot2_encode, 0, Opcode_bge_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { + Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_blt_Slot_dual_slot2_encode, 0, Opcode_blt_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { + Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_Slot_dual_slot2_encode, 0, Opcode_bgeu_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { + Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_Slot_dual_slot2_encode, 0, Opcode_bltu_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { + Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bany_Slot_dual_slot2_encode, 0, Opcode_bany_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { + Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_Slot_dual_slot2_encode, 0, Opcode_bnone_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { + Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ball_Slot_dual_slot2_encode, 0, Opcode_ball_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { + Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_Slot_dual_slot2_encode, 0, Opcode_bnall_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { + Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_Slot_dual_slot2_encode, 0, Opcode_bbc_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { + Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_Slot_dual_slot2_encode, 0, Opcode_bbs_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { + Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_Slot_dual_slot2_encode, 0, Opcode_beqz_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { + Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_Slot_dual_slot2_encode, 0, Opcode_bnez_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { + Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_Slot_dual_slot2_encode, 0, Opcode_bgez_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { + Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_Slot_dual_slot2_encode, 0, Opcode_bltz_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { + Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { + Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { + Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_gp_slot2_encode, 0, Opcode_extui_Slot_gp_slot0_encode, 0, 0, 0, Opcode_extui_Slot_pq_slot2_encode, 0, Opcode_extui_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_extui_Slot_smod_slot0_encode, 0, 0, 0, Opcode_extui_Slot_dual_slot2_encode, 0, Opcode_extui_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { + Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { + Opcode_j_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { + Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { + Opcode_l16ui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l16ui_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { + Opcode_l16si_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l16si_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { + Opcode_l32i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32i_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { + Opcode_l32r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l32r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { + Opcode_l8ui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_l8ui_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { + Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { + Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { + Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { + Opcode_movi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movi_Slot_dual_slot2_encode, 0, Opcode_movi_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { + Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_gp_slot2_encode, 0, Opcode_moveqz_Slot_gp_slot0_encode, 0, 0, 0, Opcode_moveqz_Slot_pq_slot2_encode, 0, Opcode_moveqz_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_moveqz_Slot_smod_slot0_encode, 0, 0, 0, Opcode_moveqz_Slot_dual_slot2_encode, 0, Opcode_moveqz_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { + Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_gp_slot2_encode, 0, Opcode_movnez_Slot_gp_slot0_encode, 0, 0, 0, Opcode_movnez_Slot_pq_slot2_encode, 0, Opcode_movnez_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_movnez_Slot_smod_slot0_encode, 0, 0, 0, Opcode_movnez_Slot_dual_slot2_encode, 0, Opcode_movnez_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { + Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_gp_slot2_encode, 0, Opcode_movltz_Slot_gp_slot0_encode, 0, 0, 0, Opcode_movltz_Slot_pq_slot2_encode, 0, Opcode_movltz_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_movltz_Slot_smod_slot0_encode, 0, 0, 0, Opcode_movltz_Slot_dual_slot2_encode, 0, Opcode_movltz_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { + Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_gp_slot2_encode, 0, Opcode_movgez_Slot_gp_slot0_encode, 0, 0, 0, Opcode_movgez_Slot_pq_slot2_encode, 0, Opcode_movgez_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_movgez_Slot_smod_slot0_encode, 0, 0, 0, Opcode_movgez_Slot_dual_slot2_encode, 0, Opcode_movgez_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { + Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_gp_slot2_encode, 0, Opcode_neg_Slot_gp_slot0_encode, 0, 0, Opcode_neg_Slot_dot_slot0_encode, Opcode_neg_Slot_pq_slot2_encode, 0, Opcode_neg_Slot_pq_slot0_encode, 0, 0, Opcode_neg_Slot_acc2_slot0_encode, 0, 0, Opcode_neg_Slot_smod_slot0_encode, 0, 0, Opcode_neg_Slot_llr_slot0_encode, Opcode_neg_Slot_dual_slot2_encode, 0, Opcode_neg_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { + Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_gp_slot2_encode, 0, Opcode_abs_Slot_gp_slot0_encode, 0, 0, 0, Opcode_abs_Slot_pq_slot2_encode, 0, Opcode_abs_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_abs_Slot_smod_slot0_encode, 0, 0, 0, Opcode_abs_Slot_dual_slot2_encode, 0, Opcode_abs_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { + Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_gp_slot2_encode, Opcode_nop_Slot_gp_slot1_encode, Opcode_nop_Slot_gp_slot0_encode, Opcode_nop_Slot_dot_slot2_encode, Opcode_nop_Slot_dot_slot1_encode, Opcode_nop_Slot_dot_slot0_encode, Opcode_nop_Slot_pq_slot2_encode, Opcode_nop_Slot_pq_slot1_encode, Opcode_nop_Slot_pq_slot0_encode, Opcode_nop_Slot_acc2_slot2_encode, Opcode_nop_Slot_acc2_slot1_encode, Opcode_nop_Slot_acc2_slot0_encode, Opcode_nop_Slot_smod_slot2_encode, Opcode_nop_Slot_smod_slot1_encode, Opcode_nop_Slot_smod_slot0_encode, Opcode_nop_Slot_llr_slot2_encode, Opcode_nop_Slot_llr_slot1_encode, Opcode_nop_Slot_llr_slot0_encode, Opcode_nop_Slot_dual_slot2_encode, Opcode_nop_Slot_dual_slot1_encode, Opcode_nop_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { + Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { + Opcode_s16i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s16i_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { + Opcode_s32i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s32i_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { + Opcode_s8i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_s8i_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { + Opcode_ssr_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssr_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_ssr_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_ssr_Slot_smod_slot0_encode, 0, 0, 0, Opcode_ssr_Slot_dual_slot2_encode, 0, Opcode_ssr_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { + Opcode_ssl_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssl_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_ssl_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_ssl_Slot_smod_slot0_encode, 0, 0, 0, Opcode_ssl_Slot_dual_slot2_encode, 0, Opcode_ssl_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { + Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssa8l_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_ssa8l_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_ssa8l_Slot_smod_slot0_encode, 0, 0, 0, Opcode_ssa8l_Slot_dual_slot2_encode, 0, Opcode_ssa8l_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { + Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssa8b_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_ssa8b_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_ssa8b_Slot_smod_slot0_encode, 0, 0, 0, Opcode_ssa8b_Slot_dual_slot2_encode, 0, Opcode_ssa8b_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { + Opcode_ssai_Slot_inst_encode, 0, 0, 0, 0, Opcode_ssai_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_ssai_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_ssai_Slot_smod_slot0_encode, 0, 0, 0, Opcode_ssai_Slot_dual_slot2_encode, 0, Opcode_ssai_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { + Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_gp_slot2_encode, 0, Opcode_sll_Slot_gp_slot0_encode, 0, 0, Opcode_sll_Slot_dot_slot0_encode, Opcode_sll_Slot_pq_slot2_encode, 0, Opcode_sll_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_sll_Slot_smod_slot0_encode, 0, 0, Opcode_sll_Slot_llr_slot0_encode, Opcode_sll_Slot_dual_slot2_encode, 0, Opcode_sll_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { + Opcode_src_Slot_inst_encode, 0, 0, 0, 0, Opcode_src_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_src_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_src_Slot_smod_slot0_encode, 0, 0, 0, Opcode_src_Slot_dual_slot2_encode, 0, Opcode_src_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { + Opcode_srl_Slot_inst_encode, 0, 0, 0, 0, Opcode_srl_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_srl_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_srl_Slot_smod_slot0_encode, 0, 0, 0, Opcode_srl_Slot_dual_slot2_encode, 0, Opcode_srl_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { + Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_gp_slot2_encode, 0, Opcode_sra_Slot_gp_slot0_encode, 0, 0, Opcode_sra_Slot_dot_slot0_encode, Opcode_sra_Slot_pq_slot2_encode, 0, Opcode_sra_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_sra_Slot_smod_slot0_encode, 0, 0, Opcode_sra_Slot_llr_slot0_encode, Opcode_sra_Slot_dual_slot2_encode, 0, Opcode_sra_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { + Opcode_slli_Slot_inst_encode, 0, 0, 0, 0, Opcode_slli_Slot_gp_slot0_encode, 0, 0, Opcode_slli_Slot_dot_slot0_encode, 0, 0, Opcode_slli_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_slli_Slot_smod_slot0_encode, 0, 0, Opcode_slli_Slot_llr_slot0_encode, Opcode_slli_Slot_dual_slot2_encode, 0, Opcode_slli_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { + Opcode_srai_Slot_inst_encode, 0, 0, 0, 0, Opcode_srai_Slot_gp_slot0_encode, 0, 0, Opcode_srai_Slot_dot_slot0_encode, 0, 0, Opcode_srai_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_srai_Slot_smod_slot0_encode, 0, 0, Opcode_srai_Slot_llr_slot0_encode, Opcode_srai_Slot_dual_slot2_encode, 0, Opcode_srai_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { + Opcode_srli_Slot_inst_encode, 0, 0, 0, 0, Opcode_srli_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_srli_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_srli_Slot_smod_slot0_encode, 0, 0, 0, Opcode_srli_Slot_dual_slot2_encode, 0, Opcode_srli_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { + Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { + Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { + Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { + Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { + Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { + Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { + Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { + Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { + Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { + Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { + Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { + Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { + Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { + Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { + Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { + Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { + Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { + Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { + Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { + Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = { + Opcode_wsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { + Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { + Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { + Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { + Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { + Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { + Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { + Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { + Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { + Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { + Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { + Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { + Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { + Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { + Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { + Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { + Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { + Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { + Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { + Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { + Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { + Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { + Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { + Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { + Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { + Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { + Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { + Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { + Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { + Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { + Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { + Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { + Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { + Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { + Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { + Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { + Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { + Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { + Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { + Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { + Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { + Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { + Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { + Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { + Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { + Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { + Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { + Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { + Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { + Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { + Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { + Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { + Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { + Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { + Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { + Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { + Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { + Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { + 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { + Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { + Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { + Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { + Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { + Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { + Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { + Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { + Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { + Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { + Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, Opcode_andb_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_andb_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_andb_Slot_smod_slot0_encode, 0, 0, 0, Opcode_andb_Slot_dual_slot2_encode, 0, Opcode_andb_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { + Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { + Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, Opcode_orb_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_orb_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_orb_Slot_smod_slot0_encode, 0, 0, 0, Opcode_orb_Slot_dual_slot2_encode, 0, Opcode_orb_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { + Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { + Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, Opcode_xorb_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_xorb_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_xorb_Slot_smod_slot0_encode, 0, 0, 0, Opcode_xorb_Slot_dual_slot2_encode, 0, Opcode_xorb_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { + Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, Opcode_any4_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_any4_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_any4_Slot_smod_slot0_encode, 0, 0, 0, Opcode_any4_Slot_dual_slot2_encode, 0, Opcode_any4_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { + Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { + Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, Opcode_any8_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_any8_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_any8_Slot_smod_slot0_encode, 0, 0, 0, Opcode_any8_Slot_dual_slot2_encode, 0, Opcode_any8_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { + Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { + Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { + Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { + Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { + Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, Opcode_movt_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_movt_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_movt_Slot_smod_slot0_encode, 0, 0, 0, Opcode_movt_Slot_dual_slot2_encode, 0, Opcode_movt_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { + Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { + Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { + Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { + Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { + Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { + Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { + Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { + Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { + Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { + Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { + Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { + Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { + Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { + Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { + Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { + Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { + Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { + Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { + Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { + Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { + Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { + Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { + Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { + Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { + Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { + Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { + Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { + Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { + Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { + Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { + Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { + Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { + Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { + Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { + Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { + Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { + Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { + Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { + Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { + Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { + Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { + Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { + Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { + Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { + Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { + Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { + Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { + Opcode_clamps_Slot_inst_encode, 0, 0, 0, 0, Opcode_clamps_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_clamps_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_clamps_Slot_smod_slot0_encode, 0, 0, 0, Opcode_clamps_Slot_dual_slot2_encode, 0, Opcode_clamps_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { + Opcode_min_Slot_inst_encode, 0, 0, 0, 0, Opcode_min_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_min_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_min_Slot_smod_slot0_encode, 0, 0, 0, Opcode_min_Slot_dual_slot2_encode, 0, Opcode_min_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { + Opcode_max_Slot_inst_encode, 0, 0, 0, 0, Opcode_max_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_max_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_max_Slot_smod_slot0_encode, 0, 0, 0, Opcode_max_Slot_dual_slot2_encode, 0, Opcode_max_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { + Opcode_minu_Slot_inst_encode, 0, 0, 0, 0, Opcode_minu_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_minu_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_minu_Slot_smod_slot0_encode, 0, 0, 0, Opcode_minu_Slot_dual_slot2_encode, 0, Opcode_minu_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { + Opcode_maxu_Slot_inst_encode, 0, 0, 0, 0, Opcode_maxu_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_maxu_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_maxu_Slot_smod_slot0_encode, 0, 0, 0, Opcode_maxu_Slot_dual_slot2_encode, 0, Opcode_maxu_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { + Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0, Opcode_nsa_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_nsa_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_nsa_Slot_smod_slot0_encode, 0, 0, 0, Opcode_nsa_Slot_dual_slot2_encode, 0, Opcode_nsa_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { + Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0, Opcode_nsau_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_nsau_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_nsau_Slot_smod_slot0_encode, 0, 0, 0, Opcode_nsau_Slot_dual_slot2_encode, 0, Opcode_nsau_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { + Opcode_sext_Slot_inst_encode, 0, 0, 0, 0, Opcode_sext_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_sext_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_sext_Slot_smod_slot0_encode, 0, 0, 0, Opcode_sext_Slot_dual_slot2_encode, 0, Opcode_sext_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { + Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { + Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { + Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { + Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { + Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { + Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { + Opcode_rer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { + Opcode_wer_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = { + Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = { + Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = { + Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = { + Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = { + Opcode_add_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_add_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = { + Opcode_sub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sub_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = { + Opcode_mul_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mul_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = { + Opcode_madd_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_madd_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = { + Opcode_msub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_msub_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = { + Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movf_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = { + Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movt_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = { + Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_moveqz_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = { + Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movnez_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = { + Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movltz_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = { + Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movgez_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = { + Opcode_abs_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_abs_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = { + Opcode_mov_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mov_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = { + Opcode_neg_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_neg_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = { + Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_un_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = { + Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_oeq_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = { + Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ueq_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = { + Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_olt_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = { + Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ult_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = { + Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ole_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = { + Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ule_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = { + Opcode_float_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_float_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = { + Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ufloat_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = { + Opcode_round_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_round_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = { + Opcode_ceil_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ceil_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = { + Opcode_floor_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_floor_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = { + Opcode_trunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_trunc_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = { + Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_utrunc_s_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = { + Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rfr_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = { + Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = { + Opcode_lsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lsi_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lsiu_encode_fns[] = { + Opcode_lsiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lsiu_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = { + Opcode_lsx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lsxu_encode_fns[] = { + Opcode_lsxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lsxu_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = { + Opcode_ssi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssi_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssiu_encode_fns[] = { + Opcode_ssiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssiu_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = { + Opcode_ssx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssx_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ssxu_encode_fns[] = { + Opcode_ssxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ssxu_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_argmax_encode_fns[] = { + Opcode_get_argmax_Slot_inst_encode, 0, 0, Opcode_get_argmax_Slot_gp_slot2_encode, 0, 0, Opcode_get_argmax_Slot_dot_slot2_encode, 0, 0, Opcode_get_argmax_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_get_argmax_Slot_smod_slot2_encode, 0, 0, Opcode_get_argmax_Slot_llr_slot2_encode, 0, 0, Opcode_get_argmax_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_get_hsar_encode_fns[] = { + Opcode_get_hsar_Slot_inst_encode, 0, 0, Opcode_get_hsar_Slot_gp_slot2_encode, 0, Opcode_get_hsar_Slot_gp_slot0_encode, Opcode_get_hsar_Slot_dot_slot2_encode, 0, Opcode_get_hsar_Slot_dot_slot0_encode, Opcode_get_hsar_Slot_pq_slot2_encode, 0, Opcode_get_hsar_Slot_pq_slot0_encode, 0, 0, 0, Opcode_get_hsar_Slot_smod_slot2_encode, 0, Opcode_get_hsar_Slot_smod_slot0_encode, Opcode_get_hsar_Slot_llr_slot2_encode, 0, Opcode_get_hsar_Slot_llr_slot0_encode, Opcode_get_hsar_Slot_dual_slot2_encode, 0, Opcode_get_hsar_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_hsar2sar_encode_fns[] = { + Opcode_get_hsar2sar_Slot_inst_encode, 0, 0, Opcode_get_hsar2sar_Slot_gp_slot2_encode, 0, Opcode_get_hsar2sar_Slot_gp_slot0_encode, Opcode_get_hsar2sar_Slot_dot_slot2_encode, 0, Opcode_get_hsar2sar_Slot_dot_slot0_encode, Opcode_get_hsar2sar_Slot_pq_slot2_encode, 0, Opcode_get_hsar2sar_Slot_pq_slot0_encode, 0, 0, 0, Opcode_get_hsar2sar_Slot_smod_slot2_encode, 0, Opcode_get_hsar2sar_Slot_smod_slot0_encode, Opcode_get_hsar2sar_Slot_llr_slot2_encode, 0, Opcode_get_hsar2sar_Slot_llr_slot0_encode, Opcode_get_hsar2sar_Slot_dual_slot2_encode, 0, Opcode_get_hsar2sar_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_interp_ext_n_encode_fns[] = { + Opcode_get_interp_ext_n_Slot_inst_encode, 0, 0, 0, 0, Opcode_get_interp_ext_n_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_interp_ext_n_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_interp_ext_n_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_interp_ext_n_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_interp_ext_l_encode_fns[] = { + Opcode_get_interp_ext_l_Slot_inst_encode, 0, 0, 0, 0, Opcode_get_interp_ext_l_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_interp_ext_l_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_interp_ext_l_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_interp_ext_l_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_llr_buf_encode_fns[] = { + Opcode_get_llr_buf_Slot_inst_encode, 0, 0, 0, 0, Opcode_get_llr_buf_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_llr_buf_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_llr_buf_Slot_smod_slot0_encode, 0, 0, Opcode_get_llr_buf_Slot_llr_slot0_encode, 0, 0, Opcode_get_llr_buf_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_llr_pos_encode_fns[] = { + Opcode_get_llr_pos_Slot_inst_encode, 0, 0, 0, 0, Opcode_get_llr_pos_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_llr_pos_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_llr_pos_Slot_smod_slot0_encode, 0, 0, Opcode_get_llr_pos_Slot_llr_slot0_encode, 0, 0, Opcode_get_llr_pos_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_max_encode_fns[] = { + Opcode_get_max_Slot_inst_encode, 0, 0, Opcode_get_max_Slot_gp_slot2_encode, 0, 0, Opcode_get_max_Slot_dot_slot2_encode, 0, 0, Opcode_get_max_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_get_max_Slot_smod_slot2_encode, 0, 0, Opcode_get_max_Slot_llr_slot2_encode, 0, 0, Opcode_get_max_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_get_nco_encode_fns[] = { + Opcode_get_nco_Slot_inst_encode, 0, 0, Opcode_get_nco_Slot_gp_slot2_encode, 0, 0, Opcode_get_nco_Slot_dot_slot2_encode, 0, 0, Opcode_get_nco_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_get_nco_Slot_smod_slot2_encode, 0, 0, Opcode_get_nco_Slot_llr_slot2_encode, 0, 0, Opcode_get_nco_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_get_perm_reg_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_get_perm_reg_Slot_gp_slot0_encode, 0, 0, Opcode_get_perm_reg_Slot_dot_slot0_encode, 0, 0, Opcode_get_perm_reg_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_perm_reg_Slot_smod_slot0_encode, 0, 0, Opcode_get_perm_reg_Slot_llr_slot0_encode, 0, 0, Opcode_get_perm_reg_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_phasor_n_encode_fns[] = { + Opcode_get_phasor_n_Slot_inst_encode, 0, 0, 0, 0, Opcode_get_phasor_n_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_phasor_n_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_phasor_n_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_phasor_n_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_phasor_offset_encode_fns[] = { + Opcode_get_phasor_offset_Slot_inst_encode, 0, 0, 0, 0, Opcode_get_phasor_offset_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_phasor_offset_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_phasor_offset_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_phasor_offset_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_sar_encode_fns[] = { + Opcode_get_sar_Slot_inst_encode, 0, 0, Opcode_get_sar_Slot_gp_slot2_encode, 0, Opcode_get_sar_Slot_gp_slot0_encode, Opcode_get_sar_Slot_dot_slot2_encode, 0, Opcode_get_sar_Slot_dot_slot0_encode, Opcode_get_sar_Slot_pq_slot2_encode, 0, Opcode_get_sar_Slot_pq_slot0_encode, 0, 0, 0, Opcode_get_sar_Slot_smod_slot2_encode, 0, Opcode_get_sar_Slot_smod_slot0_encode, Opcode_get_sar_Slot_llr_slot2_encode, 0, Opcode_get_sar_Slot_llr_slot0_encode, Opcode_get_sar_Slot_dual_slot2_encode, 0, Opcode_get_sar_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_scale_reg_encode_fns[] = { + Opcode_get_scale_reg_Slot_inst_encode, 0, 0, 0, 0, Opcode_get_scale_reg_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_scale_reg_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_scale_reg_Slot_smod_slot0_encode, 0, 0, Opcode_get_scale_reg_Slot_llr_slot0_encode, 0, 0, Opcode_get_scale_reg_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_smod_buf_encode_fns[] = { + Opcode_get_smod_buf_Slot_inst_encode, 0, 0, 0, 0, Opcode_get_smod_buf_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_smod_buf_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_smod_buf_Slot_smod_slot0_encode, 0, 0, Opcode_get_smod_buf_Slot_llr_slot0_encode, 0, 0, Opcode_get_smod_buf_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_smod_offset_table_encode_fns[] = { + Opcode_get_smod_offset_table_Slot_inst_encode, 0, 0, 0, 0, Opcode_get_smod_offset_table_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_smod_offset_table_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_smod_offset_table_Slot_smod_slot0_encode, 0, 0, Opcode_get_smod_offset_table_Slot_llr_slot0_encode, 0, 0, Opcode_get_smod_offset_table_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_smod_pos_encode_fns[] = { + Opcode_get_smod_pos_Slot_inst_encode, 0, 0, 0, 0, Opcode_get_smod_pos_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_smod_pos_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_smod_pos_Slot_smod_slot0_encode, 0, 0, Opcode_get_smod_pos_Slot_llr_slot0_encode, 0, 0, Opcode_get_smod_pos_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_sov_encode_fns[] = { + Opcode_get_sov_Slot_inst_encode, 0, 0, 0, 0, Opcode_get_sov_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_sov_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_sov_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_sov_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_get_wght_encode_fns[] = { + Opcode_get_wght_Slot_inst_encode, 0, 0, 0, 0, Opcode_get_wght_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_wght_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_get_wght_Slot_smod_slot0_encode, 0, 0, Opcode_get_wght_Slot_llr_slot0_encode, 0, 0, Opcode_get_wght_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_set_argmax_encode_fns[] = { + Opcode_set_argmax_Slot_inst_encode, 0, 0, Opcode_set_argmax_Slot_gp_slot2_encode, 0, 0, Opcode_set_argmax_Slot_dot_slot2_encode, 0, 0, Opcode_set_argmax_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_set_argmax_Slot_smod_slot2_encode, 0, 0, Opcode_set_argmax_Slot_llr_slot2_encode, 0, 0, Opcode_set_argmax_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_set_ext_regs_encode_fns[] = { + Opcode_set_ext_regs_Slot_inst_encode, 0, 0, Opcode_set_ext_regs_Slot_gp_slot2_encode, 0, 0, Opcode_set_ext_regs_Slot_dot_slot2_encode, 0, 0, Opcode_set_ext_regs_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_set_ext_regs_Slot_smod_slot2_encode, 0, 0, Opcode_set_ext_regs_Slot_llr_slot2_encode, 0, 0, Opcode_set_ext_regs_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_set_hsar_encode_fns[] = { + 0, 0, 0, Opcode_set_hsar_Slot_gp_slot2_encode, 0, 0, Opcode_set_hsar_Slot_dot_slot2_encode, 0, 0, Opcode_set_hsar_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_set_hsar_Slot_smod_slot2_encode, 0, 0, Opcode_set_hsar_Slot_llr_slot2_encode, 0, 0, Opcode_set_hsar_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_set_llr_buf_encode_fns[] = { + Opcode_set_llr_buf_Slot_inst_encode, 0, 0, 0, 0, Opcode_set_llr_buf_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_llr_buf_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_llr_buf_Slot_smod_slot0_encode, 0, 0, Opcode_set_llr_buf_Slot_llr_slot0_encode, 0, 0, Opcode_set_llr_buf_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_set_llr_pos_encode_fns[] = { + Opcode_set_llr_pos_Slot_inst_encode, 0, 0, 0, 0, Opcode_set_llr_pos_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_llr_pos_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_llr_pos_Slot_smod_slot0_encode, 0, 0, Opcode_set_llr_pos_Slot_llr_slot0_encode, 0, 0, Opcode_set_llr_pos_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_set_max_encode_fns[] = { + Opcode_set_max_Slot_inst_encode, 0, 0, Opcode_set_max_Slot_gp_slot2_encode, 0, 0, Opcode_set_max_Slot_dot_slot2_encode, 0, 0, Opcode_set_max_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_set_max_Slot_smod_slot2_encode, 0, 0, Opcode_set_max_Slot_llr_slot2_encode, 0, 0, Opcode_set_max_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_set_nco_encode_fns[] = { + Opcode_set_nco_Slot_inst_encode, 0, 0, Opcode_set_nco_Slot_gp_slot2_encode, 0, 0, Opcode_set_nco_Slot_dot_slot2_encode, 0, 0, Opcode_set_nco_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_set_nco_Slot_smod_slot2_encode, 0, 0, Opcode_set_nco_Slot_llr_slot2_encode, 0, 0, Opcode_set_nco_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_set_perm_reg_encode_fns[] = { + 0, 0, 0, 0, 0, Opcode_set_perm_reg_Slot_gp_slot0_encode, 0, 0, Opcode_set_perm_reg_Slot_dot_slot0_encode, 0, 0, Opcode_set_perm_reg_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_perm_reg_Slot_smod_slot0_encode, 0, 0, Opcode_set_perm_reg_Slot_llr_slot0_encode, 0, 0, Opcode_set_perm_reg_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_set_phasor_n_encode_fns[] = { + Opcode_set_phasor_n_Slot_inst_encode, 0, 0, 0, 0, Opcode_set_phasor_n_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_phasor_n_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_phasor_n_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_phasor_n_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_set_phasor_offset_encode_fns[] = { + Opcode_set_phasor_offset_Slot_inst_encode, 0, 0, 0, 0, Opcode_set_phasor_offset_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_phasor_offset_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_phasor_offset_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_phasor_offset_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_set_sar_encode_fns[] = { + Opcode_set_sar_Slot_inst_encode, 0, 0, Opcode_set_sar_Slot_gp_slot2_encode, 0, Opcode_set_sar_Slot_gp_slot0_encode, Opcode_set_sar_Slot_dot_slot2_encode, 0, Opcode_set_sar_Slot_dot_slot0_encode, Opcode_set_sar_Slot_pq_slot2_encode, 0, Opcode_set_sar_Slot_pq_slot0_encode, 0, 0, 0, Opcode_set_sar_Slot_smod_slot2_encode, 0, Opcode_set_sar_Slot_smod_slot0_encode, Opcode_set_sar_Slot_llr_slot2_encode, 0, Opcode_set_sar_Slot_llr_slot0_encode, Opcode_set_sar_Slot_dual_slot2_encode, 0, Opcode_set_sar_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_set_scale_reg_encode_fns[] = { + Opcode_set_scale_reg_Slot_inst_encode, 0, 0, 0, 0, Opcode_set_scale_reg_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_scale_reg_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_scale_reg_Slot_smod_slot0_encode, 0, 0, Opcode_set_scale_reg_Slot_llr_slot0_encode, 0, 0, Opcode_set_scale_reg_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_set_smod_buf_encode_fns[] = { + Opcode_set_smod_buf_Slot_inst_encode, 0, 0, 0, 0, Opcode_set_smod_buf_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_smod_buf_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_smod_buf_Slot_smod_slot0_encode, 0, 0, Opcode_set_smod_buf_Slot_llr_slot0_encode, 0, 0, Opcode_set_smod_buf_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_set_smod_offset_table_encode_fns[] = { + Opcode_set_smod_offset_table_Slot_inst_encode, 0, 0, 0, 0, Opcode_set_smod_offset_table_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_smod_offset_table_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_smod_offset_table_Slot_smod_slot0_encode, 0, 0, Opcode_set_smod_offset_table_Slot_llr_slot0_encode, 0, 0, Opcode_set_smod_offset_table_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_set_smod_pos_encode_fns[] = { + Opcode_set_smod_pos_Slot_inst_encode, 0, 0, 0, 0, Opcode_set_smod_pos_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_smod_pos_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_smod_pos_Slot_smod_slot0_encode, 0, 0, Opcode_set_smod_pos_Slot_llr_slot0_encode, 0, 0, Opcode_set_smod_pos_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_set_sov_encode_fns[] = { + Opcode_set_sov_Slot_inst_encode, 0, 0, 0, 0, Opcode_set_sov_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_sov_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_sov_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_sov_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_set_wght_encode_fns[] = { + Opcode_set_wght_Slot_inst_encode, 0, 0, 0, 0, Opcode_set_wght_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_wght_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_set_wght_Slot_smod_slot0_encode, 0, 0, Opcode_set_wght_Slot_llr_slot0_encode, 0, 0, Opcode_set_wght_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lac2x32_encode_fns[] = { + Opcode_lac2x32_Slot_inst_encode, 0, 0, 0, 0, Opcode_lac2x32_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_lac2x32_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lac2x32_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lac2x64_0_encode_fns[] = { + Opcode_lac2x64_0_Slot_inst_encode, 0, 0, 0, 0, Opcode_lac2x64_0_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_lac2x64_0_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lac2x64_0_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lac2x64_1_encode_fns[] = { + Opcode_lac2x64_1_Slot_inst_encode, 0, 0, 0, 0, Opcode_lac2x64_1_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_lac2x64_1_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lac2x64_1_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lac2x64_2_encode_fns[] = { + Opcode_lac2x64_2_Slot_inst_encode, 0, 0, 0, 0, Opcode_lac2x64_2_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_lac2x64_2_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lac2x64_2_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lac2x64_3_encode_fns[] = { + Opcode_lac2x64_3_Slot_inst_encode, 0, 0, 0, 0, Opcode_lac2x64_3_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_lac2x64_3_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lac2x64_3_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lac32_r_encode_fns[] = { + Opcode_lac32_r_Slot_inst_encode, 0, 0, 0, 0, Opcode_lac32_r_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_lac32_r_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lac32_r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lac_ih_encode_fns[] = { + Opcode_lac_ih_Slot_inst_encode, 0, 0, 0, 0, Opcode_lac_ih_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_lac_ih_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lac_ih_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lac_il_encode_fns[] = { + Opcode_lac_il_Slot_inst_encode, 0, 0, 0, 0, Opcode_lac_il_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_lac_il_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lac_il_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lac_rh_encode_fns[] = { + Opcode_lac_rh_Slot_inst_encode, 0, 0, 0, 0, Opcode_lac_rh_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_lac_rh_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lac_rh_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lac_rl_encode_fns[] = { + Opcode_lac_rl_Slot_inst_encode, 0, 0, 0, 0, Opcode_lac_rl_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_lac_rl_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lac_rl_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lcm_encode_fns[] = { + Opcode_lcm_Slot_inst_encode, 0, 0, 0, 0, Opcode_lcm_Slot_gp_slot0_encode, 0, 0, Opcode_lcm_Slot_dot_slot0_encode, 0, 0, Opcode_lcm_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_lcm_Slot_smod_slot0_encode, 0, 0, Opcode_lcm_Slot_llr_slot0_encode, 0, 0, Opcode_lcm_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lcm_pinc_encode_fns[] = { + Opcode_lcm_pinc_Slot_inst_encode, 0, 0, 0, 0, Opcode_lcm_pinc_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_lcm_pinc_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_lcm_pinc_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_lcm_pinc_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lcm_pinc_x_encode_fns[] = { + Opcode_lcm_pinc_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_lcm_pinc_x_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_lcm_pinc_x_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_lcm_pinc_x_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_lcm_pinc_x_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lcm_u_encode_fns[] = { + Opcode_lcm_u_Slot_inst_encode, 0, 0, 0, 0, Opcode_lcm_u_Slot_gp_slot0_encode, 0, 0, Opcode_lcm_u_Slot_dot_slot0_encode, 0, 0, Opcode_lcm_u_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_lcm_u_Slot_smod_slot0_encode, 0, 0, Opcode_lcm_u_Slot_llr_slot0_encode, 0, 0, Opcode_lcm_u_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lcm_x_encode_fns[] = { + Opcode_lcm_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_lcm_x_Slot_gp_slot0_encode, 0, 0, Opcode_lcm_x_Slot_dot_slot0_encode, 0, 0, Opcode_lcm_x_Slot_pq_slot0_encode, 0, 0, Opcode_lcm_x_Slot_acc2_slot0_encode, 0, 0, Opcode_lcm_x_Slot_smod_slot0_encode, 0, 0, Opcode_lcm_x_Slot_llr_slot0_encode, 0, 0, Opcode_lcm_x_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lcm_xu_encode_fns[] = { + Opcode_lcm_xu_Slot_inst_encode, 0, 0, 0, 0, Opcode_lcm_xu_Slot_gp_slot0_encode, 0, 0, Opcode_lcm_xu_Slot_dot_slot0_encode, 0, 0, Opcode_lcm_xu_Slot_pq_slot0_encode, 0, 0, Opcode_lcm_xu_Slot_acc2_slot0_encode, 0, 0, Opcode_lcm_xu_Slot_smod_slot0_encode, 0, 0, Opcode_lcm_xu_Slot_llr_slot0_encode, 0, 0, Opcode_lcm_xu_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lp_encode_fns[] = { + Opcode_lp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lp_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lp_x_encode_fns[] = { + Opcode_lp_x_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lp_x_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lq_encode_fns[] = { + Opcode_lq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lq_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lq_x_encode_fns[] = { + Opcode_lq_x_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lq_x_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lut0_encode_fns[] = { + Opcode_lut0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lut0_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lut1_encode_fns[] = { + Opcode_lut1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lut1_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lut2_encode_fns[] = { + Opcode_lut2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lut2_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lut3_encode_fns[] = { + Opcode_lut3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_lut3_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sac2x32_encode_fns[] = { + Opcode_sac2x32_Slot_inst_encode, 0, 0, 0, 0, Opcode_sac2x32_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_sac2x32_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sac2x32_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sac2x64_0_encode_fns[] = { + Opcode_sac2x64_0_Slot_inst_encode, 0, 0, 0, 0, Opcode_sac2x64_0_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_sac2x64_0_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sac2x64_0_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sac2x64_1_encode_fns[] = { + Opcode_sac2x64_1_Slot_inst_encode, 0, 0, 0, 0, Opcode_sac2x64_1_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_sac2x64_1_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sac2x64_1_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sac2x64_2_encode_fns[] = { + Opcode_sac2x64_2_Slot_inst_encode, 0, 0, 0, 0, Opcode_sac2x64_2_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_sac2x64_2_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sac2x64_2_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sac2x64_3_encode_fns[] = { + Opcode_sac2x64_3_Slot_inst_encode, 0, 0, 0, 0, Opcode_sac2x64_3_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_sac2x64_3_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sac2x64_3_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sac32_r_encode_fns[] = { + Opcode_sac32_r_Slot_inst_encode, 0, 0, 0, 0, Opcode_sac32_r_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_sac32_r_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sac32_r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sac_ih_encode_fns[] = { + Opcode_sac_ih_Slot_inst_encode, 0, 0, 0, 0, Opcode_sac_ih_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_sac_ih_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sac_ih_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sac_il_encode_fns[] = { + Opcode_sac_il_Slot_inst_encode, 0, 0, 0, 0, Opcode_sac_il_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_sac_il_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sac_il_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sac_rh_encode_fns[] = { + Opcode_sac_rh_Slot_inst_encode, 0, 0, 0, 0, Opcode_sac_rh_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_sac_rh_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sac_rh_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sac_rl_encode_fns[] = { + Opcode_sac_rl_Slot_inst_encode, 0, 0, 0, 0, Opcode_sac_rl_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_sac_rl_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sac_rl_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_scm_encode_fns[] = { + Opcode_scm_Slot_inst_encode, 0, 0, 0, 0, Opcode_scm_Slot_gp_slot0_encode, 0, 0, Opcode_scm_Slot_dot_slot0_encode, 0, 0, Opcode_scm_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_scm_Slot_smod_slot0_encode, 0, 0, Opcode_scm_Slot_llr_slot0_encode, 0, 0, Opcode_scm_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_scm_pinc_encode_fns[] = { + Opcode_scm_pinc_Slot_inst_encode, 0, 0, 0, 0, Opcode_scm_pinc_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_scm_pinc_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_scm_pinc_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_scm_pinc_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_scm_pinc_x_encode_fns[] = { + Opcode_scm_pinc_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_scm_pinc_x_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_scm_pinc_x_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_scm_pinc_x_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_scm_pinc_x_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_scm_u_encode_fns[] = { + Opcode_scm_u_Slot_inst_encode, 0, 0, 0, 0, Opcode_scm_u_Slot_gp_slot0_encode, 0, 0, Opcode_scm_u_Slot_dot_slot0_encode, 0, 0, Opcode_scm_u_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_scm_u_Slot_smod_slot0_encode, 0, 0, Opcode_scm_u_Slot_llr_slot0_encode, 0, 0, Opcode_scm_u_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_scm_x_encode_fns[] = { + Opcode_scm_x_Slot_inst_encode, 0, 0, 0, 0, Opcode_scm_x_Slot_gp_slot0_encode, 0, 0, Opcode_scm_x_Slot_dot_slot0_encode, 0, 0, Opcode_scm_x_Slot_pq_slot0_encode, 0, 0, Opcode_scm_x_Slot_acc2_slot0_encode, 0, 0, Opcode_scm_x_Slot_smod_slot0_encode, 0, 0, Opcode_scm_x_Slot_llr_slot0_encode, 0, 0, Opcode_scm_x_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_scm_xu_encode_fns[] = { + Opcode_scm_xu_Slot_inst_encode, 0, 0, 0, 0, Opcode_scm_xu_Slot_gp_slot0_encode, 0, 0, Opcode_scm_xu_Slot_dot_slot0_encode, 0, 0, Opcode_scm_xu_Slot_pq_slot0_encode, 0, 0, Opcode_scm_xu_Slot_acc2_slot0_encode, 0, 0, Opcode_scm_xu_Slot_smod_slot0_encode, 0, 0, Opcode_scm_xu_Slot_llr_slot0_encode, 0, 0, Opcode_scm_xu_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_store_p_encode_fns[] = { + Opcode_store_p_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_store_p_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_store_p_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_store_q_encode_fns[] = { + Opcode_store_q_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_store_q_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_store_q_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ar2cm_dup_encode_fns[] = { + Opcode_ar2cm_dup_Slot_inst_encode, 0, 0, Opcode_ar2cm_dup_Slot_gp_slot2_encode, 0, Opcode_ar2cm_dup_Slot_gp_slot0_encode, Opcode_ar2cm_dup_Slot_dot_slot2_encode, 0, Opcode_ar2cm_dup_Slot_dot_slot0_encode, Opcode_ar2cm_dup_Slot_pq_slot2_encode, 0, Opcode_ar2cm_dup_Slot_pq_slot0_encode, 0, 0, 0, Opcode_ar2cm_dup_Slot_smod_slot2_encode, 0, Opcode_ar2cm_dup_Slot_smod_slot0_encode, Opcode_ar2cm_dup_Slot_llr_slot2_encode, 0, Opcode_ar2cm_dup_Slot_llr_slot0_encode, Opcode_ar2cm_dup_Slot_dual_slot2_encode, 0, Opcode_ar2cm_dup_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ar2cm_ln_encode_fns[] = { + Opcode_ar2cm_ln_Slot_inst_encode, 0, 0, Opcode_ar2cm_ln_Slot_gp_slot2_encode, 0, Opcode_ar2cm_ln_Slot_gp_slot0_encode, Opcode_ar2cm_ln_Slot_dot_slot2_encode, 0, Opcode_ar2cm_ln_Slot_dot_slot0_encode, Opcode_ar2cm_ln_Slot_pq_slot2_encode, 0, Opcode_ar2cm_ln_Slot_pq_slot0_encode, 0, 0, 0, Opcode_ar2cm_ln_Slot_smod_slot2_encode, 0, Opcode_ar2cm_ln_Slot_smod_slot0_encode, Opcode_ar2cm_ln_Slot_llr_slot2_encode, 0, Opcode_ar2cm_ln_Slot_llr_slot0_encode, Opcode_ar2cm_ln_Slot_dual_slot2_encode, 0, Opcode_ar2cm_ln_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ar2cm_ln_i_encode_fns[] = { + Opcode_ar2cm_ln_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ar2cm_ln_i_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_ar2cm_ln_i_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_ar2cm_ln_i_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_ar2cm_ln_i_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ar2cm_ln_r_encode_fns[] = { + Opcode_ar2cm_ln_r_Slot_inst_encode, 0, 0, 0, 0, Opcode_ar2cm_ln_r_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_ar2cm_ln_r_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_ar2cm_ln_r_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_ar2cm_ln_r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ar2pq_ln_encode_fns[] = { + 0, 0, 0, Opcode_ar2pq_ln_Slot_gp_slot2_encode, 0, 0, Opcode_ar2pq_ln_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ar2pq_ln_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ar2sar_dup_encode_fns[] = { + 0, 0, 0, Opcode_ar2sar_dup_Slot_gp_slot2_encode, 0, 0, Opcode_ar2sar_dup_Slot_dot_slot2_encode, 0, 0, Opcode_ar2sar_dup_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_ar2sar_dup_Slot_smod_slot2_encode, 0, 0, Opcode_ar2sar_dup_Slot_llr_slot2_encode, 0, 0, Opcode_ar2sar_dup_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrac_encode_fns[] = { + Opcode_clrac_Slot_inst_encode, 0, 0, 0, 0, Opcode_clrac_Slot_gp_slot0_encode, 0, 0, Opcode_clrac_Slot_dot_slot0_encode, 0, 0, Opcode_clrac_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clrac_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_clrcm_encode_fns[] = { + Opcode_clrcm_Slot_inst_encode, 0, 0, Opcode_clrcm_Slot_gp_slot2_encode, 0, Opcode_clrcm_Slot_gp_slot0_encode, Opcode_clrcm_Slot_dot_slot2_encode, 0, Opcode_clrcm_Slot_dot_slot0_encode, Opcode_clrcm_Slot_pq_slot2_encode, 0, Opcode_clrcm_Slot_pq_slot0_encode, Opcode_clrcm_Slot_acc2_slot2_encode, 0, Opcode_clrcm_Slot_acc2_slot0_encode, Opcode_clrcm_Slot_smod_slot2_encode, 0, Opcode_clrcm_Slot_smod_slot0_encode, Opcode_clrcm_Slot_llr_slot2_encode, 0, Opcode_clrcm_Slot_llr_slot0_encode, Opcode_clrcm_Slot_dual_slot2_encode, 0, Opcode_clrcm_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_cm2ar_ln_encode_fns[] = { + Opcode_cm2ar_ln_Slot_inst_encode, 0, 0, Opcode_cm2ar_ln_Slot_gp_slot2_encode, 0, Opcode_cm2ar_ln_Slot_gp_slot0_encode, Opcode_cm2ar_ln_Slot_dot_slot2_encode, 0, Opcode_cm2ar_ln_Slot_dot_slot0_encode, Opcode_cm2ar_ln_Slot_pq_slot2_encode, 0, Opcode_cm2ar_ln_Slot_pq_slot0_encode, 0, 0, 0, Opcode_cm2ar_ln_Slot_smod_slot2_encode, 0, Opcode_cm2ar_ln_Slot_smod_slot0_encode, Opcode_cm2ar_ln_Slot_llr_slot2_encode, 0, Opcode_cm2ar_ln_Slot_llr_slot0_encode, Opcode_cm2ar_ln_Slot_dual_slot2_encode, 0, Opcode_cm2ar_ln_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_cm2ar_ln_i_encode_fns[] = { + Opcode_cm2ar_ln_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_cm2ar_ln_i_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_cm2ar_ln_i_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_cm2ar_ln_i_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_cm2ar_ln_i_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_cm2ar_ln_r_encode_fns[] = { + Opcode_cm2ar_ln_r_Slot_inst_encode, 0, 0, 0, 0, Opcode_cm2ar_ln_r_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_cm2ar_ln_r_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_cm2ar_ln_r_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_cm2ar_ln_r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_comb_ar_encode_fns[] = { + Opcode_comb_ar_Slot_inst_encode, 0, 0, 0, 0, Opcode_comb_ar_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_comb_ar_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_comb_ar_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_comb_ar_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_conj_encode_fns[] = { + Opcode_conj_Slot_inst_encode, 0, 0, Opcode_conj_Slot_gp_slot2_encode, 0, Opcode_conj_Slot_gp_slot0_encode, Opcode_conj_Slot_dot_slot2_encode, 0, Opcode_conj_Slot_dot_slot0_encode, Opcode_conj_Slot_pq_slot2_encode, 0, Opcode_conj_Slot_pq_slot0_encode, Opcode_conj_Slot_acc2_slot2_encode, 0, Opcode_conj_Slot_acc2_slot0_encode, Opcode_conj_Slot_smod_slot2_encode, 0, Opcode_conj_Slot_smod_slot0_encode, Opcode_conj_Slot_llr_slot2_encode, 0, Opcode_conj_Slot_llr_slot0_encode, Opcode_conj_Slot_dual_slot2_encode, 0, Opcode_conj_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_mov2ac32_i_encode_fns[] = { + Opcode_mov2ac32_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_mov2ac32_i_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_mov2ac32_i_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mov2ac32_i_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_mov2ac32_r_encode_fns[] = { + Opcode_mov2ac32_r_Slot_inst_encode, 0, 0, 0, 0, Opcode_mov2ac32_r_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_mov2ac32_r_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mov2ac32_r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_mov2cm2pq_encode_fns[] = { + 0, 0, 0, Opcode_mov2cm2pq_Slot_gp_slot2_encode, 0, 0, Opcode_mov2cm2pq_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mov2cm2pq_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movac_encode_fns[] = { + Opcode_movac_Slot_inst_encode, 0, 0, 0, 0, Opcode_movac_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_movac_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movac_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movac_i_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movac_i_Slot_llr_slot1_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movac_i2r_encode_fns[] = { + Opcode_movac_i2r_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movac_r_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movac_r_Slot_llr_slot1_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movac_r2i_encode_fns[] = { + Opcode_movac_r2i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movar2_encode_fns[] = { + 0, 0, 0, Opcode_movar2_Slot_gp_slot2_encode, 0, 0, Opcode_movar2_Slot_dot_slot2_encode, 0, 0, Opcode_movar2_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movar2_Slot_smod_slot2_encode, 0, 0, Opcode_movar2_Slot_llr_slot2_encode, 0, 0, Opcode_movar2_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcm_encode_fns[] = { + Opcode_movcm_Slot_inst_encode, 0, 0, Opcode_movcm_Slot_gp_slot2_encode, 0, Opcode_movcm_Slot_gp_slot0_encode, Opcode_movcm_Slot_dot_slot2_encode, 0, Opcode_movcm_Slot_dot_slot0_encode, Opcode_movcm_Slot_pq_slot2_encode, 0, Opcode_movcm_Slot_pq_slot0_encode, Opcode_movcm_Slot_acc2_slot2_encode, 0, Opcode_movcm_Slot_acc2_slot0_encode, Opcode_movcm_Slot_smod_slot2_encode, 0, Opcode_movcm_Slot_smod_slot0_encode, Opcode_movcm_Slot_llr_slot2_encode, 0, Opcode_movcm_Slot_llr_slot0_encode, Opcode_movcm_Slot_dual_slot2_encode, 0, Opcode_movcm_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movcm2pq_encode_fns[] = { + Opcode_movcm2pq_Slot_inst_encode, 0, 0, Opcode_movcm2pq_Slot_gp_slot2_encode, 0, 0, Opcode_movcm2pq_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_movcm2pq_Slot_acc2_slot0_encode, Opcode_movcm2pq_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_movcm2pq_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movcnd_0_encode_fns[] = { + 0, 0, 0, Opcode_movcnd_0_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd_0_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd_0_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd_0_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd_0_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd_0_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd_1_encode_fns[] = { + 0, 0, 0, Opcode_movcnd_1_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd_1_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd_1_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd_1_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd_1_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd_1_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd_2_encode_fns[] = { + 0, 0, 0, Opcode_movcnd_2_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd_2_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd_2_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd_2_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd_2_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd_2_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd_3_encode_fns[] = { + 0, 0, 0, Opcode_movcnd_3_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd_3_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd_3_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd_3_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd_3_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd_3_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd_4_encode_fns[] = { + 0, 0, 0, Opcode_movcnd_4_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd_4_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd_4_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd_4_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd_4_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd_4_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd_5_encode_fns[] = { + 0, 0, 0, Opcode_movcnd_5_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd_5_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd_5_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd_5_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd_5_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd_5_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd_6_encode_fns[] = { + 0, 0, 0, Opcode_movcnd_6_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd_6_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd_6_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd_6_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd_6_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd_6_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd_7_encode_fns[] = { + 0, 0, 0, Opcode_movcnd_7_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd_7_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd_7_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd_7_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd_7_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd_7_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd8_0_encode_fns[] = { + 0, 0, 0, Opcode_movcnd8_0_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd8_0_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd8_0_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd8_0_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd8_0_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd8_0_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd8_1_encode_fns[] = { + 0, 0, 0, Opcode_movcnd8_1_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd8_1_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd8_1_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd8_1_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd8_1_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd8_1_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd8_2_encode_fns[] = { + 0, 0, 0, Opcode_movcnd8_2_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd8_2_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd8_2_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd8_2_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd8_2_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd8_2_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd8_3_encode_fns[] = { + 0, 0, 0, Opcode_movcnd8_3_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd8_3_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd8_3_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd8_3_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd8_3_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd8_3_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd8_4_encode_fns[] = { + 0, 0, 0, Opcode_movcnd8_4_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd8_4_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd8_4_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd8_4_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd8_4_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd8_4_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd8_5_encode_fns[] = { + 0, 0, 0, Opcode_movcnd8_5_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd8_5_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd8_5_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd8_5_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd8_5_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd8_5_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd8_6_encode_fns[] = { + 0, 0, 0, Opcode_movcnd8_6_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd8_6_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd8_6_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd8_6_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd8_6_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd8_6_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_movcnd8_7_encode_fns[] = { + 0, 0, 0, Opcode_movcnd8_7_Slot_gp_slot2_encode, 0, 0, Opcode_movcnd8_7_Slot_dot_slot2_encode, 0, 0, Opcode_movcnd8_7_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_movcnd8_7_Slot_smod_slot2_encode, 0, 0, Opcode_movcnd8_7_Slot_llr_slot2_encode, 0, 0, Opcode_movcnd8_7_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_i_encode_fns[] = { + Opcode_mov_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_mov_i_Slot_gp_slot0_encode, 0, 0, Opcode_mov_i_Slot_dot_slot0_encode, 0, 0, Opcode_mov_i_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_mov_i_Slot_smod_slot0_encode, 0, 0, Opcode_mov_i_Slot_llr_slot0_encode, 0, 0, Opcode_mov_i_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_movpq2pq_encode_fns[] = { + 0, 0, 0, Opcode_movpq2pq_Slot_gp_slot2_encode, 0, 0, Opcode_movpq2pq_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_movpq2pq_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov_r_encode_fns[] = { + Opcode_mov_r_Slot_inst_encode, 0, 0, 0, 0, Opcode_mov_r_Slot_gp_slot0_encode, 0, 0, Opcode_mov_r_Slot_dot_slot0_encode, 0, 0, Opcode_mov_r_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_mov_r_Slot_smod_slot0_encode, 0, 0, Opcode_mov_r_Slot_llr_slot0_encode, 0, 0, Opcode_mov_r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_negcm_encode_fns[] = { + Opcode_negcm_Slot_inst_encode, 0, 0, Opcode_negcm_Slot_gp_slot2_encode, 0, Opcode_negcm_Slot_gp_slot0_encode, Opcode_negcm_Slot_dot_slot2_encode, 0, Opcode_negcm_Slot_dot_slot0_encode, Opcode_negcm_Slot_pq_slot2_encode, 0, Opcode_negcm_Slot_pq_slot0_encode, Opcode_negcm_Slot_acc2_slot2_encode, 0, Opcode_negcm_Slot_acc2_slot0_encode, Opcode_negcm_Slot_smod_slot2_encode, 0, Opcode_negcm_Slot_smod_slot0_encode, Opcode_negcm_Slot_llr_slot2_encode, 0, Opcode_negcm_Slot_llr_slot0_encode, Opcode_negcm_Slot_dual_slot2_encode, 0, Opcode_negcm_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop16llr_1_encode_fns[] = { + Opcode_pop16llr_1_Slot_inst_encode, 0, 0, 0, 0, Opcode_pop16llr_1_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_pop16llr_1_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_pop16llr_1_Slot_llr_slot0_encode, 0, 0, Opcode_pop16llr_1_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pq2cm_encode_fns[] = { + Opcode_pq2cm_Slot_inst_encode, 0, 0, Opcode_pq2cm_Slot_gp_slot2_encode, 0, 0, Opcode_pq2cm_Slot_dot_slot2_encode, 0, 0, Opcode_pq2cm_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_pq2cm_Slot_smod_slot2_encode, 0, 0, Opcode_pq2cm_Slot_llr_slot2_encode, 0, 0, Opcode_pq2cm_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_swapac_r_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_swapac_r_Slot_acc2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_swapac_ri_encode_fns[] = { + Opcode_swapac_ri_Slot_inst_encode, 0, 0, 0, 0, Opcode_swapac_ri_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_swapac_ri_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_swapac_ri_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_swapb_encode_fns[] = { + Opcode_swapb_Slot_inst_encode, 0, 0, Opcode_swapb_Slot_gp_slot2_encode, 0, 0, Opcode_swapb_Slot_dot_slot2_encode, 0, 0, Opcode_swapb_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_swapb_Slot_smod_slot2_encode, 0, 0, Opcode_swapb_Slot_llr_slot2_encode, 0, 0, Opcode_swapb_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add2ac_encode_fns[] = { + 0, 0, 0, 0, Opcode_add2ac_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addac_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addac_Slot_llr_slot1_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cdot_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_cdot_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cdotac_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_cdotac_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cdotacs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_cdotacs_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cmac_encode_fns[] = { + 0, 0, 0, 0, Opcode_cmac_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cmac_Slot_smod_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cmacs_encode_fns[] = { + 0, 0, 0, 0, Opcode_cmacs_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cmpy_encode_fns[] = { + 0, 0, 0, 0, Opcode_cmpy_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cmpy_Slot_smod_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cmpy2cm_encode_fns[] = { + 0, 0, 0, 0, Opcode_cmpy2cm_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cmpy2cm_Slot_smod_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cmpy2pq_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cmpy2pq_Slot_pq_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cmpys_encode_fns[] = { + 0, 0, 0, 0, Opcode_cmpys_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cmpyxp2pq_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_cmpyxp2pq_Slot_pq_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_comb32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_comb32_Slot_llr_slot1_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dot_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_dot_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dotac_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_dotac_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_dotacs_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_dotacs_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lin_int_encode_fns[] = { + 0, 0, 0, 0, Opcode_lin_int_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_llrpre1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_llrpre1_Slot_acc2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_llrpre2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_llrpre2_Slot_llr_slot1_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mac_encode_fns[] = { + 0, 0, 0, 0, Opcode_mac_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mac_Slot_smod_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mac8_encode_fns[] = { + 0, 0, 0, 0, Opcode_mac8_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_macd8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_macd8_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_macpqxp_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_macpqxp_0_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_macpqxp_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_macpqxp_1_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_macpqxp_2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_macpqxp_2_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_macpqxp_3_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_macpqxp_3_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_macs_encode_fns[] = { + 0, 0, 0, 0, Opcode_macs_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_macxp2_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_macxp2_0_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_macxp2_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_macxp2_1_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_macxp_0_encode_fns[] = { + 0, 0, 0, 0, Opcode_macxp_0_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_macxp_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_macxp_1_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_macxp_2_encode_fns[] = { + 0, 0, 0, 0, Opcode_macxp_2_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_macxp_3_encode_fns[] = { + 0, 0, 0, 0, Opcode_macxp_3_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mov2ac_encode_fns[] = { + 0, 0, 0, 0, Opcode_mov2ac_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpy_encode_fns[] = { + 0, 0, 0, 0, Opcode_mpy_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mpy_Slot_smod_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpy2cm_encode_fns[] = { + 0, 0, 0, 0, Opcode_mpy2cm_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mpy2cm_Slot_smod_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpy2pq_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mpy2pq_Slot_pq_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpy8_encode_fns[] = { + 0, 0, 0, 0, Opcode_mpy8_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpyadd8_2cm_encode_fns[] = { + 0, 0, 0, 0, Opcode_mpyadd8_2cm_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mpyadd8_2cm_Slot_smod_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpyd8_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_mpyd8_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpypqxp_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_mpypqxp_0_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpypqxp_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_mpypqxp_1_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpypqxp_2_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_mpypqxp_2_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpypqxp_3_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_mpypqxp_3_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpys_encode_fns[] = { + 0, 0, 0, 0, Opcode_mpys_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpyxp2pq_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_mpyxp2pq_Slot_pq_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpyxp2_0_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_mpyxp2_0_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpyxp2_1_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, Opcode_mpyxp2_1_Slot_dot_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpyxp_0_encode_fns[] = { + 0, 0, 0, 0, Opcode_mpyxp_0_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpyxp_1_encode_fns[] = { + 0, 0, 0, 0, Opcode_mpyxp_1_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpyxp_2_encode_fns[] = { + 0, 0, 0, 0, Opcode_mpyxp_2_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mpyxp_3_encode_fns[] = { + 0, 0, 0, 0, Opcode_mpyxp_3_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_normacd_encode_fns[] = { + 0, 0, 0, 0, Opcode_normacd_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_normacd_Slot_smod_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_normacpq_i_encode_fns[] = { + 0, 0, 0, 0, Opcode_normacpq_i_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_normacpq_r_encode_fns[] = { + 0, 0, 0, 0, Opcode_normacpq_r_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_normd_encode_fns[] = { + 0, 0, 0, 0, Opcode_normd_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_normd_Slot_smod_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_normpypq_i_encode_fns[] = { + 0, 0, 0, 0, Opcode_normpypq_i_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_normpypq_r_encode_fns[] = { + 0, 0, 0, 0, Opcode_normpypq_r_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rcmac_encode_fns[] = { + 0, 0, 0, 0, Opcode_rcmac_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rcmpy_encode_fns[] = { + 0, 0, 0, 0, Opcode_rcmpy_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rcmpy2cm_encode_fns[] = { + 0, 0, 0, 0, Opcode_rcmpy2cm_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rcmpy2cm_Slot_smod_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfir_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rfir_Slot_acc2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfira_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rfira_Slot_acc2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfird_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rfird_Slot_acc2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rfirda_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rfirda_Slot_acc2_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rmac_encode_fns[] = { + 0, 0, 0, 0, Opcode_rmac_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rmpy_encode_fns[] = { + 0, 0, 0, 0, Opcode_rmpy_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rmpy2cm_encode_fns[] = { + 0, 0, 0, 0, Opcode_rmpy2cm_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_rmpy2cm_Slot_smod_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_smod_align_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_smod_align_Slot_smod_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_smod_scr_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_smod_scr_Slot_smod_slot1_encode, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_sub2ac_encode_fns[] = { + 0, 0, 0, 0, Opcode_sub2ac_Slot_gp_slot1_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wght32_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_wght32_Slot_llr_slot1_encode, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clrtiep_encode_fns[] = { + Opcode_clrtiep_Slot_inst_encode, 0, 0, Opcode_clrtiep_Slot_gp_slot2_encode, 0, 0, Opcode_clrtiep_Slot_dot_slot2_encode, 0, 0, Opcode_clrtiep_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_clrtiep_Slot_smod_slot2_encode, 0, 0, Opcode_clrtiep_Slot_llr_slot2_encode, 0, 0, Opcode_clrtiep_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ext_2fifo_0_encode_fns[] = { + Opcode_ext_2fifo_0_Slot_inst_encode, 0, 0, 0, 0, Opcode_ext_2fifo_0_Slot_gp_slot0_encode, 0, 0, Opcode_ext_2fifo_0_Slot_dot_slot0_encode, 0, 0, Opcode_ext_2fifo_0_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ext_2fifo_0_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ext_2fifo_1_encode_fns[] = { + Opcode_ext_2fifo_1_Slot_inst_encode, 0, 0, 0, 0, Opcode_ext_2fifo_1_Slot_gp_slot0_encode, 0, 0, Opcode_ext_2fifo_1_Slot_dot_slot0_encode, 0, 0, Opcode_ext_2fifo_1_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ext_2fifo_1_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ext_2fifo_2_encode_fns[] = { + Opcode_ext_2fifo_2_Slot_inst_encode, 0, 0, 0, 0, Opcode_ext_2fifo_2_Slot_gp_slot0_encode, 0, 0, Opcode_ext_2fifo_2_Slot_dot_slot0_encode, 0, 0, Opcode_ext_2fifo_2_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ext_2fifo_2_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ext_2fifo_3_encode_fns[] = { + Opcode_ext_2fifo_3_Slot_inst_encode, 0, 0, 0, 0, Opcode_ext_2fifo_3_Slot_gp_slot0_encode, 0, 0, Opcode_ext_2fifo_3_Slot_dot_slot0_encode, 0, 0, Opcode_ext_2fifo_3_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ext_2fifo_3_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ext_r2fifo_0_encode_fns[] = { + Opcode_ext_r2fifo_0_Slot_inst_encode, 0, 0, 0, 0, Opcode_ext_r2fifo_0_Slot_gp_slot0_encode, 0, 0, Opcode_ext_r2fifo_0_Slot_dot_slot0_encode, 0, 0, Opcode_ext_r2fifo_0_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ext_r2fifo_0_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ext_r2fifo_1_encode_fns[] = { + Opcode_ext_r2fifo_1_Slot_inst_encode, 0, 0, 0, 0, Opcode_ext_r2fifo_1_Slot_gp_slot0_encode, 0, 0, Opcode_ext_r2fifo_1_Slot_dot_slot0_encode, 0, 0, Opcode_ext_r2fifo_1_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ext_r2fifo_1_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ext_r2fifo_2_encode_fns[] = { + Opcode_ext_r2fifo_2_Slot_inst_encode, 0, 0, 0, 0, Opcode_ext_r2fifo_2_Slot_gp_slot0_encode, 0, 0, Opcode_ext_r2fifo_2_Slot_dot_slot0_encode, 0, 0, Opcode_ext_r2fifo_2_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ext_r2fifo_2_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ext_r2fifo_3_encode_fns[] = { + Opcode_ext_r2fifo_3_Slot_inst_encode, 0, 0, 0, 0, Opcode_ext_r2fifo_3_Slot_gp_slot0_encode, 0, 0, Opcode_ext_r2fifo_3_Slot_dot_slot0_encode, 0, 0, Opcode_ext_r2fifo_3_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ext_r2fifo_3_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_lut_encode_fns[] = { + 0, 0, 0, Opcode_lut_Slot_gp_slot2_encode, 0, 0, Opcode_lut_Slot_dot_slot2_encode, 0, 0, Opcode_lut_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_lut_Slot_smod_slot2_encode, 0, 0, Opcode_lut_Slot_llr_slot2_encode, 0, 0, Opcode_lut_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lut_ar_encode_fns[] = { + 0, 0, 0, Opcode_lut_ar_Slot_gp_slot2_encode, 0, 0, Opcode_lut_ar_Slot_dot_slot2_encode, 0, 0, Opcode_lut_ar_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_lut_ar_Slot_smod_slot2_encode, 0, 0, Opcode_lut_ar_Slot_llr_slot2_encode, 0, 0, Opcode_lut_ar_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lut_iext_encode_fns[] = { + 0, 0, 0, Opcode_lut_iext_Slot_gp_slot2_encode, 0, 0, Opcode_lut_iext_Slot_dot_slot2_encode, 0, 0, Opcode_lut_iext_Slot_pq_slot2_encode, 0, 0, Opcode_lut_iext_Slot_acc2_slot2_encode, 0, 0, Opcode_lut_iext_Slot_smod_slot2_encode, 0, 0, Opcode_lut_iext_Slot_llr_slot2_encode, 0, 0, Opcode_lut_iext_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lut_phasor_encode_fns[] = { + 0, 0, 0, Opcode_lut_phasor_Slot_gp_slot2_encode, 0, 0, Opcode_lut_phasor_Slot_dot_slot2_encode, 0, 0, Opcode_lut_phasor_Slot_pq_slot2_encode, 0, 0, Opcode_lut_phasor_Slot_acc2_slot2_encode, 0, 0, Opcode_lut_phasor_Slot_smod_slot2_encode, 0, 0, Opcode_lut_phasor_Slot_llr_slot2_encode, 0, 0, Opcode_lut_phasor_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lut_rext_encode_fns[] = { + 0, 0, 0, Opcode_lut_rext_Slot_gp_slot2_encode, 0, 0, Opcode_lut_rext_Slot_dot_slot2_encode, 0, 0, Opcode_lut_rext_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_lut_rext_Slot_smod_slot2_encode, 0, 0, Opcode_lut_rext_Slot_llr_slot2_encode, 0, 0, Opcode_lut_rext_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lut_write_encode_fns[] = { + 0, 0, 0, Opcode_lut_write_Slot_gp_slot2_encode, 0, 0, Opcode_lut_write_Slot_dot_slot2_encode, 0, 0, Opcode_lut_write_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_lut_write_Slot_smod_slot2_encode, 0, 0, Opcode_lut_write_Slot_llr_slot2_encode, 0, 0, Opcode_lut_write_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveq128_0_encode_fns[] = { + Opcode_moveq128_0_Slot_inst_encode, 0, 0, Opcode_moveq128_0_Slot_gp_slot2_encode, 0, 0, Opcode_moveq128_0_Slot_dot_slot2_encode, 0, 0, Opcode_moveq128_0_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_moveq128_0_Slot_smod_slot2_encode, 0, 0, Opcode_moveq128_0_Slot_llr_slot2_encode, 0, 0, Opcode_moveq128_0_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveq128_1_encode_fns[] = { + Opcode_moveq128_1_Slot_inst_encode, 0, 0, Opcode_moveq128_1_Slot_gp_slot2_encode, 0, 0, Opcode_moveq128_1_Slot_dot_slot2_encode, 0, 0, Opcode_moveq128_1_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_moveq128_1_Slot_smod_slot2_encode, 0, 0, Opcode_moveq128_1_Slot_llr_slot2_encode, 0, 0, Opcode_moveq128_1_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveq128_2_encode_fns[] = { + Opcode_moveq128_2_Slot_inst_encode, 0, 0, Opcode_moveq128_2_Slot_gp_slot2_encode, 0, 0, Opcode_moveq128_2_Slot_dot_slot2_encode, 0, 0, Opcode_moveq128_2_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_moveq128_2_Slot_smod_slot2_encode, 0, 0, Opcode_moveq128_2_Slot_llr_slot2_encode, 0, 0, Opcode_moveq128_2_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveq128_3_encode_fns[] = { + Opcode_moveq128_3_Slot_inst_encode, 0, 0, Opcode_moveq128_3_Slot_gp_slot2_encode, 0, 0, Opcode_moveq128_3_Slot_dot_slot2_encode, 0, 0, Opcode_moveq128_3_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_moveq128_3_Slot_smod_slot2_encode, 0, 0, Opcode_moveq128_3_Slot_llr_slot2_encode, 0, 0, Opcode_moveq128_3_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveq128_4_encode_fns[] = { + Opcode_moveq128_4_Slot_inst_encode, 0, 0, Opcode_moveq128_4_Slot_gp_slot2_encode, 0, 0, Opcode_moveq128_4_Slot_dot_slot2_encode, 0, 0, Opcode_moveq128_4_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_moveq128_4_Slot_smod_slot2_encode, 0, 0, Opcode_moveq128_4_Slot_llr_slot2_encode, 0, 0, Opcode_moveq128_4_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveq128_5_encode_fns[] = { + Opcode_moveq128_5_Slot_inst_encode, 0, 0, Opcode_moveq128_5_Slot_gp_slot2_encode, 0, 0, Opcode_moveq128_5_Slot_dot_slot2_encode, 0, 0, Opcode_moveq128_5_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_moveq128_5_Slot_smod_slot2_encode, 0, 0, Opcode_moveq128_5_Slot_llr_slot2_encode, 0, 0, Opcode_moveq128_5_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveq32_0_encode_fns[] = { + Opcode_moveq32_0_Slot_inst_encode, 0, 0, Opcode_moveq32_0_Slot_gp_slot2_encode, 0, 0, Opcode_moveq32_0_Slot_dot_slot2_encode, 0, 0, Opcode_moveq32_0_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_moveq32_0_Slot_smod_slot2_encode, 0, 0, Opcode_moveq32_0_Slot_llr_slot2_encode, 0, 0, Opcode_moveq32_0_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveq32_1_encode_fns[] = { + Opcode_moveq32_1_Slot_inst_encode, 0, 0, Opcode_moveq32_1_Slot_gp_slot2_encode, 0, 0, Opcode_moveq32_1_Slot_dot_slot2_encode, 0, 0, Opcode_moveq32_1_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_moveq32_1_Slot_smod_slot2_encode, 0, 0, Opcode_moveq32_1_Slot_llr_slot2_encode, 0, 0, Opcode_moveq32_1_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveq32_2_encode_fns[] = { + Opcode_moveq32_2_Slot_inst_encode, 0, 0, Opcode_moveq32_2_Slot_gp_slot2_encode, 0, 0, Opcode_moveq32_2_Slot_dot_slot2_encode, 0, 0, Opcode_moveq32_2_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_moveq32_2_Slot_smod_slot2_encode, 0, 0, Opcode_moveq32_2_Slot_llr_slot2_encode, 0, 0, Opcode_moveq32_2_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_moveq32_3_encode_fns[] = { + Opcode_moveq32_3_Slot_inst_encode, 0, 0, Opcode_moveq32_3_Slot_gp_slot2_encode, 0, 0, Opcode_moveq32_3_Slot_dot_slot2_encode, 0, 0, Opcode_moveq32_3_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_moveq32_3_Slot_smod_slot2_encode, 0, 0, Opcode_moveq32_3_Slot_llr_slot2_encode, 0, 0, Opcode_moveq32_3_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_nco_update_encode_fns[] = { + 0, 0, 0, Opcode_nco_update_Slot_gp_slot2_encode, 0, 0, Opcode_nco_update_Slot_dot_slot2_encode, 0, 0, Opcode_nco_update_Slot_pq_slot2_encode, 0, 0, Opcode_nco_update_Slot_acc2_slot2_encode, 0, 0, Opcode_nco_update_Slot_smod_slot2_encode, 0, 0, Opcode_nco_update_Slot_llr_slot2_encode, 0, 0, Opcode_nco_update_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pop128_0_encode_fns[] = { + Opcode_pop128_0_Slot_inst_encode, 0, 0, Opcode_pop128_0_Slot_gp_slot2_encode, 0, Opcode_pop128_0_Slot_gp_slot0_encode, Opcode_pop128_0_Slot_dot_slot2_encode, 0, Opcode_pop128_0_Slot_dot_slot0_encode, Opcode_pop128_0_Slot_pq_slot2_encode, 0, Opcode_pop128_0_Slot_pq_slot0_encode, Opcode_pop128_0_Slot_acc2_slot2_encode, 0, Opcode_pop128_0_Slot_acc2_slot0_encode, Opcode_pop128_0_Slot_smod_slot2_encode, 0, Opcode_pop128_0_Slot_smod_slot0_encode, Opcode_pop128_0_Slot_llr_slot2_encode, 0, Opcode_pop128_0_Slot_llr_slot0_encode, Opcode_pop128_0_Slot_dual_slot2_encode, 0, Opcode_pop128_0_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_1_encode_fns[] = { + Opcode_pop128_1_Slot_inst_encode, 0, 0, Opcode_pop128_1_Slot_gp_slot2_encode, 0, Opcode_pop128_1_Slot_gp_slot0_encode, Opcode_pop128_1_Slot_dot_slot2_encode, 0, Opcode_pop128_1_Slot_dot_slot0_encode, Opcode_pop128_1_Slot_pq_slot2_encode, 0, Opcode_pop128_1_Slot_pq_slot0_encode, Opcode_pop128_1_Slot_acc2_slot2_encode, 0, Opcode_pop128_1_Slot_acc2_slot0_encode, Opcode_pop128_1_Slot_smod_slot2_encode, 0, Opcode_pop128_1_Slot_smod_slot0_encode, Opcode_pop128_1_Slot_llr_slot2_encode, 0, Opcode_pop128_1_Slot_llr_slot0_encode, Opcode_pop128_1_Slot_dual_slot2_encode, 0, Opcode_pop128_1_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2_encode_fns[] = { + Opcode_pop128_2_Slot_inst_encode, 0, 0, Opcode_pop128_2_Slot_gp_slot2_encode, 0, Opcode_pop128_2_Slot_gp_slot0_encode, Opcode_pop128_2_Slot_dot_slot2_encode, 0, Opcode_pop128_2_Slot_dot_slot0_encode, Opcode_pop128_2_Slot_pq_slot2_encode, 0, Opcode_pop128_2_Slot_pq_slot0_encode, Opcode_pop128_2_Slot_acc2_slot2_encode, 0, Opcode_pop128_2_Slot_acc2_slot0_encode, Opcode_pop128_2_Slot_smod_slot2_encode, 0, Opcode_pop128_2_Slot_smod_slot0_encode, Opcode_pop128_2_Slot_llr_slot2_encode, 0, Opcode_pop128_2_Slot_llr_slot0_encode, Opcode_pop128_2_Slot_dual_slot2_encode, 0, Opcode_pop128_2_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_3_encode_fns[] = { + Opcode_pop128_3_Slot_inst_encode, 0, 0, Opcode_pop128_3_Slot_gp_slot2_encode, 0, Opcode_pop128_3_Slot_gp_slot0_encode, Opcode_pop128_3_Slot_dot_slot2_encode, 0, Opcode_pop128_3_Slot_dot_slot0_encode, Opcode_pop128_3_Slot_pq_slot2_encode, 0, Opcode_pop128_3_Slot_pq_slot0_encode, Opcode_pop128_3_Slot_acc2_slot2_encode, 0, Opcode_pop128_3_Slot_acc2_slot0_encode, Opcode_pop128_3_Slot_smod_slot2_encode, 0, Opcode_pop128_3_Slot_smod_slot0_encode, Opcode_pop128_3_Slot_llr_slot2_encode, 0, Opcode_pop128_3_Slot_llr_slot0_encode, Opcode_pop128_3_Slot_dual_slot2_encode, 0, Opcode_pop128_3_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_4_encode_fns[] = { + Opcode_pop128_4_Slot_inst_encode, 0, 0, Opcode_pop128_4_Slot_gp_slot2_encode, 0, Opcode_pop128_4_Slot_gp_slot0_encode, Opcode_pop128_4_Slot_dot_slot2_encode, 0, Opcode_pop128_4_Slot_dot_slot0_encode, Opcode_pop128_4_Slot_pq_slot2_encode, 0, Opcode_pop128_4_Slot_pq_slot0_encode, Opcode_pop128_4_Slot_acc2_slot2_encode, 0, Opcode_pop128_4_Slot_acc2_slot0_encode, Opcode_pop128_4_Slot_smod_slot2_encode, 0, Opcode_pop128_4_Slot_smod_slot0_encode, Opcode_pop128_4_Slot_llr_slot2_encode, 0, Opcode_pop128_4_Slot_llr_slot0_encode, Opcode_pop128_4_Slot_dual_slot2_encode, 0, Opcode_pop128_4_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_5_encode_fns[] = { + Opcode_pop128_5_Slot_inst_encode, 0, 0, Opcode_pop128_5_Slot_gp_slot2_encode, 0, Opcode_pop128_5_Slot_gp_slot0_encode, Opcode_pop128_5_Slot_dot_slot2_encode, 0, Opcode_pop128_5_Slot_dot_slot0_encode, Opcode_pop128_5_Slot_pq_slot2_encode, 0, Opcode_pop128_5_Slot_pq_slot0_encode, Opcode_pop128_5_Slot_acc2_slot2_encode, 0, Opcode_pop128_5_Slot_acc2_slot0_encode, Opcode_pop128_5_Slot_smod_slot2_encode, 0, Opcode_pop128_5_Slot_smod_slot0_encode, Opcode_pop128_5_Slot_llr_slot2_encode, 0, Opcode_pop128_5_Slot_llr_slot0_encode, Opcode_pop128_5_Slot_dual_slot2_encode, 0, Opcode_pop128_5_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2cmpq_0_encode_fns[] = { + 0, 0, 0, Opcode_pop128_2cmpq_0_Slot_gp_slot2_encode, 0, 0, Opcode_pop128_2cmpq_0_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2cmpq_0_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2cmpq_1_encode_fns[] = { + 0, 0, 0, Opcode_pop128_2cmpq_1_Slot_gp_slot2_encode, 0, 0, Opcode_pop128_2cmpq_1_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2cmpq_1_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2cmpq_2_encode_fns[] = { + 0, 0, 0, Opcode_pop128_2cmpq_2_Slot_gp_slot2_encode, 0, 0, Opcode_pop128_2cmpq_2_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2cmpq_2_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2cmpq_3_encode_fns[] = { + 0, 0, 0, Opcode_pop128_2cmpq_3_Slot_gp_slot2_encode, 0, 0, Opcode_pop128_2cmpq_3_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2cmpq_3_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2m_0_encode_fns[] = { + Opcode_pop128_2m_0_Slot_inst_encode, 0, 0, 0, 0, Opcode_pop128_2m_0_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_pop128_2m_0_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_pop128_2m_0_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_pop128_2m_0_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2m_1_encode_fns[] = { + Opcode_pop128_2m_1_Slot_inst_encode, 0, 0, 0, 0, Opcode_pop128_2m_1_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_pop128_2m_1_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_pop128_2m_1_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_pop128_2m_1_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2m_2_encode_fns[] = { + Opcode_pop128_2m_2_Slot_inst_encode, 0, 0, 0, 0, Opcode_pop128_2m_2_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_pop128_2m_2_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_pop128_2m_2_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_pop128_2m_2_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2m_3_encode_fns[] = { + Opcode_pop128_2m_3_Slot_inst_encode, 0, 0, 0, 0, Opcode_pop128_2m_3_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_pop128_2m_3_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_pop128_2m_3_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_pop128_2m_3_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2pq_0_encode_fns[] = { + Opcode_pop128_2pq_0_Slot_inst_encode, 0, 0, Opcode_pop128_2pq_0_Slot_gp_slot2_encode, 0, 0, Opcode_pop128_2pq_0_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2pq_0_Slot_acc2_slot0_encode, Opcode_pop128_2pq_0_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2pq_0_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2pq_1_encode_fns[] = { + Opcode_pop128_2pq_1_Slot_inst_encode, 0, 0, Opcode_pop128_2pq_1_Slot_gp_slot2_encode, 0, 0, Opcode_pop128_2pq_1_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2pq_1_Slot_acc2_slot0_encode, Opcode_pop128_2pq_1_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2pq_1_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2pq_2_encode_fns[] = { + Opcode_pop128_2pq_2_Slot_inst_encode, 0, 0, Opcode_pop128_2pq_2_Slot_gp_slot2_encode, 0, 0, Opcode_pop128_2pq_2_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2pq_2_Slot_acc2_slot0_encode, Opcode_pop128_2pq_2_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2pq_2_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2pq_3_encode_fns[] = { + Opcode_pop128_2pq_3_Slot_inst_encode, 0, 0, Opcode_pop128_2pq_3_Slot_gp_slot2_encode, 0, 0, Opcode_pop128_2pq_3_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2pq_3_Slot_acc2_slot0_encode, Opcode_pop128_2pq_3_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2pq_3_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2pq_4_encode_fns[] = { + Opcode_pop128_2pq_4_Slot_inst_encode, 0, 0, Opcode_pop128_2pq_4_Slot_gp_slot2_encode, 0, 0, Opcode_pop128_2pq_4_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2pq_4_Slot_acc2_slot0_encode, Opcode_pop128_2pq_4_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2pq_4_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop128_2pq_5_encode_fns[] = { + Opcode_pop128_2pq_5_Slot_inst_encode, 0, 0, Opcode_pop128_2pq_5_Slot_gp_slot2_encode, 0, 0, Opcode_pop128_2pq_5_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2pq_5_Slot_acc2_slot0_encode, Opcode_pop128_2pq_5_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop128_2pq_5_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop2x128_2pq_01_encode_fns[] = { + Opcode_pop2x128_2pq_01_Slot_inst_encode, 0, 0, Opcode_pop2x128_2pq_01_Slot_gp_slot2_encode, 0, 0, Opcode_pop2x128_2pq_01_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop2x128_2pq_01_Slot_acc2_slot0_encode, Opcode_pop2x128_2pq_01_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop2x128_2pq_01_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop2x128_2pq_03_encode_fns[] = { + Opcode_pop2x128_2pq_03_Slot_inst_encode, 0, 0, Opcode_pop2x128_2pq_03_Slot_gp_slot2_encode, 0, 0, Opcode_pop2x128_2pq_03_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop2x128_2pq_03_Slot_acc2_slot0_encode, Opcode_pop2x128_2pq_03_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop2x128_2pq_03_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop2x128_2pq_21_encode_fns[] = { + Opcode_pop2x128_2pq_21_Slot_inst_encode, 0, 0, Opcode_pop2x128_2pq_21_Slot_gp_slot2_encode, 0, 0, Opcode_pop2x128_2pq_21_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop2x128_2pq_21_Slot_acc2_slot0_encode, Opcode_pop2x128_2pq_21_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop2x128_2pq_21_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop2x128_2pq_23_encode_fns[] = { + Opcode_pop2x128_2pq_23_Slot_inst_encode, 0, 0, Opcode_pop2x128_2pq_23_Slot_gp_slot2_encode, 0, 0, Opcode_pop2x128_2pq_23_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop2x128_2pq_23_Slot_acc2_slot0_encode, Opcode_pop2x128_2pq_23_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_pop2x128_2pq_23_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop32_0_encode_fns[] = { + Opcode_pop32_0_Slot_inst_encode, 0, 0, Opcode_pop32_0_Slot_gp_slot2_encode, 0, Opcode_pop32_0_Slot_gp_slot0_encode, Opcode_pop32_0_Slot_dot_slot2_encode, 0, Opcode_pop32_0_Slot_dot_slot0_encode, Opcode_pop32_0_Slot_pq_slot2_encode, 0, Opcode_pop32_0_Slot_pq_slot0_encode, Opcode_pop32_0_Slot_acc2_slot2_encode, 0, Opcode_pop32_0_Slot_acc2_slot0_encode, Opcode_pop32_0_Slot_smod_slot2_encode, 0, Opcode_pop32_0_Slot_smod_slot0_encode, Opcode_pop32_0_Slot_llr_slot2_encode, 0, Opcode_pop32_0_Slot_llr_slot0_encode, Opcode_pop32_0_Slot_dual_slot2_encode, 0, Opcode_pop32_0_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop32_1_encode_fns[] = { + Opcode_pop32_1_Slot_inst_encode, 0, 0, Opcode_pop32_1_Slot_gp_slot2_encode, 0, Opcode_pop32_1_Slot_gp_slot0_encode, Opcode_pop32_1_Slot_dot_slot2_encode, 0, Opcode_pop32_1_Slot_dot_slot0_encode, Opcode_pop32_1_Slot_pq_slot2_encode, 0, Opcode_pop32_1_Slot_pq_slot0_encode, Opcode_pop32_1_Slot_acc2_slot2_encode, 0, Opcode_pop32_1_Slot_acc2_slot0_encode, Opcode_pop32_1_Slot_smod_slot2_encode, 0, Opcode_pop32_1_Slot_smod_slot0_encode, Opcode_pop32_1_Slot_llr_slot2_encode, 0, Opcode_pop32_1_Slot_llr_slot0_encode, Opcode_pop32_1_Slot_dual_slot2_encode, 0, Opcode_pop32_1_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop32_2_encode_fns[] = { + Opcode_pop32_2_Slot_inst_encode, 0, 0, Opcode_pop32_2_Slot_gp_slot2_encode, 0, Opcode_pop32_2_Slot_gp_slot0_encode, Opcode_pop32_2_Slot_dot_slot2_encode, 0, Opcode_pop32_2_Slot_dot_slot0_encode, Opcode_pop32_2_Slot_pq_slot2_encode, 0, Opcode_pop32_2_Slot_pq_slot0_encode, Opcode_pop32_2_Slot_acc2_slot2_encode, 0, Opcode_pop32_2_Slot_acc2_slot0_encode, Opcode_pop32_2_Slot_smod_slot2_encode, 0, Opcode_pop32_2_Slot_smod_slot0_encode, Opcode_pop32_2_Slot_llr_slot2_encode, 0, Opcode_pop32_2_Slot_llr_slot0_encode, Opcode_pop32_2_Slot_dual_slot2_encode, 0, Opcode_pop32_2_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_pop32_3_encode_fns[] = { + Opcode_pop32_3_Slot_inst_encode, 0, 0, Opcode_pop32_3_Slot_gp_slot2_encode, 0, Opcode_pop32_3_Slot_gp_slot0_encode, Opcode_pop32_3_Slot_dot_slot2_encode, 0, Opcode_pop32_3_Slot_dot_slot0_encode, Opcode_pop32_3_Slot_pq_slot2_encode, 0, Opcode_pop32_3_Slot_pq_slot0_encode, Opcode_pop32_3_Slot_acc2_slot2_encode, 0, Opcode_pop32_3_Slot_acc2_slot0_encode, Opcode_pop32_3_Slot_smod_slot2_encode, 0, Opcode_pop32_3_Slot_smod_slot0_encode, Opcode_pop32_3_Slot_llr_slot2_encode, 0, Opcode_pop32_3_Slot_llr_slot0_encode, Opcode_pop32_3_Slot_dual_slot2_encode, 0, Opcode_pop32_3_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_push128_encode_fns[] = { + Opcode_push128_Slot_inst_encode, 0, 0, Opcode_push128_Slot_gp_slot2_encode, 0, Opcode_push128_Slot_gp_slot0_encode, Opcode_push128_Slot_dot_slot2_encode, 0, Opcode_push128_Slot_dot_slot0_encode, Opcode_push128_Slot_pq_slot2_encode, 0, Opcode_push128_Slot_pq_slot0_encode, Opcode_push128_Slot_acc2_slot2_encode, 0, Opcode_push128_Slot_acc2_slot0_encode, Opcode_push128_Slot_smod_slot2_encode, 0, Opcode_push128_Slot_smod_slot0_encode, Opcode_push128_Slot_llr_slot2_encode, 0, Opcode_push128_Slot_llr_slot0_encode, Opcode_push128_Slot_dual_slot2_encode, 0, Opcode_push128_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_push128_m_encode_fns[] = { + Opcode_push128_m_Slot_inst_encode, 0, 0, 0, 0, Opcode_push128_m_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_push128_m_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, Opcode_push128_m_Slot_smod_slot0_encode, 0, 0, 0, 0, 0, Opcode_push128_m_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_push128_pq_encode_fns[] = { + Opcode_push128_pq_Slot_inst_encode, 0, 0, Opcode_push128_pq_Slot_gp_slot2_encode, 0, 0, Opcode_push128_pq_Slot_dot_slot2_encode, 0, 0, Opcode_push128_pq_Slot_pq_slot2_encode, 0, 0, 0, 0, Opcode_push128_pq_Slot_acc2_slot0_encode, Opcode_push128_pq_Slot_smod_slot2_encode, 0, 0, Opcode_push128_pq_Slot_llr_slot2_encode, 0, Opcode_push128_pq_Slot_llr_slot0_encode, Opcode_push128_pq_Slot_dual_slot2_encode, 0, Opcode_push128_pq_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_push2x128_pq_encode_fns[] = { + Opcode_push2x128_pq_Slot_inst_encode, 0, 0, Opcode_push2x128_pq_Slot_gp_slot2_encode, 0, 0, Opcode_push2x128_pq_Slot_dot_slot2_encode, 0, 0, 0, 0, 0, 0, 0, Opcode_push2x128_pq_Slot_acc2_slot0_encode, Opcode_push2x128_pq_Slot_smod_slot2_encode, 0, 0, 0, 0, Opcode_push2x128_pq_Slot_llr_slot0_encode, 0, 0, Opcode_push2x128_pq_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_push32_encode_fns[] = { + Opcode_push32_Slot_inst_encode, 0, 0, Opcode_push32_Slot_gp_slot2_encode, 0, Opcode_push32_Slot_gp_slot0_encode, Opcode_push32_Slot_dot_slot2_encode, 0, Opcode_push32_Slot_dot_slot0_encode, Opcode_push32_Slot_pq_slot2_encode, 0, Opcode_push32_Slot_pq_slot0_encode, Opcode_push32_Slot_acc2_slot2_encode, 0, 0, Opcode_push32_Slot_smod_slot2_encode, 0, Opcode_push32_Slot_smod_slot0_encode, Opcode_push32_Slot_llr_slot2_encode, 0, Opcode_push32_Slot_llr_slot0_encode, Opcode_push32_Slot_dual_slot2_encode, 0, Opcode_push32_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_qready_encode_fns[] = { + Opcode_qready_Slot_inst_encode, 0, 0, Opcode_qready_Slot_gp_slot2_encode, 0, 0, Opcode_qready_Slot_dot_slot2_encode, 0, 0, Opcode_qready_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_qready_Slot_smod_slot2_encode, 0, 0, Opcode_qready_Slot_llr_slot2_encode, 0, 0, Opcode_qready_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rdtiep_encode_fns[] = { + Opcode_rdtiep_Slot_inst_encode, 0, 0, Opcode_rdtiep_Slot_gp_slot2_encode, 0, 0, Opcode_rdtiep_Slot_dot_slot2_encode, 0, 0, Opcode_rdtiep_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_rdtiep_Slot_smod_slot2_encode, 0, 0, Opcode_rdtiep_Slot_llr_slot2_encode, 0, 0, Opcode_rdtiep_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_settiep_encode_fns[] = { + Opcode_settiep_Slot_inst_encode, 0, 0, Opcode_settiep_Slot_gp_slot2_encode, 0, 0, Opcode_settiep_Slot_dot_slot2_encode, 0, 0, Opcode_settiep_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_settiep_Slot_smod_slot2_encode, 0, 0, Opcode_settiep_Slot_llr_slot2_encode, 0, 0, Opcode_settiep_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_smod_lut_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_smod_lut_Slot_smod_slot2_encode, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrtbsigq_encode_fns[] = { + Opcode_wrtbsigq_Slot_inst_encode, 0, 0, Opcode_wrtbsigq_Slot_gp_slot2_encode, 0, 0, Opcode_wrtbsigq_Slot_dot_slot2_encode, 0, 0, Opcode_wrtbsigq_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_wrtbsigq_Slot_smod_slot2_encode, 0, 0, Opcode_wrtbsigq_Slot_llr_slot2_encode, 0, 0, Opcode_wrtbsigq_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrtbsigqm_encode_fns[] = { + Opcode_wrtbsigqm_Slot_inst_encode, 0, 0, Opcode_wrtbsigqm_Slot_gp_slot2_encode, 0, 0, Opcode_wrtbsigqm_Slot_dot_slot2_encode, 0, 0, Opcode_wrtbsigqm_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_wrtbsigqm_Slot_smod_slot2_encode, 0, 0, Opcode_wrtbsigqm_Slot_llr_slot2_encode, 0, 0, Opcode_wrtbsigqm_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrtiep_encode_fns[] = { + Opcode_wrtiep_Slot_inst_encode, 0, 0, Opcode_wrtiep_Slot_gp_slot2_encode, 0, 0, Opcode_wrtiep_Slot_dot_slot2_encode, 0, 0, Opcode_wrtiep_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_wrtiep_Slot_smod_slot2_encode, 0, 0, Opcode_wrtiep_Slot_llr_slot2_encode, 0, 0, Opcode_wrtiep_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wrtsigq_encode_fns[] = { + Opcode_wrtsigq_Slot_inst_encode, 0, 0, Opcode_wrtsigq_Slot_gp_slot2_encode, 0, 0, Opcode_wrtsigq_Slot_dot_slot2_encode, 0, 0, Opcode_wrtsigq_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_wrtsigq_Slot_smod_slot2_encode, 0, 0, Opcode_wrtsigq_Slot_llr_slot2_encode, 0, 0, Opcode_wrtsigq_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_abs8_encode_fns[] = { + 0, 0, 0, Opcode_abs8_Slot_gp_slot2_encode, 0, 0, Opcode_abs8_Slot_dot_slot2_encode, 0, 0, Opcode_abs8_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_abs8_Slot_smod_slot2_encode, 0, 0, Opcode_abs8_Slot_llr_slot2_encode, 0, 0, Opcode_abs8_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add16_encode_fns[] = { + 0, 0, 0, Opcode_add16_Slot_gp_slot2_encode, 0, 0, Opcode_add16_Slot_dot_slot2_encode, 0, 0, Opcode_add16_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_add16_Slot_smod_slot2_encode, 0, 0, Opcode_add16_Slot_llr_slot2_encode, 0, 0, Opcode_add16_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_add32_encode_fns[] = { + 0, 0, 0, Opcode_add32_Slot_gp_slot2_encode, 0, 0, Opcode_add32_Slot_dot_slot2_encode, 0, 0, Opcode_add32_Slot_pq_slot2_encode, 0, 0, Opcode_add32_Slot_acc2_slot2_encode, 0, 0, Opcode_add32_Slot_smod_slot2_encode, 0, 0, Opcode_add32_Slot_llr_slot2_encode, 0, 0, Opcode_add32_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addac_i2r_encode_fns[] = { + Opcode_addac_i2r_Slot_inst_encode, 0, 0, 0, 0, Opcode_addac_i2r_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_addac_i2r_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addac_i2r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addac_r2i_encode_fns[] = { + Opcode_addac_r2i_Slot_inst_encode, 0, 0, 0, 0, Opcode_addac_r2i_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_addac_r2i_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_addac_r2i_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_addar2_encode_fns[] = { + 0, 0, 0, Opcode_addar2_Slot_gp_slot2_encode, 0, 0, Opcode_addar2_Slot_dot_slot2_encode, 0, 0, Opcode_addar2_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_addar2_Slot_smod_slot2_encode, 0, 0, Opcode_addar2_Slot_llr_slot2_encode, 0, 0, Opcode_addar2_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addcm_encode_fns[] = { + 0, 0, 0, Opcode_addcm_Slot_gp_slot2_encode, 0, 0, Opcode_addcm_Slot_dot_slot2_encode, 0, 0, Opcode_addcm_Slot_pq_slot2_encode, 0, 0, Opcode_addcm_Slot_acc2_slot2_encode, 0, 0, Opcode_addcm_Slot_smod_slot2_encode, 0, 0, Opcode_addcm_Slot_llr_slot2_encode, 0, 0, Opcode_addcm_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_addwrp_encode_fns[] = { + 0, 0, 0, Opcode_addwrp_Slot_gp_slot2_encode, 0, 0, Opcode_addwrp_Slot_dot_slot2_encode, 0, 0, Opcode_addwrp_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_addwrp_Slot_smod_slot2_encode, 0, 0, Opcode_addwrp_Slot_llr_slot2_encode, 0, 0, Opcode_addwrp_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_and128_encode_fns[] = { + 0, 0, 0, Opcode_and128_Slot_gp_slot2_encode, 0, 0, Opcode_and128_Slot_dot_slot2_encode, 0, 0, Opcode_and128_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_and128_Slot_smod_slot2_encode, 0, 0, Opcode_and128_Slot_llr_slot2_encode, 0, 0, Opcode_and128_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_argmax8_encode_fns[] = { + 0, 0, 0, Opcode_argmax8_Slot_gp_slot2_encode, 0, 0, Opcode_argmax8_Slot_dot_slot2_encode, 0, 0, Opcode_argmax8_Slot_pq_slot2_encode, 0, 0, Opcode_argmax8_Slot_acc2_slot2_encode, 0, 0, Opcode_argmax8_Slot_smod_slot2_encode, 0, 0, Opcode_argmax8_Slot_llr_slot2_encode, 0, 0, Opcode_argmax8_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_asl_encode_fns[] = { + 0, 0, 0, Opcode_asl_Slot_gp_slot2_encode, 0, 0, Opcode_asl_Slot_dot_slot2_encode, 0, 0, Opcode_asl_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_asl_Slot_smod_slot2_encode, 0, 0, Opcode_asl_Slot_llr_slot2_encode, 0, 0, Opcode_asl_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_asl32_encode_fns[] = { + 0, 0, 0, Opcode_asl32_Slot_gp_slot2_encode, 0, 0, Opcode_asl32_Slot_dot_slot2_encode, 0, 0, Opcode_asl32_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_asl32_Slot_smod_slot2_encode, 0, 0, Opcode_asl32_Slot_llr_slot2_encode, 0, 0, Opcode_asl32_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_aslacm_encode_fns[] = { + Opcode_aslacm_Slot_inst_encode, 0, 0, 0, 0, Opcode_aslacm_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_aslacm_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_aslacm_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_aslm_encode_fns[] = { + 0, 0, 0, Opcode_aslm_Slot_gp_slot2_encode, 0, 0, Opcode_aslm_Slot_dot_slot2_encode, 0, 0, Opcode_aslm_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_aslm_Slot_smod_slot2_encode, 0, 0, Opcode_aslm_Slot_llr_slot2_encode, 0, 0, Opcode_aslm_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_aslm32_encode_fns[] = { + 0, 0, 0, Opcode_aslm32_Slot_gp_slot2_encode, 0, 0, Opcode_aslm32_Slot_dot_slot2_encode, 0, 0, Opcode_aslm32_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_aslm32_Slot_smod_slot2_encode, 0, 0, Opcode_aslm32_Slot_llr_slot2_encode, 0, 0, Opcode_aslm32_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_asr_encode_fns[] = { + 0, 0, 0, Opcode_asr_Slot_gp_slot2_encode, 0, 0, Opcode_asr_Slot_dot_slot2_encode, 0, 0, Opcode_asr_Slot_pq_slot2_encode, 0, 0, Opcode_asr_Slot_acc2_slot2_encode, 0, 0, Opcode_asr_Slot_smod_slot2_encode, 0, 0, Opcode_asr_Slot_llr_slot2_encode, 0, 0, Opcode_asr_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_asr32_encode_fns[] = { + 0, 0, 0, Opcode_asr32_Slot_gp_slot2_encode, 0, 0, Opcode_asr32_Slot_dot_slot2_encode, 0, 0, Opcode_asr32_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_asr32_Slot_smod_slot2_encode, 0, 0, Opcode_asr32_Slot_llr_slot2_encode, 0, 0, Opcode_asr32_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_asrac_encode_fns[] = { + Opcode_asrac_Slot_inst_encode, 0, 0, 0, 0, Opcode_asrac_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_asrac_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_asrac_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_asrm_encode_fns[] = { + 0, 0, 0, Opcode_asrm_Slot_gp_slot2_encode, 0, 0, Opcode_asrm_Slot_dot_slot2_encode, 0, 0, Opcode_asrm_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_asrm_Slot_smod_slot2_encode, 0, 0, Opcode_asrm_Slot_llr_slot2_encode, 0, 0, Opcode_asrm_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bitfext_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bitfext_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_bitfins_encode_fns[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_bitfins_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_clb_c_encode_fns[] = { + Opcode_clb_c_Slot_inst_encode, 0, 0, 0, 0, Opcode_clb_c_Slot_gp_slot0_encode, 0, 0, Opcode_clb_c_Slot_dot_slot0_encode, 0, 0, Opcode_clb_c_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clb_c_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_clb_r_encode_fns[] = { + Opcode_clb_r_Slot_inst_encode, 0, 0, 0, 0, Opcode_clb_r_Slot_gp_slot0_encode, 0, 0, Opcode_clb_r_Slot_dot_slot0_encode, 0, 0, Opcode_clb_r_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_clb_r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_cmp8_encode_fns[] = { + 0, 0, 0, Opcode_cmp8_Slot_gp_slot2_encode, 0, 0, Opcode_cmp8_Slot_dot_slot2_encode, 0, 0, Opcode_cmp8_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_cmp8_Slot_smod_slot2_encode, 0, 0, Opcode_cmp8_Slot_llr_slot2_encode, 0, 0, Opcode_cmp8_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cmp_i_encode_fns[] = { + 0, 0, 0, Opcode_cmp_i_Slot_gp_slot2_encode, 0, 0, Opcode_cmp_i_Slot_dot_slot2_encode, 0, 0, Opcode_cmp_i_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_cmp_i_Slot_smod_slot2_encode, 0, 0, Opcode_cmp_i_Slot_llr_slot2_encode, 0, 0, Opcode_cmp_i_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_cmp_r_encode_fns[] = { + 0, 0, 0, Opcode_cmp_r_Slot_gp_slot2_encode, 0, 0, Opcode_cmp_r_Slot_dot_slot2_encode, 0, 0, Opcode_cmp_r_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_cmp_r_Slot_smod_slot2_encode, 0, 0, Opcode_cmp_r_Slot_llr_slot2_encode, 0, 0, Opcode_cmp_r_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_ext_encode_fns[] = { + Opcode_ext_Slot_inst_encode, 0, 0, 0, 0, Opcode_ext_Slot_gp_slot0_encode, 0, 0, Opcode_ext_Slot_dot_slot0_encode, 0, 0, Opcode_ext_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ext_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ext_r_encode_fns[] = { + Opcode_ext_r_Slot_inst_encode, 0, 0, 0, 0, Opcode_ext_r_Slot_gp_slot0_encode, 0, 0, Opcode_ext_r_Slot_dot_slot0_encode, 0, 0, Opcode_ext_r_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ext_r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ext32_i_encode_fns[] = { + Opcode_ext32_i_Slot_inst_encode, 0, 0, 0, 0, Opcode_ext32_i_Slot_gp_slot0_encode, 0, 0, Opcode_ext32_i_Slot_dot_slot0_encode, 0, 0, Opcode_ext32_i_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ext32_i_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_ext32_r_encode_fns[] = { + Opcode_ext32_r_Slot_inst_encode, 0, 0, 0, 0, Opcode_ext32_r_Slot_gp_slot0_encode, 0, 0, Opcode_ext32_r_Slot_dot_slot0_encode, 0, 0, Opcode_ext32_r_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_ext32_r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_extui4_encode_fns[] = { + 0, 0, 0, Opcode_extui4_Slot_gp_slot2_encode, 0, 0, Opcode_extui4_Slot_dot_slot2_encode, 0, 0, Opcode_extui4_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_extui4_Slot_smod_slot2_encode, 0, 0, Opcode_extui4_Slot_llr_slot2_encode, 0, 0, Opcode_extui4_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lslm_encode_fns[] = { + 0, 0, 0, Opcode_lslm_Slot_gp_slot2_encode, 0, 0, Opcode_lslm_Slot_dot_slot2_encode, 0, 0, Opcode_lslm_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_lslm_Slot_smod_slot2_encode, 0, 0, Opcode_lslm_Slot_llr_slot2_encode, 0, 0, Opcode_lslm_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_lsrm_encode_fns[] = { + 0, 0, 0, Opcode_lsrm_Slot_gp_slot2_encode, 0, 0, Opcode_lsrm_Slot_dot_slot2_encode, 0, 0, Opcode_lsrm_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_lsrm_Slot_smod_slot2_encode, 0, 0, Opcode_lsrm_Slot_llr_slot2_encode, 0, 0, Opcode_lsrm_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_max8_encode_fns[] = { + 0, 0, 0, Opcode_max8_Slot_gp_slot2_encode, 0, 0, Opcode_max8_Slot_dot_slot2_encode, 0, 0, Opcode_max8_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_max8_Slot_smod_slot2_encode, 0, 0, Opcode_max8_Slot_llr_slot2_encode, 0, 0, Opcode_max8_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mean_encode_fns[] = { + 0, 0, 0, Opcode_mean_Slot_gp_slot2_encode, 0, 0, Opcode_mean_Slot_dot_slot2_encode, 0, 0, Opcode_mean_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_mean_Slot_smod_slot2_encode, 0, 0, Opcode_mean_Slot_llr_slot2_encode, 0, 0, Opcode_mean_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_mean32_encode_fns[] = { + 0, 0, 0, Opcode_mean32_Slot_gp_slot2_encode, 0, 0, Opcode_mean32_Slot_dot_slot2_encode, 0, 0, Opcode_mean32_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_mean32_Slot_smod_slot2_encode, 0, 0, Opcode_mean32_Slot_llr_slot2_encode, 0, 0, Opcode_mean32_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_min8_encode_fns[] = { + 0, 0, 0, Opcode_min8_Slot_gp_slot2_encode, 0, 0, Opcode_min8_Slot_dot_slot2_encode, 0, 0, Opcode_min8_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_min8_Slot_smod_slot2_encode, 0, 0, Opcode_min8_Slot_llr_slot2_encode, 0, 0, Opcode_min8_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_minclb_c_encode_fns[] = { + Opcode_minclb_c_Slot_inst_encode, 0, 0, 0, 0, Opcode_minclb_c_Slot_gp_slot0_encode, 0, 0, Opcode_minclb_c_Slot_dot_slot0_encode, 0, 0, Opcode_minclb_c_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minclb_c_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_minclb_r_encode_fns[] = { + Opcode_minclb_r_Slot_inst_encode, 0, 0, 0, 0, Opcode_minclb_r_Slot_gp_slot0_encode, 0, 0, Opcode_minclb_r_Slot_dot_slot0_encode, 0, 0, Opcode_minclb_r_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_minclb_r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_not128_encode_fns[] = { + 0, 0, 0, Opcode_not128_Slot_gp_slot2_encode, 0, 0, Opcode_not128_Slot_dot_slot2_encode, 0, 0, Opcode_not128_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_not128_Slot_smod_slot2_encode, 0, 0, Opcode_not128_Slot_llr_slot2_encode, 0, 0, Opcode_not128_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_or128_encode_fns[] = { + 0, 0, 0, Opcode_or128_Slot_gp_slot2_encode, 0, 0, Opcode_or128_Slot_dot_slot2_encode, 0, 0, Opcode_or128_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_or128_Slot_smod_slot2_encode, 0, 0, Opcode_or128_Slot_llr_slot2_encode, 0, 0, Opcode_or128_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_perm_encode_fns[] = { + 0, 0, 0, Opcode_perm_Slot_gp_slot2_encode, 0, 0, Opcode_perm_Slot_dot_slot2_encode, 0, 0, Opcode_perm_Slot_pq_slot2_encode, 0, 0, Opcode_perm_Slot_acc2_slot2_encode, 0, 0, Opcode_perm_Slot_smod_slot2_encode, 0, 0, Opcode_perm_Slot_llr_slot2_encode, 0, 0, Opcode_perm_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_redac_encode_fns[] = { + Opcode_redac_Slot_inst_encode, 0, 0, 0, 0, Opcode_redac_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_redac_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_redac_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_redac2_encode_fns[] = { + Opcode_redac2_Slot_inst_encode, 0, 0, 0, 0, Opcode_redac2_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_redac2_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_redac2_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_redac4_encode_fns[] = { + Opcode_redac4_Slot_inst_encode, 0, 0, 0, 0, Opcode_redac4_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_redac4_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_redac4_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_redacs_encode_fns[] = { + Opcode_redacs_Slot_inst_encode, 0, 0, 0, 0, Opcode_redacs_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_redacs_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_redacs_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sminclb_c_encode_fns[] = { + Opcode_sminclb_c_Slot_inst_encode, 0, 0, 0, 0, Opcode_sminclb_c_Slot_gp_slot0_encode, 0, 0, Opcode_sminclb_c_Slot_dot_slot0_encode, 0, 0, Opcode_sminclb_c_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sminclb_c_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sminclb_r_encode_fns[] = { + Opcode_sminclb_r_Slot_inst_encode, 0, 0, 0, 0, Opcode_sminclb_r_Slot_gp_slot0_encode, 0, 0, Opcode_sminclb_r_Slot_dot_slot0_encode, 0, 0, Opcode_sminclb_r_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_sminclb_r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_stswapbm_encode_fns[] = { + Opcode_stswapbm_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_stswapbm_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_stswapbmu_encode_fns[] = { + Opcode_stswapbmu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_stswapbmu_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_sub32_encode_fns[] = { + 0, 0, 0, Opcode_sub32_Slot_gp_slot2_encode, 0, 0, Opcode_sub32_Slot_dot_slot2_encode, 0, 0, Opcode_sub32_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_sub32_Slot_smod_slot2_encode, 0, 0, Opcode_sub32_Slot_llr_slot2_encode, 0, 0, Opcode_sub32_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subac_i2r_encode_fns[] = { + Opcode_subac_i2r_Slot_inst_encode, 0, 0, 0, 0, Opcode_subac_i2r_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_subac_i2r_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subac_i2r_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_subac_r2i_encode_fns[] = { + Opcode_subac_r2i_Slot_inst_encode, 0, 0, 0, 0, Opcode_subac_r2i_Slot_gp_slot0_encode, 0, 0, 0, 0, 0, Opcode_subac_r2i_Slot_pq_slot0_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Opcode_subac_r2i_Slot_dual_slot0_encode +}; + +static xtensa_opcode_encode_fn Opcode_subarx_encode_fns[] = { + 0, 0, 0, Opcode_subarx_Slot_gp_slot2_encode, 0, 0, Opcode_subarx_Slot_dot_slot2_encode, 0, 0, Opcode_subarx_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_subarx_Slot_smod_slot2_encode, 0, 0, Opcode_subarx_Slot_llr_slot2_encode, 0, 0, Opcode_subarx_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subcm_encode_fns[] = { + 0, 0, 0, Opcode_subcm_Slot_gp_slot2_encode, 0, 0, Opcode_subcm_Slot_dot_slot2_encode, 0, 0, Opcode_subcm_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_subcm_Slot_smod_slot2_encode, 0, 0, Opcode_subcm_Slot_llr_slot2_encode, 0, 0, Opcode_subcm_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_submean_encode_fns[] = { + 0, 0, 0, Opcode_submean_Slot_gp_slot2_encode, 0, 0, Opcode_submean_Slot_dot_slot2_encode, 0, 0, Opcode_submean_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_submean_Slot_smod_slot2_encode, 0, 0, Opcode_submean_Slot_llr_slot2_encode, 0, 0, Opcode_submean_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_subwrp_encode_fns[] = { + 0, 0, 0, Opcode_subwrp_Slot_gp_slot2_encode, 0, 0, Opcode_subwrp_Slot_dot_slot2_encode, 0, 0, Opcode_subwrp_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_subwrp_Slot_smod_slot2_encode, 0, 0, Opcode_subwrp_Slot_llr_slot2_encode, 0, 0, Opcode_subwrp_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_trans_encode_fns[] = { + 0, 0, 0, Opcode_trans_Slot_gp_slot2_encode, 0, 0, Opcode_trans_Slot_dot_slot2_encode, 0, 0, Opcode_trans_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_trans_Slot_smod_slot2_encode, 0, 0, Opcode_trans_Slot_llr_slot2_encode, 0, 0, Opcode_trans_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_xor128_encode_fns[] = { + 0, 0, 0, Opcode_xor128_Slot_gp_slot2_encode, 0, 0, Opcode_xor128_Slot_dot_slot2_encode, 0, 0, Opcode_xor128_Slot_pq_slot2_encode, 0, 0, 0, 0, 0, Opcode_xor128_Slot_smod_slot2_encode, 0, 0, Opcode_xor128_Slot_llr_slot2_encode, 0, 0, Opcode_xor128_Slot_dual_slot2_encode, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { + Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { + Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_sov_encode_fns[] = { + Opcode_rur_sov_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_sov_encode_fns[] = { + Opcode_wur_sov_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_sat_mode_encode_fns[] = { + Opcode_rur_sat_mode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_sat_mode_encode_fns[] = { + Opcode_wur_sat_mode_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_sar0_encode_fns[] = { + Opcode_rur_sar0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_sar0_encode_fns[] = { + Opcode_wur_sar0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_sar1_encode_fns[] = { + Opcode_rur_sar1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_sar1_encode_fns[] = { + Opcode_wur_sar1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_sar2_encode_fns[] = { + Opcode_rur_sar2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_sar2_encode_fns[] = { + Opcode_wur_sar2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_sar3_encode_fns[] = { + Opcode_rur_sar3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_sar3_encode_fns[] = { + Opcode_wur_sar3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_hsar0_encode_fns[] = { + Opcode_rur_hsar0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_hsar0_encode_fns[] = { + Opcode_wur_hsar0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_hsar1_encode_fns[] = { + Opcode_rur_hsar1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_hsar1_encode_fns[] = { + Opcode_wur_hsar1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_hsar2_encode_fns[] = { + Opcode_rur_hsar2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_hsar2_encode_fns[] = { + Opcode_wur_hsar2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_hsar3_encode_fns[] = { + Opcode_rur_hsar3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_hsar3_encode_fns[] = { + Opcode_wur_hsar3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_max_reg_0_encode_fns[] = { + Opcode_rur_max_reg_0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_max_reg_0_encode_fns[] = { + Opcode_wur_max_reg_0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_max_reg_1_encode_fns[] = { + Opcode_rur_max_reg_1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_max_reg_1_encode_fns[] = { + Opcode_wur_max_reg_1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_max_reg_2_encode_fns[] = { + Opcode_rur_max_reg_2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_max_reg_2_encode_fns[] = { + Opcode_wur_max_reg_2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_max_reg_3_encode_fns[] = { + Opcode_rur_max_reg_3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_max_reg_3_encode_fns[] = { + Opcode_wur_max_reg_3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_arg_max_reg_0_encode_fns[] = { + Opcode_rur_arg_max_reg_0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_arg_max_reg_0_encode_fns[] = { + Opcode_wur_arg_max_reg_0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_arg_max_reg_1_encode_fns[] = { + Opcode_rur_arg_max_reg_1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_arg_max_reg_1_encode_fns[] = { + Opcode_wur_arg_max_reg_1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_arg_max_reg_2_encode_fns[] = { + Opcode_rur_arg_max_reg_2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_arg_max_reg_2_encode_fns[] = { + Opcode_wur_arg_max_reg_2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_arg_max_reg_3_encode_fns[] = { + Opcode_rur_arg_max_reg_3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_arg_max_reg_3_encode_fns[] = { + Opcode_wur_arg_max_reg_3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_nco_counter_0_encode_fns[] = { + Opcode_rur_nco_counter_0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_nco_counter_0_encode_fns[] = { + Opcode_wur_nco_counter_0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_nco_counter_1_encode_fns[] = { + Opcode_rur_nco_counter_1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_nco_counter_1_encode_fns[] = { + Opcode_wur_nco_counter_1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_nco_counter_2_encode_fns[] = { + Opcode_rur_nco_counter_2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_nco_counter_2_encode_fns[] = { + Opcode_wur_nco_counter_2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_nco_counter_3_encode_fns[] = { + Opcode_rur_nco_counter_3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_nco_counter_3_encode_fns[] = { + Opcode_wur_nco_counter_3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_interp_ext_n_encode_fns[] = { + Opcode_rur_interp_ext_n_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_interp_ext_n_encode_fns[] = { + Opcode_wur_interp_ext_n_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_interp_ext_l_encode_fns[] = { + Opcode_rur_interp_ext_l_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_interp_ext_l_encode_fns[] = { + Opcode_wur_interp_ext_l_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_0_encode_fns[] = { + Opcode_rur_llr_buf_0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_0_encode_fns[] = { + Opcode_wur_llr_buf_0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_1_encode_fns[] = { + Opcode_rur_llr_buf_1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_1_encode_fns[] = { + Opcode_wur_llr_buf_1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_2_encode_fns[] = { + Opcode_rur_llr_buf_2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_2_encode_fns[] = { + Opcode_wur_llr_buf_2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_3_encode_fns[] = { + Opcode_rur_llr_buf_3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_3_encode_fns[] = { + Opcode_wur_llr_buf_3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_4_encode_fns[] = { + Opcode_rur_llr_buf_4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_4_encode_fns[] = { + Opcode_wur_llr_buf_4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_5_encode_fns[] = { + Opcode_rur_llr_buf_5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_5_encode_fns[] = { + Opcode_wur_llr_buf_5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_6_encode_fns[] = { + Opcode_rur_llr_buf_6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_6_encode_fns[] = { + Opcode_wur_llr_buf_6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_7_encode_fns[] = { + Opcode_rur_llr_buf_7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_7_encode_fns[] = { + Opcode_wur_llr_buf_7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_8_encode_fns[] = { + Opcode_rur_llr_buf_8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_8_encode_fns[] = { + Opcode_wur_llr_buf_8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_9_encode_fns[] = { + Opcode_rur_llr_buf_9_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_9_encode_fns[] = { + Opcode_wur_llr_buf_9_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_10_encode_fns[] = { + Opcode_rur_llr_buf_10_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_10_encode_fns[] = { + Opcode_wur_llr_buf_10_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_11_encode_fns[] = { + Opcode_rur_llr_buf_11_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_11_encode_fns[] = { + Opcode_wur_llr_buf_11_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_12_encode_fns[] = { + Opcode_rur_llr_buf_12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_12_encode_fns[] = { + Opcode_wur_llr_buf_12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_13_encode_fns[] = { + Opcode_rur_llr_buf_13_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_13_encode_fns[] = { + Opcode_wur_llr_buf_13_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_14_encode_fns[] = { + Opcode_rur_llr_buf_14_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_14_encode_fns[] = { + Opcode_wur_llr_buf_14_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_15_encode_fns[] = { + Opcode_rur_llr_buf_15_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_15_encode_fns[] = { + Opcode_wur_llr_buf_15_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_16_encode_fns[] = { + Opcode_rur_llr_buf_16_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_16_encode_fns[] = { + Opcode_wur_llr_buf_16_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_17_encode_fns[] = { + Opcode_rur_llr_buf_17_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_17_encode_fns[] = { + Opcode_wur_llr_buf_17_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_18_encode_fns[] = { + Opcode_rur_llr_buf_18_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_18_encode_fns[] = { + Opcode_wur_llr_buf_18_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_19_encode_fns[] = { + Opcode_rur_llr_buf_19_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_19_encode_fns[] = { + Opcode_wur_llr_buf_19_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_20_encode_fns[] = { + Opcode_rur_llr_buf_20_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_20_encode_fns[] = { + Opcode_wur_llr_buf_20_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_21_encode_fns[] = { + Opcode_rur_llr_buf_21_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_21_encode_fns[] = { + Opcode_wur_llr_buf_21_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_22_encode_fns[] = { + Opcode_rur_llr_buf_22_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_22_encode_fns[] = { + Opcode_wur_llr_buf_22_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_buf_23_encode_fns[] = { + Opcode_rur_llr_buf_23_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_buf_23_encode_fns[] = { + Opcode_wur_llr_buf_23_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_smod_buf_0_encode_fns[] = { + Opcode_rur_smod_buf_0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_smod_buf_0_encode_fns[] = { + Opcode_wur_smod_buf_0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_smod_buf_1_encode_fns[] = { + Opcode_rur_smod_buf_1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_smod_buf_1_encode_fns[] = { + Opcode_wur_smod_buf_1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_smod_buf_2_encode_fns[] = { + Opcode_rur_smod_buf_2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_smod_buf_2_encode_fns[] = { + Opcode_wur_smod_buf_2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_smod_buf_3_encode_fns[] = { + Opcode_rur_smod_buf_3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_smod_buf_3_encode_fns[] = { + Opcode_wur_smod_buf_3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_smod_buf_4_encode_fns[] = { + Opcode_rur_smod_buf_4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_smod_buf_4_encode_fns[] = { + Opcode_wur_smod_buf_4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_smod_buf_5_encode_fns[] = { + Opcode_rur_smod_buf_5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_smod_buf_5_encode_fns[] = { + Opcode_wur_smod_buf_5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_smod_buf_6_encode_fns[] = { + Opcode_rur_smod_buf_6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_smod_buf_6_encode_fns[] = { + Opcode_wur_smod_buf_6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_smod_buf_7_encode_fns[] = { + Opcode_rur_smod_buf_7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_smod_buf_7_encode_fns[] = { + Opcode_wur_smod_buf_7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_weight_reg_encode_fns[] = { + Opcode_rur_weight_reg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_weight_reg_encode_fns[] = { + Opcode_wur_weight_reg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_scale_reg_encode_fns[] = { + Opcode_rur_scale_reg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_scale_reg_encode_fns[] = { + Opcode_wur_scale_reg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_llr_pos_encode_fns[] = { + Opcode_rur_llr_pos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_llr_pos_encode_fns[] = { + Opcode_wur_llr_pos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_smod_pos_encode_fns[] = { + Opcode_rur_smod_pos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_smod_pos_encode_fns[] = { + Opcode_wur_smod_pos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_perm_reg_encode_fns[] = { + Opcode_rur_perm_reg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_perm_reg_encode_fns[] = { + Opcode_wur_perm_reg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_smod_offset_table_0_encode_fns[] = { + Opcode_rur_smod_offset_table_0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_smod_offset_table_0_encode_fns[] = { + Opcode_wur_smod_offset_table_0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_smod_offset_table_1_encode_fns[] = { + Opcode_rur_smod_offset_table_1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_smod_offset_table_1_encode_fns[] = { + Opcode_wur_smod_offset_table_1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_smod_offset_table_2_encode_fns[] = { + Opcode_rur_smod_offset_table_2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_smod_offset_table_2_encode_fns[] = { + Opcode_wur_smod_offset_table_2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_smod_offset_table_3_encode_fns[] = { + Opcode_rur_smod_offset_table_3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_smod_offset_table_3_encode_fns[] = { + Opcode_wur_smod_offset_table_3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_phasor_n_encode_fns[] = { + Opcode_rur_phasor_n_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_phasor_n_encode_fns[] = { + Opcode_wur_phasor_n_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_rur_phasor_offset_encode_fns[] = { + Opcode_rur_phasor_offset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static xtensa_opcode_encode_fn Opcode_wur_phasor_offset_encode_fns[] = { + Opcode_wur_phasor_offset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + + +/* Opcode table. */ + +static xtensa_opcode_internal opcodes[] = { + { "excw", ICLASS_xt_iclass_excw, + 0, + Opcode_excw_encode_fns, 0, 0 }, + { "rfe", ICLASS_xt_iclass_rfe, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfe_encode_fns, 0, 0 }, + { "rfde", ICLASS_xt_iclass_rfde, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfde_encode_fns, 0, 0 }, + { "syscall", ICLASS_xt_iclass_syscall, + 0, + Opcode_syscall_encode_fns, 0, 0 }, + { "simcall", ICLASS_xt_iclass_simcall, + 0, + Opcode_simcall_encode_fns, 0, 0 }, + { "call12", ICLASS_xt_iclass_call12, + XTENSA_OPCODE_IS_CALL, + Opcode_call12_encode_fns, 0, 0 }, + { "call8", ICLASS_xt_iclass_call8, + XTENSA_OPCODE_IS_CALL, + Opcode_call8_encode_fns, 0, 0 }, + { "call4", ICLASS_xt_iclass_call4, + XTENSA_OPCODE_IS_CALL, + Opcode_call4_encode_fns, 0, 0 }, + { "callx12", ICLASS_xt_iclass_callx12, + XTENSA_OPCODE_IS_CALL, + Opcode_callx12_encode_fns, 0, 0 }, + { "callx8", ICLASS_xt_iclass_callx8, + XTENSA_OPCODE_IS_CALL, + Opcode_callx8_encode_fns, 0, 0 }, + { "callx4", ICLASS_xt_iclass_callx4, + XTENSA_OPCODE_IS_CALL, + Opcode_callx4_encode_fns, 0, 0 }, + { "entry", ICLASS_xt_iclass_entry, + 0, + Opcode_entry_encode_fns, 0, 0 }, + { "movsp", ICLASS_xt_iclass_movsp, + 0, + Opcode_movsp_encode_fns, 0, 0 }, + { "rotw", ICLASS_xt_iclass_rotw, + 0, + Opcode_rotw_encode_fns, 0, 0 }, + { "retw", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_encode_fns, 0, 0 }, + { "retw.n", ICLASS_xt_iclass_retw, + XTENSA_OPCODE_IS_JUMP, + Opcode_retw_n_encode_fns, 0, 0 }, + { "rfwo", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwo_encode_fns, 0, 0 }, + { "rfwu", ICLASS_xt_iclass_rfwou, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfwu_encode_fns, 0, 0 }, + { "l32e", ICLASS_xt_iclass_l32e, + 0, + Opcode_l32e_encode_fns, 0, 0 }, + { "s32e", ICLASS_xt_iclass_s32e, + 0, + Opcode_s32e_encode_fns, 0, 0 }, + { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, + 0, + Opcode_rsr_windowbase_encode_fns, 0, 0 }, + { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, + 0, + Opcode_wsr_windowbase_encode_fns, 0, 0 }, + { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, + 0, + Opcode_xsr_windowbase_encode_fns, 0, 0 }, + { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, + 0, + Opcode_rsr_windowstart_encode_fns, 0, 0 }, + { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, + 0, + Opcode_wsr_windowstart_encode_fns, 0, 0 }, + { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, + 0, + Opcode_xsr_windowstart_encode_fns, 0, 0 }, + { "add.n", ICLASS_xt_iclass_add_n, + 0, + Opcode_add_n_encode_fns, 0, 0 }, + { "addi.n", ICLASS_xt_iclass_addi_n, + 0, + Opcode_addi_n_encode_fns, 0, 0 }, + { "beqz.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_n_encode_fns, 0, 0 }, + { "bnez.n", ICLASS_xt_iclass_bz6, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_n_encode_fns, 0, 0 }, + { "ill.n", ICLASS_xt_iclass_ill_n, + 0, + Opcode_ill_n_encode_fns, 0, 0 }, + { "l32i.n", ICLASS_xt_iclass_loadi4, + 0, + Opcode_l32i_n_encode_fns, 0, 0 }, + { "mov.n", ICLASS_xt_iclass_mov_n, + 0, + Opcode_mov_n_encode_fns, 0, 0 }, + { "movi.n", ICLASS_xt_iclass_movi_n, + 0, + Opcode_movi_n_encode_fns, 0, 0 }, + { "nop.n", ICLASS_xt_iclass_nopn, + 0, + Opcode_nop_n_encode_fns, 0, 0 }, + { "ret.n", ICLASS_xt_iclass_retn, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_n_encode_fns, 0, 0 }, + { "s32i.n", ICLASS_xt_iclass_storei4, + 0, + Opcode_s32i_n_encode_fns, 0, 0 }, + { "rur.threadptr", ICLASS_rur_threadptr, + 0, + Opcode_rur_threadptr_encode_fns, 0, 0 }, + { "wur.threadptr", ICLASS_wur_threadptr, + 0, + Opcode_wur_threadptr_encode_fns, 0, 0 }, + { "addi", ICLASS_xt_iclass_addi, + 0, + Opcode_addi_encode_fns, 0, 0 }, + { "addmi", ICLASS_xt_iclass_addmi, + 0, + Opcode_addmi_encode_fns, 0, 0 }, + { "add", ICLASS_xt_iclass_addsub, + 0, + Opcode_add_encode_fns, 0, 0 }, + { "sub", ICLASS_xt_iclass_addsub, + 0, + Opcode_sub_encode_fns, 0, 0 }, + { "addx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx2_encode_fns, 0, 0 }, + { "addx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx4_encode_fns, 0, 0 }, + { "addx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_addx8_encode_fns, 0, 0 }, + { "subx2", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx2_encode_fns, 0, 0 }, + { "subx4", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx4_encode_fns, 0, 0 }, + { "subx8", ICLASS_xt_iclass_addsub, + 0, + Opcode_subx8_encode_fns, 0, 0 }, + { "and", ICLASS_xt_iclass_bit, + 0, + Opcode_and_encode_fns, 0, 0 }, + { "or", ICLASS_xt_iclass_bit, + 0, + Opcode_or_encode_fns, 0, 0 }, + { "xor", ICLASS_xt_iclass_bit, + 0, + Opcode_xor_encode_fns, 0, 0 }, + { "beqi", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqi_encode_fns, 0, 0 }, + { "bnei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnei_encode_fns, 0, 0 }, + { "bgei", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgei_encode_fns, 0, 0 }, + { "blti", ICLASS_xt_iclass_bsi8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blti_encode_fns, 0, 0 }, + { "bbci", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbci_encode_fns, 0, 0 }, + { "bbsi", ICLASS_xt_iclass_bsi8b, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbsi_encode_fns, 0, 0 }, + { "bgeui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeui_encode_fns, 0, 0 }, + { "bltui", ICLASS_xt_iclass_bsi8u, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltui_encode_fns, 0, 0 }, + { "beq", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beq_encode_fns, 0, 0 }, + { "bne", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bne_encode_fns, 0, 0 }, + { "bge", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bge_encode_fns, 0, 0 }, + { "blt", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_blt_encode_fns, 0, 0 }, + { "bgeu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgeu_encode_fns, 0, 0 }, + { "bltu", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltu_encode_fns, 0, 0 }, + { "bany", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bany_encode_fns, 0, 0 }, + { "bnone", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnone_encode_fns, 0, 0 }, + { "ball", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_ball_encode_fns, 0, 0 }, + { "bnall", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnall_encode_fns, 0, 0 }, + { "bbc", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbc_encode_fns, 0, 0 }, + { "bbs", ICLASS_xt_iclass_bst8, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bbs_encode_fns, 0, 0 }, + { "beqz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_beqz_encode_fns, 0, 0 }, + { "bnez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bnez_encode_fns, 0, 0 }, + { "bgez", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bgez_encode_fns, 0, 0 }, + { "bltz", ICLASS_xt_iclass_bsz12, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bltz_encode_fns, 0, 0 }, + { "call0", ICLASS_xt_iclass_call0, + XTENSA_OPCODE_IS_CALL, + Opcode_call0_encode_fns, 0, 0 }, + { "callx0", ICLASS_xt_iclass_callx0, + XTENSA_OPCODE_IS_CALL, + Opcode_callx0_encode_fns, 0, 0 }, + { "extui", ICLASS_xt_iclass_exti, + 0, + Opcode_extui_encode_fns, 0, 0 }, + { "ill", ICLASS_xt_iclass_ill, + 0, + Opcode_ill_encode_fns, 0, 0 }, + { "j", ICLASS_xt_iclass_jump, + XTENSA_OPCODE_IS_JUMP, + Opcode_j_encode_fns, 0, 0 }, + { "jx", ICLASS_xt_iclass_jumpx, + XTENSA_OPCODE_IS_JUMP, + Opcode_jx_encode_fns, 0, 0 }, + { "l16ui", ICLASS_xt_iclass_l16ui, + 0, + Opcode_l16ui_encode_fns, 0, 0 }, + { "l16si", ICLASS_xt_iclass_l16si, + 0, + Opcode_l16si_encode_fns, 0, 0 }, + { "l32i", ICLASS_xt_iclass_l32i, + 0, + Opcode_l32i_encode_fns, 0, 0 }, + { "l32r", ICLASS_xt_iclass_l32r, + 0, + Opcode_l32r_encode_fns, 0, 0 }, + { "l8ui", ICLASS_xt_iclass_l8i, + 0, + Opcode_l8ui_encode_fns, 0, 0 }, + { "loop", ICLASS_xt_iclass_loop, + XTENSA_OPCODE_IS_LOOP, + Opcode_loop_encode_fns, 0, 0 }, + { "loopnez", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopnez_encode_fns, 0, 0 }, + { "loopgtz", ICLASS_xt_iclass_loopz, + XTENSA_OPCODE_IS_LOOP, + Opcode_loopgtz_encode_fns, 0, 0 }, + { "movi", ICLASS_xt_iclass_movi, + 0, + Opcode_movi_encode_fns, 0, 0 }, + { "moveqz", ICLASS_xt_iclass_movz, + 0, + Opcode_moveqz_encode_fns, 0, 0 }, + { "movnez", ICLASS_xt_iclass_movz, + 0, + Opcode_movnez_encode_fns, 0, 0 }, + { "movltz", ICLASS_xt_iclass_movz, + 0, + Opcode_movltz_encode_fns, 0, 0 }, + { "movgez", ICLASS_xt_iclass_movz, + 0, + Opcode_movgez_encode_fns, 0, 0 }, + { "neg", ICLASS_xt_iclass_neg, + 0, + Opcode_neg_encode_fns, 0, 0 }, + { "abs", ICLASS_xt_iclass_neg, + 0, + Opcode_abs_encode_fns, 0, 0 }, + { "nop", ICLASS_xt_iclass_nop, + 0, + Opcode_nop_encode_fns, 0, 0 }, + { "ret", ICLASS_xt_iclass_return, + XTENSA_OPCODE_IS_JUMP, + Opcode_ret_encode_fns, 0, 0 }, + { "s16i", ICLASS_xt_iclass_s16i, + 0, + Opcode_s16i_encode_fns, 0, 0 }, + { "s32i", ICLASS_xt_iclass_s32i, + 0, + Opcode_s32i_encode_fns, 0, 0 }, + { "s8i", ICLASS_xt_iclass_s8i, + 0, + Opcode_s8i_encode_fns, 0, 0 }, + { "ssr", ICLASS_xt_iclass_sar, + 0, + Opcode_ssr_encode_fns, 0, 0 }, + { "ssl", ICLASS_xt_iclass_sar, + 0, + Opcode_ssl_encode_fns, 0, 0 }, + { "ssa8l", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8l_encode_fns, 0, 0 }, + { "ssa8b", ICLASS_xt_iclass_sar, + 0, + Opcode_ssa8b_encode_fns, 0, 0 }, + { "ssai", ICLASS_xt_iclass_sari, + 0, + Opcode_ssai_encode_fns, 0, 0 }, + { "sll", ICLASS_xt_iclass_shifts, + 0, + Opcode_sll_encode_fns, 0, 0 }, + { "src", ICLASS_xt_iclass_shiftst, + 0, + Opcode_src_encode_fns, 0, 0 }, + { "srl", ICLASS_xt_iclass_shiftt, + 0, + Opcode_srl_encode_fns, 0, 0 }, + { "sra", ICLASS_xt_iclass_shiftt, + 0, + Opcode_sra_encode_fns, 0, 0 }, + { "slli", ICLASS_xt_iclass_slli, + 0, + Opcode_slli_encode_fns, 0, 0 }, + { "srai", ICLASS_xt_iclass_srai, + 0, + Opcode_srai_encode_fns, 0, 0 }, + { "srli", ICLASS_xt_iclass_srli, + 0, + Opcode_srli_encode_fns, 0, 0 }, + { "memw", ICLASS_xt_iclass_memw, + 0, + Opcode_memw_encode_fns, 0, 0 }, + { "extw", ICLASS_xt_iclass_extw, + 0, + Opcode_extw_encode_fns, 0, 0 }, + { "isync", ICLASS_xt_iclass_isync, + 0, + Opcode_isync_encode_fns, 0, 0 }, + { "rsync", ICLASS_xt_iclass_sync, + 0, + Opcode_rsync_encode_fns, 0, 0 }, + { "esync", ICLASS_xt_iclass_sync, + 0, + Opcode_esync_encode_fns, 0, 0 }, + { "dsync", ICLASS_xt_iclass_sync, + 0, + Opcode_dsync_encode_fns, 0, 0 }, + { "rsil", ICLASS_xt_iclass_rsil, + 0, + Opcode_rsil_encode_fns, 0, 0 }, + { "rsr.lend", ICLASS_xt_iclass_rsr_lend, + 0, + Opcode_rsr_lend_encode_fns, 0, 0 }, + { "wsr.lend", ICLASS_xt_iclass_wsr_lend, + 0, + Opcode_wsr_lend_encode_fns, 0, 0 }, + { "xsr.lend", ICLASS_xt_iclass_xsr_lend, + 0, + Opcode_xsr_lend_encode_fns, 0, 0 }, + { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, + 0, + Opcode_rsr_lcount_encode_fns, 0, 0 }, + { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, + 0, + Opcode_wsr_lcount_encode_fns, 0, 0 }, + { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, + 0, + Opcode_xsr_lcount_encode_fns, 0, 0 }, + { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, + 0, + Opcode_rsr_lbeg_encode_fns, 0, 0 }, + { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, + 0, + Opcode_wsr_lbeg_encode_fns, 0, 0 }, + { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, + 0, + Opcode_xsr_lbeg_encode_fns, 0, 0 }, + { "rsr.sar", ICLASS_xt_iclass_rsr_sar, + 0, + Opcode_rsr_sar_encode_fns, 0, 0 }, + { "wsr.sar", ICLASS_xt_iclass_wsr_sar, + 0, + Opcode_wsr_sar_encode_fns, 0, 0 }, + { "xsr.sar", ICLASS_xt_iclass_xsr_sar, + 0, + Opcode_xsr_sar_encode_fns, 0, 0 }, + { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, + 0, + Opcode_rsr_litbase_encode_fns, 0, 0 }, + { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, + 0, + Opcode_wsr_litbase_encode_fns, 0, 0 }, + { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, + 0, + Opcode_xsr_litbase_encode_fns, 0, 0 }, + { "rsr.176", ICLASS_xt_iclass_rsr_176, + 0, + Opcode_rsr_176_encode_fns, 0, 0 }, + { "wsr.176", ICLASS_xt_iclass_wsr_176, + 0, + Opcode_wsr_176_encode_fns, 0, 0 }, + { "rsr.208", ICLASS_xt_iclass_rsr_208, + 0, + Opcode_rsr_208_encode_fns, 0, 0 }, + { "rsr.ps", ICLASS_xt_iclass_rsr_ps, + 0, + Opcode_rsr_ps_encode_fns, 0, 0 }, + { "wsr.ps", ICLASS_xt_iclass_wsr_ps, + 0, + Opcode_wsr_ps_encode_fns, 0, 0 }, + { "xsr.ps", ICLASS_xt_iclass_xsr_ps, + 0, + Opcode_xsr_ps_encode_fns, 0, 0 }, + { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, + 0, + Opcode_rsr_epc1_encode_fns, 0, 0 }, + { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, + 0, + Opcode_wsr_epc1_encode_fns, 0, 0 }, + { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, + 0, + Opcode_xsr_epc1_encode_fns, 0, 0 }, + { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, + 0, + Opcode_rsr_excsave1_encode_fns, 0, 0 }, + { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, + 0, + Opcode_wsr_excsave1_encode_fns, 0, 0 }, + { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, + 0, + Opcode_xsr_excsave1_encode_fns, 0, 0 }, + { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, + 0, + Opcode_rsr_epc2_encode_fns, 0, 0 }, + { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, + 0, + Opcode_wsr_epc2_encode_fns, 0, 0 }, + { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, + 0, + Opcode_xsr_epc2_encode_fns, 0, 0 }, + { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, + 0, + Opcode_rsr_excsave2_encode_fns, 0, 0 }, + { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, + 0, + Opcode_wsr_excsave2_encode_fns, 0, 0 }, + { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, + 0, + Opcode_xsr_excsave2_encode_fns, 0, 0 }, + { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, + 0, + Opcode_rsr_epc3_encode_fns, 0, 0 }, + { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, + 0, + Opcode_wsr_epc3_encode_fns, 0, 0 }, + { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, + 0, + Opcode_xsr_epc3_encode_fns, 0, 0 }, + { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, + 0, + Opcode_rsr_excsave3_encode_fns, 0, 0 }, + { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, + 0, + Opcode_wsr_excsave3_encode_fns, 0, 0 }, + { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, + 0, + Opcode_xsr_excsave3_encode_fns, 0, 0 }, + { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, + 0, + Opcode_rsr_epc4_encode_fns, 0, 0 }, + { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, + 0, + Opcode_wsr_epc4_encode_fns, 0, 0 }, + { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, + 0, + Opcode_xsr_epc4_encode_fns, 0, 0 }, + { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, + 0, + Opcode_rsr_excsave4_encode_fns, 0, 0 }, + { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, + 0, + Opcode_wsr_excsave4_encode_fns, 0, 0 }, + { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, + 0, + Opcode_xsr_excsave4_encode_fns, 0, 0 }, + { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, + 0, + Opcode_rsr_epc5_encode_fns, 0, 0 }, + { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, + 0, + Opcode_wsr_epc5_encode_fns, 0, 0 }, + { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, + 0, + Opcode_xsr_epc5_encode_fns, 0, 0 }, + { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, + 0, + Opcode_rsr_excsave5_encode_fns, 0, 0 }, + { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, + 0, + Opcode_wsr_excsave5_encode_fns, 0, 0 }, + { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, + 0, + Opcode_xsr_excsave5_encode_fns, 0, 0 }, + { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, + 0, + Opcode_rsr_epc6_encode_fns, 0, 0 }, + { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, + 0, + Opcode_wsr_epc6_encode_fns, 0, 0 }, + { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, + 0, + Opcode_xsr_epc6_encode_fns, 0, 0 }, + { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, + 0, + Opcode_rsr_excsave6_encode_fns, 0, 0 }, + { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, + 0, + Opcode_wsr_excsave6_encode_fns, 0, 0 }, + { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, + 0, + Opcode_xsr_excsave6_encode_fns, 0, 0 }, + { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, + 0, + Opcode_rsr_eps2_encode_fns, 0, 0 }, + { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, + 0, + Opcode_wsr_eps2_encode_fns, 0, 0 }, + { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, + 0, + Opcode_xsr_eps2_encode_fns, 0, 0 }, + { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, + 0, + Opcode_rsr_eps3_encode_fns, 0, 0 }, + { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, + 0, + Opcode_wsr_eps3_encode_fns, 0, 0 }, + { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, + 0, + Opcode_xsr_eps3_encode_fns, 0, 0 }, + { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, + 0, + Opcode_rsr_eps4_encode_fns, 0, 0 }, + { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, + 0, + Opcode_wsr_eps4_encode_fns, 0, 0 }, + { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, + 0, + Opcode_xsr_eps4_encode_fns, 0, 0 }, + { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, + 0, + Opcode_rsr_eps5_encode_fns, 0, 0 }, + { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, + 0, + Opcode_wsr_eps5_encode_fns, 0, 0 }, + { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, + 0, + Opcode_xsr_eps5_encode_fns, 0, 0 }, + { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, + 0, + Opcode_rsr_eps6_encode_fns, 0, 0 }, + { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, + 0, + Opcode_wsr_eps6_encode_fns, 0, 0 }, + { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, + 0, + Opcode_xsr_eps6_encode_fns, 0, 0 }, + { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, + 0, + Opcode_rsr_excvaddr_encode_fns, 0, 0 }, + { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, + 0, + Opcode_wsr_excvaddr_encode_fns, 0, 0 }, + { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, + 0, + Opcode_xsr_excvaddr_encode_fns, 0, 0 }, + { "rsr.depc", ICLASS_xt_iclass_rsr_depc, + 0, + Opcode_rsr_depc_encode_fns, 0, 0 }, + { "wsr.depc", ICLASS_xt_iclass_wsr_depc, + 0, + Opcode_wsr_depc_encode_fns, 0, 0 }, + { "xsr.depc", ICLASS_xt_iclass_xsr_depc, + 0, + Opcode_xsr_depc_encode_fns, 0, 0 }, + { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, + 0, + Opcode_rsr_exccause_encode_fns, 0, 0 }, + { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, + 0, + Opcode_wsr_exccause_encode_fns, 0, 0 }, + { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, + 0, + Opcode_xsr_exccause_encode_fns, 0, 0 }, + { "rsr.prid", ICLASS_xt_iclass_rsr_prid, + 0, + Opcode_rsr_prid_encode_fns, 0, 0 }, + { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, + 0, + Opcode_rsr_vecbase_encode_fns, 0, 0 }, + { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, + 0, + Opcode_wsr_vecbase_encode_fns, 0, 0 }, + { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, + 0, + Opcode_xsr_vecbase_encode_fns, 0, 0 }, + { "mul16u", ICLASS_xt_mul16, + 0, + Opcode_mul16u_encode_fns, 0, 0 }, + { "mul16s", ICLASS_xt_mul16, + 0, + Opcode_mul16s_encode_fns, 0, 0 }, + { "rfi", ICLASS_xt_iclass_rfi, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfi_encode_fns, 0, 0 }, + { "waiti", ICLASS_xt_iclass_wait, + 0, + Opcode_waiti_encode_fns, 0, 0 }, + { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, + 0, + Opcode_rsr_interrupt_encode_fns, 0, 0 }, + { "wsr.intset", ICLASS_xt_iclass_wsr_intset, + 0, + Opcode_wsr_intset_encode_fns, 0, 0 }, + { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, + 0, + Opcode_wsr_intclear_encode_fns, 0, 0 }, + { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, + 0, + Opcode_rsr_intenable_encode_fns, 0, 0 }, + { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, + 0, + Opcode_wsr_intenable_encode_fns, 0, 0 }, + { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, + 0, + Opcode_xsr_intenable_encode_fns, 0, 0 }, + { "break", ICLASS_xt_iclass_break, + 0, + Opcode_break_encode_fns, 0, 0 }, + { "break.n", ICLASS_xt_iclass_break_n, + 0, + Opcode_break_n_encode_fns, 0, 0 }, + { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, + 0, + Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, + { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, + 0, + Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, + { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, + 0, + Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, + { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, + 0, + Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, + { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, + 0, + Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, + { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, + 0, + Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, + { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, + 0, + Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, + { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, + 0, + Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, + { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, + 0, + Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, + { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, + 0, + Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, + { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, + 0, + Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, + { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, + 0, + Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, + { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, + 0, + Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, + { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, + 0, + Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, + { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, + 0, + Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, + { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, + 0, + Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, + { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, + 0, + Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, + { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, + 0, + Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, + { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, + 0, + Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, + { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, + 0, + Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, + { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, + 0, + Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, + { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, + 0, + Opcode_rsr_debugcause_encode_fns, 0, 0 }, + { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, + 0, + Opcode_wsr_debugcause_encode_fns, 0, 0 }, + { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, + 0, + Opcode_xsr_debugcause_encode_fns, 0, 0 }, + { "rsr.icount", ICLASS_xt_iclass_rsr_icount, + 0, + Opcode_rsr_icount_encode_fns, 0, 0 }, + { "wsr.icount", ICLASS_xt_iclass_wsr_icount, + 0, + Opcode_wsr_icount_encode_fns, 0, 0 }, + { "xsr.icount", ICLASS_xt_iclass_xsr_icount, + 0, + Opcode_xsr_icount_encode_fns, 0, 0 }, + { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, + 0, + Opcode_rsr_icountlevel_encode_fns, 0, 0 }, + { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, + 0, + Opcode_wsr_icountlevel_encode_fns, 0, 0 }, + { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, + 0, + Opcode_xsr_icountlevel_encode_fns, 0, 0 }, + { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, + 0, + Opcode_rsr_ddr_encode_fns, 0, 0 }, + { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, + 0, + Opcode_wsr_ddr_encode_fns, 0, 0 }, + { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, + 0, + Opcode_xsr_ddr_encode_fns, 0, 0 }, + { "rfdo", ICLASS_xt_iclass_rfdo, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdo_encode_fns, 0, 0 }, + { "rfdd", ICLASS_xt_iclass_rfdd, + XTENSA_OPCODE_IS_JUMP, + Opcode_rfdd_encode_fns, 0, 0 }, + { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, + 0, + Opcode_wsr_mmid_encode_fns, 0, 0 }, + { "andb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andb_encode_fns, 0, 0 }, + { "andbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_andbc_encode_fns, 0, 0 }, + { "orb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orb_encode_fns, 0, 0 }, + { "orbc", ICLASS_xt_iclass_bbool1, + 0, + Opcode_orbc_encode_fns, 0, 0 }, + { "xorb", ICLASS_xt_iclass_bbool1, + 0, + Opcode_xorb_encode_fns, 0, 0 }, + { "any4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_any4_encode_fns, 0, 0 }, + { "all4", ICLASS_xt_iclass_bbool4, + 0, + Opcode_all4_encode_fns, 0, 0 }, + { "any8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_any8_encode_fns, 0, 0 }, + { "all8", ICLASS_xt_iclass_bbool8, + 0, + Opcode_all8_encode_fns, 0, 0 }, + { "bf", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bf_encode_fns, 0, 0 }, + { "bt", ICLASS_xt_iclass_bbranch, + XTENSA_OPCODE_IS_BRANCH, + Opcode_bt_encode_fns, 0, 0 }, + { "movf", ICLASS_xt_iclass_bmove, + 0, + Opcode_movf_encode_fns, 0, 0 }, + { "movt", ICLASS_xt_iclass_bmove, + 0, + Opcode_movt_encode_fns, 0, 0 }, + { "rsr.br", ICLASS_xt_iclass_RSR_BR, + 0, + Opcode_rsr_br_encode_fns, 0, 0 }, + { "wsr.br", ICLASS_xt_iclass_WSR_BR, + 0, + Opcode_wsr_br_encode_fns, 0, 0 }, + { "xsr.br", ICLASS_xt_iclass_XSR_BR, + 0, + Opcode_xsr_br_encode_fns, 0, 0 }, + { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, + 0, + Opcode_rsr_ccount_encode_fns, 0, 0 }, + { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, + 0, + Opcode_wsr_ccount_encode_fns, 0, 0 }, + { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, + 0, + Opcode_xsr_ccount_encode_fns, 0, 0 }, + { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, + 0, + Opcode_rsr_ccompare0_encode_fns, 0, 0 }, + { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, + 0, + Opcode_wsr_ccompare0_encode_fns, 0, 0 }, + { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, + 0, + Opcode_xsr_ccompare0_encode_fns, 0, 0 }, + { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, + 0, + Opcode_rsr_ccompare1_encode_fns, 0, 0 }, + { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, + 0, + Opcode_wsr_ccompare1_encode_fns, 0, 0 }, + { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, + 0, + Opcode_xsr_ccompare1_encode_fns, 0, 0 }, + { "ipf", ICLASS_xt_iclass_icache, + 0, + Opcode_ipf_encode_fns, 0, 0 }, + { "ihi", ICLASS_xt_iclass_icache, + 0, + Opcode_ihi_encode_fns, 0, 0 }, + { "ipfl", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ipfl_encode_fns, 0, 0 }, + { "ihu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_ihu_encode_fns, 0, 0 }, + { "iiu", ICLASS_xt_iclass_icache_lock, + 0, + Opcode_iiu_encode_fns, 0, 0 }, + { "iii", ICLASS_xt_iclass_icache_inv, + 0, + Opcode_iii_encode_fns, 0, 0 }, + { "lict", ICLASS_xt_iclass_licx, + 0, + Opcode_lict_encode_fns, 0, 0 }, + { "licw", ICLASS_xt_iclass_licx, + 0, + Opcode_licw_encode_fns, 0, 0 }, + { "sict", ICLASS_xt_iclass_sicx, + 0, + Opcode_sict_encode_fns, 0, 0 }, + { "sicw", ICLASS_xt_iclass_sicx, + 0, + Opcode_sicw_encode_fns, 0, 0 }, + { "dhwb", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwb_encode_fns, 0, 0 }, + { "dhwbi", ICLASS_xt_iclass_dcache, + 0, + Opcode_dhwbi_encode_fns, 0, 0 }, + { "diwb", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwb_encode_fns, 0, 0 }, + { "diwbi", ICLASS_xt_iclass_dcache_ind, + 0, + Opcode_diwbi_encode_fns, 0, 0 }, + { "dhi", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dhi_encode_fns, 0, 0 }, + { "dii", ICLASS_xt_iclass_dcache_inv, + 0, + Opcode_dii_encode_fns, 0, 0 }, + { "dpfr", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfr_encode_fns, 0, 0 }, + { "dpfw", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfw_encode_fns, 0, 0 }, + { "dpfro", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfro_encode_fns, 0, 0 }, + { "dpfwo", ICLASS_xt_iclass_dpf, + 0, + Opcode_dpfwo_encode_fns, 0, 0 }, + { "dpfl", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dpfl_encode_fns, 0, 0 }, + { "dhu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_dhu_encode_fns, 0, 0 }, + { "diu", ICLASS_xt_iclass_dcache_lock, + 0, + Opcode_diu_encode_fns, 0, 0 }, + { "sdct", ICLASS_xt_iclass_sdct, + 0, + Opcode_sdct_encode_fns, 0, 0 }, + { "ldct", ICLASS_xt_iclass_ldct, + 0, + Opcode_ldct_encode_fns, 0, 0 }, + { "idtlb", ICLASS_xt_iclass_idtlb, + 0, + Opcode_idtlb_encode_fns, 0, 0 }, + { "pdtlb", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_pdtlb_encode_fns, 0, 0 }, + { "rdtlb0", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb0_encode_fns, 0, 0 }, + { "rdtlb1", ICLASS_xt_iclass_rdtlb, + 0, + Opcode_rdtlb1_encode_fns, 0, 0 }, + { "wdtlb", ICLASS_xt_iclass_wdtlb, + 0, + Opcode_wdtlb_encode_fns, 0, 0 }, + { "iitlb", ICLASS_xt_iclass_iitlb, + 0, + Opcode_iitlb_encode_fns, 0, 0 }, + { "pitlb", ICLASS_xt_iclass_ritlb, + 0, + Opcode_pitlb_encode_fns, 0, 0 }, + { "ritlb0", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb0_encode_fns, 0, 0 }, + { "ritlb1", ICLASS_xt_iclass_ritlb, + 0, + Opcode_ritlb1_encode_fns, 0, 0 }, + { "witlb", ICLASS_xt_iclass_witlb, + 0, + Opcode_witlb_encode_fns, 0, 0 }, + { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, + 0, + Opcode_rsr_cpenable_encode_fns, 0, 0 }, + { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, + 0, + Opcode_wsr_cpenable_encode_fns, 0, 0 }, + { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, + 0, + Opcode_xsr_cpenable_encode_fns, 0, 0 }, + { "clamps", ICLASS_xt_iclass_clamp, + 0, + Opcode_clamps_encode_fns, 0, 0 }, + { "min", ICLASS_xt_iclass_minmax, + 0, + Opcode_min_encode_fns, 0, 0 }, + { "max", ICLASS_xt_iclass_minmax, + 0, + Opcode_max_encode_fns, 0, 0 }, + { "minu", ICLASS_xt_iclass_minmax, + 0, + Opcode_minu_encode_fns, 0, 0 }, + { "maxu", ICLASS_xt_iclass_minmax, + 0, + Opcode_maxu_encode_fns, 0, 0 }, + { "nsa", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsa_encode_fns, 0, 0 }, + { "nsau", ICLASS_xt_iclass_nsa, + 0, + Opcode_nsau_encode_fns, 0, 0 }, + { "sext", ICLASS_xt_iclass_sx, + 0, + Opcode_sext_encode_fns, 0, 0 }, + { "l32ai", ICLASS_xt_iclass_l32ai, + 0, + Opcode_l32ai_encode_fns, 0, 0 }, + { "s32ri", ICLASS_xt_iclass_s32ri, + 0, + Opcode_s32ri_encode_fns, 0, 0 }, + { "s32c1i", ICLASS_xt_iclass_s32c1i, + 0, + Opcode_s32c1i_encode_fns, 0, 0 }, + { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, + 0, + Opcode_rsr_scompare1_encode_fns, 0, 0 }, + { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, + 0, + Opcode_wsr_scompare1_encode_fns, 0, 0 }, + { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, + 0, + Opcode_xsr_scompare1_encode_fns, 0, 0 }, + { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, + 0, + Opcode_rsr_atomctl_encode_fns, 0, 0 }, + { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, + 0, + Opcode_wsr_atomctl_encode_fns, 0, 0 }, + { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, + 0, + Opcode_xsr_atomctl_encode_fns, 0, 0 }, + { "rer", ICLASS_xt_iclass_rer, + 0, + Opcode_rer_encode_fns, 0, 0 }, + { "wer", ICLASS_xt_iclass_wer, + 0, + Opcode_wer_encode_fns, 0, 0 }, + { "rur.fcr", ICLASS_rur_fcr, + 0, + Opcode_rur_fcr_encode_fns, 0, 0 }, + { "wur.fcr", ICLASS_wur_fcr, + 0, + Opcode_wur_fcr_encode_fns, 0, 0 }, + { "rur.fsr", ICLASS_rur_fsr, + 0, + Opcode_rur_fsr_encode_fns, 0, 0 }, + { "wur.fsr", ICLASS_wur_fsr, + 0, + Opcode_wur_fsr_encode_fns, 0, 0 }, + { "add.s", ICLASS_fp, + 0, + Opcode_add_s_encode_fns, 0, 0 }, + { "sub.s", ICLASS_fp, + 0, + Opcode_sub_s_encode_fns, 0, 0 }, + { "mul.s", ICLASS_fp, + 0, + Opcode_mul_s_encode_fns, 0, 0 }, + { "madd.s", ICLASS_fp_mac, + 0, + Opcode_madd_s_encode_fns, 0, 0 }, + { "msub.s", ICLASS_fp_mac, + 0, + Opcode_msub_s_encode_fns, 0, 0 }, + { "movf.s", ICLASS_fp_cmov, + 0, + Opcode_movf_s_encode_fns, 0, 0 }, + { "movt.s", ICLASS_fp_cmov, + 0, + Opcode_movt_s_encode_fns, 0, 0 }, + { "moveqz.s", ICLASS_fp_mov, + 0, + Opcode_moveqz_s_encode_fns, 0, 0 }, + { "movnez.s", ICLASS_fp_mov, + 0, + Opcode_movnez_s_encode_fns, 0, 0 }, + { "movltz.s", ICLASS_fp_mov, + 0, + Opcode_movltz_s_encode_fns, 0, 0 }, + { "movgez.s", ICLASS_fp_mov, + 0, + Opcode_movgez_s_encode_fns, 0, 0 }, + { "abs.s", ICLASS_fp_mov2, + 0, + Opcode_abs_s_encode_fns, 0, 0 }, + { "mov.s", ICLASS_fp_mov2, + 0, + Opcode_mov_s_encode_fns, 0, 0 }, + { "neg.s", ICLASS_fp_mov2, + 0, + Opcode_neg_s_encode_fns, 0, 0 }, + { "un.s", ICLASS_fp_cmp, + 0, + Opcode_un_s_encode_fns, 0, 0 }, + { "oeq.s", ICLASS_fp_cmp, + 0, + Opcode_oeq_s_encode_fns, 0, 0 }, + { "ueq.s", ICLASS_fp_cmp, + 0, + Opcode_ueq_s_encode_fns, 0, 0 }, + { "olt.s", ICLASS_fp_cmp, + 0, + Opcode_olt_s_encode_fns, 0, 0 }, + { "ult.s", ICLASS_fp_cmp, + 0, + Opcode_ult_s_encode_fns, 0, 0 }, + { "ole.s", ICLASS_fp_cmp, + 0, + Opcode_ole_s_encode_fns, 0, 0 }, + { "ule.s", ICLASS_fp_cmp, + 0, + Opcode_ule_s_encode_fns, 0, 0 }, + { "float.s", ICLASS_fp_float, + 0, + Opcode_float_s_encode_fns, 0, 0 }, + { "ufloat.s", ICLASS_fp_float, + 0, + Opcode_ufloat_s_encode_fns, 0, 0 }, + { "round.s", ICLASS_fp_int, + 0, + Opcode_round_s_encode_fns, 0, 0 }, + { "ceil.s", ICLASS_fp_int, + 0, + Opcode_ceil_s_encode_fns, 0, 0 }, + { "floor.s", ICLASS_fp_int, + 0, + Opcode_floor_s_encode_fns, 0, 0 }, + { "trunc.s", ICLASS_fp_int, + 0, + Opcode_trunc_s_encode_fns, 0, 0 }, + { "utrunc.s", ICLASS_fp_int, + 0, + Opcode_utrunc_s_encode_fns, 0, 0 }, + { "rfr", ICLASS_fp_rfr, + 0, + Opcode_rfr_encode_fns, 0, 0 }, + { "wfr", ICLASS_fp_wfr, + 0, + Opcode_wfr_encode_fns, 0, 0 }, + { "lsi", ICLASS_fp_lsi, + 0, + Opcode_lsi_encode_fns, 0, 0 }, + { "lsiu", ICLASS_fp_lsiu, + 0, + Opcode_lsiu_encode_fns, 0, 0 }, + { "lsx", ICLASS_fp_lsx, + 0, + Opcode_lsx_encode_fns, 0, 0 }, + { "lsxu", ICLASS_fp_lsxu, + 0, + Opcode_lsxu_encode_fns, 0, 0 }, + { "ssi", ICLASS_fp_ssi, + 0, + Opcode_ssi_encode_fns, 0, 0 }, + { "ssiu", ICLASS_fp_ssiu, + 0, + Opcode_ssiu_encode_fns, 0, 0 }, + { "ssx", ICLASS_fp_ssx, + 0, + Opcode_ssx_encode_fns, 0, 0 }, + { "ssxu", ICLASS_fp_ssxu, + 0, + Opcode_ssxu_encode_fns, 0, 0 }, + { "get_argmax", ICLASS_iclass_GET_ARGMAX, + 0, + Opcode_get_argmax_encode_fns, 0, 0 }, + { "get_hsar", ICLASS_iclass_GET_HSAR, + 0, + Opcode_get_hsar_encode_fns, 0, 0 }, + { "get_hsar2sar", ICLASS_iclass_GET_HSAR2SAR, + 0, + Opcode_get_hsar2sar_encode_fns, 0, 0 }, + { "get_interp_ext_n", ICLASS_iclass_GET_INTERP_EXT_N, + 0, + Opcode_get_interp_ext_n_encode_fns, 0, 0 }, + { "get_interp_ext_l", ICLASS_iclass_GET_INTERP_EXT_L, + 0, + Opcode_get_interp_ext_l_encode_fns, 0, 0 }, + { "get_llr_buf", ICLASS_iclass_GET_LLR_BUF, + 0, + Opcode_get_llr_buf_encode_fns, 0, 0 }, + { "get_llr_pos", ICLASS_iclass_GET_LLR_POS, + 0, + Opcode_get_llr_pos_encode_fns, 0, 0 }, + { "get_max", ICLASS_iclass_GET_MAX, + 0, + Opcode_get_max_encode_fns, 0, 0 }, + { "get_nco", ICLASS_iclass_GET_NCO, + 0, + Opcode_get_nco_encode_fns, 0, 0 }, + { "get_perm_reg", ICLASS_iclass_GET_PERM_REG, + 0, + Opcode_get_perm_reg_encode_fns, 0, 0 }, + { "get_phasor_n", ICLASS_iclass_GET_PHASOR_N, + 0, + Opcode_get_phasor_n_encode_fns, 0, 0 }, + { "get_phasor_offset", ICLASS_iclass_GET_PHASOR_OFFSET, + 0, + Opcode_get_phasor_offset_encode_fns, 0, 0 }, + { "get_sar", ICLASS_iclass_GET_SAR, + 0, + Opcode_get_sar_encode_fns, 0, 0 }, + { "get_scale_reg", ICLASS_iclass_GET_SCALE_REG, + 0, + Opcode_get_scale_reg_encode_fns, 0, 0 }, + { "get_smod_buf", ICLASS_iclass_GET_SMOD_BUF, + 0, + Opcode_get_smod_buf_encode_fns, 0, 0 }, + { "get_smod_offset_table", ICLASS_iclass_GET_SMOD_OFFSET_TABLE, + 0, + Opcode_get_smod_offset_table_encode_fns, 0, 0 }, + { "get_smod_pos", ICLASS_iclass_GET_SMOD_POS, + 0, + Opcode_get_smod_pos_encode_fns, 0, 0 }, + { "get_sov", ICLASS_iclass_GET_SOV, + 0, + Opcode_get_sov_encode_fns, 0, 0 }, + { "get_wght", ICLASS_iclass_GET_WGHT, + 0, + Opcode_get_wght_encode_fns, 0, 0 }, + { "set_argmax", ICLASS_iclass_SET_ARGMAX, + 0, + Opcode_set_argmax_encode_fns, 0, 0 }, + { "set_ext_regs", ICLASS_iclass_SET_EXT_REGS, + 0, + Opcode_set_ext_regs_encode_fns, 0, 0 }, + { "set_hsar", ICLASS_iclass_SET_HSAR, + 0, + Opcode_set_hsar_encode_fns, 0, 0 }, + { "set_llr_buf", ICLASS_iclass_SET_LLR_BUF, + 0, + Opcode_set_llr_buf_encode_fns, 0, 0 }, + { "set_llr_pos", ICLASS_iclass_SET_LLR_POS, + 0, + Opcode_set_llr_pos_encode_fns, 0, 0 }, + { "set_max", ICLASS_iclass_SET_MAX, + 0, + Opcode_set_max_encode_fns, 0, 0 }, + { "set_nco", ICLASS_iclass_SET_NCO, + 0, + Opcode_set_nco_encode_fns, 0, 0 }, + { "set_perm_reg", ICLASS_iclass_SET_PERM_REG, + 0, + Opcode_set_perm_reg_encode_fns, 0, 0 }, + { "set_phasor_n", ICLASS_iclass_SET_PHASOR_N, + 0, + Opcode_set_phasor_n_encode_fns, 0, 0 }, + { "set_phasor_offset", ICLASS_iclass_SET_PHASOR_OFFSET, + 0, + Opcode_set_phasor_offset_encode_fns, 0, 0 }, + { "set_sar", ICLASS_iclass_SET_SAR, + 0, + Opcode_set_sar_encode_fns, 0, 0 }, + { "set_scale_reg", ICLASS_iclass_SET_SCALE_REG, + 0, + Opcode_set_scale_reg_encode_fns, 0, 0 }, + { "set_smod_buf", ICLASS_iclass_SET_SMOD_BUF, + 0, + Opcode_set_smod_buf_encode_fns, 0, 0 }, + { "set_smod_offset_table", ICLASS_iclass_SET_SMOD_OFFSET_TABLE, + 0, + Opcode_set_smod_offset_table_encode_fns, 0, 0 }, + { "set_smod_pos", ICLASS_iclass_SET_SMOD_POS, + 0, + Opcode_set_smod_pos_encode_fns, 0, 0 }, + { "set_sov", ICLASS_iclass_SET_SOV, + 0, + Opcode_set_sov_encode_fns, 0, 0 }, + { "set_wght", ICLASS_iclass_SET_WGHT, + 0, + Opcode_set_wght_encode_fns, 0, 0 }, + { "lac2x32", ICLASS_iclass_LAC2X32, + 0, + Opcode_lac2x32_encode_fns, 0, 0 }, + { "lac2x64_0", ICLASS_iclass_LAC2X64_0, + 0, + Opcode_lac2x64_0_encode_fns, 0, 0 }, + { "lac2x64_1", ICLASS_iclass_LAC2X64_1, + 0, + Opcode_lac2x64_1_encode_fns, 0, 0 }, + { "lac2x64_2", ICLASS_iclass_LAC2X64_2, + 0, + Opcode_lac2x64_2_encode_fns, 0, 0 }, + { "lac2x64_3", ICLASS_iclass_LAC2X64_3, + 0, + Opcode_lac2x64_3_encode_fns, 0, 0 }, + { "lac32_r", ICLASS_iclass_LAC32_R, + 0, + Opcode_lac32_r_encode_fns, 0, 0 }, + { "lac_ih", ICLASS_iclass_LAC_IH, + 0, + Opcode_lac_ih_encode_fns, 0, 0 }, + { "lac_il", ICLASS_iclass_LAC_IL, + 0, + Opcode_lac_il_encode_fns, 0, 0 }, + { "lac_rh", ICLASS_iclass_LAC_RH, + 0, + Opcode_lac_rh_encode_fns, 0, 0 }, + { "lac_rl", ICLASS_iclass_LAC_RL, + 0, + Opcode_lac_rl_encode_fns, 0, 0 }, + { "lcm", ICLASS_iclass_LCM, + 0, + Opcode_lcm_encode_fns, 0, 0 }, + { "lcm_pinc", ICLASS_iclass_LCM_PINC, + 0, + Opcode_lcm_pinc_encode_fns, 0, 0 }, + { "lcm_pinc_x", ICLASS_iclass_LCM_PINC_X, + 0, + Opcode_lcm_pinc_x_encode_fns, 0, 0 }, + { "lcm_u", ICLASS_iclass_LCM_U, + 0, + Opcode_lcm_u_encode_fns, 0, 0 }, + { "lcm_x", ICLASS_iclass_LCM_X, + 0, + Opcode_lcm_x_encode_fns, 0, 0 }, + { "lcm_xu", ICLASS_iclass_LCM_XU, + 0, + Opcode_lcm_xu_encode_fns, 0, 0 }, + { "lp", ICLASS_iclass_LP, + 0, + Opcode_lp_encode_fns, 0, 0 }, + { "lp_x", ICLASS_iclass_LP_X, + 0, + Opcode_lp_x_encode_fns, 0, 0 }, + { "lq", ICLASS_iclass_LQ, + 0, + Opcode_lq_encode_fns, 0, 0 }, + { "lq_x", ICLASS_iclass_LQ_X, + 0, + Opcode_lq_x_encode_fns, 0, 0 }, + { "lut0", ICLASS_iclass_LUT0, + 0, + Opcode_lut0_encode_fns, 0, 0 }, + { "lut1", ICLASS_iclass_LUT1, + 0, + Opcode_lut1_encode_fns, 0, 0 }, + { "lut2", ICLASS_iclass_LUT2, + 0, + Opcode_lut2_encode_fns, 0, 0 }, + { "lut3", ICLASS_iclass_LUT3, + 0, + Opcode_lut3_encode_fns, 0, 0 }, + { "sac2x32", ICLASS_iclass_SAC2X32, + 0, + Opcode_sac2x32_encode_fns, 0, 0 }, + { "sac2x64_0", ICLASS_iclass_SAC2X64_0, + 0, + Opcode_sac2x64_0_encode_fns, 0, 0 }, + { "sac2x64_1", ICLASS_iclass_SAC2X64_1, + 0, + Opcode_sac2x64_1_encode_fns, 0, 0 }, + { "sac2x64_2", ICLASS_iclass_SAC2X64_2, + 0, + Opcode_sac2x64_2_encode_fns, 0, 0 }, + { "sac2x64_3", ICLASS_iclass_SAC2X64_3, + 0, + Opcode_sac2x64_3_encode_fns, 0, 0 }, + { "sac32_r", ICLASS_iclass_SAC32_R, + 0, + Opcode_sac32_r_encode_fns, 0, 0 }, + { "sac_ih", ICLASS_iclass_SAC_IH, + 0, + Opcode_sac_ih_encode_fns, 0, 0 }, + { "sac_il", ICLASS_iclass_SAC_IL, + 0, + Opcode_sac_il_encode_fns, 0, 0 }, + { "sac_rh", ICLASS_iclass_SAC_RH, + 0, + Opcode_sac_rh_encode_fns, 0, 0 }, + { "sac_rl", ICLASS_iclass_SAC_RL, + 0, + Opcode_sac_rl_encode_fns, 0, 0 }, + { "scm", ICLASS_iclass_SCM, + 0, + Opcode_scm_encode_fns, 0, 0 }, + { "scm_pinc", ICLASS_iclass_SCM_PINC, + 0, + Opcode_scm_pinc_encode_fns, 0, 0 }, + { "scm_pinc_x", ICLASS_iclass_SCM_PINC_X, + 0, + Opcode_scm_pinc_x_encode_fns, 0, 0 }, + { "scm_u", ICLASS_iclass_SCM_U, + 0, + Opcode_scm_u_encode_fns, 0, 0 }, + { "scm_x", ICLASS_iclass_SCM_X, + 0, + Opcode_scm_x_encode_fns, 0, 0 }, + { "scm_xu", ICLASS_iclass_SCM_XU, + 0, + Opcode_scm_xu_encode_fns, 0, 0 }, + { "store_p", ICLASS_iclass_STORE_P, + 0, + Opcode_store_p_encode_fns, 0, 0 }, + { "store_q", ICLASS_iclass_STORE_Q, + 0, + Opcode_store_q_encode_fns, 0, 0 }, + { "ar2cm_dup", ICLASS_iclass_AR2CM_DUP, + 0, + Opcode_ar2cm_dup_encode_fns, 0, 0 }, + { "ar2cm_ln", ICLASS_iclass_AR2CM_LN, + 0, + Opcode_ar2cm_ln_encode_fns, 0, 0 }, + { "ar2cm_ln_i", ICLASS_iclass_AR2CM_LN_I, + 0, + Opcode_ar2cm_ln_i_encode_fns, 0, 0 }, + { "ar2cm_ln_r", ICLASS_iclass_AR2CM_LN_R, + 0, + Opcode_ar2cm_ln_r_encode_fns, 0, 0 }, + { "ar2pq_ln", ICLASS_iclass_AR2PQ_LN, + 0, + Opcode_ar2pq_ln_encode_fns, 0, 0 }, + { "ar2sar_dup", ICLASS_iclass_AR2SAR_DUP, + 0, + Opcode_ar2sar_dup_encode_fns, 0, 0 }, + { "clrac", ICLASS_iclass_CLRAC, + 0, + Opcode_clrac_encode_fns, 0, 0 }, + { "clrcm", ICLASS_iclass_CLRCM, + 0, + Opcode_clrcm_encode_fns, 0, 0 }, + { "cm2ar_ln", ICLASS_iclass_CM2AR_LN, + 0, + Opcode_cm2ar_ln_encode_fns, 0, 0 }, + { "cm2ar_ln_i", ICLASS_iclass_CM2AR_LN_I, + 0, + Opcode_cm2ar_ln_i_encode_fns, 0, 0 }, + { "cm2ar_ln_r", ICLASS_iclass_CM2AR_LN_R, + 0, + Opcode_cm2ar_ln_r_encode_fns, 0, 0 }, + { "comb_ar", ICLASS_iclass_COMB_AR, + 0, + Opcode_comb_ar_encode_fns, 0, 0 }, + { "conj", ICLASS_iclass_CONJ, + 0, + Opcode_conj_encode_fns, 0, 0 }, + { "mov2ac32_i", ICLASS_iclass_MOV2AC32_I, + 0, + Opcode_mov2ac32_i_encode_fns, 0, 0 }, + { "mov2ac32_r", ICLASS_iclass_MOV2AC32_R, + 0, + Opcode_mov2ac32_r_encode_fns, 0, 0 }, + { "mov2cm2pq", ICLASS_iclass_MOV2CM2PQ, + 0, + Opcode_mov2cm2pq_encode_fns, 0, 0 }, + { "movac", ICLASS_iclass_MOVAC, + 0, + Opcode_movac_encode_fns, 0, 0 }, + { "movac_i", ICLASS_iclass_MOVAC_I, + 0, + Opcode_movac_i_encode_fns, 0, 0 }, + { "movac_i2r", ICLASS_iclass_MOVAC_I2R, + 0, + Opcode_movac_i2r_encode_fns, 0, 0 }, + { "movac_r", ICLASS_iclass_MOVAC_R, + 0, + Opcode_movac_r_encode_fns, 0, 0 }, + { "movac_r2i", ICLASS_iclass_MOVAC_R2I, + 0, + Opcode_movac_r2i_encode_fns, 0, 0 }, + { "movar2", ICLASS_iclass_MOVAR2, + 0, + Opcode_movar2_encode_fns, 0, 0 }, + { "movcm", ICLASS_iclass_MOVCM, + 0, + Opcode_movcm_encode_fns, 0, 0 }, + { "movcm2pq", ICLASS_iclass_MOVCM2PQ, + 0, + Opcode_movcm2pq_encode_fns, 0, 0 }, + { "movcnd_0", ICLASS_iclass_MOVCND_0, + 0, + Opcode_movcnd_0_encode_fns, 0, 0 }, + { "movcnd_1", ICLASS_iclass_MOVCND_1, + 0, + Opcode_movcnd_1_encode_fns, 0, 0 }, + { "movcnd_2", ICLASS_iclass_MOVCND_2, + 0, + Opcode_movcnd_2_encode_fns, 0, 0 }, + { "movcnd_3", ICLASS_iclass_MOVCND_3, + 0, + Opcode_movcnd_3_encode_fns, 0, 0 }, + { "movcnd_4", ICLASS_iclass_MOVCND_4, + 0, + Opcode_movcnd_4_encode_fns, 0, 0 }, + { "movcnd_5", ICLASS_iclass_MOVCND_5, + 0, + Opcode_movcnd_5_encode_fns, 0, 0 }, + { "movcnd_6", ICLASS_iclass_MOVCND_6, + 0, + Opcode_movcnd_6_encode_fns, 0, 0 }, + { "movcnd_7", ICLASS_iclass_MOVCND_7, + 0, + Opcode_movcnd_7_encode_fns, 0, 0 }, + { "movcnd8_0", ICLASS_iclass_MOVCND8_0, + 0, + Opcode_movcnd8_0_encode_fns, 0, 0 }, + { "movcnd8_1", ICLASS_iclass_MOVCND8_1, + 0, + Opcode_movcnd8_1_encode_fns, 0, 0 }, + { "movcnd8_2", ICLASS_iclass_MOVCND8_2, + 0, + Opcode_movcnd8_2_encode_fns, 0, 0 }, + { "movcnd8_3", ICLASS_iclass_MOVCND8_3, + 0, + Opcode_movcnd8_3_encode_fns, 0, 0 }, + { "movcnd8_4", ICLASS_iclass_MOVCND8_4, + 0, + Opcode_movcnd8_4_encode_fns, 0, 0 }, + { "movcnd8_5", ICLASS_iclass_MOVCND8_5, + 0, + Opcode_movcnd8_5_encode_fns, 0, 0 }, + { "movcnd8_6", ICLASS_iclass_MOVCND8_6, + 0, + Opcode_movcnd8_6_encode_fns, 0, 0 }, + { "movcnd8_7", ICLASS_iclass_MOVCND8_7, + 0, + Opcode_movcnd8_7_encode_fns, 0, 0 }, + { "mov_i", ICLASS_iclass_MOV_I, + 0, + Opcode_mov_i_encode_fns, 0, 0 }, + { "movpq2pq", ICLASS_iclass_MOVPQ2PQ, + 0, + Opcode_movpq2pq_encode_fns, 0, 0 }, + { "mov_r", ICLASS_iclass_MOV_R, + 0, + Opcode_mov_r_encode_fns, 0, 0 }, + { "negcm", ICLASS_iclass_NEGCM, + 0, + Opcode_negcm_encode_fns, 0, 0 }, + { "pop16llr_1", ICLASS_iclass_POP16LLR_1, + 0, + Opcode_pop16llr_1_encode_fns, 0, 0 }, + { "pq2cm", ICLASS_iclass_PQ2CM, + 0, + Opcode_pq2cm_encode_fns, 0, 0 }, + { "swapac_r", ICLASS_iclass_SWAPAC_R, + 0, + Opcode_swapac_r_encode_fns, 0, 0 }, + { "swapac_ri", ICLASS_iclass_SWAPAC_RI, + 0, + Opcode_swapac_ri_encode_fns, 0, 0 }, + { "swapb", ICLASS_iclass_SWAPB, + 0, + Opcode_swapb_encode_fns, 0, 0 }, + { "add2ac", ICLASS_iclass_ADD2AC, + 0, + Opcode_add2ac_encode_fns, 0, 0 }, + { "addac", ICLASS_iclass_ADDAC, + 0, + Opcode_addac_encode_fns, 0, 0 }, + { "cdot", ICLASS_iclass_CDOT, + 0, + Opcode_cdot_encode_fns, 0, 0 }, + { "cdotac", ICLASS_iclass_CDOTAC, + 0, + Opcode_cdotac_encode_fns, 0, 0 }, + { "cdotacs", ICLASS_iclass_CDOTACS, + 0, + Opcode_cdotacs_encode_fns, 0, 0 }, + { "cmac", ICLASS_iclass_CMAC, + 0, + Opcode_cmac_encode_fns, 0, 0 }, + { "cmacs", ICLASS_iclass_CMACS, + 0, + Opcode_cmacs_encode_fns, 0, 0 }, + { "cmpy", ICLASS_iclass_CMPY, + 0, + Opcode_cmpy_encode_fns, 0, 0 }, + { "cmpy2cm", ICLASS_iclass_CMPY2CM, + 0, + Opcode_cmpy2cm_encode_fns, 0, 0 }, + { "cmpy2pq", ICLASS_iclass_CMPY2PQ, + 0, + Opcode_cmpy2pq_encode_fns, 0, 0 }, + { "cmpys", ICLASS_iclass_CMPYS, + 0, + Opcode_cmpys_encode_fns, 0, 0 }, + { "cmpyxp2pq", ICLASS_iclass_CMPYXP2PQ, + 0, + Opcode_cmpyxp2pq_encode_fns, 0, 0 }, + { "comb32", ICLASS_iclass_COMB32, + 0, + Opcode_comb32_encode_fns, 0, 0 }, + { "dot", ICLASS_iclass_DOT, + 0, + Opcode_dot_encode_fns, 0, 0 }, + { "dotac", ICLASS_iclass_DOTAC, + 0, + Opcode_dotac_encode_fns, 0, 0 }, + { "dotacs", ICLASS_iclass_DOTACS, + 0, + Opcode_dotacs_encode_fns, 0, 0 }, + { "lin_int", ICLASS_iclass_LIN_INT, + 0, + Opcode_lin_int_encode_fns, 0, 0 }, + { "llrpre1", ICLASS_iclass_LLRPRE1, + 0, + Opcode_llrpre1_encode_fns, 0, 0 }, + { "llrpre2", ICLASS_iclass_LLRPRE2, + 0, + Opcode_llrpre2_encode_fns, 0, 0 }, + { "mac", ICLASS_iclass_MAC, + 0, + Opcode_mac_encode_fns, 0, 0 }, + { "mac8", ICLASS_iclass_MAC8, + 0, + Opcode_mac8_encode_fns, 0, 0 }, + { "macd8", ICLASS_iclass_MACD8, + 0, + Opcode_macd8_encode_fns, 0, 0 }, + { "macpqxp_0", ICLASS_iclass_MACPQXP_0, + 0, + Opcode_macpqxp_0_encode_fns, 0, 0 }, + { "macpqxp_1", ICLASS_iclass_MACPQXP_1, + 0, + Opcode_macpqxp_1_encode_fns, 0, 0 }, + { "macpqxp_2", ICLASS_iclass_MACPQXP_2, + 0, + Opcode_macpqxp_2_encode_fns, 0, 0 }, + { "macpqxp_3", ICLASS_iclass_MACPQXP_3, + 0, + Opcode_macpqxp_3_encode_fns, 0, 0 }, + { "macs", ICLASS_iclass_MACS, + 0, + Opcode_macs_encode_fns, 0, 0 }, + { "macxp2_0", ICLASS_iclass_MACXP2_0, + 0, + Opcode_macxp2_0_encode_fns, 0, 0 }, + { "macxp2_1", ICLASS_iclass_MACXP2_1, + 0, + Opcode_macxp2_1_encode_fns, 0, 0 }, + { "macxp_0", ICLASS_iclass_MACXP_0, + 0, + Opcode_macxp_0_encode_fns, 0, 0 }, + { "macxp_1", ICLASS_iclass_MACXP_1, + 0, + Opcode_macxp_1_encode_fns, 0, 0 }, + { "macxp_2", ICLASS_iclass_MACXP_2, + 0, + Opcode_macxp_2_encode_fns, 0, 0 }, + { "macxp_3", ICLASS_iclass_MACXP_3, + 0, + Opcode_macxp_3_encode_fns, 0, 0 }, + { "mov2ac", ICLASS_iclass_MOV2AC, + 0, + Opcode_mov2ac_encode_fns, 0, 0 }, + { "mpy", ICLASS_iclass_MPY, + 0, + Opcode_mpy_encode_fns, 0, 0 }, + { "mpy2cm", ICLASS_iclass_MPY2CM, + 0, + Opcode_mpy2cm_encode_fns, 0, 0 }, + { "mpy2pq", ICLASS_iclass_MPY2PQ, + 0, + Opcode_mpy2pq_encode_fns, 0, 0 }, + { "mpy8", ICLASS_iclass_MPY8, + 0, + Opcode_mpy8_encode_fns, 0, 0 }, + { "mpyadd8_2cm", ICLASS_iclass_MPYADD8_2CM, + 0, + Opcode_mpyadd8_2cm_encode_fns, 0, 0 }, + { "mpyd8", ICLASS_iclass_MPYD8, + 0, + Opcode_mpyd8_encode_fns, 0, 0 }, + { "mpypqxp_0", ICLASS_iclass_MPYPQXP_0, + 0, + Opcode_mpypqxp_0_encode_fns, 0, 0 }, + { "mpypqxp_1", ICLASS_iclass_MPYPQXP_1, + 0, + Opcode_mpypqxp_1_encode_fns, 0, 0 }, + { "mpypqxp_2", ICLASS_iclass_MPYPQXP_2, + 0, + Opcode_mpypqxp_2_encode_fns, 0, 0 }, + { "mpypqxp_3", ICLASS_iclass_MPYPQXP_3, + 0, + Opcode_mpypqxp_3_encode_fns, 0, 0 }, + { "mpys", ICLASS_iclass_MPYS, + 0, + Opcode_mpys_encode_fns, 0, 0 }, + { "mpyxp2pq", ICLASS_iclass_MPYXP2PQ, + 0, + Opcode_mpyxp2pq_encode_fns, 0, 0 }, + { "mpyxp2_0", ICLASS_iclass_MPYXP2_0, + 0, + Opcode_mpyxp2_0_encode_fns, 0, 0 }, + { "mpyxp2_1", ICLASS_iclass_MPYXP2_1, + 0, + Opcode_mpyxp2_1_encode_fns, 0, 0 }, + { "mpyxp_0", ICLASS_iclass_MPYXP_0, + 0, + Opcode_mpyxp_0_encode_fns, 0, 0 }, + { "mpyxp_1", ICLASS_iclass_MPYXP_1, + 0, + Opcode_mpyxp_1_encode_fns, 0, 0 }, + { "mpyxp_2", ICLASS_iclass_MPYXP_2, + 0, + Opcode_mpyxp_2_encode_fns, 0, 0 }, + { "mpyxp_3", ICLASS_iclass_MPYXP_3, + 0, + Opcode_mpyxp_3_encode_fns, 0, 0 }, + { "normacd", ICLASS_iclass_NORMACD, + 0, + Opcode_normacd_encode_fns, 0, 0 }, + { "normacpq_i", ICLASS_iclass_NORMACPQ_I, + 0, + Opcode_normacpq_i_encode_fns, 0, 0 }, + { "normacpq_r", ICLASS_iclass_NORMACPQ_R, + 0, + Opcode_normacpq_r_encode_fns, 0, 0 }, + { "normd", ICLASS_iclass_NORMD, + 0, + Opcode_normd_encode_fns, 0, 0 }, + { "normpypq_i", ICLASS_iclass_NORMPYPQ_I, + 0, + Opcode_normpypq_i_encode_fns, 0, 0 }, + { "normpypq_r", ICLASS_iclass_NORMPYPQ_R, + 0, + Opcode_normpypq_r_encode_fns, 0, 0 }, + { "rcmac", ICLASS_iclass_RCMAC, + 0, + Opcode_rcmac_encode_fns, 0, 0 }, + { "rcmpy", ICLASS_iclass_RCMPY, + 0, + Opcode_rcmpy_encode_fns, 0, 0 }, + { "rcmpy2cm", ICLASS_iclass_RCMPY2CM, + 0, + Opcode_rcmpy2cm_encode_fns, 0, 0 }, + { "rfir", ICLASS_iclass_RFIR, + 0, + Opcode_rfir_encode_fns, 0, 0 }, + { "rfira", ICLASS_iclass_RFIRA, + 0, + Opcode_rfira_encode_fns, 0, 0 }, + { "rfird", ICLASS_iclass_RFIRD, + 0, + Opcode_rfird_encode_fns, 0, 0 }, + { "rfirda", ICLASS_iclass_RFIRDA, + 0, + Opcode_rfirda_encode_fns, 0, 0 }, + { "rmac", ICLASS_iclass_RMAC, + 0, + Opcode_rmac_encode_fns, 0, 0 }, + { "rmpy", ICLASS_iclass_RMPY, + 0, + Opcode_rmpy_encode_fns, 0, 0 }, + { "rmpy2cm", ICLASS_iclass_RMPY2CM, + 0, + Opcode_rmpy2cm_encode_fns, 0, 0 }, + { "smod_align", ICLASS_iclass_SMOD_ALIGN, + 0, + Opcode_smod_align_encode_fns, 0, 0 }, + { "smod_scr", ICLASS_iclass_SMOD_SCR, + 0, + Opcode_smod_scr_encode_fns, 0, 0 }, + { "sub2ac", ICLASS_iclass_SUB2AC, + 0, + Opcode_sub2ac_encode_fns, 0, 0 }, + { "wght32", ICLASS_iclass_WGHT32, + 0, + Opcode_wght32_encode_fns, 0, 0 }, + { "clrtiep", ICLASS_iclass_CLRTIEP, + 0, + Opcode_clrtiep_encode_fns, 0, 0 }, + { "ext_2fifo_0", ICLASS_iclass_EXT_2FIFO_0, + 0, + Opcode_ext_2fifo_0_encode_fns, 0, 0 }, + { "ext_2fifo_1", ICLASS_iclass_EXT_2FIFO_1, + 0, + Opcode_ext_2fifo_1_encode_fns, 0, 0 }, + { "ext_2fifo_2", ICLASS_iclass_EXT_2FIFO_2, + 0, + Opcode_ext_2fifo_2_encode_fns, 0, 0 }, + { "ext_2fifo_3", ICLASS_iclass_EXT_2FIFO_3, + 0, + Opcode_ext_2fifo_3_encode_fns, 0, 0 }, + { "ext_r2fifo_0", ICLASS_iclass_EXT_R2FIFO_0, + 0, + Opcode_ext_r2fifo_0_encode_fns, 0, 0 }, + { "ext_r2fifo_1", ICLASS_iclass_EXT_R2FIFO_1, + 0, + Opcode_ext_r2fifo_1_encode_fns, 0, 0 }, + { "ext_r2fifo_2", ICLASS_iclass_EXT_R2FIFO_2, + 0, + Opcode_ext_r2fifo_2_encode_fns, 0, 0 }, + { "ext_r2fifo_3", ICLASS_iclass_EXT_R2FIFO_3, + 0, + Opcode_ext_r2fifo_3_encode_fns, 0, 0 }, + { "lut", ICLASS_iclass_LUT, + 0, + Opcode_lut_encode_fns, 0, 0 }, + { "lut_ar", ICLASS_iclass_LUT_AR, + 0, + Opcode_lut_ar_encode_fns, 0, 0 }, + { "lut_iext", ICLASS_iclass_LUT_IEXT, + 0, + Opcode_lut_iext_encode_fns, 0, 0 }, + { "lut_phasor", ICLASS_iclass_LUT_PHASOR, + 0, + Opcode_lut_phasor_encode_fns, 0, 0 }, + { "lut_rext", ICLASS_iclass_LUT_REXT, + 0, + Opcode_lut_rext_encode_fns, 0, 0 }, + { "lut_write", ICLASS_iclass_LUT_WRITE, + 0, + Opcode_lut_write_encode_fns, 0, 0 }, + { "moveq128_0", ICLASS_iclass_MOVEQ128_0, + 0, + Opcode_moveq128_0_encode_fns, 0, 0 }, + { "moveq128_1", ICLASS_iclass_MOVEQ128_1, + 0, + Opcode_moveq128_1_encode_fns, 0, 0 }, + { "moveq128_2", ICLASS_iclass_MOVEQ128_2, + 0, + Opcode_moveq128_2_encode_fns, 0, 0 }, + { "moveq128_3", ICLASS_iclass_MOVEQ128_3, + 0, + Opcode_moveq128_3_encode_fns, 0, 0 }, + { "moveq128_4", ICLASS_iclass_MOVEQ128_4, + 0, + Opcode_moveq128_4_encode_fns, 0, 0 }, + { "moveq128_5", ICLASS_iclass_MOVEQ128_5, + 0, + Opcode_moveq128_5_encode_fns, 0, 0 }, + { "moveq32_0", ICLASS_iclass_MOVEQ32_0, + 0, + Opcode_moveq32_0_encode_fns, 0, 0 }, + { "moveq32_1", ICLASS_iclass_MOVEQ32_1, + 0, + Opcode_moveq32_1_encode_fns, 0, 0 }, + { "moveq32_2", ICLASS_iclass_MOVEQ32_2, + 0, + Opcode_moveq32_2_encode_fns, 0, 0 }, + { "moveq32_3", ICLASS_iclass_MOVEQ32_3, + 0, + Opcode_moveq32_3_encode_fns, 0, 0 }, + { "nco_update", ICLASS_iclass_NCO_UPDATE, + 0, + Opcode_nco_update_encode_fns, 0, 0 }, + { "pop128_0", ICLASS_iclass_POP128_0, + 0, + Opcode_pop128_0_encode_fns, 0, 0 }, + { "pop128_1", ICLASS_iclass_POP128_1, + 0, + Opcode_pop128_1_encode_fns, 0, 0 }, + { "pop128_2", ICLASS_iclass_POP128_2, + 0, + Opcode_pop128_2_encode_fns, 0, 0 }, + { "pop128_3", ICLASS_iclass_POP128_3, + 0, + Opcode_pop128_3_encode_fns, 0, 0 }, + { "pop128_4", ICLASS_iclass_POP128_4, + 0, + Opcode_pop128_4_encode_fns, 0, 0 }, + { "pop128_5", ICLASS_iclass_POP128_5, + 0, + Opcode_pop128_5_encode_fns, 0, 0 }, + { "pop128_2cmpq_0", ICLASS_iclass_POP128_2CMPQ_0, + 0, + Opcode_pop128_2cmpq_0_encode_fns, 0, 0 }, + { "pop128_2cmpq_1", ICLASS_iclass_POP128_2CMPQ_1, + 0, + Opcode_pop128_2cmpq_1_encode_fns, 0, 0 }, + { "pop128_2cmpq_2", ICLASS_iclass_POP128_2CMPQ_2, + 0, + Opcode_pop128_2cmpq_2_encode_fns, 0, 0 }, + { "pop128_2cmpq_3", ICLASS_iclass_POP128_2CMPQ_3, + 0, + Opcode_pop128_2cmpq_3_encode_fns, 0, 0 }, + { "pop128_2m_0", ICLASS_iclass_POP128_2M_0, + 0, + Opcode_pop128_2m_0_encode_fns, 0, 0 }, + { "pop128_2m_1", ICLASS_iclass_POP128_2M_1, + 0, + Opcode_pop128_2m_1_encode_fns, 0, 0 }, + { "pop128_2m_2", ICLASS_iclass_POP128_2M_2, + 0, + Opcode_pop128_2m_2_encode_fns, 0, 0 }, + { "pop128_2m_3", ICLASS_iclass_POP128_2M_3, + 0, + Opcode_pop128_2m_3_encode_fns, 0, 0 }, + { "pop128_2pq_0", ICLASS_iclass_POP128_2PQ_0, + 0, + Opcode_pop128_2pq_0_encode_fns, 0, 0 }, + { "pop128_2pq_1", ICLASS_iclass_POP128_2PQ_1, + 0, + Opcode_pop128_2pq_1_encode_fns, 0, 0 }, + { "pop128_2pq_2", ICLASS_iclass_POP128_2PQ_2, + 0, + Opcode_pop128_2pq_2_encode_fns, 0, 0 }, + { "pop128_2pq_3", ICLASS_iclass_POP128_2PQ_3, + 0, + Opcode_pop128_2pq_3_encode_fns, 0, 0 }, + { "pop128_2pq_4", ICLASS_iclass_POP128_2PQ_4, + 0, + Opcode_pop128_2pq_4_encode_fns, 0, 0 }, + { "pop128_2pq_5", ICLASS_iclass_POP128_2PQ_5, + 0, + Opcode_pop128_2pq_5_encode_fns, 0, 0 }, + { "pop2x128_2pq_01", ICLASS_iclass_POP2X128_2PQ_01, + 0, + Opcode_pop2x128_2pq_01_encode_fns, 0, 0 }, + { "pop2x128_2pq_03", ICLASS_iclass_POP2X128_2PQ_03, + 0, + Opcode_pop2x128_2pq_03_encode_fns, 0, 0 }, + { "pop2x128_2pq_21", ICLASS_iclass_POP2X128_2PQ_21, + 0, + Opcode_pop2x128_2pq_21_encode_fns, 0, 0 }, + { "pop2x128_2pq_23", ICLASS_iclass_POP2X128_2PQ_23, + 0, + Opcode_pop2x128_2pq_23_encode_fns, 0, 0 }, + { "pop32_0", ICLASS_iclass_POP32_0, + 0, + Opcode_pop32_0_encode_fns, 0, 0 }, + { "pop32_1", ICLASS_iclass_POP32_1, + 0, + Opcode_pop32_1_encode_fns, 0, 0 }, + { "pop32_2", ICLASS_iclass_POP32_2, + 0, + Opcode_pop32_2_encode_fns, 0, 0 }, + { "pop32_3", ICLASS_iclass_POP32_3, + 0, + Opcode_pop32_3_encode_fns, 0, 0 }, + { "push128", ICLASS_iclass_PUSH128, + 0, + Opcode_push128_encode_fns, 0, 0 }, + { "push128_m", ICLASS_iclass_PUSH128_M, + 0, + Opcode_push128_m_encode_fns, 0, 0 }, + { "push128_pq", ICLASS_iclass_PUSH128_PQ, + 0, + Opcode_push128_pq_encode_fns, 0, 0 }, + { "push2x128_pq", ICLASS_iclass_PUSH2X128_PQ, + 0, + Opcode_push2x128_pq_encode_fns, 0, 0 }, + { "push32", ICLASS_iclass_PUSH32, + 0, + Opcode_push32_encode_fns, 0, 0 }, + { "qready", ICLASS_iclass_QREADY, + 0, + Opcode_qready_encode_fns, 0, 0 }, + { "rdtiep", ICLASS_iclass_RDTIEP, + 0, + Opcode_rdtiep_encode_fns, 0, 0 }, + { "settiep", ICLASS_iclass_SETTIEP, + 0, + Opcode_settiep_encode_fns, 0, 0 }, + { "smod_lut", ICLASS_iclass_SMOD_LUT, + 0, + Opcode_smod_lut_encode_fns, 0, 0 }, + { "wrtbsigq", ICLASS_iclass_WRTBSIGQ, + 0, + Opcode_wrtbsigq_encode_fns, 0, 0 }, + { "wrtbsigqm", ICLASS_iclass_WRTBSIGQM, + 0, + Opcode_wrtbsigqm_encode_fns, 0, 0 }, + { "wrtiep", ICLASS_iclass_WRTIEP, + 0, + Opcode_wrtiep_encode_fns, 0, 0 }, + { "wrtsigq", ICLASS_iclass_WRTSIGQ, + 0, + Opcode_wrtsigq_encode_fns, 0, 0 }, + { "abs8", ICLASS_iclass_ABS8, + 0, + Opcode_abs8_encode_fns, 0, 0 }, + { "add16", ICLASS_iclass_ADD16, + 0, + Opcode_add16_encode_fns, 0, 0 }, + { "add32", ICLASS_iclass_ADD32, + 0, + Opcode_add32_encode_fns, 0, 0 }, + { "addac_i2r", ICLASS_iclass_ADDAC_I2R, + 0, + Opcode_addac_i2r_encode_fns, 0, 0 }, + { "addac_r2i", ICLASS_iclass_ADDAC_R2I, + 0, + Opcode_addac_r2i_encode_fns, 0, 0 }, + { "addar2", ICLASS_iclass_ADDAR2, + 0, + Opcode_addar2_encode_fns, 0, 0 }, + { "addcm", ICLASS_iclass_ADDCM, + 0, + Opcode_addcm_encode_fns, 0, 0 }, + { "addwrp", ICLASS_iclass_ADDWRP, + 0, + Opcode_addwrp_encode_fns, 0, 0 }, + { "and128", ICLASS_iclass_AND128, + 0, + Opcode_and128_encode_fns, 0, 0 }, + { "argmax8", ICLASS_iclass_ARGMAX8, + 0, + Opcode_argmax8_encode_fns, 0, 0 }, + { "asl", ICLASS_iclass_ASL, + 0, + Opcode_asl_encode_fns, 0, 0 }, + { "asl32", ICLASS_iclass_ASL32, + 0, + Opcode_asl32_encode_fns, 0, 0 }, + { "aslacm", ICLASS_iclass_ASLACM, + 0, + Opcode_aslacm_encode_fns, 0, 0 }, + { "aslm", ICLASS_iclass_ASLM, + 0, + Opcode_aslm_encode_fns, 0, 0 }, + { "aslm32", ICLASS_iclass_ASLM32, + 0, + Opcode_aslm32_encode_fns, 0, 0 }, + { "asr", ICLASS_iclass_ASR, + 0, + Opcode_asr_encode_fns, 0, 0 }, + { "asr32", ICLASS_iclass_ASR32, + 0, + Opcode_asr32_encode_fns, 0, 0 }, + { "asrac", ICLASS_iclass_ASRAC, + 0, + Opcode_asrac_encode_fns, 0, 0 }, + { "asrm", ICLASS_iclass_ASRM, + 0, + Opcode_asrm_encode_fns, 0, 0 }, + { "bitfext", ICLASS_iclass_BITFEXT, + 0, + Opcode_bitfext_encode_fns, 0, 0 }, + { "bitfins", ICLASS_iclass_BITFINS, + 0, + Opcode_bitfins_encode_fns, 0, 0 }, + { "clb_c", ICLASS_iclass_CLB_C, + 0, + Opcode_clb_c_encode_fns, 0, 0 }, + { "clb_r", ICLASS_iclass_CLB_R, + 0, + Opcode_clb_r_encode_fns, 0, 0 }, + { "cmp8", ICLASS_iclass_CMP8, + 0, + Opcode_cmp8_encode_fns, 0, 0 }, + { "cmp_i", ICLASS_iclass_CMP_I, + 0, + Opcode_cmp_i_encode_fns, 0, 0 }, + { "cmp_r", ICLASS_iclass_CMP_R, + 0, + Opcode_cmp_r_encode_fns, 0, 0 }, + { "ext", ICLASS_iclass_EXT, + 0, + Opcode_ext_encode_fns, 0, 0 }, + { "ext_r", ICLASS_iclass_EXT_R, + 0, + Opcode_ext_r_encode_fns, 0, 0 }, + { "ext32_i", ICLASS_iclass_EXT32_I, + 0, + Opcode_ext32_i_encode_fns, 0, 0 }, + { "ext32_r", ICLASS_iclass_EXT32_R, + 0, + Opcode_ext32_r_encode_fns, 0, 0 }, + { "extui4", ICLASS_iclass_EXTUI4, + 0, + Opcode_extui4_encode_fns, 0, 0 }, + { "lslm", ICLASS_iclass_LSLM, + 0, + Opcode_lslm_encode_fns, 0, 0 }, + { "lsrm", ICLASS_iclass_LSRM, + 0, + Opcode_lsrm_encode_fns, 0, 0 }, + { "max8", ICLASS_iclass_MAX8, + 0, + Opcode_max8_encode_fns, 0, 0 }, + { "mean", ICLASS_iclass_MEAN, + 0, + Opcode_mean_encode_fns, 0, 0 }, + { "mean32", ICLASS_iclass_MEAN32, + 0, + Opcode_mean32_encode_fns, 0, 0 }, + { "min8", ICLASS_iclass_MIN8, + 0, + Opcode_min8_encode_fns, 0, 0 }, + { "minclb_c", ICLASS_iclass_MINCLB_C, + 0, + Opcode_minclb_c_encode_fns, 0, 0 }, + { "minclb_r", ICLASS_iclass_MINCLB_R, + 0, + Opcode_minclb_r_encode_fns, 0, 0 }, + { "not128", ICLASS_iclass_NOT128, + 0, + Opcode_not128_encode_fns, 0, 0 }, + { "or128", ICLASS_iclass_OR128, + 0, + Opcode_or128_encode_fns, 0, 0 }, + { "perm", ICLASS_iclass_PERM, + 0, + Opcode_perm_encode_fns, 0, 0 }, + { "redac", ICLASS_iclass_REDAC, + 0, + Opcode_redac_encode_fns, 0, 0 }, + { "redac2", ICLASS_iclass_REDAC2, + 0, + Opcode_redac2_encode_fns, 0, 0 }, + { "redac4", ICLASS_iclass_REDAC4, + 0, + Opcode_redac4_encode_fns, 0, 0 }, + { "redacs", ICLASS_iclass_REDACS, + 0, + Opcode_redacs_encode_fns, 0, 0 }, + { "sminclb_c", ICLASS_iclass_SMINCLB_C, + 0, + Opcode_sminclb_c_encode_fns, 0, 0 }, + { "sminclb_r", ICLASS_iclass_SMINCLB_R, + 0, + Opcode_sminclb_r_encode_fns, 0, 0 }, + { "stswapbm", ICLASS_iclass_STSWAPBM, + 0, + Opcode_stswapbm_encode_fns, 0, 0 }, + { "stswapbmu", ICLASS_iclass_STSWAPBMU, + 0, + Opcode_stswapbmu_encode_fns, 0, 0 }, + { "sub32", ICLASS_iclass_SUB32, + 0, + Opcode_sub32_encode_fns, 0, 0 }, + { "subac_i2r", ICLASS_iclass_SUBAC_I2R, + 0, + Opcode_subac_i2r_encode_fns, 0, 0 }, + { "subac_r2i", ICLASS_iclass_SUBAC_R2I, + 0, + Opcode_subac_r2i_encode_fns, 0, 0 }, + { "subarx", ICLASS_iclass_SUBARX, + 0, + Opcode_subarx_encode_fns, 0, 0 }, + { "subcm", ICLASS_iclass_SUBCM, + 0, + Opcode_subcm_encode_fns, 0, 0 }, + { "submean", ICLASS_iclass_SUBMEAN, + 0, + Opcode_submean_encode_fns, 0, 0 }, + { "subwrp", ICLASS_iclass_SUBWRP, + 0, + Opcode_subwrp_encode_fns, 0, 0 }, + { "trans", ICLASS_iclass_TRANS, + 0, + Opcode_trans_encode_fns, 0, 0 }, + { "xor128", ICLASS_iclass_XOR128, + 0, + Opcode_xor128_encode_fns, 0, 0 }, + { "rur.expstate", ICLASS_rur_expstate, + 0, + Opcode_rur_expstate_encode_fns, 0, 0 }, + { "wur.expstate", ICLASS_wur_expstate, + 0, + Opcode_wur_expstate_encode_fns, 0, 0 }, + { "rur.sov", ICLASS_rur_sov, + 0, + Opcode_rur_sov_encode_fns, 0, 0 }, + { "wur.sov", ICLASS_wur_sov, + 0, + Opcode_wur_sov_encode_fns, 0, 0 }, + { "rur.sat_mode", ICLASS_rur_sat_mode, + 0, + Opcode_rur_sat_mode_encode_fns, 0, 0 }, + { "wur.sat_mode", ICLASS_wur_sat_mode, + 0, + Opcode_wur_sat_mode_encode_fns, 0, 0 }, + { "rur.sar0", ICLASS_rur_sar0, + 0, + Opcode_rur_sar0_encode_fns, 0, 0 }, + { "wur.sar0", ICLASS_wur_sar0, + 0, + Opcode_wur_sar0_encode_fns, 0, 0 }, + { "rur.sar1", ICLASS_rur_sar1, + 0, + Opcode_rur_sar1_encode_fns, 0, 0 }, + { "wur.sar1", ICLASS_wur_sar1, + 0, + Opcode_wur_sar1_encode_fns, 0, 0 }, + { "rur.sar2", ICLASS_rur_sar2, + 0, + Opcode_rur_sar2_encode_fns, 0, 0 }, + { "wur.sar2", ICLASS_wur_sar2, + 0, + Opcode_wur_sar2_encode_fns, 0, 0 }, + { "rur.sar3", ICLASS_rur_sar3, + 0, + Opcode_rur_sar3_encode_fns, 0, 0 }, + { "wur.sar3", ICLASS_wur_sar3, + 0, + Opcode_wur_sar3_encode_fns, 0, 0 }, + { "rur.hsar0", ICLASS_rur_hsar0, + 0, + Opcode_rur_hsar0_encode_fns, 0, 0 }, + { "wur.hsar0", ICLASS_wur_hsar0, + 0, + Opcode_wur_hsar0_encode_fns, 0, 0 }, + { "rur.hsar1", ICLASS_rur_hsar1, + 0, + Opcode_rur_hsar1_encode_fns, 0, 0 }, + { "wur.hsar1", ICLASS_wur_hsar1, + 0, + Opcode_wur_hsar1_encode_fns, 0, 0 }, + { "rur.hsar2", ICLASS_rur_hsar2, + 0, + Opcode_rur_hsar2_encode_fns, 0, 0 }, + { "wur.hsar2", ICLASS_wur_hsar2, + 0, + Opcode_wur_hsar2_encode_fns, 0, 0 }, + { "rur.hsar3", ICLASS_rur_hsar3, + 0, + Opcode_rur_hsar3_encode_fns, 0, 0 }, + { "wur.hsar3", ICLASS_wur_hsar3, + 0, + Opcode_wur_hsar3_encode_fns, 0, 0 }, + { "rur.max_reg_0", ICLASS_rur_max_reg_0, + 0, + Opcode_rur_max_reg_0_encode_fns, 0, 0 }, + { "wur.max_reg_0", ICLASS_wur_max_reg_0, + 0, + Opcode_wur_max_reg_0_encode_fns, 0, 0 }, + { "rur.max_reg_1", ICLASS_rur_max_reg_1, + 0, + Opcode_rur_max_reg_1_encode_fns, 0, 0 }, + { "wur.max_reg_1", ICLASS_wur_max_reg_1, + 0, + Opcode_wur_max_reg_1_encode_fns, 0, 0 }, + { "rur.max_reg_2", ICLASS_rur_max_reg_2, + 0, + Opcode_rur_max_reg_2_encode_fns, 0, 0 }, + { "wur.max_reg_2", ICLASS_wur_max_reg_2, + 0, + Opcode_wur_max_reg_2_encode_fns, 0, 0 }, + { "rur.max_reg_3", ICLASS_rur_max_reg_3, + 0, + Opcode_rur_max_reg_3_encode_fns, 0, 0 }, + { "wur.max_reg_3", ICLASS_wur_max_reg_3, + 0, + Opcode_wur_max_reg_3_encode_fns, 0, 0 }, + { "rur.arg_max_reg_0", ICLASS_rur_arg_max_reg_0, + 0, + Opcode_rur_arg_max_reg_0_encode_fns, 0, 0 }, + { "wur.arg_max_reg_0", ICLASS_wur_arg_max_reg_0, + 0, + Opcode_wur_arg_max_reg_0_encode_fns, 0, 0 }, + { "rur.arg_max_reg_1", ICLASS_rur_arg_max_reg_1, + 0, + Opcode_rur_arg_max_reg_1_encode_fns, 0, 0 }, + { "wur.arg_max_reg_1", ICLASS_wur_arg_max_reg_1, + 0, + Opcode_wur_arg_max_reg_1_encode_fns, 0, 0 }, + { "rur.arg_max_reg_2", ICLASS_rur_arg_max_reg_2, + 0, + Opcode_rur_arg_max_reg_2_encode_fns, 0, 0 }, + { "wur.arg_max_reg_2", ICLASS_wur_arg_max_reg_2, + 0, + Opcode_wur_arg_max_reg_2_encode_fns, 0, 0 }, + { "rur.arg_max_reg_3", ICLASS_rur_arg_max_reg_3, + 0, + Opcode_rur_arg_max_reg_3_encode_fns, 0, 0 }, + { "wur.arg_max_reg_3", ICLASS_wur_arg_max_reg_3, + 0, + Opcode_wur_arg_max_reg_3_encode_fns, 0, 0 }, + { "rur.nco_counter_0", ICLASS_rur_nco_counter_0, + 0, + Opcode_rur_nco_counter_0_encode_fns, 0, 0 }, + { "wur.nco_counter_0", ICLASS_wur_nco_counter_0, + 0, + Opcode_wur_nco_counter_0_encode_fns, 0, 0 }, + { "rur.nco_counter_1", ICLASS_rur_nco_counter_1, + 0, + Opcode_rur_nco_counter_1_encode_fns, 0, 0 }, + { "wur.nco_counter_1", ICLASS_wur_nco_counter_1, + 0, + Opcode_wur_nco_counter_1_encode_fns, 0, 0 }, + { "rur.nco_counter_2", ICLASS_rur_nco_counter_2, + 0, + Opcode_rur_nco_counter_2_encode_fns, 0, 0 }, + { "wur.nco_counter_2", ICLASS_wur_nco_counter_2, + 0, + Opcode_wur_nco_counter_2_encode_fns, 0, 0 }, + { "rur.nco_counter_3", ICLASS_rur_nco_counter_3, + 0, + Opcode_rur_nco_counter_3_encode_fns, 0, 0 }, + { "wur.nco_counter_3", ICLASS_wur_nco_counter_3, + 0, + Opcode_wur_nco_counter_3_encode_fns, 0, 0 }, + { "rur.interp_ext_n", ICLASS_rur_interp_ext_n, + 0, + Opcode_rur_interp_ext_n_encode_fns, 0, 0 }, + { "wur.interp_ext_n", ICLASS_wur_interp_ext_n, + 0, + Opcode_wur_interp_ext_n_encode_fns, 0, 0 }, + { "rur.interp_ext_l", ICLASS_rur_interp_ext_l, + 0, + Opcode_rur_interp_ext_l_encode_fns, 0, 0 }, + { "wur.interp_ext_l", ICLASS_wur_interp_ext_l, + 0, + Opcode_wur_interp_ext_l_encode_fns, 0, 0 }, + { "rur.llr_buf_0", ICLASS_rur_llr_buf_0, + 0, + Opcode_rur_llr_buf_0_encode_fns, 0, 0 }, + { "wur.llr_buf_0", ICLASS_wur_llr_buf_0, + 0, + Opcode_wur_llr_buf_0_encode_fns, 0, 0 }, + { "rur.llr_buf_1", ICLASS_rur_llr_buf_1, + 0, + Opcode_rur_llr_buf_1_encode_fns, 0, 0 }, + { "wur.llr_buf_1", ICLASS_wur_llr_buf_1, + 0, + Opcode_wur_llr_buf_1_encode_fns, 0, 0 }, + { "rur.llr_buf_2", ICLASS_rur_llr_buf_2, + 0, + Opcode_rur_llr_buf_2_encode_fns, 0, 0 }, + { "wur.llr_buf_2", ICLASS_wur_llr_buf_2, + 0, + Opcode_wur_llr_buf_2_encode_fns, 0, 0 }, + { "rur.llr_buf_3", ICLASS_rur_llr_buf_3, + 0, + Opcode_rur_llr_buf_3_encode_fns, 0, 0 }, + { "wur.llr_buf_3", ICLASS_wur_llr_buf_3, + 0, + Opcode_wur_llr_buf_3_encode_fns, 0, 0 }, + { "rur.llr_buf_4", ICLASS_rur_llr_buf_4, + 0, + Opcode_rur_llr_buf_4_encode_fns, 0, 0 }, + { "wur.llr_buf_4", ICLASS_wur_llr_buf_4, + 0, + Opcode_wur_llr_buf_4_encode_fns, 0, 0 }, + { "rur.llr_buf_5", ICLASS_rur_llr_buf_5, + 0, + Opcode_rur_llr_buf_5_encode_fns, 0, 0 }, + { "wur.llr_buf_5", ICLASS_wur_llr_buf_5, + 0, + Opcode_wur_llr_buf_5_encode_fns, 0, 0 }, + { "rur.llr_buf_6", ICLASS_rur_llr_buf_6, + 0, + Opcode_rur_llr_buf_6_encode_fns, 0, 0 }, + { "wur.llr_buf_6", ICLASS_wur_llr_buf_6, + 0, + Opcode_wur_llr_buf_6_encode_fns, 0, 0 }, + { "rur.llr_buf_7", ICLASS_rur_llr_buf_7, + 0, + Opcode_rur_llr_buf_7_encode_fns, 0, 0 }, + { "wur.llr_buf_7", ICLASS_wur_llr_buf_7, + 0, + Opcode_wur_llr_buf_7_encode_fns, 0, 0 }, + { "rur.llr_buf_8", ICLASS_rur_llr_buf_8, + 0, + Opcode_rur_llr_buf_8_encode_fns, 0, 0 }, + { "wur.llr_buf_8", ICLASS_wur_llr_buf_8, + 0, + Opcode_wur_llr_buf_8_encode_fns, 0, 0 }, + { "rur.llr_buf_9", ICLASS_rur_llr_buf_9, + 0, + Opcode_rur_llr_buf_9_encode_fns, 0, 0 }, + { "wur.llr_buf_9", ICLASS_wur_llr_buf_9, + 0, + Opcode_wur_llr_buf_9_encode_fns, 0, 0 }, + { "rur.llr_buf_10", ICLASS_rur_llr_buf_10, + 0, + Opcode_rur_llr_buf_10_encode_fns, 0, 0 }, + { "wur.llr_buf_10", ICLASS_wur_llr_buf_10, + 0, + Opcode_wur_llr_buf_10_encode_fns, 0, 0 }, + { "rur.llr_buf_11", ICLASS_rur_llr_buf_11, + 0, + Opcode_rur_llr_buf_11_encode_fns, 0, 0 }, + { "wur.llr_buf_11", ICLASS_wur_llr_buf_11, + 0, + Opcode_wur_llr_buf_11_encode_fns, 0, 0 }, + { "rur.llr_buf_12", ICLASS_rur_llr_buf_12, + 0, + Opcode_rur_llr_buf_12_encode_fns, 0, 0 }, + { "wur.llr_buf_12", ICLASS_wur_llr_buf_12, + 0, + Opcode_wur_llr_buf_12_encode_fns, 0, 0 }, + { "rur.llr_buf_13", ICLASS_rur_llr_buf_13, + 0, + Opcode_rur_llr_buf_13_encode_fns, 0, 0 }, + { "wur.llr_buf_13", ICLASS_wur_llr_buf_13, + 0, + Opcode_wur_llr_buf_13_encode_fns, 0, 0 }, + { "rur.llr_buf_14", ICLASS_rur_llr_buf_14, + 0, + Opcode_rur_llr_buf_14_encode_fns, 0, 0 }, + { "wur.llr_buf_14", ICLASS_wur_llr_buf_14, + 0, + Opcode_wur_llr_buf_14_encode_fns, 0, 0 }, + { "rur.llr_buf_15", ICLASS_rur_llr_buf_15, + 0, + Opcode_rur_llr_buf_15_encode_fns, 0, 0 }, + { "wur.llr_buf_15", ICLASS_wur_llr_buf_15, + 0, + Opcode_wur_llr_buf_15_encode_fns, 0, 0 }, + { "rur.llr_buf_16", ICLASS_rur_llr_buf_16, + 0, + Opcode_rur_llr_buf_16_encode_fns, 0, 0 }, + { "wur.llr_buf_16", ICLASS_wur_llr_buf_16, + 0, + Opcode_wur_llr_buf_16_encode_fns, 0, 0 }, + { "rur.llr_buf_17", ICLASS_rur_llr_buf_17, + 0, + Opcode_rur_llr_buf_17_encode_fns, 0, 0 }, + { "wur.llr_buf_17", ICLASS_wur_llr_buf_17, + 0, + Opcode_wur_llr_buf_17_encode_fns, 0, 0 }, + { "rur.llr_buf_18", ICLASS_rur_llr_buf_18, + 0, + Opcode_rur_llr_buf_18_encode_fns, 0, 0 }, + { "wur.llr_buf_18", ICLASS_wur_llr_buf_18, + 0, + Opcode_wur_llr_buf_18_encode_fns, 0, 0 }, + { "rur.llr_buf_19", ICLASS_rur_llr_buf_19, + 0, + Opcode_rur_llr_buf_19_encode_fns, 0, 0 }, + { "wur.llr_buf_19", ICLASS_wur_llr_buf_19, + 0, + Opcode_wur_llr_buf_19_encode_fns, 0, 0 }, + { "rur.llr_buf_20", ICLASS_rur_llr_buf_20, + 0, + Opcode_rur_llr_buf_20_encode_fns, 0, 0 }, + { "wur.llr_buf_20", ICLASS_wur_llr_buf_20, + 0, + Opcode_wur_llr_buf_20_encode_fns, 0, 0 }, + { "rur.llr_buf_21", ICLASS_rur_llr_buf_21, + 0, + Opcode_rur_llr_buf_21_encode_fns, 0, 0 }, + { "wur.llr_buf_21", ICLASS_wur_llr_buf_21, + 0, + Opcode_wur_llr_buf_21_encode_fns, 0, 0 }, + { "rur.llr_buf_22", ICLASS_rur_llr_buf_22, + 0, + Opcode_rur_llr_buf_22_encode_fns, 0, 0 }, + { "wur.llr_buf_22", ICLASS_wur_llr_buf_22, + 0, + Opcode_wur_llr_buf_22_encode_fns, 0, 0 }, + { "rur.llr_buf_23", ICLASS_rur_llr_buf_23, + 0, + Opcode_rur_llr_buf_23_encode_fns, 0, 0 }, + { "wur.llr_buf_23", ICLASS_wur_llr_buf_23, + 0, + Opcode_wur_llr_buf_23_encode_fns, 0, 0 }, + { "rur.smod_buf_0", ICLASS_rur_smod_buf_0, + 0, + Opcode_rur_smod_buf_0_encode_fns, 0, 0 }, + { "wur.smod_buf_0", ICLASS_wur_smod_buf_0, + 0, + Opcode_wur_smod_buf_0_encode_fns, 0, 0 }, + { "rur.smod_buf_1", ICLASS_rur_smod_buf_1, + 0, + Opcode_rur_smod_buf_1_encode_fns, 0, 0 }, + { "wur.smod_buf_1", ICLASS_wur_smod_buf_1, + 0, + Opcode_wur_smod_buf_1_encode_fns, 0, 0 }, + { "rur.smod_buf_2", ICLASS_rur_smod_buf_2, + 0, + Opcode_rur_smod_buf_2_encode_fns, 0, 0 }, + { "wur.smod_buf_2", ICLASS_wur_smod_buf_2, + 0, + Opcode_wur_smod_buf_2_encode_fns, 0, 0 }, + { "rur.smod_buf_3", ICLASS_rur_smod_buf_3, + 0, + Opcode_rur_smod_buf_3_encode_fns, 0, 0 }, + { "wur.smod_buf_3", ICLASS_wur_smod_buf_3, + 0, + Opcode_wur_smod_buf_3_encode_fns, 0, 0 }, + { "rur.smod_buf_4", ICLASS_rur_smod_buf_4, + 0, + Opcode_rur_smod_buf_4_encode_fns, 0, 0 }, + { "wur.smod_buf_4", ICLASS_wur_smod_buf_4, + 0, + Opcode_wur_smod_buf_4_encode_fns, 0, 0 }, + { "rur.smod_buf_5", ICLASS_rur_smod_buf_5, + 0, + Opcode_rur_smod_buf_5_encode_fns, 0, 0 }, + { "wur.smod_buf_5", ICLASS_wur_smod_buf_5, + 0, + Opcode_wur_smod_buf_5_encode_fns, 0, 0 }, + { "rur.smod_buf_6", ICLASS_rur_smod_buf_6, + 0, + Opcode_rur_smod_buf_6_encode_fns, 0, 0 }, + { "wur.smod_buf_6", ICLASS_wur_smod_buf_6, + 0, + Opcode_wur_smod_buf_6_encode_fns, 0, 0 }, + { "rur.smod_buf_7", ICLASS_rur_smod_buf_7, + 0, + Opcode_rur_smod_buf_7_encode_fns, 0, 0 }, + { "wur.smod_buf_7", ICLASS_wur_smod_buf_7, + 0, + Opcode_wur_smod_buf_7_encode_fns, 0, 0 }, + { "rur.weight_reg", ICLASS_rur_weight_reg, + 0, + Opcode_rur_weight_reg_encode_fns, 0, 0 }, + { "wur.weight_reg", ICLASS_wur_weight_reg, + 0, + Opcode_wur_weight_reg_encode_fns, 0, 0 }, + { "rur.scale_reg", ICLASS_rur_scale_reg, + 0, + Opcode_rur_scale_reg_encode_fns, 0, 0 }, + { "wur.scale_reg", ICLASS_wur_scale_reg, + 0, + Opcode_wur_scale_reg_encode_fns, 0, 0 }, + { "rur.llr_pos", ICLASS_rur_llr_pos, + 0, + Opcode_rur_llr_pos_encode_fns, 0, 0 }, + { "wur.llr_pos", ICLASS_wur_llr_pos, + 0, + Opcode_wur_llr_pos_encode_fns, 0, 0 }, + { "rur.smod_pos", ICLASS_rur_smod_pos, + 0, + Opcode_rur_smod_pos_encode_fns, 0, 0 }, + { "wur.smod_pos", ICLASS_wur_smod_pos, + 0, + Opcode_wur_smod_pos_encode_fns, 0, 0 }, + { "rur.perm_reg", ICLASS_rur_perm_reg, + 0, + Opcode_rur_perm_reg_encode_fns, 0, 0 }, + { "wur.perm_reg", ICLASS_wur_perm_reg, + 0, + Opcode_wur_perm_reg_encode_fns, 0, 0 }, + { "rur.smod_offset_table_0", ICLASS_rur_smod_offset_table_0, + 0, + Opcode_rur_smod_offset_table_0_encode_fns, 0, 0 }, + { "wur.smod_offset_table_0", ICLASS_wur_smod_offset_table_0, + 0, + Opcode_wur_smod_offset_table_0_encode_fns, 0, 0 }, + { "rur.smod_offset_table_1", ICLASS_rur_smod_offset_table_1, + 0, + Opcode_rur_smod_offset_table_1_encode_fns, 0, 0 }, + { "wur.smod_offset_table_1", ICLASS_wur_smod_offset_table_1, + 0, + Opcode_wur_smod_offset_table_1_encode_fns, 0, 0 }, + { "rur.smod_offset_table_2", ICLASS_rur_smod_offset_table_2, + 0, + Opcode_rur_smod_offset_table_2_encode_fns, 0, 0 }, + { "wur.smod_offset_table_2", ICLASS_wur_smod_offset_table_2, + 0, + Opcode_wur_smod_offset_table_2_encode_fns, 0, 0 }, + { "rur.smod_offset_table_3", ICLASS_rur_smod_offset_table_3, + 0, + Opcode_rur_smod_offset_table_3_encode_fns, 0, 0 }, + { "wur.smod_offset_table_3", ICLASS_wur_smod_offset_table_3, + 0, + Opcode_wur_smod_offset_table_3_encode_fns, 0, 0 }, + { "rur.phasor_n", ICLASS_rur_phasor_n, + 0, + Opcode_rur_phasor_n_encode_fns, 0, 0 }, + { "wur.phasor_n", ICLASS_wur_phasor_n, + 0, + Opcode_wur_phasor_n_encode_fns, 0, 0 }, + { "rur.phasor_offset", ICLASS_rur_phasor_offset, + 0, + Opcode_rur_phasor_offset_encode_fns, 0, 0 }, + { "wur.phasor_offset", ICLASS_wur_phasor_offset, + 0, + Opcode_wur_phasor_offset_encode_fns, 0, 0 } +}; + +enum xtensa_opcode_id { + OPCODE_EXCW, + OPCODE_RFE, + OPCODE_RFDE, + OPCODE_SYSCALL, + OPCODE_SIMCALL, + OPCODE_CALL12, + OPCODE_CALL8, + OPCODE_CALL4, + OPCODE_CALLX12, + OPCODE_CALLX8, + OPCODE_CALLX4, + OPCODE_ENTRY, + OPCODE_MOVSP, + OPCODE_ROTW, + OPCODE_RETW, + OPCODE_RETW_N, + OPCODE_RFWO, + OPCODE_RFWU, + OPCODE_L32E, + OPCODE_S32E, + OPCODE_RSR_WINDOWBASE, + OPCODE_WSR_WINDOWBASE, + OPCODE_XSR_WINDOWBASE, + OPCODE_RSR_WINDOWSTART, + OPCODE_WSR_WINDOWSTART, + OPCODE_XSR_WINDOWSTART, + OPCODE_ADD_N, + OPCODE_ADDI_N, + OPCODE_BEQZ_N, + OPCODE_BNEZ_N, + OPCODE_ILL_N, + OPCODE_L32I_N, + OPCODE_MOV_N, + OPCODE_MOVI_N, + OPCODE_NOP_N, + OPCODE_RET_N, + OPCODE_S32I_N, + OPCODE_RUR_THREADPTR, + OPCODE_WUR_THREADPTR, + OPCODE_ADDI, + OPCODE_ADDMI, + OPCODE_ADD, + OPCODE_SUB, + OPCODE_ADDX2, + OPCODE_ADDX4, + OPCODE_ADDX8, + OPCODE_SUBX2, + OPCODE_SUBX4, + OPCODE_SUBX8, + OPCODE_AND, + OPCODE_OR, + OPCODE_XOR, + OPCODE_BEQI, + OPCODE_BNEI, + OPCODE_BGEI, + OPCODE_BLTI, + OPCODE_BBCI, + OPCODE_BBSI, + OPCODE_BGEUI, + OPCODE_BLTUI, + OPCODE_BEQ, + OPCODE_BNE, + OPCODE_BGE, + OPCODE_BLT, + OPCODE_BGEU, + OPCODE_BLTU, + OPCODE_BANY, + OPCODE_BNONE, + OPCODE_BALL, + OPCODE_BNALL, + OPCODE_BBC, + OPCODE_BBS, + OPCODE_BEQZ, + OPCODE_BNEZ, + OPCODE_BGEZ, + OPCODE_BLTZ, + OPCODE_CALL0, + OPCODE_CALLX0, + OPCODE_EXTUI, + OPCODE_ILL, + OPCODE_J, + OPCODE_JX, + OPCODE_L16UI, + OPCODE_L16SI, + OPCODE_L32I, + OPCODE_L32R, + OPCODE_L8UI, + OPCODE_LOOP, + OPCODE_LOOPNEZ, + OPCODE_LOOPGTZ, + OPCODE_MOVI, + OPCODE_MOVEQZ, + OPCODE_MOVNEZ, + OPCODE_MOVLTZ, + OPCODE_MOVGEZ, + OPCODE_NEG, + OPCODE_ABS, + OPCODE_NOP, + OPCODE_RET, + OPCODE_S16I, + OPCODE_S32I, + OPCODE_S8I, + OPCODE_SSR, + OPCODE_SSL, + OPCODE_SSA8L, + OPCODE_SSA8B, + OPCODE_SSAI, + OPCODE_SLL, + OPCODE_SRC, + OPCODE_SRL, + OPCODE_SRA, + OPCODE_SLLI, + OPCODE_SRAI, + OPCODE_SRLI, + OPCODE_MEMW, + OPCODE_EXTW, + OPCODE_ISYNC, + OPCODE_RSYNC, + OPCODE_ESYNC, + OPCODE_DSYNC, + OPCODE_RSIL, + OPCODE_RSR_LEND, + OPCODE_WSR_LEND, + OPCODE_XSR_LEND, + OPCODE_RSR_LCOUNT, + OPCODE_WSR_LCOUNT, + OPCODE_XSR_LCOUNT, + OPCODE_RSR_LBEG, + OPCODE_WSR_LBEG, + OPCODE_XSR_LBEG, + OPCODE_RSR_SAR, + OPCODE_WSR_SAR, + OPCODE_XSR_SAR, + OPCODE_RSR_LITBASE, + OPCODE_WSR_LITBASE, + OPCODE_XSR_LITBASE, + OPCODE_RSR_176, + OPCODE_WSR_176, + OPCODE_RSR_208, + OPCODE_RSR_PS, + OPCODE_WSR_PS, + OPCODE_XSR_PS, + OPCODE_RSR_EPC1, + OPCODE_WSR_EPC1, + OPCODE_XSR_EPC1, + OPCODE_RSR_EXCSAVE1, + OPCODE_WSR_EXCSAVE1, + OPCODE_XSR_EXCSAVE1, + OPCODE_RSR_EPC2, + OPCODE_WSR_EPC2, + OPCODE_XSR_EPC2, + OPCODE_RSR_EXCSAVE2, + OPCODE_WSR_EXCSAVE2, + OPCODE_XSR_EXCSAVE2, + OPCODE_RSR_EPC3, + OPCODE_WSR_EPC3, + OPCODE_XSR_EPC3, + OPCODE_RSR_EXCSAVE3, + OPCODE_WSR_EXCSAVE3, + OPCODE_XSR_EXCSAVE3, + OPCODE_RSR_EPC4, + OPCODE_WSR_EPC4, + OPCODE_XSR_EPC4, + OPCODE_RSR_EXCSAVE4, + OPCODE_WSR_EXCSAVE4, + OPCODE_XSR_EXCSAVE4, + OPCODE_RSR_EPC5, + OPCODE_WSR_EPC5, + OPCODE_XSR_EPC5, + OPCODE_RSR_EXCSAVE5, + OPCODE_WSR_EXCSAVE5, + OPCODE_XSR_EXCSAVE5, + OPCODE_RSR_EPC6, + OPCODE_WSR_EPC6, + OPCODE_XSR_EPC6, + OPCODE_RSR_EXCSAVE6, + OPCODE_WSR_EXCSAVE6, + OPCODE_XSR_EXCSAVE6, + OPCODE_RSR_EPS2, + OPCODE_WSR_EPS2, + OPCODE_XSR_EPS2, + OPCODE_RSR_EPS3, + OPCODE_WSR_EPS3, + OPCODE_XSR_EPS3, + OPCODE_RSR_EPS4, + OPCODE_WSR_EPS4, + OPCODE_XSR_EPS4, + OPCODE_RSR_EPS5, + OPCODE_WSR_EPS5, + OPCODE_XSR_EPS5, + OPCODE_RSR_EPS6, + OPCODE_WSR_EPS6, + OPCODE_XSR_EPS6, + OPCODE_RSR_EXCVADDR, + OPCODE_WSR_EXCVADDR, + OPCODE_XSR_EXCVADDR, + OPCODE_RSR_DEPC, + OPCODE_WSR_DEPC, + OPCODE_XSR_DEPC, + OPCODE_RSR_EXCCAUSE, + OPCODE_WSR_EXCCAUSE, + OPCODE_XSR_EXCCAUSE, + OPCODE_RSR_PRID, + OPCODE_RSR_VECBASE, + OPCODE_WSR_VECBASE, + OPCODE_XSR_VECBASE, + OPCODE_MUL16U, + OPCODE_MUL16S, + OPCODE_RFI, + OPCODE_WAITI, + OPCODE_RSR_INTERRUPT, + OPCODE_WSR_INTSET, + OPCODE_WSR_INTCLEAR, + OPCODE_RSR_INTENABLE, + OPCODE_WSR_INTENABLE, + OPCODE_XSR_INTENABLE, + OPCODE_BREAK, + OPCODE_BREAK_N, + OPCODE_RSR_DBREAKA0, + OPCODE_WSR_DBREAKA0, + OPCODE_XSR_DBREAKA0, + OPCODE_RSR_DBREAKC0, + OPCODE_WSR_DBREAKC0, + OPCODE_XSR_DBREAKC0, + OPCODE_RSR_DBREAKA1, + OPCODE_WSR_DBREAKA1, + OPCODE_XSR_DBREAKA1, + OPCODE_RSR_DBREAKC1, + OPCODE_WSR_DBREAKC1, + OPCODE_XSR_DBREAKC1, + OPCODE_RSR_IBREAKA0, + OPCODE_WSR_IBREAKA0, + OPCODE_XSR_IBREAKA0, + OPCODE_RSR_IBREAKA1, + OPCODE_WSR_IBREAKA1, + OPCODE_XSR_IBREAKA1, + OPCODE_RSR_IBREAKENABLE, + OPCODE_WSR_IBREAKENABLE, + OPCODE_XSR_IBREAKENABLE, + OPCODE_RSR_DEBUGCAUSE, + OPCODE_WSR_DEBUGCAUSE, + OPCODE_XSR_DEBUGCAUSE, + OPCODE_RSR_ICOUNT, + OPCODE_WSR_ICOUNT, + OPCODE_XSR_ICOUNT, + OPCODE_RSR_ICOUNTLEVEL, + OPCODE_WSR_ICOUNTLEVEL, + OPCODE_XSR_ICOUNTLEVEL, + OPCODE_RSR_DDR, + OPCODE_WSR_DDR, + OPCODE_XSR_DDR, + OPCODE_RFDO, + OPCODE_RFDD, + OPCODE_WSR_MMID, + OPCODE_ANDB, + OPCODE_ANDBC, + OPCODE_ORB, + OPCODE_ORBC, + OPCODE_XORB, + OPCODE_ANY4, + OPCODE_ALL4, + OPCODE_ANY8, + OPCODE_ALL8, + OPCODE_BF, + OPCODE_BT, + OPCODE_MOVF, + OPCODE_MOVT, + OPCODE_RSR_BR, + OPCODE_WSR_BR, + OPCODE_XSR_BR, + OPCODE_RSR_CCOUNT, + OPCODE_WSR_CCOUNT, + OPCODE_XSR_CCOUNT, + OPCODE_RSR_CCOMPARE0, + OPCODE_WSR_CCOMPARE0, + OPCODE_XSR_CCOMPARE0, + OPCODE_RSR_CCOMPARE1, + OPCODE_WSR_CCOMPARE1, + OPCODE_XSR_CCOMPARE1, + OPCODE_IPF, + OPCODE_IHI, + OPCODE_IPFL, + OPCODE_IHU, + OPCODE_IIU, + OPCODE_III, + OPCODE_LICT, + OPCODE_LICW, + OPCODE_SICT, + OPCODE_SICW, + OPCODE_DHWB, + OPCODE_DHWBI, + OPCODE_DIWB, + OPCODE_DIWBI, + OPCODE_DHI, + OPCODE_DII, + OPCODE_DPFR, + OPCODE_DPFW, + OPCODE_DPFRO, + OPCODE_DPFWO, + OPCODE_DPFL, + OPCODE_DHU, + OPCODE_DIU, + OPCODE_SDCT, + OPCODE_LDCT, + OPCODE_IDTLB, + OPCODE_PDTLB, + OPCODE_RDTLB0, + OPCODE_RDTLB1, + OPCODE_WDTLB, + OPCODE_IITLB, + OPCODE_PITLB, + OPCODE_RITLB0, + OPCODE_RITLB1, + OPCODE_WITLB, + OPCODE_RSR_CPENABLE, + OPCODE_WSR_CPENABLE, + OPCODE_XSR_CPENABLE, + OPCODE_CLAMPS, + OPCODE_MIN, + OPCODE_MAX, + OPCODE_MINU, + OPCODE_MAXU, + OPCODE_NSA, + OPCODE_NSAU, + OPCODE_SEXT, + OPCODE_L32AI, + OPCODE_S32RI, + OPCODE_S32C1I, + OPCODE_RSR_SCOMPARE1, + OPCODE_WSR_SCOMPARE1, + OPCODE_XSR_SCOMPARE1, + OPCODE_RSR_ATOMCTL, + OPCODE_WSR_ATOMCTL, + OPCODE_XSR_ATOMCTL, + OPCODE_RER, + OPCODE_WER, + OPCODE_RUR_FCR, + OPCODE_WUR_FCR, + OPCODE_RUR_FSR, + OPCODE_WUR_FSR, + OPCODE_ADD_S, + OPCODE_SUB_S, + OPCODE_MUL_S, + OPCODE_MADD_S, + OPCODE_MSUB_S, + OPCODE_MOVF_S, + OPCODE_MOVT_S, + OPCODE_MOVEQZ_S, + OPCODE_MOVNEZ_S, + OPCODE_MOVLTZ_S, + OPCODE_MOVGEZ_S, + OPCODE_ABS_S, + OPCODE_MOV_S, + OPCODE_NEG_S, + OPCODE_UN_S, + OPCODE_OEQ_S, + OPCODE_UEQ_S, + OPCODE_OLT_S, + OPCODE_ULT_S, + OPCODE_OLE_S, + OPCODE_ULE_S, + OPCODE_FLOAT_S, + OPCODE_UFLOAT_S, + OPCODE_ROUND_S, + OPCODE_CEIL_S, + OPCODE_FLOOR_S, + OPCODE_TRUNC_S, + OPCODE_UTRUNC_S, + OPCODE_RFR, + OPCODE_WFR, + OPCODE_LSI, + OPCODE_LSIU, + OPCODE_LSX, + OPCODE_LSXU, + OPCODE_SSI, + OPCODE_SSIU, + OPCODE_SSX, + OPCODE_SSXU, + OPCODE_GET_ARGMAX, + OPCODE_GET_HSAR, + OPCODE_GET_HSAR2SAR, + OPCODE_GET_INTERP_EXT_N, + OPCODE_GET_INTERP_EXT_L, + OPCODE_GET_LLR_BUF, + OPCODE_GET_LLR_POS, + OPCODE_GET_MAX, + OPCODE_GET_NCO, + OPCODE_GET_PERM_REG, + OPCODE_GET_PHASOR_N, + OPCODE_GET_PHASOR_OFFSET, + OPCODE_GET_SAR, + OPCODE_GET_SCALE_REG, + OPCODE_GET_SMOD_BUF, + OPCODE_GET_SMOD_OFFSET_TABLE, + OPCODE_GET_SMOD_POS, + OPCODE_GET_SOV, + OPCODE_GET_WGHT, + OPCODE_SET_ARGMAX, + OPCODE_SET_EXT_REGS, + OPCODE_SET_HSAR, + OPCODE_SET_LLR_BUF, + OPCODE_SET_LLR_POS, + OPCODE_SET_MAX, + OPCODE_SET_NCO, + OPCODE_SET_PERM_REG, + OPCODE_SET_PHASOR_N, + OPCODE_SET_PHASOR_OFFSET, + OPCODE_SET_SAR, + OPCODE_SET_SCALE_REG, + OPCODE_SET_SMOD_BUF, + OPCODE_SET_SMOD_OFFSET_TABLE, + OPCODE_SET_SMOD_POS, + OPCODE_SET_SOV, + OPCODE_SET_WGHT, + OPCODE_LAC2X32, + OPCODE_LAC2X64_0, + OPCODE_LAC2X64_1, + OPCODE_LAC2X64_2, + OPCODE_LAC2X64_3, + OPCODE_LAC32_R, + OPCODE_LAC_IH, + OPCODE_LAC_IL, + OPCODE_LAC_RH, + OPCODE_LAC_RL, + OPCODE_LCM, + OPCODE_LCM_PINC, + OPCODE_LCM_PINC_X, + OPCODE_LCM_U, + OPCODE_LCM_X, + OPCODE_LCM_XU, + OPCODE_LP, + OPCODE_LP_X, + OPCODE_LQ, + OPCODE_LQ_X, + OPCODE_LUT0, + OPCODE_LUT1, + OPCODE_LUT2, + OPCODE_LUT3, + OPCODE_SAC2X32, + OPCODE_SAC2X64_0, + OPCODE_SAC2X64_1, + OPCODE_SAC2X64_2, + OPCODE_SAC2X64_3, + OPCODE_SAC32_R, + OPCODE_SAC_IH, + OPCODE_SAC_IL, + OPCODE_SAC_RH, + OPCODE_SAC_RL, + OPCODE_SCM, + OPCODE_SCM_PINC, + OPCODE_SCM_PINC_X, + OPCODE_SCM_U, + OPCODE_SCM_X, + OPCODE_SCM_XU, + OPCODE_STORE_P, + OPCODE_STORE_Q, + OPCODE_AR2CM_DUP, + OPCODE_AR2CM_LN, + OPCODE_AR2CM_LN_I, + OPCODE_AR2CM_LN_R, + OPCODE_AR2PQ_LN, + OPCODE_AR2SAR_DUP, + OPCODE_CLRAC, + OPCODE_CLRCM, + OPCODE_CM2AR_LN, + OPCODE_CM2AR_LN_I, + OPCODE_CM2AR_LN_R, + OPCODE_COMB_AR, + OPCODE_CONJ, + OPCODE_MOV2AC32_I, + OPCODE_MOV2AC32_R, + OPCODE_MOV2CM2PQ, + OPCODE_MOVAC, + OPCODE_MOVAC_I, + OPCODE_MOVAC_I2R, + OPCODE_MOVAC_R, + OPCODE_MOVAC_R2I, + OPCODE_MOVAR2, + OPCODE_MOVCM, + OPCODE_MOVCM2PQ, + OPCODE_MOVCND_0, + OPCODE_MOVCND_1, + OPCODE_MOVCND_2, + OPCODE_MOVCND_3, + OPCODE_MOVCND_4, + OPCODE_MOVCND_5, + OPCODE_MOVCND_6, + OPCODE_MOVCND_7, + OPCODE_MOVCND8_0, + OPCODE_MOVCND8_1, + OPCODE_MOVCND8_2, + OPCODE_MOVCND8_3, + OPCODE_MOVCND8_4, + OPCODE_MOVCND8_5, + OPCODE_MOVCND8_6, + OPCODE_MOVCND8_7, + OPCODE_MOV_I, + OPCODE_MOVPQ2PQ, + OPCODE_MOV_R, + OPCODE_NEGCM, + OPCODE_POP16LLR_1, + OPCODE_PQ2CM, + OPCODE_SWAPAC_R, + OPCODE_SWAPAC_RI, + OPCODE_SWAPB, + OPCODE_ADD2AC, + OPCODE_ADDAC, + OPCODE_CDOT, + OPCODE_CDOTAC, + OPCODE_CDOTACS, + OPCODE_CMAC, + OPCODE_CMACS, + OPCODE_CMPY, + OPCODE_CMPY2CM, + OPCODE_CMPY2PQ, + OPCODE_CMPYS, + OPCODE_CMPYXP2PQ, + OPCODE_COMB32, + OPCODE_DOT, + OPCODE_DOTAC, + OPCODE_DOTACS, + OPCODE_LIN_INT, + OPCODE_LLRPRE1, + OPCODE_LLRPRE2, + OPCODE_MAC, + OPCODE_MAC8, + OPCODE_MACD8, + OPCODE_MACPQXP_0, + OPCODE_MACPQXP_1, + OPCODE_MACPQXP_2, + OPCODE_MACPQXP_3, + OPCODE_MACS, + OPCODE_MACXP2_0, + OPCODE_MACXP2_1, + OPCODE_MACXP_0, + OPCODE_MACXP_1, + OPCODE_MACXP_2, + OPCODE_MACXP_3, + OPCODE_MOV2AC, + OPCODE_MPY, + OPCODE_MPY2CM, + OPCODE_MPY2PQ, + OPCODE_MPY8, + OPCODE_MPYADD8_2CM, + OPCODE_MPYD8, + OPCODE_MPYPQXP_0, + OPCODE_MPYPQXP_1, + OPCODE_MPYPQXP_2, + OPCODE_MPYPQXP_3, + OPCODE_MPYS, + OPCODE_MPYXP2PQ, + OPCODE_MPYXP2_0, + OPCODE_MPYXP2_1, + OPCODE_MPYXP_0, + OPCODE_MPYXP_1, + OPCODE_MPYXP_2, + OPCODE_MPYXP_3, + OPCODE_NORMACD, + OPCODE_NORMACPQ_I, + OPCODE_NORMACPQ_R, + OPCODE_NORMD, + OPCODE_NORMPYPQ_I, + OPCODE_NORMPYPQ_R, + OPCODE_RCMAC, + OPCODE_RCMPY, + OPCODE_RCMPY2CM, + OPCODE_RFIR, + OPCODE_RFIRA, + OPCODE_RFIRD, + OPCODE_RFIRDA, + OPCODE_RMAC, + OPCODE_RMPY, + OPCODE_RMPY2CM, + OPCODE_SMOD_ALIGN, + OPCODE_SMOD_SCR, + OPCODE_SUB2AC, + OPCODE_WGHT32, + OPCODE_CLRTIEP, + OPCODE_EXT_2FIFO_0, + OPCODE_EXT_2FIFO_1, + OPCODE_EXT_2FIFO_2, + OPCODE_EXT_2FIFO_3, + OPCODE_EXT_R2FIFO_0, + OPCODE_EXT_R2FIFO_1, + OPCODE_EXT_R2FIFO_2, + OPCODE_EXT_R2FIFO_3, + OPCODE_LUT, + OPCODE_LUT_AR, + OPCODE_LUT_IEXT, + OPCODE_LUT_PHASOR, + OPCODE_LUT_REXT, + OPCODE_LUT_WRITE, + OPCODE_MOVEQ128_0, + OPCODE_MOVEQ128_1, + OPCODE_MOVEQ128_2, + OPCODE_MOVEQ128_3, + OPCODE_MOVEQ128_4, + OPCODE_MOVEQ128_5, + OPCODE_MOVEQ32_0, + OPCODE_MOVEQ32_1, + OPCODE_MOVEQ32_2, + OPCODE_MOVEQ32_3, + OPCODE_NCO_UPDATE, + OPCODE_POP128_0, + OPCODE_POP128_1, + OPCODE_POP128_2, + OPCODE_POP128_3, + OPCODE_POP128_4, + OPCODE_POP128_5, + OPCODE_POP128_2CMPQ_0, + OPCODE_POP128_2CMPQ_1, + OPCODE_POP128_2CMPQ_2, + OPCODE_POP128_2CMPQ_3, + OPCODE_POP128_2M_0, + OPCODE_POP128_2M_1, + OPCODE_POP128_2M_2, + OPCODE_POP128_2M_3, + OPCODE_POP128_2PQ_0, + OPCODE_POP128_2PQ_1, + OPCODE_POP128_2PQ_2, + OPCODE_POP128_2PQ_3, + OPCODE_POP128_2PQ_4, + OPCODE_POP128_2PQ_5, + OPCODE_POP2X128_2PQ_01, + OPCODE_POP2X128_2PQ_03, + OPCODE_POP2X128_2PQ_21, + OPCODE_POP2X128_2PQ_23, + OPCODE_POP32_0, + OPCODE_POP32_1, + OPCODE_POP32_2, + OPCODE_POP32_3, + OPCODE_PUSH128, + OPCODE_PUSH128_M, + OPCODE_PUSH128_PQ, + OPCODE_PUSH2X128_PQ, + OPCODE_PUSH32, + OPCODE_QREADY, + OPCODE_RDTIEP, + OPCODE_SETTIEP, + OPCODE_SMOD_LUT, + OPCODE_WRTBSIGQ, + OPCODE_WRTBSIGQM, + OPCODE_WRTIEP, + OPCODE_WRTSIGQ, + OPCODE_ABS8, + OPCODE_ADD16, + OPCODE_ADD32, + OPCODE_ADDAC_I2R, + OPCODE_ADDAC_R2I, + OPCODE_ADDAR2, + OPCODE_ADDCM, + OPCODE_ADDWRP, + OPCODE_AND128, + OPCODE_ARGMAX8, + OPCODE_ASL, + OPCODE_ASL32, + OPCODE_ASLACM, + OPCODE_ASLM, + OPCODE_ASLM32, + OPCODE_ASR, + OPCODE_ASR32, + OPCODE_ASRAC, + OPCODE_ASRM, + OPCODE_BITFEXT, + OPCODE_BITFINS, + OPCODE_CLB_C, + OPCODE_CLB_R, + OPCODE_CMP8, + OPCODE_CMP_I, + OPCODE_CMP_R, + OPCODE_EXT, + OPCODE_EXT_R, + OPCODE_EXT32_I, + OPCODE_EXT32_R, + OPCODE_EXTUI4, + OPCODE_LSLM, + OPCODE_LSRM, + OPCODE_MAX8, + OPCODE_MEAN, + OPCODE_MEAN32, + OPCODE_MIN8, + OPCODE_MINCLB_C, + OPCODE_MINCLB_R, + OPCODE_NOT128, + OPCODE_OR128, + OPCODE_PERM, + OPCODE_REDAC, + OPCODE_REDAC2, + OPCODE_REDAC4, + OPCODE_REDACS, + OPCODE_SMINCLB_C, + OPCODE_SMINCLB_R, + OPCODE_STSWAPBM, + OPCODE_STSWAPBMU, + OPCODE_SUB32, + OPCODE_SUBAC_I2R, + OPCODE_SUBAC_R2I, + OPCODE_SUBARX, + OPCODE_SUBCM, + OPCODE_SUBMEAN, + OPCODE_SUBWRP, + OPCODE_TRANS, + OPCODE_XOR128, + OPCODE_RUR_EXPSTATE, + OPCODE_WUR_EXPSTATE, + OPCODE_RUR_SOV, + OPCODE_WUR_SOV, + OPCODE_RUR_SAT_MODE, + OPCODE_WUR_SAT_MODE, + OPCODE_RUR_SAR0, + OPCODE_WUR_SAR0, + OPCODE_RUR_SAR1, + OPCODE_WUR_SAR1, + OPCODE_RUR_SAR2, + OPCODE_WUR_SAR2, + OPCODE_RUR_SAR3, + OPCODE_WUR_SAR3, + OPCODE_RUR_HSAR0, + OPCODE_WUR_HSAR0, + OPCODE_RUR_HSAR1, + OPCODE_WUR_HSAR1, + OPCODE_RUR_HSAR2, + OPCODE_WUR_HSAR2, + OPCODE_RUR_HSAR3, + OPCODE_WUR_HSAR3, + OPCODE_RUR_MAX_REG_0, + OPCODE_WUR_MAX_REG_0, + OPCODE_RUR_MAX_REG_1, + OPCODE_WUR_MAX_REG_1, + OPCODE_RUR_MAX_REG_2, + OPCODE_WUR_MAX_REG_2, + OPCODE_RUR_MAX_REG_3, + OPCODE_WUR_MAX_REG_3, + OPCODE_RUR_ARG_MAX_REG_0, + OPCODE_WUR_ARG_MAX_REG_0, + OPCODE_RUR_ARG_MAX_REG_1, + OPCODE_WUR_ARG_MAX_REG_1, + OPCODE_RUR_ARG_MAX_REG_2, + OPCODE_WUR_ARG_MAX_REG_2, + OPCODE_RUR_ARG_MAX_REG_3, + OPCODE_WUR_ARG_MAX_REG_3, + OPCODE_RUR_NCO_COUNTER_0, + OPCODE_WUR_NCO_COUNTER_0, + OPCODE_RUR_NCO_COUNTER_1, + OPCODE_WUR_NCO_COUNTER_1, + OPCODE_RUR_NCO_COUNTER_2, + OPCODE_WUR_NCO_COUNTER_2, + OPCODE_RUR_NCO_COUNTER_3, + OPCODE_WUR_NCO_COUNTER_3, + OPCODE_RUR_INTERP_EXT_N, + OPCODE_WUR_INTERP_EXT_N, + OPCODE_RUR_INTERP_EXT_L, + OPCODE_WUR_INTERP_EXT_L, + OPCODE_RUR_LLR_BUF_0, + OPCODE_WUR_LLR_BUF_0, + OPCODE_RUR_LLR_BUF_1, + OPCODE_WUR_LLR_BUF_1, + OPCODE_RUR_LLR_BUF_2, + OPCODE_WUR_LLR_BUF_2, + OPCODE_RUR_LLR_BUF_3, + OPCODE_WUR_LLR_BUF_3, + OPCODE_RUR_LLR_BUF_4, + OPCODE_WUR_LLR_BUF_4, + OPCODE_RUR_LLR_BUF_5, + OPCODE_WUR_LLR_BUF_5, + OPCODE_RUR_LLR_BUF_6, + OPCODE_WUR_LLR_BUF_6, + OPCODE_RUR_LLR_BUF_7, + OPCODE_WUR_LLR_BUF_7, + OPCODE_RUR_LLR_BUF_8, + OPCODE_WUR_LLR_BUF_8, + OPCODE_RUR_LLR_BUF_9, + OPCODE_WUR_LLR_BUF_9, + OPCODE_RUR_LLR_BUF_10, + OPCODE_WUR_LLR_BUF_10, + OPCODE_RUR_LLR_BUF_11, + OPCODE_WUR_LLR_BUF_11, + OPCODE_RUR_LLR_BUF_12, + OPCODE_WUR_LLR_BUF_12, + OPCODE_RUR_LLR_BUF_13, + OPCODE_WUR_LLR_BUF_13, + OPCODE_RUR_LLR_BUF_14, + OPCODE_WUR_LLR_BUF_14, + OPCODE_RUR_LLR_BUF_15, + OPCODE_WUR_LLR_BUF_15, + OPCODE_RUR_LLR_BUF_16, + OPCODE_WUR_LLR_BUF_16, + OPCODE_RUR_LLR_BUF_17, + OPCODE_WUR_LLR_BUF_17, + OPCODE_RUR_LLR_BUF_18, + OPCODE_WUR_LLR_BUF_18, + OPCODE_RUR_LLR_BUF_19, + OPCODE_WUR_LLR_BUF_19, + OPCODE_RUR_LLR_BUF_20, + OPCODE_WUR_LLR_BUF_20, + OPCODE_RUR_LLR_BUF_21, + OPCODE_WUR_LLR_BUF_21, + OPCODE_RUR_LLR_BUF_22, + OPCODE_WUR_LLR_BUF_22, + OPCODE_RUR_LLR_BUF_23, + OPCODE_WUR_LLR_BUF_23, + OPCODE_RUR_SMOD_BUF_0, + OPCODE_WUR_SMOD_BUF_0, + OPCODE_RUR_SMOD_BUF_1, + OPCODE_WUR_SMOD_BUF_1, + OPCODE_RUR_SMOD_BUF_2, + OPCODE_WUR_SMOD_BUF_2, + OPCODE_RUR_SMOD_BUF_3, + OPCODE_WUR_SMOD_BUF_3, + OPCODE_RUR_SMOD_BUF_4, + OPCODE_WUR_SMOD_BUF_4, + OPCODE_RUR_SMOD_BUF_5, + OPCODE_WUR_SMOD_BUF_5, + OPCODE_RUR_SMOD_BUF_6, + OPCODE_WUR_SMOD_BUF_6, + OPCODE_RUR_SMOD_BUF_7, + OPCODE_WUR_SMOD_BUF_7, + OPCODE_RUR_WEIGHT_REG, + OPCODE_WUR_WEIGHT_REG, + OPCODE_RUR_SCALE_REG, + OPCODE_WUR_SCALE_REG, + OPCODE_RUR_LLR_POS, + OPCODE_WUR_LLR_POS, + OPCODE_RUR_SMOD_POS, + OPCODE_WUR_SMOD_POS, + OPCODE_RUR_PERM_REG, + OPCODE_WUR_PERM_REG, + OPCODE_RUR_SMOD_OFFSET_TABLE_0, + OPCODE_WUR_SMOD_OFFSET_TABLE_0, + OPCODE_RUR_SMOD_OFFSET_TABLE_1, + OPCODE_WUR_SMOD_OFFSET_TABLE_1, + OPCODE_RUR_SMOD_OFFSET_TABLE_2, + OPCODE_WUR_SMOD_OFFSET_TABLE_2, + OPCODE_RUR_SMOD_OFFSET_TABLE_3, + OPCODE_WUR_SMOD_OFFSET_TABLE_3, + OPCODE_RUR_PHASOR_N, + OPCODE_WUR_PHASOR_N, + OPCODE_RUR_PHASOR_OFFSET, + OPCODE_WUR_PHASOR_OFFSET +}; + + +/* Slot-specific opcode decode functions. */ + +static int +Slot_inst_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2021_Slot_inst_get (insn)) + { + case 3: + if (Field_sa4_Slot_inst_get (insn) == 0 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 4 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LCM_PINC_X; + if (Field_sa4_Slot_inst_get (insn) == 1 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 4 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SCM_PINC_X; + break; + case 4: + if (Field_sa4_Slot_inst_get (insn) == 0 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 4 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LCM_X; + if (Field_sa4_Slot_inst_get (insn) == 1 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 4 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SCM_X; + break; + case 5: + if (Field_sa4_Slot_inst_get (insn) == 0 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 4 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LCM_XU; + if (Field_sa4_Slot_inst_get (insn) == 1 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 4 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SCM_XU; + break; + case 6: + if (Field_sa4_Slot_inst_get (insn) == 0 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 4 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LP_X; + break; + case 7: + if (Field_sa4_Slot_inst_get (insn) == 0 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 4 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LQ_X; + break; + } + if (Field_dsp340050b49a6c_fld2035_Slot_inst_get (insn) == 2 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2047_Slot_inst_get (insn) == 0) + return OPCODE_LQ; + switch (Field_dsp340050b49a6c_fld2037_Slot_inst_get (insn)) + { + case 0: + if (Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LCM_PINC; + break; + case 1: + if (Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LCM_U; + break; + case 2: + if (Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LP; + break; + } + switch (Field_dsp340050b49a6c_fld2048_Slot_inst_get (insn)) + { + case 0: + if (Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LAC2X32; + break; + case 1: + if (Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LAC32_R; + break; + } + if (Field_dsp340050b49a6c_fld2082inst_Slot_inst_get (insn) == 0 && + Field_r2_Slot_inst_get (insn) == 1 && + Field_bbi4_Slot_inst_get (insn) == 0 && + Field_op0_Slot_inst_get (insn) == 3) + return OPCODE_LAC_IH; + if (Field_dsp340050b49a6c_fld2083inst_Slot_inst_get (insn) == 1 && + Field_r2_Slot_inst_get (insn) == 1 && + Field_bbi4_Slot_inst_get (insn) == 0 && + Field_op0_Slot_inst_get (insn) == 3) + return OPCODE_LAC_IL; + if (Field_dsp340050b49a6c_fld2084inst_Slot_inst_get (insn) == 2 && + Field_r2_Slot_inst_get (insn) == 1 && + Field_bbi4_Slot_inst_get (insn) == 0 && + Field_op0_Slot_inst_get (insn) == 3) + return OPCODE_LAC_RH; + switch (Field_dsp340050b49a6c_fld2085inst_Slot_inst_get (insn)) + { + case 3: + if (Field_r2_Slot_inst_get (insn) == 1 && + Field_bbi4_Slot_inst_get (insn) == 0 && + Field_op0_Slot_inst_get (insn) == 3) + return OPCODE_LAC2X64_1; + break; + case 19: + if (Field_r2_Slot_inst_get (insn) == 1 && + Field_bbi4_Slot_inst_get (insn) == 0 && + Field_op0_Slot_inst_get (insn) == 3) + return OPCODE_LAC2X64_2; + break; + } + if (Field_dsp340050b49a6c_fld2086inst_Slot_inst_get (insn) == 2 && + Field_r2_Slot_inst_get (insn) == 1 && + Field_bbi4_Slot_inst_get (insn) == 0 && + Field_op0_Slot_inst_get (insn) == 3 && + Field_dsp340050b49a6c_fld3634_Slot_inst_get (insn) == 0) + return OPCODE_LAC_RL; + if (Field_dsp340050b49a6c_fld2088inst_Slot_inst_get (insn) == 3 && + Field_r2_Slot_inst_get (insn) == 1 && + Field_bbi4_Slot_inst_get (insn) == 0 && + Field_op0_Slot_inst_get (insn) == 3 && + Field_dsp340050b49a6c_fld3633inst_Slot_inst_get (insn) == 0) + return OPCODE_LAC2X64_3; + if (Field_dsp340050b49a6c_fld2089inst_Slot_inst_get (insn) == 1 && + Field_r2_Slot_inst_get (insn) == 1 && + Field_bbi4_Slot_inst_get (insn) == 0 && + Field_op0_Slot_inst_get (insn) == 3 && + Field_dsp340050b49a6c_fld3631inst_Slot_inst_get (insn) == 0) + return OPCODE_LAC2X64_0; + if (Field_dsp340050b49a6c_fld2090inst_Slot_inst_get (insn) == 1 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_PQ2CM; + if (Field_dsp340050b49a6c_fld2091inst_Slot_inst_get (insn) == 10 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_AR2CM_DUP; + if (Field_dsp340050b49a6c_fld2092inst_Slot_inst_get (insn) == 88 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_CLRTIEP; + if (Field_dsp340050b49a6c_fld2094inst_Slot_inst_get (insn) == 89 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_SMOD_BUF; + if (Field_dsp340050b49a6c_fld2095inst_Slot_inst_get (insn) == 90 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SETTIEP; + if (Field_dsp340050b49a6c_fld2096inst_Slot_inst_get (insn) == 182 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_CLRCM; + if (Field_dsp340050b49a6c_fld2098inst_Slot_inst_get (insn) == 183 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_ARGMAX; + if (Field_dsp340050b49a6c_fld2099inst_Slot_inst_get (insn) == 92 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_WRTBSIGQM; + if (Field_dsp340050b49a6c_fld2100inst_Slot_inst_get (insn) == 186 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_HSAR; + if (Field_dsp340050b49a6c_fld2101inst_Slot_inst_get (insn) == 187 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_MAX; + if (Field_dsp340050b49a6c_fld2102inst_Slot_inst_get (insn) == 188 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_HSAR2SAR; + if (Field_dsp340050b49a6c_fld2103inst_Slot_inst_get (insn) == 189 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_NCO; + if (Field_dsp340050b49a6c_fld2104inst_Slot_inst_get (insn) == 190 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_SAR; + if (Field_dsp340050b49a6c_fld2105inst_Slot_inst_get (insn) == 191 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_SMOD_OFFSET_TABLE; + if (Field_dsp340050b49a6c_fld2106inst_Slot_inst_get (insn) == 18 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_PUSH128_PQ; + if (Field_dsp340050b49a6c_fld2107inst_Slot_inst_get (insn) == 152 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP128_2PQ_0; + if (Field_dsp340050b49a6c_fld2108inst_Slot_inst_get (insn) == 153 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP128_2PQ_2; + if (Field_dsp340050b49a6c_fld2109inst_Slot_inst_get (insn) == 154 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP128_2PQ_3; + if (Field_dsp340050b49a6c_fld2110inst_Slot_inst_get (insn) == 155 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP128_2PQ_5; + if (Field_dsp340050b49a6c_fld2111inst_Slot_inst_get (insn) == 156 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP128_2PQ_4; + if (Field_dsp340050b49a6c_fld2112inst_Slot_inst_get (insn) == 301 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SET_LLR_POS; + if (Field_dsp340050b49a6c_fld2113inst_Slot_inst_get (insn) == 317 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SET_PHASOR_OFFSET; + if (Field_dsp340050b49a6c_fld2114inst_Slot_inst_get (insn) == 302 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SET_PHASOR_N; + if (Field_dsp340050b49a6c_fld2115inst_Slot_inst_get (insn) == 303 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SET_SCALE_REG; + if (Field_dsp340050b49a6c_fld2116inst_Slot_inst_get (insn) == 318 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SET_SMOD_POS; + if (Field_dsp340050b49a6c_fld2117inst_Slot_inst_get (insn) == 319 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SET_SOV; + if (Field_dsp340050b49a6c_fld2118inst_Slot_inst_get (insn) == 208 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP128_2PQ_1; + if (Field_dsp340050b49a6c_fld2119inst_Slot_inst_get (insn) == 417 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SET_WGHT; + if (Field_dsp340050b49a6c_fld2120inst_Slot_inst_get (insn) == 6913 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOVEQ128_0; + if (Field_dsp340050b49a6c_fld2122inst_Slot_inst_get (insn) == 6929 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOVEQ128_1; + if (Field_dsp340050b49a6c_fld2123inst_Slot_inst_get (insn) == 6945 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOVEQ128_2; + if (Field_dsp340050b49a6c_fld2124inst_Slot_inst_get (insn) == 6961 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOVEQ128_5; + if (Field_dsp340050b49a6c_fld2125inst_Slot_inst_get (insn) == 6977 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOVEQ128_3; + if (Field_dsp340050b49a6c_fld2126inst_Slot_inst_get (insn) == 6993 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOVEQ32_0; + if (Field_dsp340050b49a6c_fld2127inst_Slot_inst_get (insn) == 7009 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOVEQ32_1; + if (Field_dsp340050b49a6c_fld2128inst_Slot_inst_get (insn) == 7025 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOVEQ32_2; + if (Field_dsp340050b49a6c_fld2129inst_Slot_inst_get (insn) == 1761 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2035_Slot_inst_get (insn) == 0) + return OPCODE_MOVEQ128_4; + if (Field_dsp340050b49a6c_fld2131inst_Slot_inst_get (insn) == 1777 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2035_Slot_inst_get (insn) == 0) + return OPCODE_MOVEQ32_3; + if (Field_dsp340050b49a6c_fld2132inst_Slot_inst_get (insn) == 105 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3659inst_Slot_inst_get (insn) == 0) + return OPCODE_WRTBSIGQ; + if (Field_dsp340050b49a6c_fld2133inst_Slot_inst_get (insn) == 53 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3660inst_Slot_inst_get (insn) == 0) + return OPCODE_WRTSIGQ; + if (Field_dsp340050b49a6c_fld2134inst_Slot_inst_get (insn) == 53 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2050_Slot_inst_get (insn) == 0) + return OPCODE_CLRAC; + if (Field_dsp340050b49a6c_fld2136inst_Slot_inst_get (insn) == 55 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2050_Slot_inst_get (insn) == 0) + return OPCODE_POP16LLR_1; + if (Field_dsp340050b49a6c_fld2137inst_Slot_inst_get (insn) == 34 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_WRTIEP; + if (Field_dsp340050b49a6c_fld2138inst_Slot_inst_get (insn) == 560 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld2139inst_Slot_inst_get (insn) == 561 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld2140inst_Slot_inst_get (insn) == 562 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP128_4; + if (Field_dsp340050b49a6c_fld2141inst_Slot_inst_get (insn) == 563 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP2X128_2PQ_03; + if (Field_dsp340050b49a6c_fld2142inst_Slot_inst_get (insn) == 564 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld2143inst_Slot_inst_get (insn) == 565 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP2X128_2PQ_21; + if (Field_dsp340050b49a6c_fld2144inst_Slot_inst_get (insn) == 283 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2047_Slot_inst_get (insn) == 0) + return OPCODE_POP2X128_2PQ_23; + if (Field_dsp340050b49a6c_fld2145inst_Slot_inst_get (insn) == 71 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2037_Slot_inst_get (insn) == 0) + return OPCODE_POP2X128_2PQ_01; + if (Field_dsp340050b49a6c_fld2146inst_Slot_inst_get (insn) == 21 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3649inst_Slot_inst_get (insn) == 0) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld2147inst_Slot_inst_get (insn) == 13 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3650inst_Slot_inst_get (insn) == 0) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld2149inst_Slot_inst_get (insn) == 5 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3627inst_Slot_inst_get (insn) == 0) + return OPCODE_GET_LLR_BUF; + if (Field_dsp340050b49a6c_fld2151inst_Slot_inst_get (insn) == 5 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3657inst_Slot_inst_get (insn) == 0) + return OPCODE_PUSH2X128_PQ; + if (Field_dsp340050b49a6c_fld2153inst_Slot_inst_get (insn) == 1 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3635inst_Slot_inst_get (insn) == 0) + return OPCODE_AR2CM_LN; + if (Field_dsp340050b49a6c_fld2154inst_Slot_inst_get (insn) == 3 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3636inst_Slot_inst_get (insn) == 0) + return OPCODE_AR2CM_LN_I; + if (Field_dsp340050b49a6c_fld2155inst_Slot_inst_get (insn) == 3 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3637inst_Slot_inst_get (insn) == 0) + return OPCODE_AR2CM_LN_R; + if (Field_dsp340050b49a6c_fld2156inst_Slot_inst_get (insn) == 3 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LCM; + if (Field_dsp340050b49a6c_fld2157inst_Slot_inst_get (insn) == 19 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_CONJ; + if (Field_dsp340050b49a6c_fld2158inst_Slot_inst_get (insn) == 27 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOVCM; + if (Field_dsp340050b49a6c_fld2159inst_Slot_inst_get (insn) == 51 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOV_I; + if (Field_dsp340050b49a6c_fld2160inst_Slot_inst_get (insn) == 59 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SET_EXT_REGS; + if (Field_dsp340050b49a6c_fld2161inst_Slot_inst_get (insn) == 83 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOV_R; + if (Field_dsp340050b49a6c_fld2162inst_Slot_inst_get (insn) == 171 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_ASRAC; + if (Field_dsp340050b49a6c_fld2163inst_Slot_inst_get (insn) == 187 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_CLB_R; + if (Field_dsp340050b49a6c_fld2164inst_Slot_inst_get (insn) == 227 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_CLB_C; + if (Field_dsp340050b49a6c_fld2165inst_Slot_inst_get (insn) == 235 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MINCLB_C; + if (Field_dsp340050b49a6c_fld2166inst_Slot_inst_get (insn) == 243 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MINCLB_R; + if (Field_dsp340050b49a6c_fld2167inst_Slot_inst_get (insn) == 251 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SMINCLB_C; + if (Field_dsp340050b49a6c_fld2168inst_Slot_inst_get (insn) == 147 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_NEGCM; + if (Field_dsp340050b49a6c_fld2169inst_Slot_inst_get (insn) == 310 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_PUSH128; + if (Field_dsp340050b49a6c_fld2171inst_Slot_inst_get (insn) == 599 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOVAC; + if (Field_dsp340050b49a6c_fld2172inst_Slot_inst_get (insn) == 631 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOVAC_I2R; + if (Field_dsp340050b49a6c_fld2173inst_Slot_inst_get (insn) == 358 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SET_LLR_BUF; + if (Field_dsp340050b49a6c_fld2174inst_Slot_inst_get (insn) == 711 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOVAC_R2I; + if (Field_dsp340050b49a6c_fld2175inst_Slot_inst_get (insn) == 5944 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_ADDAC_I2R; + if (Field_dsp340050b49a6c_fld2177inst_Slot_inst_get (insn) == 5945 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_ADDAC_R2I; + if (Field_dsp340050b49a6c_fld2178inst_Slot_inst_get (insn) == 5946 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_REDAC; + if (Field_dsp340050b49a6c_fld2179inst_Slot_inst_get (insn) == 5947 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_REDAC4; + if (Field_dsp340050b49a6c_fld2180inst_Slot_inst_get (insn) == 5948 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_REDAC2; + if (Field_dsp340050b49a6c_fld2181inst_Slot_inst_get (insn) == 5949 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_REDACS; + if (Field_dsp340050b49a6c_fld2182inst_Slot_inst_get (insn) == 5950 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SUBAC_I2R; + if (Field_dsp340050b49a6c_fld2183inst_Slot_inst_get (insn) == 5951 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SUBAC_R2I; + if (Field_dsp340050b49a6c_fld2184inst_Slot_inst_get (insn) == 374 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3642inst_Slot_inst_get (insn) == 0) + return OPCODE_SWAPAC_RI; + if (Field_dsp340050b49a6c_fld2185inst_Slot_inst_get (insn) == 3000 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_INTERP_EXT_L; + if (Field_dsp340050b49a6c_fld2186inst_Slot_inst_get (insn) == 3001 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_INTERP_EXT_N; + if (Field_dsp340050b49a6c_fld2187inst_Slot_inst_get (insn) == 3002 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_LLR_POS; + if (Field_dsp340050b49a6c_fld2188inst_Slot_inst_get (insn) == 3003 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_PHASOR_OFFSET; + if (Field_dsp340050b49a6c_fld2189inst_Slot_inst_get (insn) == 3004 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_PHASOR_N; + if (Field_dsp340050b49a6c_fld2190inst_Slot_inst_get (insn) == 3005 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_SCALE_REG; + if (Field_dsp340050b49a6c_fld2191inst_Slot_inst_get (insn) == 3006 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_SMOD_POS; + if (Field_dsp340050b49a6c_fld2192inst_Slot_inst_get (insn) == 3007 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_SOV; + if (Field_dsp340050b49a6c_fld2193inst_Slot_inst_get (insn) == 211 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3662inst_Slot_inst_get (insn) == 0) + return OPCODE_SMINCLB_R; + if (Field_dsp340050b49a6c_fld2194inst_Slot_inst_get (insn) == 3504 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_GET_WGHT; + if (Field_dsp340050b49a6c_fld2195inst_Slot_inst_get (insn) == 3505 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld2196inst_Slot_inst_get (insn) == 3506 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld2197inst_Slot_inst_get (insn) == 3507 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SET_ARGMAX; + if (Field_dsp340050b49a6c_fld2198inst_Slot_inst_get (insn) == 3508 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld2199inst_Slot_inst_get (insn) == 3509 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SET_MAX; + if (Field_dsp340050b49a6c_fld2200inst_Slot_inst_get (insn) == 3510 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SET_NCO; + if (Field_dsp340050b49a6c_fld2201inst_Slot_inst_get (insn) == 3511 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SET_SAR; + if (Field_dsp340050b49a6c_fld2202inst_Slot_inst_get (insn) == 878 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2254_Slot_inst_get (insn) == 0) + return OPCODE_RDTIEP; + if (Field_dsp340050b49a6c_fld2203inst_Slot_inst_get (insn) == 879 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2254_Slot_inst_get (insn) == 0) + return OPCODE_SET_SMOD_OFFSET_TABLE; + if (Field_dsp340050b49a6c_fld2204inst_Slot_inst_get (insn) == 123 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3656inst_Slot_inst_get (insn) == 0) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld2205inst_Slot_inst_get (insn) == 3 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_MOVCM2PQ; + if (Field_dsp340050b49a6c_fld2206inst_Slot_inst_get (insn) == 7 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_QREADY; + if (Field_dsp340050b49a6c_fld2207inst_Slot_inst_get (insn) == 19 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_EXT32_I; + if (Field_dsp340050b49a6c_fld2208inst_Slot_inst_get (insn) == 23 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_EXT_2FIFO_2; + if (Field_dsp340050b49a6c_fld2209inst_Slot_inst_get (insn) == 27 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_EXT_2FIFO_3; + if (Field_dsp340050b49a6c_fld2210inst_Slot_inst_get (insn) == 31 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_EXT_R2FIFO_0; + if (Field_dsp340050b49a6c_fld2211inst_Slot_inst_get (insn) == 35 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_EXT32_R; + if (Field_dsp340050b49a6c_fld2212inst_Slot_inst_get (insn) == 39 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_EXT_R2FIFO_1; + if (Field_dsp340050b49a6c_fld2213inst_Slot_inst_get (insn) == 23 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3647inst_Slot_inst_get (insn) == 0) + return OPCODE_EXT_R2FIFO_2; + if (Field_dsp340050b49a6c_fld2214inst_Slot_inst_get (insn) == 27 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3648inst_Slot_inst_get (insn) == 0) + return OPCODE_EXT_R2FIFO_3; + if (Field_dsp340050b49a6c_fld2215inst_Slot_inst_get (insn) == 31 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3630inst_Slot_inst_get (insn) == 0) + return OPCODE_SET_SMOD_BUF; + if (Field_dsp340050b49a6c_fld2216inst_Slot_inst_get (insn) == 7 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3644inst_Slot_inst_get (insn) == 0) + return OPCODE_EXT_2FIFO_0; + if (Field_dsp340050b49a6c_fld2217inst_Slot_inst_get (insn) == 7 && + Field_sae4_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 3 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3645inst_Slot_inst_get (insn) == 0) + return OPCODE_EXT_2FIFO_1; + if (Field_dsp340050b49a6c_fld2218inst_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2021_Slot_inst_get (insn) == 6 && + Field_sa4_Slot_inst_get (insn) == 1 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 4 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_EXT; + if (Field_dsp340050b49a6c_fld2219inst_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2021_Slot_inst_get (insn) == 6 && + Field_sa4_Slot_inst_get (insn) == 1 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 4 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_EXT_R; + if (Field_dsp340050b49a6c_fld2220inst_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2021_Slot_inst_get (insn) == 7 && + Field_sa4_Slot_inst_get (insn) == 1 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 4 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_PUSH128_M; + if (Field_dsp340050b49a6c_fld2221inst_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2021_Slot_inst_get (insn) == 7 && + Field_sa4_Slot_inst_get (insn) == 1 && + Field_sae4_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 4 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SAC2X64_0; + if (Field_dsp340050b49a6c_fld2222inst_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SAC2X32; + if (Field_dsp340050b49a6c_fld2223inst_Slot_inst_get (insn) == 1 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SAC32_R; + if (Field_dsp340050b49a6c_fld2224inst_Slot_inst_get (insn) == 2 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SCM_PINC; + if (Field_dsp340050b49a6c_fld2225inst_Slot_inst_get (insn) == 5 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LUT0; + if (Field_dsp340050b49a6c_fld2226inst_Slot_inst_get (insn) == 7 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LUT1; + if (Field_dsp340050b49a6c_fld2227inst_Slot_inst_get (insn) == 4 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SCM_U; + if (Field_dsp340050b49a6c_fld2228inst_Slot_inst_get (insn) == 9 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LUT2; + if (Field_dsp340050b49a6c_fld2229inst_Slot_inst_get (insn) == 11 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SCM; + if (Field_dsp340050b49a6c_fld2230inst_Slot_inst_get (insn) == 12 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_LUT3; + if (Field_dsp340050b49a6c_fld2231inst_Slot_inst_get (insn) == 14 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_STORE_P; + if (Field_dsp340050b49a6c_fld2232inst_Slot_inst_get (insn) == 14 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SAC_IH; + if (Field_dsp340050b49a6c_fld2234inst_Slot_inst_get (insn) == 15 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SAC_IL; + if (Field_dsp340050b49a6c_fld2235inst_Slot_inst_get (insn) == 16 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_COMB_AR; + if (Field_dsp340050b49a6c_fld2236inst_Slot_inst_get (insn) == 18 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_STSWAPBM; + if (Field_dsp340050b49a6c_fld2237inst_Slot_inst_get (insn) == 18 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SAC_RH; + if (Field_dsp340050b49a6c_fld2238inst_Slot_inst_get (insn) == 35 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SAC2X64_1; + if (Field_dsp340050b49a6c_fld2239inst_Slot_inst_get (insn) == 39 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SAC2X64_2; + if (Field_dsp340050b49a6c_fld2240inst_Slot_inst_get (insn) == 20 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SAC_RL; + if (Field_dsp340050b49a6c_fld2241inst_Slot_inst_get (insn) == 41 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_SAC2X64_3; + if (Field_dsp340050b49a6c_fld2242inst_Slot_inst_get (insn) == 45 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3661inst_Slot_inst_get (insn) == 0) + return OPCODE_ASLACM; + if (Field_dsp340050b49a6c_fld2243inst_Slot_inst_get (insn) == 21 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_STSWAPBMU; + if (Field_dsp340050b49a6c_fld2244inst_Slot_inst_get (insn) == 92 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_CM2AR_LN; + if (Field_dsp340050b49a6c_fld2245inst_Slot_inst_get (insn) == 93 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_CM2AR_LN_I; + if (Field_dsp340050b49a6c_fld2246inst_Slot_inst_get (insn) == 47 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3638inst_Slot_inst_get (insn) == 0) + return OPCODE_CM2AR_LN_R; + if (Field_dsp340050b49a6c_fld2247inst_Slot_inst_get (insn) == 24 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0) + return OPCODE_STORE_Q; + if (Field_dsp340050b49a6c_fld2248inst_Slot_inst_get (insn) == 50 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3651inst_Slot_inst_get (insn) == 0) + return OPCODE_POP128_2M_0; + if (Field_dsp340050b49a6c_fld2249inst_Slot_inst_get (insn) == 51 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3655inst_Slot_inst_get (insn) == 0) + return OPCODE_POP128_2M_3; + if (Field_dsp340050b49a6c_fld2250inst_Slot_inst_get (insn) == 26 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3653inst_Slot_inst_get (insn) == 0) + return OPCODE_POP128_2M_1; + if (Field_dsp340050b49a6c_fld2251inst_Slot_inst_get (insn) == 216 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3658inst_Slot_inst_get (insn) == 0) + return OPCODE_PUSH32; + if (Field_dsp340050b49a6c_fld2252inst_Slot_inst_get (insn) == 217 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3643inst_Slot_inst_get (insn) == 0) + return OPCODE_SWAPB; + if (Field_dsp340050b49a6c_fld2253inst_Slot_inst_get (insn) == 109 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3639inst_Slot_inst_get (insn) == 0) + return OPCODE_MOV2AC32_I; + if (Field_dsp340050b49a6c_fld2255inst_Slot_inst_get (insn) == 55 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3640inst_Slot_inst_get (insn) == 0) + return OPCODE_MOV2AC32_R; + if (Field_dsp340050b49a6c_fld2257inst_Slot_inst_get (insn) == 7 && + Field_dsp340050b49a6c_fld2019_Slot_inst_get (insn) == 6 && + Field_op0_Slot_inst_get (insn) == 0 && + Field_dsp340050b49a6c_fld3654inst_Slot_inst_get (insn) == 0) + return OPCODE_POP128_2M_2; + switch (Field_op0_Slot_inst_get (insn)) + { + case 0: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + if (Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return OPCODE_ILL; + break; + case 2: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return OPCODE_RET; + case 1: + return OPCODE_RETW; + case 2: + return OPCODE_JX; + } + break; + case 3: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return OPCODE_CALLX0; + case 1: + return OPCODE_CALLX4; + case 2: + return OPCODE_CALLX8; + case 3: + return OPCODE_CALLX12; + } + break; + } + break; + case 1: + return OPCODE_MOVSP; + case 2: + if (Field_s_Slot_inst_get (insn) == 0) + { + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return OPCODE_ISYNC; + case 1: + return OPCODE_RSYNC; + case 2: + return OPCODE_ESYNC; + case 3: + return OPCODE_DSYNC; + case 8: + return OPCODE_EXCW; + case 12: + return OPCODE_MEMW; + case 13: + return OPCODE_EXTW; + case 15: + return OPCODE_NOP; + } + } + break; + case 3: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return OPCODE_RFE; + case 2: + return OPCODE_RFDE; + case 4: + return OPCODE_RFWO; + case 5: + return OPCODE_RFWU; + } + break; + case 1: + return OPCODE_RFI; + } + break; + case 4: + return OPCODE_BREAK; + case 5: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SYSCALL; + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SIMCALL; + break; + } + break; + case 6: + return OPCODE_RSIL; + case 7: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_WAITI; + break; + case 8: + return OPCODE_ANY4; + case 9: + return OPCODE_ALL4; + case 10: + return OPCODE_ANY8; + case 11: + return OPCODE_ALL8; + } + break; + case 1: + return OPCODE_AND; + case 2: + return OPCODE_OR; + case 3: + return OPCODE_XOR; + case 4: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSR; + break; + case 1: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSL; + break; + case 2: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8L; + break; + case 3: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SSA8B; + break; + case 4: + if (Field_thi3_Slot_inst_get (insn) == 0) + return OPCODE_SSAI; + break; + case 6: + return OPCODE_RER; + case 7: + return OPCODE_WER; + case 8: + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_ROTW; + break; + case 14: + return OPCODE_NSA; + case 15: + return OPCODE_NSAU; + } + break; + case 5: + switch (Field_r_Slot_inst_get (insn)) + { + case 3: + return OPCODE_RITLB0; + case 4: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IITLB; + break; + case 5: + return OPCODE_PITLB; + case 6: + return OPCODE_WITLB; + case 7: + return OPCODE_RITLB1; + case 11: + return OPCODE_RDTLB0; + case 12: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_IDTLB; + break; + case 13: + return OPCODE_PDTLB; + case 14: + return OPCODE_WDTLB; + case 15: + return OPCODE_RDTLB1; + } + break; + case 6: + switch (Field_s_Slot_inst_get (insn)) + { + case 0: + return OPCODE_NEG; + case 1: + return OPCODE_ABS; + } + break; + case 8: + return OPCODE_ADD; + case 9: + return OPCODE_ADDX2; + case 10: + return OPCODE_ADDX4; + case 11: + return OPCODE_ADDX8; + case 12: + return OPCODE_SUB; + case 13: + return OPCODE_SUBX2; + case 14: + return OPCODE_SUBX4; + case 15: + return OPCODE_SUBX8; + } + break; + case 1: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + case 1: + return OPCODE_SLLI; + case 2: + case 3: + return OPCODE_SRAI; + case 4: + return OPCODE_SRLI; + case 6: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return OPCODE_XSR_LBEG; + case 1: + return OPCODE_XSR_LEND; + case 2: + return OPCODE_XSR_LCOUNT; + case 3: + return OPCODE_XSR_SAR; + case 4: + return OPCODE_XSR_BR; + case 5: + return OPCODE_XSR_LITBASE; + case 12: + return OPCODE_XSR_SCOMPARE1; + case 72: + return OPCODE_XSR_WINDOWBASE; + case 73: + return OPCODE_XSR_WINDOWSTART; + case 96: + return OPCODE_XSR_IBREAKENABLE; + case 99: + return OPCODE_XSR_ATOMCTL; + case 104: + return OPCODE_XSR_DDR; + case 128: + return OPCODE_XSR_IBREAKA0; + case 129: + return OPCODE_XSR_IBREAKA1; + case 144: + return OPCODE_XSR_DBREAKA0; + case 145: + return OPCODE_XSR_DBREAKA1; + case 160: + return OPCODE_XSR_DBREAKC0; + case 161: + return OPCODE_XSR_DBREAKC1; + case 177: + return OPCODE_XSR_EPC1; + case 178: + return OPCODE_XSR_EPC2; + case 179: + return OPCODE_XSR_EPC3; + case 180: + return OPCODE_XSR_EPC4; + case 181: + return OPCODE_XSR_EPC5; + case 182: + return OPCODE_XSR_EPC6; + case 192: + return OPCODE_XSR_DEPC; + case 194: + return OPCODE_XSR_EPS2; + case 195: + return OPCODE_XSR_EPS3; + case 196: + return OPCODE_XSR_EPS4; + case 197: + return OPCODE_XSR_EPS5; + case 198: + return OPCODE_XSR_EPS6; + case 209: + return OPCODE_XSR_EXCSAVE1; + case 210: + return OPCODE_XSR_EXCSAVE2; + case 211: + return OPCODE_XSR_EXCSAVE3; + case 212: + return OPCODE_XSR_EXCSAVE4; + case 213: + return OPCODE_XSR_EXCSAVE5; + case 214: + return OPCODE_XSR_EXCSAVE6; + case 224: + return OPCODE_XSR_CPENABLE; + case 228: + return OPCODE_XSR_INTENABLE; + case 230: + return OPCODE_XSR_PS; + case 231: + return OPCODE_XSR_VECBASE; + case 232: + return OPCODE_XSR_EXCCAUSE; + case 233: + return OPCODE_XSR_DEBUGCAUSE; + case 234: + return OPCODE_XSR_CCOUNT; + case 236: + return OPCODE_XSR_ICOUNT; + case 237: + return OPCODE_XSR_ICOUNTLEVEL; + case 238: + return OPCODE_XSR_EXCVADDR; + case 240: + return OPCODE_XSR_CCOMPARE0; + case 241: + return OPCODE_XSR_CCOMPARE1; + } + break; + case 8: + return OPCODE_SRC; + case 9: + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRL; + break; + case 10: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_SLL; + break; + case 11: + if (Field_s_Slot_inst_get (insn) == 0) + return OPCODE_SRA; + break; + case 12: + return OPCODE_MUL16U; + case 13: + return OPCODE_MUL16S; + case 15: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return OPCODE_LICT; + case 1: + return OPCODE_SICT; + case 2: + return OPCODE_LICW; + case 3: + return OPCODE_SICW; + case 8: + return OPCODE_LDCT; + case 9: + return OPCODE_SDCT; + case 14: + if (Field_t_Slot_inst_get (insn) == 0) + return OPCODE_RFDO; + if (Field_t_Slot_inst_get (insn) == 1) + return OPCODE_RFDD; + break; + } + break; + } + break; + case 2: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + return OPCODE_ANDB; + case 1: + return OPCODE_ANDBC; + case 2: + return OPCODE_ORB; + case 3: + return OPCODE_ORBC; + case 4: + return OPCODE_XORB; + } + break; + case 3: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return OPCODE_RSR_LBEG; + case 1: + return OPCODE_RSR_LEND; + case 2: + return OPCODE_RSR_LCOUNT; + case 3: + return OPCODE_RSR_SAR; + case 4: + return OPCODE_RSR_BR; + case 5: + return OPCODE_RSR_LITBASE; + case 12: + return OPCODE_RSR_SCOMPARE1; + case 72: + return OPCODE_RSR_WINDOWBASE; + case 73: + return OPCODE_RSR_WINDOWSTART; + case 96: + return OPCODE_RSR_IBREAKENABLE; + case 99: + return OPCODE_RSR_ATOMCTL; + case 104: + return OPCODE_RSR_DDR; + case 128: + return OPCODE_RSR_IBREAKA0; + case 129: + return OPCODE_RSR_IBREAKA1; + case 144: + return OPCODE_RSR_DBREAKA0; + case 145: + return OPCODE_RSR_DBREAKA1; + case 160: + return OPCODE_RSR_DBREAKC0; + case 161: + return OPCODE_RSR_DBREAKC1; + case 176: + return OPCODE_RSR_176; + case 177: + return OPCODE_RSR_EPC1; + case 178: + return OPCODE_RSR_EPC2; + case 179: + return OPCODE_RSR_EPC3; + case 180: + return OPCODE_RSR_EPC4; + case 181: + return OPCODE_RSR_EPC5; + case 182: + return OPCODE_RSR_EPC6; + case 192: + return OPCODE_RSR_DEPC; + case 194: + return OPCODE_RSR_EPS2; + case 195: + return OPCODE_RSR_EPS3; + case 196: + return OPCODE_RSR_EPS4; + case 197: + return OPCODE_RSR_EPS5; + case 198: + return OPCODE_RSR_EPS6; + case 208: + return OPCODE_RSR_208; + case 209: + return OPCODE_RSR_EXCSAVE1; + case 210: + return OPCODE_RSR_EXCSAVE2; + case 211: + return OPCODE_RSR_EXCSAVE3; + case 212: + return OPCODE_RSR_EXCSAVE4; + case 213: + return OPCODE_RSR_EXCSAVE5; + case 214: + return OPCODE_RSR_EXCSAVE6; + case 224: + return OPCODE_RSR_CPENABLE; + case 226: + return OPCODE_RSR_INTERRUPT; + case 228: + return OPCODE_RSR_INTENABLE; + case 230: + return OPCODE_RSR_PS; + case 231: + return OPCODE_RSR_VECBASE; + case 232: + return OPCODE_RSR_EXCCAUSE; + case 233: + return OPCODE_RSR_DEBUGCAUSE; + case 234: + return OPCODE_RSR_CCOUNT; + case 235: + return OPCODE_RSR_PRID; + case 236: + return OPCODE_RSR_ICOUNT; + case 237: + return OPCODE_RSR_ICOUNTLEVEL; + case 238: + return OPCODE_RSR_EXCVADDR; + case 240: + return OPCODE_RSR_CCOMPARE0; + case 241: + return OPCODE_RSR_CCOMPARE1; + } + break; + case 1: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return OPCODE_WSR_LBEG; + case 1: + return OPCODE_WSR_LEND; + case 2: + return OPCODE_WSR_LCOUNT; + case 3: + return OPCODE_WSR_SAR; + case 4: + return OPCODE_WSR_BR; + case 5: + return OPCODE_WSR_LITBASE; + case 12: + return OPCODE_WSR_SCOMPARE1; + case 72: + return OPCODE_WSR_WINDOWBASE; + case 73: + return OPCODE_WSR_WINDOWSTART; + case 89: + return OPCODE_WSR_MMID; + case 96: + return OPCODE_WSR_IBREAKENABLE; + case 99: + return OPCODE_WSR_ATOMCTL; + case 104: + return OPCODE_WSR_DDR; + case 128: + return OPCODE_WSR_IBREAKA0; + case 129: + return OPCODE_WSR_IBREAKA1; + case 144: + return OPCODE_WSR_DBREAKA0; + case 145: + return OPCODE_WSR_DBREAKA1; + case 160: + return OPCODE_WSR_DBREAKC0; + case 161: + return OPCODE_WSR_DBREAKC1; + case 176: + return OPCODE_WSR_176; + case 177: + return OPCODE_WSR_EPC1; + case 178: + return OPCODE_WSR_EPC2; + case 179: + return OPCODE_WSR_EPC3; + case 180: + return OPCODE_WSR_EPC4; + case 181: + return OPCODE_WSR_EPC5; + case 182: + return OPCODE_WSR_EPC6; + case 192: + return OPCODE_WSR_DEPC; + case 194: + return OPCODE_WSR_EPS2; + case 195: + return OPCODE_WSR_EPS3; + case 196: + return OPCODE_WSR_EPS4; + case 197: + return OPCODE_WSR_EPS5; + case 198: + return OPCODE_WSR_EPS6; + case 209: + return OPCODE_WSR_EXCSAVE1; + case 210: + return OPCODE_WSR_EXCSAVE2; + case 211: + return OPCODE_WSR_EXCSAVE3; + case 212: + return OPCODE_WSR_EXCSAVE4; + case 213: + return OPCODE_WSR_EXCSAVE5; + case 214: + return OPCODE_WSR_EXCSAVE6; + case 224: + return OPCODE_WSR_CPENABLE; + case 226: + return OPCODE_WSR_INTSET; + case 227: + return OPCODE_WSR_INTCLEAR; + case 228: + return OPCODE_WSR_INTENABLE; + case 230: + return OPCODE_WSR_PS; + case 231: + return OPCODE_WSR_VECBASE; + case 232: + return OPCODE_WSR_EXCCAUSE; + case 233: + return OPCODE_WSR_DEBUGCAUSE; + case 234: + return OPCODE_WSR_CCOUNT; + case 236: + return OPCODE_WSR_ICOUNT; + case 237: + return OPCODE_WSR_ICOUNTLEVEL; + case 238: + return OPCODE_WSR_EXCVADDR; + case 240: + return OPCODE_WSR_CCOMPARE0; + case 241: + return OPCODE_WSR_CCOMPARE1; + } + break; + case 2: + return OPCODE_SEXT; + case 3: + return OPCODE_CLAMPS; + case 4: + return OPCODE_MIN; + case 5: + return OPCODE_MAX; + case 6: + return OPCODE_MINU; + case 7: + return OPCODE_MAXU; + case 8: + return OPCODE_MOVEQZ; + case 9: + return OPCODE_MOVNEZ; + case 10: + return OPCODE_MOVLTZ; + case 11: + return OPCODE_MOVGEZ; + case 12: + return OPCODE_MOVF; + case 13: + return OPCODE_MOVT; + case 14: + switch (Field_st_Slot_inst_get (insn)) + { + case 0: + return OPCODE_RUR_EXPSTATE; + case 1: + return OPCODE_RUR_SOV; + case 2: + return OPCODE_RUR_SAT_MODE; + case 3: + return OPCODE_RUR_SAR0; + case 4: + return OPCODE_RUR_SAR1; + case 5: + return OPCODE_RUR_SAR2; + case 6: + return OPCODE_RUR_SAR3; + case 7: + return OPCODE_RUR_HSAR0; + case 8: + return OPCODE_RUR_HSAR1; + case 9: + return OPCODE_RUR_HSAR2; + case 10: + return OPCODE_RUR_HSAR3; + case 11: + return OPCODE_RUR_MAX_REG_0; + case 12: + return OPCODE_RUR_MAX_REG_1; + case 13: + return OPCODE_RUR_MAX_REG_2; + case 14: + return OPCODE_RUR_MAX_REG_3; + case 15: + return OPCODE_RUR_ARG_MAX_REG_0; + case 16: + return OPCODE_RUR_ARG_MAX_REG_1; + case 17: + return OPCODE_RUR_ARG_MAX_REG_2; + case 18: + return OPCODE_RUR_ARG_MAX_REG_3; + case 19: + return OPCODE_RUR_NCO_COUNTER_0; + case 20: + return OPCODE_RUR_NCO_COUNTER_1; + case 21: + return OPCODE_RUR_NCO_COUNTER_2; + case 22: + return OPCODE_RUR_NCO_COUNTER_3; + case 23: + return OPCODE_RUR_INTERP_EXT_N; + case 24: + return OPCODE_RUR_INTERP_EXT_L; + case 25: + return OPCODE_RUR_LLR_BUF_0; + case 26: + return OPCODE_RUR_LLR_BUF_1; + case 27: + return OPCODE_RUR_LLR_BUF_2; + case 28: + return OPCODE_RUR_LLR_BUF_3; + case 29: + return OPCODE_RUR_LLR_BUF_4; + case 30: + return OPCODE_RUR_LLR_BUF_5; + case 31: + return OPCODE_RUR_LLR_BUF_6; + case 32: + return OPCODE_RUR_LLR_BUF_7; + case 33: + return OPCODE_RUR_LLR_BUF_8; + case 34: + return OPCODE_RUR_LLR_BUF_9; + case 35: + return OPCODE_RUR_LLR_BUF_10; + case 36: + return OPCODE_RUR_LLR_BUF_11; + case 37: + return OPCODE_RUR_LLR_BUF_12; + case 38: + return OPCODE_RUR_LLR_BUF_13; + case 39: + return OPCODE_RUR_LLR_BUF_14; + case 40: + return OPCODE_RUR_LLR_BUF_15; + case 41: + return OPCODE_RUR_LLR_BUF_16; + case 42: + return OPCODE_RUR_LLR_BUF_17; + case 43: + return OPCODE_RUR_LLR_BUF_18; + case 44: + return OPCODE_RUR_LLR_BUF_19; + case 45: + return OPCODE_RUR_LLR_BUF_20; + case 46: + return OPCODE_RUR_LLR_BUF_21; + case 47: + return OPCODE_RUR_LLR_BUF_22; + case 48: + return OPCODE_RUR_LLR_BUF_23; + case 49: + return OPCODE_RUR_SMOD_BUF_0; + case 50: + return OPCODE_RUR_SMOD_BUF_1; + case 51: + return OPCODE_RUR_SMOD_BUF_2; + case 52: + return OPCODE_RUR_SMOD_BUF_3; + case 53: + return OPCODE_RUR_SMOD_BUF_4; + case 54: + return OPCODE_RUR_SMOD_BUF_5; + case 55: + return OPCODE_RUR_SMOD_BUF_6; + case 56: + return OPCODE_RUR_SMOD_BUF_7; + case 57: + return OPCODE_RUR_WEIGHT_REG; + case 58: + return OPCODE_RUR_SCALE_REG; + case 59: + return OPCODE_RUR_LLR_POS; + case 60: + return OPCODE_RUR_SMOD_POS; + case 61: + return OPCODE_RUR_PERM_REG; + case 62: + return OPCODE_RUR_SMOD_OFFSET_TABLE_0; + case 63: + return OPCODE_RUR_SMOD_OFFSET_TABLE_1; + case 64: + return OPCODE_RUR_SMOD_OFFSET_TABLE_2; + case 65: + return OPCODE_RUR_SMOD_OFFSET_TABLE_3; + case 66: + return OPCODE_RUR_PHASOR_N; + case 67: + return OPCODE_RUR_PHASOR_OFFSET; + case 231: + return OPCODE_RUR_THREADPTR; + case 232: + return OPCODE_RUR_FCR; + case 233: + return OPCODE_RUR_FSR; + } + break; + case 15: + switch (Field_sr_Slot_inst_get (insn)) + { + case 0: + return OPCODE_WUR_EXPSTATE; + case 1: + return OPCODE_WUR_SOV; + case 2: + return OPCODE_WUR_SAT_MODE; + case 3: + return OPCODE_WUR_SAR0; + case 4: + return OPCODE_WUR_SAR1; + case 5: + return OPCODE_WUR_SAR2; + case 6: + return OPCODE_WUR_SAR3; + case 7: + return OPCODE_WUR_HSAR0; + case 8: + return OPCODE_WUR_HSAR1; + case 9: + return OPCODE_WUR_HSAR2; + case 10: + return OPCODE_WUR_HSAR3; + case 11: + return OPCODE_WUR_MAX_REG_0; + case 12: + return OPCODE_WUR_MAX_REG_1; + case 13: + return OPCODE_WUR_MAX_REG_2; + case 14: + return OPCODE_WUR_MAX_REG_3; + case 15: + return OPCODE_WUR_ARG_MAX_REG_0; + case 16: + return OPCODE_WUR_ARG_MAX_REG_1; + case 17: + return OPCODE_WUR_ARG_MAX_REG_2; + case 18: + return OPCODE_WUR_ARG_MAX_REG_3; + case 19: + return OPCODE_WUR_NCO_COUNTER_0; + case 20: + return OPCODE_WUR_NCO_COUNTER_1; + case 21: + return OPCODE_WUR_NCO_COUNTER_2; + case 22: + return OPCODE_WUR_NCO_COUNTER_3; + case 23: + return OPCODE_WUR_INTERP_EXT_N; + case 24: + return OPCODE_WUR_INTERP_EXT_L; + case 25: + return OPCODE_WUR_LLR_BUF_0; + case 26: + return OPCODE_WUR_LLR_BUF_1; + case 27: + return OPCODE_WUR_LLR_BUF_2; + case 28: + return OPCODE_WUR_LLR_BUF_3; + case 29: + return OPCODE_WUR_LLR_BUF_4; + case 30: + return OPCODE_WUR_LLR_BUF_5; + case 31: + return OPCODE_WUR_LLR_BUF_6; + case 32: + return OPCODE_WUR_LLR_BUF_7; + case 33: + return OPCODE_WUR_LLR_BUF_8; + case 34: + return OPCODE_WUR_LLR_BUF_9; + case 35: + return OPCODE_WUR_LLR_BUF_10; + case 36: + return OPCODE_WUR_LLR_BUF_11; + case 37: + return OPCODE_WUR_LLR_BUF_12; + case 38: + return OPCODE_WUR_LLR_BUF_13; + case 39: + return OPCODE_WUR_LLR_BUF_14; + case 40: + return OPCODE_WUR_LLR_BUF_15; + case 41: + return OPCODE_WUR_LLR_BUF_16; + case 42: + return OPCODE_WUR_LLR_BUF_17; + case 43: + return OPCODE_WUR_LLR_BUF_18; + case 44: + return OPCODE_WUR_LLR_BUF_19; + case 45: + return OPCODE_WUR_LLR_BUF_20; + case 46: + return OPCODE_WUR_LLR_BUF_21; + case 47: + return OPCODE_WUR_LLR_BUF_22; + case 48: + return OPCODE_WUR_LLR_BUF_23; + case 49: + return OPCODE_WUR_SMOD_BUF_0; + case 50: + return OPCODE_WUR_SMOD_BUF_1; + case 51: + return OPCODE_WUR_SMOD_BUF_2; + case 52: + return OPCODE_WUR_SMOD_BUF_3; + case 53: + return OPCODE_WUR_SMOD_BUF_4; + case 54: + return OPCODE_WUR_SMOD_BUF_5; + case 55: + return OPCODE_WUR_SMOD_BUF_6; + case 56: + return OPCODE_WUR_SMOD_BUF_7; + case 57: + return OPCODE_WUR_WEIGHT_REG; + case 58: + return OPCODE_WUR_SCALE_REG; + case 59: + return OPCODE_WUR_LLR_POS; + case 60: + return OPCODE_WUR_SMOD_POS; + case 61: + return OPCODE_WUR_PERM_REG; + case 62: + return OPCODE_WUR_SMOD_OFFSET_TABLE_0; + case 63: + return OPCODE_WUR_SMOD_OFFSET_TABLE_1; + case 64: + return OPCODE_WUR_SMOD_OFFSET_TABLE_2; + case 65: + return OPCODE_WUR_SMOD_OFFSET_TABLE_3; + case 66: + return OPCODE_WUR_PHASOR_N; + case 67: + return OPCODE_WUR_PHASOR_OFFSET; + case 231: + return OPCODE_WUR_THREADPTR; + case 232: + return OPCODE_WUR_FCR; + case 233: + return OPCODE_WUR_FSR; + } + break; + } + break; + case 4: + case 5: + return OPCODE_EXTUI; + case 8: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + return OPCODE_LSX; + case 1: + return OPCODE_LSXU; + case 4: + return OPCODE_SSX; + case 5: + return OPCODE_SSXU; + } + break; + case 9: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + return OPCODE_L32E; + case 4: + return OPCODE_S32E; + } + break; + case 10: + switch (Field_op2_Slot_inst_get (insn)) + { + case 0: + return OPCODE_ADD_S; + case 1: + return OPCODE_SUB_S; + case 2: + return OPCODE_MUL_S; + case 4: + return OPCODE_MADD_S; + case 5: + return OPCODE_MSUB_S; + case 8: + return OPCODE_ROUND_S; + case 9: + return OPCODE_TRUNC_S; + case 10: + return OPCODE_FLOOR_S; + case 11: + return OPCODE_CEIL_S; + case 12: + return OPCODE_FLOAT_S; + case 13: + return OPCODE_UFLOAT_S; + case 14: + return OPCODE_UTRUNC_S; + case 15: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return OPCODE_MOV_S; + case 1: + return OPCODE_ABS_S; + case 4: + return OPCODE_RFR; + case 5: + return OPCODE_WFR; + case 6: + return OPCODE_NEG_S; + } + break; + } + break; + case 11: + switch (Field_op2_Slot_inst_get (insn)) + { + case 1: + return OPCODE_UN_S; + case 2: + return OPCODE_OEQ_S; + case 3: + return OPCODE_UEQ_S; + case 4: + return OPCODE_OLT_S; + case 5: + return OPCODE_ULT_S; + case 6: + return OPCODE_OLE_S; + case 7: + return OPCODE_ULE_S; + case 8: + return OPCODE_MOVEQZ_S; + case 9: + return OPCODE_MOVNEZ_S; + case 10: + return OPCODE_MOVLTZ_S; + case 11: + return OPCODE_MOVGEZ_S; + case 12: + return OPCODE_MOVF_S; + case 13: + return OPCODE_MOVT_S; + } + break; + } + break; + case 1: + return OPCODE_L32R; + case 2: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return OPCODE_L8UI; + case 1: + return OPCODE_L16UI; + case 2: + return OPCODE_L32I; + case 4: + return OPCODE_S8I; + case 5: + return OPCODE_S16I; + case 6: + return OPCODE_S32I; + case 7: + switch (Field_t_Slot_inst_get (insn)) + { + case 0: + return OPCODE_DPFR; + case 1: + return OPCODE_DPFW; + case 2: + return OPCODE_DPFRO; + case 3: + return OPCODE_DPFWO; + case 4: + return OPCODE_DHWB; + case 5: + return OPCODE_DHWBI; + case 6: + return OPCODE_DHI; + case 7: + return OPCODE_DII; + case 8: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + return OPCODE_DPFL; + case 2: + return OPCODE_DHU; + case 3: + return OPCODE_DIU; + case 4: + return OPCODE_DIWB; + case 5: + return OPCODE_DIWBI; + } + break; + case 12: + return OPCODE_IPF; + case 13: + switch (Field_op1_Slot_inst_get (insn)) + { + case 0: + return OPCODE_IPFL; + case 2: + return OPCODE_IHU; + case 3: + return OPCODE_IIU; + } + break; + case 14: + return OPCODE_IHI; + case 15: + return OPCODE_III; + } + break; + case 9: + return OPCODE_L16SI; + case 10: + return OPCODE_MOVI; + case 11: + return OPCODE_L32AI; + case 12: + return OPCODE_ADDI; + case 13: + return OPCODE_ADDMI; + case 14: + return OPCODE_S32C1I; + case 15: + return OPCODE_S32RI; + } + break; + case 3: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return OPCODE_LSI; + case 4: + return OPCODE_SSI; + case 8: + return OPCODE_LSIU; + case 12: + return OPCODE_SSIU; + } + break; + case 5: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return OPCODE_CALL0; + case 1: + return OPCODE_CALL4; + case 2: + return OPCODE_CALL8; + case 3: + return OPCODE_CALL12; + } + break; + case 6: + switch (Field_n_Slot_inst_get (insn)) + { + case 0: + return OPCODE_J; + case 1: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return OPCODE_BEQZ; + case 1: + return OPCODE_BNEZ; + case 2: + return OPCODE_BLTZ; + case 3: + return OPCODE_BGEZ; + } + break; + case 2: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return OPCODE_BEQI; + case 1: + return OPCODE_BNEI; + case 2: + return OPCODE_BLTI; + case 3: + return OPCODE_BGEI; + } + break; + case 3: + switch (Field_m_Slot_inst_get (insn)) + { + case 0: + return OPCODE_ENTRY; + case 1: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return OPCODE_BF; + case 1: + return OPCODE_BT; + case 8: + return OPCODE_LOOP; + case 9: + return OPCODE_LOOPNEZ; + case 10: + return OPCODE_LOOPGTZ; + } + break; + case 2: + return OPCODE_BLTUI; + case 3: + return OPCODE_BGEUI; + } + break; + } + break; + case 7: + switch (Field_r_Slot_inst_get (insn)) + { + case 0: + return OPCODE_BNONE; + case 1: + return OPCODE_BEQ; + case 2: + return OPCODE_BLT; + case 3: + return OPCODE_BLTU; + case 4: + return OPCODE_BALL; + case 5: + return OPCODE_BBC; + case 6: + case 7: + return OPCODE_BBCI; + case 8: + return OPCODE_BANY; + case 9: + return OPCODE_BNE; + case 10: + return OPCODE_BGE; + case 11: + return OPCODE_BGEU; + case 12: + return OPCODE_BNALL; + case 13: + return OPCODE_BBS; + case 14: + case 15: + return OPCODE_BBSI; + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16b_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16b_get (insn)) + { + case 12: + switch (Field_i_Slot_inst16b_get (insn)) + { + case 0: + return OPCODE_MOVI_N; + case 1: + switch (Field_z_Slot_inst16b_get (insn)) + { + case 0: + return OPCODE_BEQZ_N; + case 1: + return OPCODE_BNEZ_N; + } + break; + } + break; + case 13: + switch (Field_r_Slot_inst16b_get (insn)) + { + case 0: + return OPCODE_MOV_N; + case 15: + switch (Field_t_Slot_inst16b_get (insn)) + { + case 0: + return OPCODE_RET_N; + case 1: + return OPCODE_RETW_N; + case 2: + return OPCODE_BREAK_N; + case 3: + if (Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_NOP_N; + break; + case 6: + if (Field_s_Slot_inst16b_get (insn) == 0) + return OPCODE_ILL_N; + break; + } + break; + } + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_inst16a_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_Slot_inst16a_get (insn)) + { + case 8: + return OPCODE_L32I_N; + case 9: + return OPCODE_S32I_N; + case 10: + return OPCODE_ADD_N; + case 11: + return OPCODE_ADDI_N; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_gp_slot2_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2258gp_slot2_Slot_gp_slot2_get (insn)) + { + case 22: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVI_N; + break; + case 24: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_AR2PQ_LN; + break; + } + if (Field_dsp340050b49a6c_fld2259gp_slot2_Slot_gp_slot2_get (insn) == 46 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_AR2CM_LN; + switch (Field_dsp340050b49a6c_fld2260gp_slot2_Slot_gp_slot2_get (insn)) + { + case 185: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_ADDAR2; + break; + case 187: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOV_N; + break; + case 189: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVPQ2PQ; + break; + case 191: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_PUSH128_PQ; + break; + case 200: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_PUSH32; + break; + case 201: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SET_EXT_REGS; + break; + case 202: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SUBARX; + break; + case 204: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_WRTIEP; + break; + } + switch (Field_dsp340050b49a6c_fld2261gp_slot2_Slot_gp_slot2_get (insn)) + { + case 1624: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_CLRTIEP; + break; + case 1625: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SETTIEP; + break; + case 1626: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_WRTBSIGQM; + break; + case 1631: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2044_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_1; + break; + } + switch (Field_dsp340050b49a6c_fld2262gp_slot2_Slot_gp_slot2_get (insn)) + { + case 3254: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP2X128_2PQ_01; + break; + case 3255: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP2X128_2PQ_03; + break; + case 3256: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_AR2SAR_DUP; + break; + case 3257: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP2X128_2PQ_21; + break; + case 3258: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP2X128_2PQ_23; + break; + case 3259: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_WRTSIGQ; + break; + case 3260: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_WRTBSIGQ; + break; + } + switch (Field_dsp340050b49a6c_fld2263gp_slot2_Slot_gp_slot2_get (insn)) + { + case 52176: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_0; + break; + case 52177: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_2; + break; + case 52178: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_3; + break; + case 52179: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_0; + break; + case 52180: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_4; + break; + case 52181: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_1; + break; + case 52182: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_2; + break; + case 52183: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_3; + break; + } + if (Field_dsp340050b49a6c_fld2264gp_slot2_Slot_gp_slot2_get (insn) == 13046 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2302_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_5; + if (Field_dsp340050b49a6c_fld2266gp_slot2_Slot_gp_slot2_get (insn) == 13047 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2302_Slot_gp_slot2_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld2267gp_slot2_Slot_gp_slot2_get (insn) == 1640 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_0; + if (Field_dsp340050b49a6c_fld2268gp_slot2_Slot_gp_slot2_get (insn) == 1641 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_1; + if (Field_dsp340050b49a6c_fld2269gp_slot2_Slot_gp_slot2_get (insn) == 1642 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_2; + if (Field_dsp340050b49a6c_fld2270gp_slot2_Slot_gp_slot2_get (insn) == 1643 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_4; + if (Field_dsp340050b49a6c_fld2271gp_slot2_Slot_gp_slot2_get (insn) == 822 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2305_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_3; + if (Field_dsp340050b49a6c_fld2273gp_slot2_Slot_gp_slot2_get (insn) == 823 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2305_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_5; + if (Field_dsp340050b49a6c_fld2274gp_slot2_Slot_gp_slot2_get (insn) == 103 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2056_Slot_gp_slot2_get (insn) == 0) + return OPCODE_PUSH2X128_PQ; + if (Field_dsp340050b49a6c_fld2275gp_slot2_Slot_gp_slot2_get (insn) == 52 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_CM2AR_LN; + if (Field_dsp340050b49a6c_fld2277gp_slot2_Slot_gp_slot2_get (insn) == 106 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_2CMPQ_1; + if (Field_dsp340050b49a6c_fld2278gp_slot2_Slot_gp_slot2_get (insn) == 107 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_2CMPQ_3; + if (Field_dsp340050b49a6c_fld2279gp_slot2_Slot_gp_slot2_get (insn) == 108 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_2CMPQ_2; + if (Field_dsp340050b49a6c_fld2280gp_slot2_Slot_gp_slot2_get (insn) == 109 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_PQ2CM; + if (Field_dsp340050b49a6c_fld2281gp_slot2_Slot_gp_slot2_get (insn) == 220 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_ABS; + if (Field_dsp340050b49a6c_fld2282gp_slot2_Slot_gp_slot2_get (insn) == 221 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_NEG; + if (Field_dsp340050b49a6c_fld2283gp_slot2_Slot_gp_slot2_get (insn) == 222 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SRA; + if (Field_dsp340050b49a6c_fld2284gp_slot2_Slot_gp_slot2_get (insn) == 3343 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_CLRCM; + if (Field_dsp340050b49a6c_fld2286gp_slot2_Slot_gp_slot2_get (insn) == 3359 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_GET_ARGMAX; + if (Field_dsp340050b49a6c_fld2287gp_slot2_Slot_gp_slot2_get (insn) == 3375 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_GET_HSAR; + if (Field_dsp340050b49a6c_fld2288gp_slot2_Slot_gp_slot2_get (insn) == 3391 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_GET_NCO; + if (Field_dsp340050b49a6c_fld2289gp_slot2_Slot_gp_slot2_get (insn) == 3407 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_GET_HSAR2SAR; + if (Field_dsp340050b49a6c_fld2290gp_slot2_Slot_gp_slot2_get (insn) == 3423 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_GET_SAR; + if (Field_dsp340050b49a6c_fld2291gp_slot2_Slot_gp_slot2_get (insn) == 3439 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld2292gp_slot2_Slot_gp_slot2_get (insn) == 3455 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld2293gp_slot2_Slot_gp_slot2_get (insn) == 3471 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_GET_MAX; + if (Field_dsp340050b49a6c_fld2294gp_slot2_Slot_gp_slot2_get (insn) == 3487 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld2295gp_slot2_Slot_gp_slot2_get (insn) == 3503 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld2296gp_slot2_Slot_gp_slot2_get (insn) == 3519 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld2297gp_slot2_Slot_gp_slot2_get (insn) == 3535 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_4; + if (Field_dsp340050b49a6c_fld2298gp_slot2_Slot_gp_slot2_get (insn) == 3551 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld2299gp_slot2_Slot_gp_slot2_get (insn) == 3567 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld2300gp_slot2_Slot_gp_slot2_get (insn) == 3583 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld2301gp_slot2_Slot_gp_slot2_get (insn) == 56 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2272_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP128_2CMPQ_0; + if (Field_dsp340050b49a6c_fld2303gp_slot2_Slot_gp_slot2_get (insn) == 57 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3671gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld2304gp_slot2_Slot_gp_slot2_get (insn) == 29 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3674gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_RDTIEP; + if (Field_dsp340050b49a6c_fld2306gp_slot2_Slot_gp_slot2_get (insn) == 120 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_QREADY; + if (Field_dsp340050b49a6c_fld2308gp_slot2_Slot_gp_slot2_get (insn) == 242 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_AR2CM_DUP; + if (Field_dsp340050b49a6c_fld2309gp_slot2_Slot_gp_slot2_get (insn) == 243 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SWAPB; + if (Field_dsp340050b49a6c_fld2310gp_slot2_Slot_gp_slot2_get (insn) == 61 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3667gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVAR2; + if (Field_dsp340050b49a6c_fld2312gp_slot2_Slot_gp_slot2_get (insn) == 31 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2386_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SLL; + if (Field_dsp340050b49a6c_fld2314gp_slot2_Slot_gp_slot2_get (insn) == 16 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_ADD32; + if (Field_dsp340050b49a6c_fld2316gp_slot2_Slot_gp_slot2_get (insn) == 17 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_ADDCM; + if (Field_dsp340050b49a6c_fld2317gp_slot2_Slot_gp_slot2_get (insn) == 18 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_ADDWRP; + if (Field_dsp340050b49a6c_fld2318gp_slot2_Slot_gp_slot2_get (insn) == 19 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_ASR; + if (Field_dsp340050b49a6c_fld2319gp_slot2_Slot_gp_slot2_get (insn) == 20 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_AND128; + if (Field_dsp340050b49a6c_fld2320gp_slot2_Slot_gp_slot2_get (insn) == 21 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_EXTUI4; + if (Field_dsp340050b49a6c_fld2321gp_slot2_Slot_gp_slot2_get (insn) == 22 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_LUT; + if (Field_dsp340050b49a6c_fld2322gp_slot2_Slot_gp_slot2_get (insn) == 23 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_LUT_IEXT; + if (Field_dsp340050b49a6c_fld2323gp_slot2_Slot_gp_slot2_get (insn) == 24 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_ASL; + if (Field_dsp340050b49a6c_fld2324gp_slot2_Slot_gp_slot2_get (insn) == 25 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_LUT_REXT; + if (Field_dsp340050b49a6c_fld2325gp_slot2_Slot_gp_slot2_get (insn) == 26 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MAX8; + if (Field_dsp340050b49a6c_fld2326gp_slot2_Slot_gp_slot2_get (insn) == 27 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MEAN32; + if (Field_dsp340050b49a6c_fld2327gp_slot2_Slot_gp_slot2_get (insn) == 28 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MEAN; + if (Field_dsp340050b49a6c_fld2328gp_slot2_Slot_gp_slot2_get (insn) == 29 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MIN8; + if (Field_dsp340050b49a6c_fld2329gp_slot2_Slot_gp_slot2_get (insn) == 30 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_OR128; + if (Field_dsp340050b49a6c_fld2330gp_slot2_Slot_gp_slot2_get (insn) == 31 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SUB32; + if (Field_dsp340050b49a6c_fld2331gp_slot2_Slot_gp_slot2_get (insn) == 0 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_ASL32; + if (Field_dsp340050b49a6c_fld2332gp_slot2_Slot_gp_slot2_get (insn) == 1 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_ASR32; + if (Field_dsp340050b49a6c_fld2333gp_slot2_Slot_gp_slot2_get (insn) == 2 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOV2CM2PQ; + if (Field_dsp340050b49a6c_fld2334gp_slot2_Slot_gp_slot2_get (insn) == 3 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCND8_2; + if (Field_dsp340050b49a6c_fld2335gp_slot2_Slot_gp_slot2_get (insn) == 4 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCND8_0; + if (Field_dsp340050b49a6c_fld2336gp_slot2_Slot_gp_slot2_get (insn) == 5 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCND8_3; + if (Field_dsp340050b49a6c_fld2337gp_slot2_Slot_gp_slot2_get (insn) == 6 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCND8_4; + if (Field_dsp340050b49a6c_fld2338gp_slot2_Slot_gp_slot2_get (insn) == 7 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCND8_5; + if (Field_dsp340050b49a6c_fld2339gp_slot2_Slot_gp_slot2_get (insn) == 8 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCND8_1; + if (Field_dsp340050b49a6c_fld2340gp_slot2_Slot_gp_slot2_get (insn) == 9 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCND8_6; + if (Field_dsp340050b49a6c_fld2341gp_slot2_Slot_gp_slot2_get (insn) == 10 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCND8_7; + if (Field_dsp340050b49a6c_fld2342gp_slot2_Slot_gp_slot2_get (insn) == 11 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCND_1; + if (Field_dsp340050b49a6c_fld2343gp_slot2_Slot_gp_slot2_get (insn) == 12 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCND_0; + if (Field_dsp340050b49a6c_fld2344gp_slot2_Slot_gp_slot2_get (insn) == 13 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCND_2; + if (Field_dsp340050b49a6c_fld2345gp_slot2_Slot_gp_slot2_get (insn) == 14 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCND_3; + if (Field_dsp340050b49a6c_fld2346gp_slot2_Slot_gp_slot2_get (insn) == 15 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCND_4; + if (Field_dsp340050b49a6c_fld2347gp_slot2_Slot_gp_slot2_get (insn) == 16 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_ASLM; + if (Field_dsp340050b49a6c_fld2348gp_slot2_Slot_gp_slot2_get (insn) == 17 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_ASRM; + if (Field_dsp340050b49a6c_fld2349gp_slot2_Slot_gp_slot2_get (insn) == 18 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_CMP8; + if (Field_dsp340050b49a6c_fld2350gp_slot2_Slot_gp_slot2_get (insn) == 19 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_LSLM; + if (Field_dsp340050b49a6c_fld2351gp_slot2_Slot_gp_slot2_get (insn) == 20 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_CMP_I; + if (Field_dsp340050b49a6c_fld2352gp_slot2_Slot_gp_slot2_get (insn) == 21 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_LSRM; + if (Field_dsp340050b49a6c_fld2353gp_slot2_Slot_gp_slot2_get (insn) == 262 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_ABS8; + if (Field_dsp340050b49a6c_fld2354gp_slot2_Slot_gp_slot2_get (insn) == 263 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_CONJ; + if (Field_dsp340050b49a6c_fld2355gp_slot2_Slot_gp_slot2_get (insn) == 278 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_LUT_PHASOR; + if (Field_dsp340050b49a6c_fld2356gp_slot2_Slot_gp_slot2_get (insn) == 279 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_NOT128; + if (Field_dsp340050b49a6c_fld2357gp_slot2_Slot_gp_slot2_get (insn) == 294 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_MOVCM; + if (Field_dsp340050b49a6c_fld2358gp_slot2_Slot_gp_slot2_get (insn) == 295 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1) + return OPCODE_TRANS; + if (Field_dsp340050b49a6c_fld2359gp_slot2_Slot_gp_slot2_get (insn) == 2102 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2384_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SET_ARGMAX; + if (Field_dsp340050b49a6c_fld2361gp_slot2_Slot_gp_slot2_get (insn) == 2103 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2384_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SET_HSAR; + if (Field_dsp340050b49a6c_fld2362gp_slot2_Slot_gp_slot2_get (insn) == 1179 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3663gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SET_MAX; + if (Field_dsp340050b49a6c_fld2364gp_slot2_Slot_gp_slot2_get (insn) == 667 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3664gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SET_NCO; + if (Field_dsp340050b49a6c_fld2366gp_slot2_Slot_gp_slot2_get (insn) == 411 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3665gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SET_SAR; + if (Field_dsp340050b49a6c_fld2368gp_slot2_Slot_gp_slot2_get (insn) == 43 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3670gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_NCO_UPDATE; + if (Field_dsp340050b49a6c_fld2369gp_slot2_Slot_gp_slot2_get (insn) == 27 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3668gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_NEGCM; + if (Field_dsp340050b49a6c_fld2370gp_slot2_Slot_gp_slot2_get (insn) == 6 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2032_Slot_gp_slot2_get (insn) == 0) + return OPCODE_CMP_R; + if (Field_dsp340050b49a6c_fld2371gp_slot2_Slot_gp_slot2_get (insn) == 11 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3675gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_ADD16; + if (Field_dsp340050b49a6c_fld2372gp_slot2_Slot_gp_slot2_get (insn) == 15 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3669gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_LUT_WRITE; + if (Field_dsp340050b49a6c_fld2373gp_slot2_Slot_gp_slot2_get (insn) == 0 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 2) + return OPCODE_MOVCND_5; + if (Field_dsp340050b49a6c_fld2374gp_slot2_Slot_gp_slot2_get (insn) == 1 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 2) + return OPCODE_MOVCND_6; + if (Field_dsp340050b49a6c_fld2375gp_slot2_Slot_gp_slot2_get (insn) == 2 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 2) + return OPCODE_MOVCND_7; + if (Field_dsp340050b49a6c_fld2376gp_slot2_Slot_gp_slot2_get (insn) == 12 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld2313_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVCM2PQ; + if (Field_dsp340050b49a6c_fld2378gp_slot2_Slot_gp_slot2_get (insn) == 13 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3676gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_ARGMAX8; + if (Field_dsp340050b49a6c_fld2379gp_slot2_Slot_gp_slot2_get (insn) == 7 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3673gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_PUSH128; + if (Field_dsp340050b49a6c_fld2381gp_slot2_Slot_gp_slot2_get (insn) == 1 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3666_Slot_gp_slot2_get (insn) == 0) + return OPCODE_PERM; + if (Field_dsp340050b49a6c_fld2383gp_slot2_Slot_gp_slot2_get (insn) == 1 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3678gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_ASLM32; + if (Field_dsp340050b49a6c_fld2385gp_slot2_Slot_gp_slot2_get (insn) == 8 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld2313_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SUBCM; + if (Field_dsp340050b49a6c_fld2387gp_slot2_Slot_gp_slot2_get (insn) == 9 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld2313_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SUBMEAN; + if (Field_dsp340050b49a6c_fld2388gp_slot2_Slot_gp_slot2_get (insn) == 5 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3679gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SUBWRP; + if (Field_dsp340050b49a6c_fld2389gp_slot2_Slot_gp_slot2_get (insn) == 3 && + Field_op0_s3_Slot_gp_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3680gp_slot2_Slot_gp_slot2_get (insn) == 0) + return OPCODE_XOR128; + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 3) + return OPCODE_EXTUI; + switch (Field_sae_Slot_gp_slot2_get (insn)) + { + case 0: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_ADD; + break; + case 1: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_ADDI_N; + break; + case 2: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_AND; + break; + case 3: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVGEZ; + break; + case 4: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_LUT_AR; + break; + case 5: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVLTZ; + break; + case 6: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVNEZ; + break; + case 7: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_OR; + break; + case 8: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_MOVEQZ; + break; + case 9: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_SUB; + break; + case 10: + if (Field_op0_s3_Slot_gp_slot2_get (insn) == 0) + return OPCODE_XOR; + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_gp_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_dsp340050b49a6c_fld2407gp_slot0_Slot_gp_slot0_get (insn) == 0 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_LAC2X32; + if (Field_dsp340050b49a6c_fld2409gp_slot0_Slot_gp_slot0_get (insn) == 1 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_LAC32_R; + if (Field_dsp340050b49a6c_fld2410gp_slot0_Slot_gp_slot0_get (insn) == 2 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_LAC_IH; + if (Field_dsp340050b49a6c_fld2411gp_slot0_Slot_gp_slot0_get (insn) == 3 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_LAC_RH; + if (Field_dsp340050b49a6c_fld2412gp_slot0_Slot_gp_slot0_get (insn) == 10 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_LAC_RL; + if (Field_dsp340050b49a6c_fld2413gp_slot0_Slot_gp_slot0_get (insn) == 11 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_LAC2X64_0; + if (Field_dsp340050b49a6c_fld2415gp_slot0_Slot_gp_slot0_get (insn) == 27 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_LAC2X64_1; + if (Field_dsp340050b49a6c_fld2416gp_slot0_Slot_gp_slot0_get (insn) == 4 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_LAC_IL; + if (Field_dsp340050b49a6c_fld2417gp_slot0_Slot_gp_slot0_get (insn) == 5 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_LAC2X64_2; + switch (Field_dsp340050b49a6c_fld2418gp_slot0_Slot_gp_slot0_get (insn)) + { + case 21: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_AR2CM_DUP; + break; + case 53: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_MOV_N; + break; + case 85: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_NSA; + break; + case 117: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_PUSH32; + break; + case 149: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_NSAU; + break; + } + if (Field_dsp340050b49a6c_fld2419gp_slot0_Slot_gp_slot0_get (insn) == 362 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_LLR_BUF; + if (Field_dsp340050b49a6c_fld2420gp_slot0_Slot_gp_slot0_get (insn) == 1452 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_ANY8; + if (Field_dsp340050b49a6c_fld2422gp_slot0_Slot_gp_slot0_get (insn) == 1453 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_SMOD_BUF; + if (Field_dsp340050b49a6c_fld2423gp_slot0_Slot_gp_slot0_get (insn) == 2908 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_CLRCM; + if (Field_dsp340050b49a6c_fld2424gp_slot0_Slot_gp_slot0_get (insn) == 2909 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_HSAR; + if (Field_dsp340050b49a6c_fld2425gp_slot0_Slot_gp_slot0_get (insn) == 2910 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_HSAR2SAR; + if (Field_dsp340050b49a6c_fld2426gp_slot0_Slot_gp_slot0_get (insn) == 2911 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_SAR; + if (Field_dsp340050b49a6c_fld2427gp_slot0_Slot_gp_slot0_get (insn) == 852 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_ANY4; + if (Field_dsp340050b49a6c_fld2429gp_slot0_Slot_gp_slot0_get (insn) == 3412 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_SMOD_OFFSET_TABLE; + if (Field_dsp340050b49a6c_fld2430gp_slot0_Slot_gp_slot0_get (insn) == 3413 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld2431gp_slot0_Slot_gp_slot0_get (insn) == 3414 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld2432gp_slot0_Slot_gp_slot0_get (insn) == 3415 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld2433gp_slot0_Slot_gp_slot0_get (insn) == 3416 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld2434gp_slot0_Slot_gp_slot0_get (insn) == 3417 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_POP128_4; + if (Field_dsp340050b49a6c_fld2435gp_slot0_Slot_gp_slot0_get (insn) == 1709 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_s8_Slot_gp_slot0_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld2436gp_slot0_Slot_gp_slot0_get (insn) == 855 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3690gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld2437gp_slot0_Slot_gp_slot0_get (insn) == 1960 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SSAI; + switch (Field_dsp340050b49a6c_fld2438gp_slot0_Slot_gp_slot0_get (insn)) + { + case 3922: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SET_LLR_POS; + break; + case 3923: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SET_PHASOR_OFFSET; + break; + case 3924: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SET_PERM_REG; + break; + case 3925: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SET_SCALE_REG; + break; + case 3926: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SET_SMOD_POS; + break; + case 3927: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SET_SOV; + break; + case 3928: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SET_PHASOR_N; + break; + case 3929: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SET_WGHT; + break; + case 3930: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SSA8B; + break; + case 3931: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SSL; + break; + case 3932: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SSA8L; + break; + case 3933: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SSR; + break; + } + if (Field_dsp340050b49a6c_fld2439gp_slot0_Slot_gp_slot0_get (insn) == 3934 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3695gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_CLRAC; + if (Field_dsp340050b49a6c_fld2440gp_slot0_Slot_gp_slot0_get (insn) == 3935 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3695gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_POP16LLR_1; + if (Field_dsp340050b49a6c_fld2441gp_slot0_Slot_gp_slot0_get (insn) == 3 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3693gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_LAC2X64_3; + switch (Field_dsp340050b49a6c_fld2443gp_slot0_Slot_gp_slot0_get (insn)) + { + case 3: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_AR2CM_LN; + break; + case 7: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_AR2CM_LN_I; + break; + } + if (Field_dsp340050b49a6c_fld2444gp_slot0_Slot_gp_slot0_get (insn) == 7 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld2067_Slot_gp_slot0_get (insn) == 0) + return OPCODE_AR2CM_LN_R; + switch (Field_dsp340050b49a6c_fld2445_Slot_gp_slot0_get (insn)) + { + case 0: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_SAC2X32; + break; + case 1: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_SAC32_R; + break; + case 2: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_SCM_PINC; + break; + case 3: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_SRAI; + break; + case 4: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_SCM_U; + break; + case 8: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_SLLI; + break; + } + if (Field_dsp340050b49a6c_fld2447gp_slot0_Slot_gp_slot0_get (insn) == 7 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3688gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_dsp340050b49a6c_fld2448_Slot_gp_slot0_get (insn) == 7 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3703gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_ASLACM; + if (Field_dsp340050b49a6c_fld2449gp_slot0_Slot_gp_slot0_get (insn) == 7 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3689gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_BNEZ_N; + if (Field_dsp340050b49a6c_fld2451gp_slot0_Slot_gp_slot0_get (insn) == 8 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_LCM_PINC; + if (Field_dsp340050b49a6c_fld2452gp_slot0_Slot_gp_slot0_get (insn) == 9 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_LCM_U; + if (Field_dsp340050b49a6c_fld2453gp_slot0_Slot_gp_slot0_get (insn) == 18 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_LCM; + if (Field_dsp340050b49a6c_fld2454gp_slot0_Slot_gp_slot0_get (insn) == 259 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_dsp340050b49a6c_fld2455gp_slot0_Slot_gp_slot0_get (insn) == 267 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_MOVCM; + if (Field_dsp340050b49a6c_fld2456gp_slot0_Slot_gp_slot0_get (insn) == 291 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_MOV_I; + if (Field_dsp340050b49a6c_fld2457gp_slot0_Slot_gp_slot0_get (insn) == 299 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_NEGCM; + if (Field_dsp340050b49a6c_fld2458gp_slot0_Slot_gp_slot0_get (insn) == 323 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_MOV_R; + if (Field_dsp340050b49a6c_fld2459gp_slot0_Slot_gp_slot0_get (insn) == 331 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SRA; + if (Field_dsp340050b49a6c_fld2460gp_slot0_Slot_gp_slot0_get (insn) == 355 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SRL; + if (Field_dsp340050b49a6c_fld2461gp_slot0_Slot_gp_slot0_get (insn) == 715 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_CLB_C; + switch (Field_dsp340050b49a6c_fld2462_Slot_gp_slot0_get (insn)) + { + case 21: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_EXT; + break; + case 23: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_EXT_R; + break; + case 33: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_MOVI_N; + break; + case 35: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_PUSH128_M; + break; + case 46: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SAC2X64_0; + break; + case 47: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SAC2X64_1; + break; + case 50: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SAC2X64_2; + break; + case 52: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SAC2X64_3; + break; + } + if (Field_dsp340050b49a6c_fld2463gp_slot0_Slot_gp_slot0_get (insn) == 731 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_CLB_R; + if (Field_dsp340050b49a6c_fld2464gp_slot0_Slot_gp_slot0_get (insn) == 387 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_NEG; + if (Field_dsp340050b49a6c_fld2465gp_slot0_Slot_gp_slot0_get (insn) == 779 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_MINCLB_C; + if (Field_dsp340050b49a6c_fld2466gp_slot0_Slot_gp_slot0_get (insn) == 795 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SMINCLB_R; + if (Field_dsp340050b49a6c_fld2467gp_slot0_Slot_gp_slot0_get (insn) == 835 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_MINCLB_R; + if (Field_dsp340050b49a6c_fld2468gp_slot0_Slot_gp_slot0_get (insn) == 13571 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_ADDAC_I2R; + if (Field_dsp340050b49a6c_fld2470gp_slot0_Slot_gp_slot0_get (insn) == 13587 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_ADDAC_R2I; + if (Field_dsp340050b49a6c_fld2471gp_slot0_Slot_gp_slot0_get (insn) == 13603 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_REDAC; + if (Field_dsp340050b49a6c_fld2472gp_slot0_Slot_gp_slot0_get (insn) == 13619 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_REDACS; + if (Field_dsp340050b49a6c_fld2473gp_slot0_Slot_gp_slot0_get (insn) == 13635 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_REDAC2; + if (Field_dsp340050b49a6c_fld2474gp_slot0_Slot_gp_slot0_get (insn) == 13651 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SUBAC_I2R; + if (Field_dsp340050b49a6c_fld2475gp_slot0_Slot_gp_slot0_get (insn) == 6835 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3695gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SUBAC_R2I; + if (Field_dsp340050b49a6c_fld2477gp_slot0_Slot_gp_slot0_get (insn) == 1715 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3705gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_REDAC4; + if (Field_dsp340050b49a6c_fld2479gp_slot0_Slot_gp_slot0_get (insn) == 6667 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_INTERP_EXT_L; + if (Field_dsp340050b49a6c_fld2480gp_slot0_Slot_gp_slot0_get (insn) == 6683 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_INTERP_EXT_N; + if (Field_dsp340050b49a6c_fld2481gp_slot0_Slot_gp_slot0_get (insn) == 6699 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_LLR_POS; + if (Field_dsp340050b49a6c_fld2482gp_slot0_Slot_gp_slot0_get (insn) == 6715 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_PHASOR_OFFSET; + if (Field_dsp340050b49a6c_fld2483gp_slot0_Slot_gp_slot0_get (insn) == 6731 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_PERM_REG; + if (Field_dsp340050b49a6c_fld2484gp_slot0_Slot_gp_slot0_get (insn) == 6747 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_SCALE_REG; + if (Field_dsp340050b49a6c_fld2485gp_slot0_Slot_gp_slot0_get (insn) == 6763 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_SMOD_POS; + if (Field_dsp340050b49a6c_fld2486gp_slot0_Slot_gp_slot0_get (insn) == 6779 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_SOV; + if (Field_dsp340050b49a6c_fld2487gp_slot0_Slot_gp_slot0_get (insn) == 6795 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_PHASOR_N; + if (Field_dsp340050b49a6c_fld2488gp_slot0_Slot_gp_slot0_get (insn) == 6811 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_GET_WGHT; + if (Field_dsp340050b49a6c_fld2489gp_slot0_Slot_gp_slot0_get (insn) == 6827 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld2490gp_slot0_Slot_gp_slot0_get (insn) == 6843 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld2491gp_slot0_Slot_gp_slot0_get (insn) == 6859 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld2492gp_slot0_Slot_gp_slot0_get (insn) == 6875 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld2493gp_slot0_Slot_gp_slot0_get (insn) == 6891 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SET_SAR; + if (Field_dsp340050b49a6c_fld2494gp_slot0_Slot_gp_slot0_get (insn) == 6907 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SET_SMOD_OFFSET_TABLE; + if (Field_dsp340050b49a6c_fld2495gp_slot0_Slot_gp_slot0_get (insn) == 115 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3706gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SMINCLB_C; + if (Field_dsp340050b49a6c_fld2496gp_slot0_Slot_gp_slot0_get (insn) == 137 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_s8_Slot_gp_slot0_get (insn) == 0) + return OPCODE_CONJ; + if (Field_dsp340050b49a6c_fld2497gp_slot0_Slot_gp_slot0_get (insn) == 277 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_EXT32_I; + if (Field_dsp340050b49a6c_fld2498gp_slot0_Slot_gp_slot0_get (insn) == 285 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_EXT_2FIFO_2; + if (Field_dsp340050b49a6c_fld2499gp_slot0_Slot_gp_slot0_get (insn) == 305 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_EXT32_R; + if (Field_dsp340050b49a6c_fld2500gp_slot0_Slot_gp_slot0_get (insn) == 309 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_EXT_2FIFO_3; + if (Field_dsp340050b49a6c_fld2501gp_slot0_Slot_gp_slot0_get (insn) == 313 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_EXT_R2FIFO_0; + if (Field_dsp340050b49a6c_fld2502gp_slot0_Slot_gp_slot0_get (insn) == 317 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_EXT_R2FIFO_1; + if (Field_dsp340050b49a6c_fld2503gp_slot0_Slot_gp_slot0_get (insn) == 337 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_EXT_2FIFO_0; + if (Field_dsp340050b49a6c_fld2504gp_slot0_Slot_gp_slot0_get (insn) == 341 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0) + return OPCODE_EXT_R2FIFO_2; + if (Field_dsp340050b49a6c_fld2505gp_slot0_Slot_gp_slot0_get (insn) == 173 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld2036_Slot_gp_slot0_get (insn) == 0) + return OPCODE_EXT_R2FIFO_3; + if (Field_dsp340050b49a6c_fld2506gp_slot0_Slot_gp_slot0_get (insn) == 93 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3692gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SET_SMOD_BUF; + if (Field_dsp340050b49a6c_fld2507gp_slot0_Slot_gp_slot0_get (insn) == 29 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3700gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_EXT_2FIFO_1; + if (Field_dsp340050b49a6c_fld2508gp_slot0_Slot_gp_slot0_get (insn) == 9 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld2058_Slot_gp_slot0_get (insn) == 0) + return OPCODE_CM2AR_LN; + if (Field_dsp340050b49a6c_fld2509gp_slot0_Slot_gp_slot0_get (insn) == 11 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld2058_Slot_gp_slot0_get (insn) == 0) + return OPCODE_CM2AR_LN_I; + if (Field_dsp340050b49a6c_fld2510gp_slot0_Slot_gp_slot0_get (insn) == 7 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3696gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_CM2AR_LN_R; + if (Field_dsp340050b49a6c_fld2512gp_slot0_Slot_gp_slot0_get (insn) == 6 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SAC_IL; + if (Field_dsp340050b49a6c_fld2514gp_slot0_Slot_gp_slot0_get (insn) == 7 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SAC_RH; + if (Field_dsp340050b49a6c_fld2515gp_slot0_Slot_gp_slot0_get (insn) == 10 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SAC_RL; + if (Field_dsp340050b49a6c_fld2516gp_slot0_Slot_gp_slot0_get (insn) == 16 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SAC_IH; + if (Field_dsp340050b49a6c_fld2517gp_slot0_Slot_gp_slot0_get (insn) == 204 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_POP128_2M_0; + if (Field_dsp340050b49a6c_fld2518gp_slot0_Slot_gp_slot0_get (insn) == 205 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_POP128_2M_1; + if (Field_dsp340050b49a6c_fld2519gp_slot0_Slot_gp_slot0_get (insn) == 206 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_POP128_2M_2; + if (Field_dsp340050b49a6c_fld2520gp_slot0_Slot_gp_slot0_get (insn) == 207 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_POP128_2M_3; + if (Field_dsp340050b49a6c_fld2521gp_slot0_Slot_gp_slot0_get (insn) == 212 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld2530_Slot_gp_slot0_get (insn) == 0) + return OPCODE_ASRAC; + if (Field_dsp340050b49a6c_fld2523gp_slot0_Slot_gp_slot0_get (insn) == 213 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3698gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_MOVAC; + if (Field_dsp340050b49a6c_fld2524gp_slot0_Slot_gp_slot0_get (insn) == 107 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3699gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SWAPAC_RI; + if (Field_dsp340050b49a6c_fld2526gp_slot0_Slot_gp_slot0_get (insn) == 432 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SLL; + if (Field_dsp340050b49a6c_fld2527gp_slot0_Slot_gp_slot0_get (insn) == 433 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld2036_Slot_gp_slot0_get (insn) == 0) + return OPCODE_MOV2AC32_I; + if (Field_dsp340050b49a6c_fld2528gp_slot0_Slot_gp_slot0_get (insn) == 217 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3697gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_MOV2AC32_R; + if (Field_dsp340050b49a6c_fld2529gp_slot0_Slot_gp_slot0_get (insn) == 109 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3702gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_PUSH128; + if (Field_dsp340050b49a6c_fld2531gp_slot0_Slot_gp_slot0_get (insn) == 55 && + Field_op0_s5_Slot_gp_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3691gp_slot0_Slot_gp_slot0_get (insn) == 0) + return OPCODE_SET_LLR_BUF; + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 3) + return OPCODE_EXTUI; + switch (Field_sae_Slot_gp_slot0_get (insn)) + { + case 0: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_MOVNEZ; + break; + case 1: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_MOVT; + break; + case 2: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_OR; + break; + case 3: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SCM; + break; + case 4: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_ORB; + break; + case 5: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SCM_PINC_X; + break; + case 8: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_S32I_N; + break; + case 9: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SCM_XU; + break; + case 10: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_ADD; + break; + case 11: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_ADDX2; + break; + case 12: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_ADDI_N; + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SCM_X; + break; + case 13: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_ADDX4; + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SEXT; + break; + case 14: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_ADDX8; + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SRC; + break; + case 15: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_AND; + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SRLI; + break; + case 18: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SUB; + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_ANDB; + break; + case 19: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_L32I_N; + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SUBX8; + break; + case 20: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SUBX2; + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_CLAMPS; + break; + case 21: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_XOR; + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_LCM_PINC_X; + break; + case 22: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_XORB; + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_LCM_X; + break; + case 23: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_LCM_XU; + break; + case 24: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 2) + return OPCODE_SUBX4; + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_COMB_AR; + break; + case 25: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_MAX; + break; + case 26: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_MAXU; + break; + case 27: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_MINU; + break; + case 28: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_MIN; + break; + case 29: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_MOVEQZ; + break; + case 30: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_MOVGEZ; + break; + case 31: + if (Field_op0_s5_Slot_gp_slot0_get (insn) == 1) + return OPCODE_MOVLTZ; + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_dot_slot0_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2068_Slot_dot_slot0_get (insn)) + { + case 0: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 0) + return OPCODE_ADD; + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 5) + return OPCODE_SUB; + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 1) + return OPCODE_AND; + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 3) + return OPCODE_OR; + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 2) + return OPCODE_LCM_X; + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 4) + return OPCODE_SCM_X; + break; + case 1: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 0) + return OPCODE_ADDI_N; + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 5) + return OPCODE_XOR; + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 1) + return OPCODE_LCM; + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 2) + return OPCODE_LCM_XU; + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 3) + return OPCODE_SCM; + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 4) + return OPCODE_SCM_XU; + break; + } + switch (Field_dsp340050b49a6c_fld2666dot_slot0_Slot_dot_slot0_get (insn)) + { + case 0: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 6) + return OPCODE_EXT; + break; + case 1: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 6) + return OPCODE_EXT_R; + break; + case 2: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 6) + return OPCODE_MOVI_N; + break; + } + if (Field_dsp340050b49a6c_fld2667dot_slot0_Slot_dot_slot0_get (insn) == 6 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 6) + return OPCODE_AR2CM_LN; + switch (Field_dsp340050b49a6c_fld2668dot_slot0_Slot_dot_slot0_get (insn)) + { + case 16: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_EXT_2FIFO_1; + break; + case 17: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_EXT_2FIFO_2; + break; + case 18: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_EXT_2FIFO_3; + break; + case 19: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_EXT_R2FIFO_2; + break; + case 20: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_EXT_R2FIFO_0; + break; + case 21: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_EXT_R2FIFO_3; + break; + case 22: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_MOV_N; + break; + case 23: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_PUSH32; + break; + case 24: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_EXT_R2FIFO_1; + break; + case 27: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld2047_Slot_dot_slot0_get (insn) == 0) + return OPCODE_SMINCLB_R; + break; + case 28: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 6) + return OPCODE_AR2CM_DUP; + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld2047_Slot_dot_slot0_get (insn) == 0) + return OPCODE_MINCLB_C; + break; + case 29: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 7 && + Field_t_Slot_dot_slot0_get (insn) == 0) + return OPCODE_SET_PERM_REG; + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 6) + return OPCODE_EXT32_I; + break; + case 30: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 6) + return OPCODE_EXT32_R; + break; + case 31: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 6) + return OPCODE_EXT_2FIFO_0; + break; + } + if (Field_dsp340050b49a6c_fld2669dot_slot0_Slot_dot_slot0_get (insn) == 0 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_CM2AR_LN; + if (Field_dsp340050b49a6c_fld2671dot_slot0_Slot_dot_slot0_get (insn) == 4 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_CONJ; + if (Field_dsp340050b49a6c_fld2672dot_slot0_Slot_dot_slot0_get (insn) == 5 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_MOV_I; + if (Field_dsp340050b49a6c_fld2673dot_slot0_Slot_dot_slot0_get (insn) == 6 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_MOV_R; + if (Field_dsp340050b49a6c_fld2674dot_slot0_Slot_dot_slot0_get (insn) == 7 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_NEG; + if (Field_dsp340050b49a6c_fld2675dot_slot0_Slot_dot_slot0_get (insn) == 8 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_MOVCM; + if (Field_dsp340050b49a6c_fld2676dot_slot0_Slot_dot_slot0_get (insn) == 9 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_NEGCM; + if (Field_dsp340050b49a6c_fld2677dot_slot0_Slot_dot_slot0_get (insn) == 10 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_SRA; + if (Field_dsp340050b49a6c_fld2678dot_slot0_Slot_dot_slot0_get (insn) == 11 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_GET_HSAR; + if (Field_dsp340050b49a6c_fld2679dot_slot0_Slot_dot_slot0_get (insn) == 27 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_GET_HSAR2SAR; + if (Field_dsp340050b49a6c_fld2680dot_slot0_Slot_dot_slot0_get (insn) == 43 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_GET_SAR; + if (Field_dsp340050b49a6c_fld2681dot_slot0_Slot_dot_slot0_get (insn) == 59 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld2682dot_slot0_Slot_dot_slot0_get (insn) == 75 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld2683dot_slot0_Slot_dot_slot0_get (insn) == 91 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld2684dot_slot0_Slot_dot_slot0_get (insn) == 107 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_POP128_4; + if (Field_dsp340050b49a6c_fld2685dot_slot0_Slot_dot_slot0_get (insn) == 123 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld2686dot_slot0_Slot_dot_slot0_get (insn) == 43 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld3736_Slot_dot_slot0_get (insn) == 0) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld2688dot_slot0_Slot_dot_slot0_get (insn) == 59 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld3735dot_slot0_Slot_dot_slot0_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld2689dot_slot0_Slot_dot_slot0_get (insn) == 12 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7 && + Field_r_Slot_dot_slot0_get (insn) == 0) + return OPCODE_CLRCM; + if (Field_dsp340050b49a6c_fld2690dot_slot0_Slot_dot_slot0_get (insn) == 13 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_GET_PERM_REG; + if (Field_dsp340050b49a6c_fld2692dot_slot0_Slot_dot_slot0_get (insn) == 29 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld2693dot_slot0_Slot_dot_slot0_get (insn) == 29 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld2705dot_slot0_Slot_dot_slot0_get (insn) == 0) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld2695dot_slot0_Slot_dot_slot0_get (insn) == 29 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld3741dot_slot0_Slot_dot_slot0_get (insn) == 0) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld2697dot_slot0_Slot_dot_slot0_get (insn) == 29 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld3738dot_slot0_Slot_dot_slot0_get (insn) == 0) + return OPCODE_SET_SAR; + if (Field_dsp340050b49a6c_fld2699dot_slot0_Slot_dot_slot0_get (insn) == 7 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld3740dot_slot0_Slot_dot_slot0_get (insn) == 0) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld2700dot_slot0_Slot_dot_slot0_get (insn) == 50 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_CLB_C; + if (Field_dsp340050b49a6c_fld2701dot_slot0_Slot_dot_slot0_get (insn) == 51 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_MINCLB_R; + if (Field_dsp340050b49a6c_fld2702dot_slot0_Slot_dot_slot0_get (insn) == 52 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_CLB_R; + if (Field_dsp340050b49a6c_fld2703dot_slot0_Slot_dot_slot0_get (insn) == 53 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7) + return OPCODE_SMINCLB_C; + if (Field_dsp340050b49a6c_fld2704dot_slot0_Slot_dot_slot0_get (insn) == 15 && + Field_op0_s8_Slot_dot_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld3739dot_slot0_Slot_dot_slot0_get (insn) == 0) + return OPCODE_CLRAC; + switch (Field_dsp340050b49a6c_fld2705dot_slot0_Slot_dot_slot0_get (insn)) + { + case 0: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 8 && + Field_dsp340050b49a6c_fld3737dot_slot0_Slot_dot_slot0_get (insn) == 0) + return OPCODE_SLL; + break; + case 1: + if (Field_op0_s8_Slot_dot_slot0_get (insn) == 8 && + Field_dsp340050b49a6c_fld3742dot_slot0_Slot_dot_slot0_get (insn) == 0) + return OPCODE_PUSH128; + break; + } + switch (Field_op0_s8_Slot_dot_slot0_get (insn)) + { + case 9: + return OPCODE_LCM_U; + case 10: + return OPCODE_SCM_U; + case 11: + return OPCODE_SLLI; + case 12: + return OPCODE_SRAI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_pq_slot2_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2706pq_slot2_Slot_pq_slot2_get (insn)) + { + case 44: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_AR2CM_LN; + break; + case 47: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3752pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_CLRTIEP; + break; + } + switch (Field_dsp340050b49a6c_fld2707pq_slot2_Slot_pq_slot2_get (insn)) + { + case 180: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_ADDAR2; + break; + case 181: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_PUSH128_PQ; + break; + case 182: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_PUSH32; + break; + case 183: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SET_EXT_REGS; + break; + case 184: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOV_N; + break; + case 185: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SUBARX; + break; + case 186: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_WRTIEP; + break; + } + switch (Field_dsp340050b49a6c_fld2708pq_slot2_Slot_pq_slot2_get (insn)) + { + case 1496: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SETTIEP; + break; + case 1497: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_WRTBSIGQM; + break; + } + switch (Field_dsp340050b49a6c_fld2709pq_slot2_Slot_pq_slot2_get (insn)) + { + case 2996: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_AR2SAR_DUP; + break; + case 2997: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_WRTSIGQ; + break; + case 2999: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0 && + Field_s_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_5; + break; + } + switch (Field_dsp340050b49a6c_fld2710pq_slot2_Slot_pq_slot2_get (insn)) + { + case 47968: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_0; + break; + case 47969: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_1; + break; + case 47970: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_2; + break; + case 47971: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_0; + break; + case 47972: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_3; + break; + case 47973: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_1; + break; + case 47974: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_2; + break; + case 47975: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_3; + break; + } + if (Field_dsp340050b49a6c_fld2711pq_slot2_Slot_pq_slot2_get (insn) == 11994 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3745pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_4; + if (Field_dsp340050b49a6c_fld2713pq_slot2_Slot_pq_slot2_get (insn) == 11995 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3745pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld2714pq_slot2_Slot_pq_slot2_get (insn) == 375 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2819_Slot_pq_slot2_get (insn) == 0) + return OPCODE_WRTBSIGQ; + if (Field_dsp340050b49a6c_fld2715pq_slot2_Slot_pq_slot2_get (insn) == 52 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_CM2AR_LN; + if (Field_dsp340050b49a6c_fld2717pq_slot2_Slot_pq_slot2_get (insn) == 212 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_ABS; + if (Field_dsp340050b49a6c_fld2718pq_slot2_Slot_pq_slot2_get (insn) == 213 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SRA; + if (Field_dsp340050b49a6c_fld2719pq_slot2_Slot_pq_slot2_get (insn) == 3334 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_CLRCM; + if (Field_dsp340050b49a6c_fld2721pq_slot2_Slot_pq_slot2_get (insn) == 3335 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_GET_ARGMAX; + if (Field_dsp340050b49a6c_fld2722pq_slot2_Slot_pq_slot2_get (insn) == 3350 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_GET_HSAR; + if (Field_dsp340050b49a6c_fld2723pq_slot2_Slot_pq_slot2_get (insn) == 3351 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_GET_SAR; + if (Field_dsp340050b49a6c_fld2724pq_slot2_Slot_pq_slot2_get (insn) == 3366 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_GET_HSAR2SAR; + if (Field_dsp340050b49a6c_fld2725pq_slot2_Slot_pq_slot2_get (insn) == 3367 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld2726pq_slot2_Slot_pq_slot2_get (insn) == 3382 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld2727pq_slot2_Slot_pq_slot2_get (insn) == 3383 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld2728pq_slot2_Slot_pq_slot2_get (insn) == 3398 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_GET_MAX; + if (Field_dsp340050b49a6c_fld2729pq_slot2_Slot_pq_slot2_get (insn) == 3399 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld2730pq_slot2_Slot_pq_slot2_get (insn) == 3414 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_POP128_4; + if (Field_dsp340050b49a6c_fld2731pq_slot2_Slot_pq_slot2_get (insn) == 3415 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld2732pq_slot2_Slot_pq_slot2_get (insn) == 3430 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld2733pq_slot2_Slot_pq_slot2_get (insn) == 3431 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld2734pq_slot2_Slot_pq_slot2_get (insn) == 3446 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld2735pq_slot2_Slot_pq_slot2_get (insn) == 3447 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld2736pq_slot2_Slot_pq_slot2_get (insn) == 438 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2819_Slot_pq_slot2_get (insn) == 0) + return OPCODE_GET_NCO; + if (Field_dsp340050b49a6c_fld2738pq_slot2_Slot_pq_slot2_get (insn) == 439 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2819_Slot_pq_slot2_get (insn) == 0) + return OPCODE_RDTIEP; + if (Field_dsp340050b49a6c_fld2739pq_slot2_Slot_pq_slot2_get (insn) == 27 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3744pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_NEG; + if (Field_dsp340050b49a6c_fld2741pq_slot2_Slot_pq_slot2_get (insn) == 112 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_PQ2CM; + if (Field_dsp340050b49a6c_fld2742pq_slot2_Slot_pq_slot2_get (insn) == 113 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_QREADY; + if (Field_dsp340050b49a6c_fld2743pq_slot2_Slot_pq_slot2_get (insn) == 114 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3750pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_AR2CM_DUP; + if (Field_dsp340050b49a6c_fld2746pq_slot2_Slot_pq_slot2_get (insn) == 115 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3750pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SWAPB; + if (Field_dsp340050b49a6c_fld2747pq_slot2_Slot_pq_slot2_get (insn) == 29 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2819_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVAR2; + if (Field_dsp340050b49a6c_fld2748pq_slot2_Slot_pq_slot2_get (insn) == 16 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_ADD32; + if (Field_dsp340050b49a6c_fld2750pq_slot2_Slot_pq_slot2_get (insn) == 17 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_ADDCM; + if (Field_dsp340050b49a6c_fld2751pq_slot2_Slot_pq_slot2_get (insn) == 18 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_ADDWRP; + if (Field_dsp340050b49a6c_fld2752pq_slot2_Slot_pq_slot2_get (insn) == 19 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_ASR; + if (Field_dsp340050b49a6c_fld2753pq_slot2_Slot_pq_slot2_get (insn) == 20 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_AND128; + if (Field_dsp340050b49a6c_fld2754pq_slot2_Slot_pq_slot2_get (insn) == 21 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_EXTUI4; + if (Field_dsp340050b49a6c_fld2755pq_slot2_Slot_pq_slot2_get (insn) == 22 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_LUT; + if (Field_dsp340050b49a6c_fld2756pq_slot2_Slot_pq_slot2_get (insn) == 23 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_LUT_IEXT; + if (Field_dsp340050b49a6c_fld2757pq_slot2_Slot_pq_slot2_get (insn) == 24 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_ASL; + if (Field_dsp340050b49a6c_fld2758pq_slot2_Slot_pq_slot2_get (insn) == 25 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_LUT_REXT; + if (Field_dsp340050b49a6c_fld2759pq_slot2_Slot_pq_slot2_get (insn) == 26 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MAX8; + if (Field_dsp340050b49a6c_fld2760pq_slot2_Slot_pq_slot2_get (insn) == 27 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MEAN32; + if (Field_dsp340050b49a6c_fld2761pq_slot2_Slot_pq_slot2_get (insn) == 28 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MEAN; + if (Field_dsp340050b49a6c_fld2762pq_slot2_Slot_pq_slot2_get (insn) == 29 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MIN8; + if (Field_dsp340050b49a6c_fld2763pq_slot2_Slot_pq_slot2_get (insn) == 30 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_OR128; + if (Field_dsp340050b49a6c_fld2764pq_slot2_Slot_pq_slot2_get (insn) == 31 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SUB32; + if (Field_dsp340050b49a6c_fld2765pq_slot2_Slot_pq_slot2_get (insn) == 0 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_ASL32; + if (Field_dsp340050b49a6c_fld2766pq_slot2_Slot_pq_slot2_get (insn) == 1 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_ASR32; + if (Field_dsp340050b49a6c_fld2767pq_slot2_Slot_pq_slot2_get (insn) == 2 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND8_0; + if (Field_dsp340050b49a6c_fld2768pq_slot2_Slot_pq_slot2_get (insn) == 3 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND8_3; + if (Field_dsp340050b49a6c_fld2769pq_slot2_Slot_pq_slot2_get (insn) == 4 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND8_1; + if (Field_dsp340050b49a6c_fld2770pq_slot2_Slot_pq_slot2_get (insn) == 5 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND8_4; + if (Field_dsp340050b49a6c_fld2771pq_slot2_Slot_pq_slot2_get (insn) == 6 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND8_5; + if (Field_dsp340050b49a6c_fld2772pq_slot2_Slot_pq_slot2_get (insn) == 7 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND8_6; + if (Field_dsp340050b49a6c_fld2773pq_slot2_Slot_pq_slot2_get (insn) == 8 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND8_2; + if (Field_dsp340050b49a6c_fld2774pq_slot2_Slot_pq_slot2_get (insn) == 9 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND8_7; + if (Field_dsp340050b49a6c_fld2775pq_slot2_Slot_pq_slot2_get (insn) == 10 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND_0; + if (Field_dsp340050b49a6c_fld2776pq_slot2_Slot_pq_slot2_get (insn) == 11 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND_2; + if (Field_dsp340050b49a6c_fld2777pq_slot2_Slot_pq_slot2_get (insn) == 12 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND_1; + if (Field_dsp340050b49a6c_fld2778pq_slot2_Slot_pq_slot2_get (insn) == 13 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND_3; + if (Field_dsp340050b49a6c_fld2779pq_slot2_Slot_pq_slot2_get (insn) == 14 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND_4; + if (Field_dsp340050b49a6c_fld2780pq_slot2_Slot_pq_slot2_get (insn) == 15 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCND_5; + if (Field_dsp340050b49a6c_fld2781pq_slot2_Slot_pq_slot2_get (insn) == 16 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_ASLM; + if (Field_dsp340050b49a6c_fld2782pq_slot2_Slot_pq_slot2_get (insn) == 17 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_ASRM; + if (Field_dsp340050b49a6c_fld2783pq_slot2_Slot_pq_slot2_get (insn) == 18 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_CMP8; + if (Field_dsp340050b49a6c_fld2784pq_slot2_Slot_pq_slot2_get (insn) == 19 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_LSLM; + if (Field_dsp340050b49a6c_fld2785pq_slot2_Slot_pq_slot2_get (insn) == 20 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_CMP_I; + if (Field_dsp340050b49a6c_fld2786pq_slot2_Slot_pq_slot2_get (insn) == 21 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_LSRM; + if (Field_dsp340050b49a6c_fld2787pq_slot2_Slot_pq_slot2_get (insn) == 262 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_ABS8; + if (Field_dsp340050b49a6c_fld2788pq_slot2_Slot_pq_slot2_get (insn) == 263 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_CONJ; + if (Field_dsp340050b49a6c_fld2789pq_slot2_Slot_pq_slot2_get (insn) == 278 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_LUT_PHASOR; + if (Field_dsp340050b49a6c_fld2790pq_slot2_Slot_pq_slot2_get (insn) == 279 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_NOT128; + if (Field_dsp340050b49a6c_fld2791pq_slot2_Slot_pq_slot2_get (insn) == 294 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_MOVCM; + if (Field_dsp340050b49a6c_fld2792pq_slot2_Slot_pq_slot2_get (insn) == 295 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1) + return OPCODE_TRANS; + if (Field_dsp340050b49a6c_fld2793pq_slot2_Slot_pq_slot2_get (insn) == 2102 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2817_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SET_ARGMAX; + if (Field_dsp340050b49a6c_fld2795pq_slot2_Slot_pq_slot2_get (insn) == 2103 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2817_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SET_HSAR; + if (Field_dsp340050b49a6c_fld2796pq_slot2_Slot_pq_slot2_get (insn) == 1179 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3746pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SET_MAX; + if (Field_dsp340050b49a6c_fld2798pq_slot2_Slot_pq_slot2_get (insn) == 667 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3747pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SET_NCO; + if (Field_dsp340050b49a6c_fld2801pq_slot2_Slot_pq_slot2_get (insn) == 411 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3749pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SET_SAR; + if (Field_dsp340050b49a6c_fld2803pq_slot2_Slot_pq_slot2_get (insn) == 43 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3754pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_NCO_UPDATE; + if (Field_dsp340050b49a6c_fld2805pq_slot2_Slot_pq_slot2_get (insn) == 27 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3751pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_NEGCM; + if (Field_dsp340050b49a6c_fld2806pq_slot2_Slot_pq_slot2_get (insn) == 12 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2025_Slot_pq_slot2_get (insn) == 0) + return OPCODE_CMP_R; + if (Field_dsp340050b49a6c_fld2807pq_slot2_Slot_pq_slot2_get (insn) == 13 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3756pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_PUSH128; + if (Field_dsp340050b49a6c_fld2808pq_slot2_Slot_pq_slot2_get (insn) == 11 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3757pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_ADD16; + if (Field_dsp340050b49a6c_fld2809pq_slot2_Slot_pq_slot2_get (insn) == 15 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3753pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_LUT_WRITE; + if (Field_dsp340050b49a6c_fld2810pq_slot2_Slot_pq_slot2_get (insn) == 0 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 2) + return OPCODE_MOVCND_6; + if (Field_dsp340050b49a6c_fld2811pq_slot2_Slot_pq_slot2_get (insn) == 1 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 2) + return OPCODE_MOVCND_7; + if (Field_dsp340050b49a6c_fld2812pq_slot2_Slot_pq_slot2_get (insn) == 1 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3748_Slot_pq_slot2_get (insn) == 0) + return OPCODE_PERM; + if (Field_dsp340050b49a6c_fld2814pq_slot2_Slot_pq_slot2_get (insn) == 1 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3758pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_ASLM32; + if (Field_dsp340050b49a6c_fld2816pq_slot2_Slot_pq_slot2_get (insn) == 1 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 2 && + Field_imm7_Slot_pq_slot2_get (insn) == 0) + return OPCODE_ARGMAX8; + if (Field_dsp340050b49a6c_fld2818pq_slot2_Slot_pq_slot2_get (insn) == 8 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld2737_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SUBCM; + if (Field_dsp340050b49a6c_fld2820pq_slot2_Slot_pq_slot2_get (insn) == 9 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld2737_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SUBMEAN; + if (Field_dsp340050b49a6c_fld2821pq_slot2_Slot_pq_slot2_get (insn) == 5 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3759pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SUBWRP; + if (Field_dsp340050b49a6c_fld2823pq_slot2_Slot_pq_slot2_get (insn) == 3 && + Field_op0_s9_Slot_pq_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3760pq_slot2_Slot_pq_slot2_get (insn) == 0) + return OPCODE_XOR128; + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 3) + return OPCODE_EXTUI; + switch (Field_sae_Slot_pq_slot2_get (insn)) + { + case 0: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_ADD; + break; + case 1: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_ADDI_N; + break; + case 2: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_AND; + break; + case 3: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVGEZ; + break; + case 4: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_LUT_AR; + break; + case 5: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVLTZ; + break; + case 6: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVNEZ; + break; + case 7: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_OR; + break; + case 8: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVEQZ; + break; + case 9: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SUB; + break; + case 10: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0) + return OPCODE_XOR; + break; + case 12: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2817_Slot_pq_slot2_get (insn) == 0) + return OPCODE_MOVI_N; + break; + case 15: + if (Field_op0_s9_Slot_pq_slot2_get (insn) == 0 && + Field_t_Slot_pq_slot2_get (insn) == 0) + return OPCODE_SLL; + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_pq_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_dsp340050b49a6c_fld2827pq_slot0_Slot_pq_slot0_get (insn) == 0 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_LAC2X32; + if (Field_dsp340050b49a6c_fld2829pq_slot0_Slot_pq_slot0_get (insn) == 1 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_LAC32_R; + if (Field_dsp340050b49a6c_fld2830pq_slot0_Slot_pq_slot0_get (insn) == 2 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_LAC_IH; + if (Field_dsp340050b49a6c_fld2831pq_slot0_Slot_pq_slot0_get (insn) == 3 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_LAC_RH; + if (Field_dsp340050b49a6c_fld2832pq_slot0_Slot_pq_slot0_get (insn) == 10 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_LAC_RL; + if (Field_dsp340050b49a6c_fld2833pq_slot0_Slot_pq_slot0_get (insn) == 11 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_LAC2X64_0; + if (Field_dsp340050b49a6c_fld2835pq_slot0_Slot_pq_slot0_get (insn) == 27 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_LAC2X64_1; + if (Field_dsp340050b49a6c_fld2836pq_slot0_Slot_pq_slot0_get (insn) == 4 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_LAC_IL; + if (Field_dsp340050b49a6c_fld2837pq_slot0_Slot_pq_slot0_get (insn) == 5 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_LAC2X64_2; + switch (Field_dsp340050b49a6c_fld2838pq_slot0_Slot_pq_slot0_get (insn)) + { + case 21: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_AR2CM_DUP; + break; + case 53: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_MOV_N; + break; + case 85: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_NSA; + break; + case 117: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_PUSH32; + break; + case 149: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_NSAU; + break; + } + if (Field_dsp340050b49a6c_fld2839pq_slot0_Slot_pq_slot0_get (insn) == 362 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_LLR_BUF; + if (Field_dsp340050b49a6c_fld2840pq_slot0_Slot_pq_slot0_get (insn) == 1452 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_ANY8; + if (Field_dsp340050b49a6c_fld2842pq_slot0_Slot_pq_slot0_get (insn) == 1453 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_SMOD_BUF; + if (Field_dsp340050b49a6c_fld2843pq_slot0_Slot_pq_slot0_get (insn) == 2908 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_CLRCM; + if (Field_dsp340050b49a6c_fld2844pq_slot0_Slot_pq_slot0_get (insn) == 2909 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_HSAR; + if (Field_dsp340050b49a6c_fld2845pq_slot0_Slot_pq_slot0_get (insn) == 2910 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_HSAR2SAR; + if (Field_dsp340050b49a6c_fld2846pq_slot0_Slot_pq_slot0_get (insn) == 2911 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_SAR; + if (Field_dsp340050b49a6c_fld2847pq_slot0_Slot_pq_slot0_get (insn) == 852 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_ANY4; + if (Field_dsp340050b49a6c_fld2849pq_slot0_Slot_pq_slot0_get (insn) == 3412 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_SMOD_OFFSET_TABLE; + if (Field_dsp340050b49a6c_fld2850pq_slot0_Slot_pq_slot0_get (insn) == 3413 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld2851pq_slot0_Slot_pq_slot0_get (insn) == 3414 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld2852pq_slot0_Slot_pq_slot0_get (insn) == 3415 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld2853pq_slot0_Slot_pq_slot0_get (insn) == 3416 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld2854pq_slot0_Slot_pq_slot0_get (insn) == 3417 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP128_4; + if (Field_dsp340050b49a6c_fld2855pq_slot0_Slot_pq_slot0_get (insn) == 1709 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_s8_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld2856pq_slot0_Slot_pq_slot0_get (insn) == 855 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3765pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld2857pq_slot0_Slot_pq_slot0_get (insn) == 1960 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SSAI; + switch (Field_dsp340050b49a6c_fld2858pq_slot0_Slot_pq_slot0_get (insn)) + { + case 3922: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SET_LLR_POS; + break; + case 3923: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SET_PHASOR_OFFSET; + break; + case 3924: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SET_PERM_REG; + break; + case 3925: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SET_SCALE_REG; + break; + case 3926: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SET_SMOD_POS; + break; + case 3927: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SET_SOV; + break; + case 3928: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SET_PHASOR_N; + break; + case 3929: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SET_WGHT; + break; + case 3930: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SSA8B; + break; + case 3931: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SSL; + break; + case 3932: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SSA8L; + break; + case 3933: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SSR; + break; + } + if (Field_dsp340050b49a6c_fld2859pq_slot0_Slot_pq_slot0_get (insn) == 3934 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld2940_Slot_pq_slot0_get (insn) == 0) + return OPCODE_CLRAC; + if (Field_dsp340050b49a6c_fld2860pq_slot0_Slot_pq_slot0_get (insn) == 3935 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld2940_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP16LLR_1; + if (Field_dsp340050b49a6c_fld2861pq_slot0_Slot_pq_slot0_get (insn) == 3 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3768pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_LAC2X64_3; + switch (Field_dsp340050b49a6c_fld2863pq_slot0_Slot_pq_slot0_get (insn)) + { + case 3: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_AR2CM_LN; + break; + case 7: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_AR2CM_LN_I; + break; + } + if (Field_dsp340050b49a6c_fld2864pq_slot0_Slot_pq_slot0_get (insn) == 7 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld2069_Slot_pq_slot0_get (insn) == 0) + return OPCODE_AR2CM_LN_R; + switch (Field_dsp340050b49a6c_fld2865_Slot_pq_slot0_get (insn)) + { + case 0: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_SAC2X32; + break; + case 1: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_SAC32_R; + break; + case 2: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_SCM_PINC; + break; + case 3: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_SRAI; + break; + case 4: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_SCM_U; + break; + case 8: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_SLLI; + break; + } + if (Field_dsp340050b49a6c_fld2867pq_slot0_Slot_pq_slot0_get (insn) == 7 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3763pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_dsp340050b49a6c_fld2869pq_slot0_Slot_pq_slot0_get (insn) == 7 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3764pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_BNEZ_N; + if (Field_dsp340050b49a6c_fld2871pq_slot0_Slot_pq_slot0_get (insn) == 8 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_LCM_PINC; + if (Field_dsp340050b49a6c_fld2872pq_slot0_Slot_pq_slot0_get (insn) == 9 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_LCM_U; + if (Field_dsp340050b49a6c_fld2873pq_slot0_Slot_pq_slot0_get (insn) == 18 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_LCM; + if (Field_dsp340050b49a6c_fld2874pq_slot0_Slot_pq_slot0_get (insn) == 259 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_ABS; + if (Field_dsp340050b49a6c_fld2875pq_slot0_Slot_pq_slot0_get (insn) == 267 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_MOVCM; + if (Field_dsp340050b49a6c_fld2876pq_slot0_Slot_pq_slot0_get (insn) == 291 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_MOV_I; + if (Field_dsp340050b49a6c_fld2877pq_slot0_Slot_pq_slot0_get (insn) == 299 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_NEGCM; + if (Field_dsp340050b49a6c_fld2878pq_slot0_Slot_pq_slot0_get (insn) == 323 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_MOV_R; + if (Field_dsp340050b49a6c_fld2879pq_slot0_Slot_pq_slot0_get (insn) == 331 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SRA; + if (Field_dsp340050b49a6c_fld2880pq_slot0_Slot_pq_slot0_get (insn) == 355 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SRL; + if (Field_dsp340050b49a6c_fld2881pq_slot0_Slot_pq_slot0_get (insn) == 715 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_CLB_C; + switch (Field_dsp340050b49a6c_fld2882_Slot_pq_slot0_get (insn)) + { + case 21: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_EXT; + break; + case 23: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_EXT_R; + break; + case 33: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_MOVI_N; + break; + case 35: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_PUSH128_M; + break; + case 52: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SAC2X64_0; + break; + case 53: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SAC2X64_2; + break; + case 54: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SAC2X64_3; + break; + case 56: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SAC2X64_1; + break; + } + if (Field_dsp340050b49a6c_fld2883pq_slot0_Slot_pq_slot0_get (insn) == 731 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_CLB_R; + if (Field_dsp340050b49a6c_fld2884pq_slot0_Slot_pq_slot0_get (insn) == 387 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_NEG; + if (Field_dsp340050b49a6c_fld2885pq_slot0_Slot_pq_slot0_get (insn) == 779 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_MINCLB_C; + if (Field_dsp340050b49a6c_fld2886pq_slot0_Slot_pq_slot0_get (insn) == 795 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SMINCLB_R; + if (Field_dsp340050b49a6c_fld2887pq_slot0_Slot_pq_slot0_get (insn) == 835 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_MINCLB_R; + if (Field_dsp340050b49a6c_fld2888pq_slot0_Slot_pq_slot0_get (insn) == 13571 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_ADDAC_I2R; + if (Field_dsp340050b49a6c_fld2890pq_slot0_Slot_pq_slot0_get (insn) == 13587 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_ADDAC_R2I; + if (Field_dsp340050b49a6c_fld2891pq_slot0_Slot_pq_slot0_get (insn) == 13603 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_REDAC; + if (Field_dsp340050b49a6c_fld2892pq_slot0_Slot_pq_slot0_get (insn) == 13619 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_REDACS; + if (Field_dsp340050b49a6c_fld2893pq_slot0_Slot_pq_slot0_get (insn) == 13635 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_REDAC2; + if (Field_dsp340050b49a6c_fld2894pq_slot0_Slot_pq_slot0_get (insn) == 13651 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SUBAC_I2R; + if (Field_dsp340050b49a6c_fld2895pq_slot0_Slot_pq_slot0_get (insn) == 6835 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld2940_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SUBAC_R2I; + if (Field_dsp340050b49a6c_fld2897pq_slot0_Slot_pq_slot0_get (insn) == 1715 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3779pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_REDAC4; + if (Field_dsp340050b49a6c_fld2899pq_slot0_Slot_pq_slot0_get (insn) == 6667 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_INTERP_EXT_L; + if (Field_dsp340050b49a6c_fld2900pq_slot0_Slot_pq_slot0_get (insn) == 6683 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_INTERP_EXT_N; + if (Field_dsp340050b49a6c_fld2901pq_slot0_Slot_pq_slot0_get (insn) == 6699 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_LLR_POS; + if (Field_dsp340050b49a6c_fld2902pq_slot0_Slot_pq_slot0_get (insn) == 6715 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_PHASOR_OFFSET; + if (Field_dsp340050b49a6c_fld2903pq_slot0_Slot_pq_slot0_get (insn) == 6731 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_PERM_REG; + if (Field_dsp340050b49a6c_fld2904pq_slot0_Slot_pq_slot0_get (insn) == 6747 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_SCALE_REG; + if (Field_dsp340050b49a6c_fld2905pq_slot0_Slot_pq_slot0_get (insn) == 6763 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_SMOD_POS; + if (Field_dsp340050b49a6c_fld2906pq_slot0_Slot_pq_slot0_get (insn) == 6779 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_SOV; + if (Field_dsp340050b49a6c_fld2907pq_slot0_Slot_pq_slot0_get (insn) == 6795 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_PHASOR_N; + if (Field_dsp340050b49a6c_fld2908pq_slot0_Slot_pq_slot0_get (insn) == 6811 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_GET_WGHT; + if (Field_dsp340050b49a6c_fld2909pq_slot0_Slot_pq_slot0_get (insn) == 6827 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld2910pq_slot0_Slot_pq_slot0_get (insn) == 6843 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld2911pq_slot0_Slot_pq_slot0_get (insn) == 6859 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld2912pq_slot0_Slot_pq_slot0_get (insn) == 6875 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld2913pq_slot0_Slot_pq_slot0_get (insn) == 6891 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SET_SAR; + if (Field_dsp340050b49a6c_fld2914pq_slot0_Slot_pq_slot0_get (insn) == 6907 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SET_SMOD_OFFSET_TABLE; + if (Field_dsp340050b49a6c_fld2915pq_slot0_Slot_pq_slot0_get (insn) == 115 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3780pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SMINCLB_C; + if (Field_dsp340050b49a6c_fld2916pq_slot0_Slot_pq_slot0_get (insn) == 137 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_s8_Slot_pq_slot0_get (insn) == 0) + return OPCODE_CONJ; + if (Field_dsp340050b49a6c_fld2917pq_slot0_Slot_pq_slot0_get (insn) == 277 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_EXT32_I; + if (Field_dsp340050b49a6c_fld2918pq_slot0_Slot_pq_slot0_get (insn) == 285 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_EXT_2FIFO_2; + if (Field_dsp340050b49a6c_fld2919pq_slot0_Slot_pq_slot0_get (insn) == 305 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_EXT32_R; + if (Field_dsp340050b49a6c_fld2920pq_slot0_Slot_pq_slot0_get (insn) == 309 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_EXT_2FIFO_3; + if (Field_dsp340050b49a6c_fld2921pq_slot0_Slot_pq_slot0_get (insn) == 313 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_EXT_R2FIFO_0; + if (Field_dsp340050b49a6c_fld2922pq_slot0_Slot_pq_slot0_get (insn) == 317 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_EXT_R2FIFO_1; + if (Field_dsp340050b49a6c_fld2923pq_slot0_Slot_pq_slot0_get (insn) == 337 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_EXT_2FIFO_0; + if (Field_dsp340050b49a6c_fld2924pq_slot0_Slot_pq_slot0_get (insn) == 341 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0) + return OPCODE_EXT_R2FIFO_2; + if (Field_dsp340050b49a6c_fld2925pq_slot0_Slot_pq_slot0_get (insn) == 173 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld2036_Slot_pq_slot0_get (insn) == 0) + return OPCODE_EXT_R2FIFO_3; + if (Field_dsp340050b49a6c_fld2926pq_slot0_Slot_pq_slot0_get (insn) == 93 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3767pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SET_SMOD_BUF; + if (Field_dsp340050b49a6c_fld2927pq_slot0_Slot_pq_slot0_get (insn) == 29 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3773pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_EXT_2FIFO_1; + if (Field_dsp340050b49a6c_fld2928pq_slot0_Slot_pq_slot0_get (insn) == 9 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld2059_Slot_pq_slot0_get (insn) == 0) + return OPCODE_CM2AR_LN; + if (Field_dsp340050b49a6c_fld2929pq_slot0_Slot_pq_slot0_get (insn) == 11 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld2059_Slot_pq_slot0_get (insn) == 0) + return OPCODE_CM2AR_LN_I; + if (Field_dsp340050b49a6c_fld2930pq_slot0_Slot_pq_slot0_get (insn) == 7 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3769pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_CM2AR_LN_R; + if (Field_dsp340050b49a6c_fld2932pq_slot0_Slot_pq_slot0_get (insn) == 6 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SAC_IL; + if (Field_dsp340050b49a6c_fld2934pq_slot0_Slot_pq_slot0_get (insn) == 7 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SAC_RH; + if (Field_dsp340050b49a6c_fld2935pq_slot0_Slot_pq_slot0_get (insn) == 10 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SAC_RL; + if (Field_dsp340050b49a6c_fld2936pq_slot0_Slot_pq_slot0_get (insn) == 16 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SAC_IH; + if (Field_dsp340050b49a6c_fld2937pq_slot0_Slot_pq_slot0_get (insn) == 220 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_ASLACM; + if (Field_dsp340050b49a6c_fld2939pq_slot0_Slot_pq_slot0_get (insn) == 442 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3772_Slot_pq_slot0_get (insn) == 0) + return OPCODE_ASRAC; + if (Field_dsp340050b49a6c_fld2941pq_slot0_Slot_pq_slot0_get (insn) == 443 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3771pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SWAPAC_RI; + if (Field_dsp340050b49a6c_fld2942pq_slot0_Slot_pq_slot0_get (insn) == 111 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3766pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_MOVAC; + if (Field_dsp340050b49a6c_fld2943pq_slot0_Slot_pq_slot0_get (insn) == 114 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3775pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP128_2M_0; + if (Field_dsp340050b49a6c_fld2945pq_slot0_Slot_pq_slot0_get (insn) == 115 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3775pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP128_2M_3; + if (Field_dsp340050b49a6c_fld2946pq_slot0_Slot_pq_slot0_get (insn) == 496 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SLL; + if (Field_dsp340050b49a6c_fld2947pq_slot0_Slot_pq_slot0_get (insn) == 497 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld2036_Slot_pq_slot0_get (insn) == 0) + return OPCODE_MOV2AC32_I; + if (Field_dsp340050b49a6c_fld2948pq_slot0_Slot_pq_slot0_get (insn) == 249 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3770pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_MOV2AC32_R; + if (Field_dsp340050b49a6c_fld2949pq_slot0_Slot_pq_slot0_get (insn) == 125 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3778pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_PUSH128; + if (Field_dsp340050b49a6c_fld2950pq_slot0_Slot_pq_slot0_get (insn) == 63 && + Field_op0_s11_Slot_pq_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3766pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_SET_LLR_BUF; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 3) + return OPCODE_EXTUI; + switch (Field_sae_Slot_pq_slot0_get (insn)) + { + case 0: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_MOVNEZ; + break; + case 1: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_MOVT; + break; + case 2: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_OR; + break; + case 3: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SCM; + break; + case 4: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_ORB; + break; + case 5: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SCM_PINC_X; + break; + case 8: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_S32I_N; + break; + case 9: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SCM_XU; + break; + case 10: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_ADD; + break; + case 11: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_ADDX2; + break; + case 12: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_ADDI_N; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SCM_X; + break; + case 13: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_ADDX4; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SEXT; + break; + case 14: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_ADDX8; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SRC; + break; + case 15: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_AND; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SRLI; + break; + case 18: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_ANDB; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_STORE_P; + break; + case 19: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_L32I_N; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SUBX2; + break; + case 20: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_CLAMPS; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_STORE_Q; + break; + case 21: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SUBX4; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_LCM_PINC_X; + break; + case 22: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SUBX8; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_LCM_X; + break; + case 23: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_XOR; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_LCM_XU; + break; + case 24: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_SUB; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_COMB_AR; + break; + case 25: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2) + return OPCODE_XORB; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_MAX; + break; + case 26: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_MAXU; + break; + case 27: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_MINU; + break; + case 28: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_MIN; + break; + case 29: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_MOVEQZ; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3776pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP128_2M_1; + break; + case 30: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_MOVGEZ; + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3777pq_slot0_Slot_pq_slot0_get (insn) == 0) + return OPCODE_POP128_2M_2; + break; + case 31: + if (Field_op0_s11_Slot_pq_slot0_get (insn) == 1) + return OPCODE_MOVLTZ; + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_acc2_slot0_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2047_Slot_acc2_slot0_get (insn)) + { + case 0: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3795acc2_slot0_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_NEG; + break; + case 1: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld2039_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_PUSH128; + break; + } + if (Field_dsp340050b49a6c_fld2056_Slot_acc2_slot0_get (insn) == 0 && + Field_op0_s14_Slot_acc2_slot0_get (insn) == 1) + return OPCODE_MOVCM2PQ; + if (Field_dsp340050b49a6c_fld2973acc2_slot0_Slot_acc2_slot0_get (insn) == 0 && + Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_dsp340050b49a6c_fld2974acc2_slot0_Slot_acc2_slot0_get (insn) == 40 && + Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_PUSH2X128_PQ; + switch (Field_dsp340050b49a6c_fld2975acc2_slot0_Slot_acc2_slot0_get (insn)) + { + case 82: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP128_2PQ_1; + break; + case 83: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP128_2PQ_4; + break; + case 84: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP128_2PQ_2; + break; + case 85: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP128_2PQ_5; + break; + case 88: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP128_2PQ_3; + break; + } + switch (Field_dsp340050b49a6c_fld2976acc2_slot0_Slot_acc2_slot0_get (insn)) + { + case 172: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_CLRCM; + break; + case 173: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP128_0; + break; + case 174: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP128_1; + break; + case 175: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP128_2; + break; + case 178: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP128_3; + break; + case 179: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP2X128_2PQ_01; + break; + case 180: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP128_4; + break; + case 181: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP2X128_2PQ_03; + break; + case 182: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP2X128_2PQ_21; + break; + case 183: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP2X128_2PQ_23; + break; + } + if (Field_dsp340050b49a6c_fld2977acc2_slot0_Slot_acc2_slot0_get (insn) == 46 && + Field_op0_s14_Slot_acc2_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3797_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld2980acc2_slot0_Slot_acc2_slot0_get (insn) == 47 && + Field_op0_s14_Slot_acc2_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3796acc2_slot0_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld2981acc2_slot0_Slot_acc2_slot0_get (insn) == 3 && + Field_op0_s14_Slot_acc2_slot0_get (insn) == 0 && + Field_dsp340050b49a6c_fld3800acc2_slot0_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP128_2PQ_0; + if (Field_dsp340050b49a6c_fld2982acc2_slot0_Slot_acc2_slot0_get (insn) == 24 && + Field_op0_s14_Slot_acc2_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3801acc2_slot0_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld2984acc2_slot0_Slot_acc2_slot0_get (insn) == 25 && + Field_op0_s14_Slot_acc2_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3801acc2_slot0_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld2985acc2_slot0_Slot_acc2_slot0_get (insn) == 13 && + Field_op0_s14_Slot_acc2_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3802acc2_slot0_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld2987acc2_slot0_Slot_acc2_slot0_get (insn) == 7 && + Field_op0_s14_Slot_acc2_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3803acc2_slot0_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld2989acc2_slot0_Slot_acc2_slot0_get (insn) == 1 && + Field_op0_s14_Slot_acc2_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3798acc2_slot0_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_MOVCM; + if (Field_dsp340050b49a6c_fld2990acc2_slot0_Slot_acc2_slot0_get (insn) == 1 && + Field_op0_s14_Slot_acc2_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3799acc2_slot0_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_NEGCM; + switch (Field_op0_s14_Slot_acc2_slot0_get (insn)) + { + case 3: + return OPCODE_ADD; + case 4: + return OPCODE_ADDI_N; + case 5: + return OPCODE_LCM_X; + case 6: + return OPCODE_LCM_XU; + case 7: + return OPCODE_SCM_X; + case 8: + return OPCODE_SCM_XU; + case 9: + return OPCODE_SUB; + } + switch (Field_r_Slot_acc2_slot0_get (insn)) + { + case 8: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_MOV_N; + break; + case 9: + if (Field_op0_s14_Slot_acc2_slot0_get (insn) == 0) + return OPCODE_PUSH128_PQ; + break; + } + if (Field_t_Slot_acc2_slot0_get (insn) == 2 && + Field_op0_s14_Slot_acc2_slot0_get (insn) == 1) + return OPCODE_CONJ; + return XTENSA_UNDEFINED; +} + +static int +Slot_smod_slot0_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld3119smod_slot0_Slot_smod_slot0_get (insn)) + { + case 0: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_LCM_PINC; + break; + case 1: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_LCM_U; + break; + case 2: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_SCM_PINC; + break; + case 3: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_SRAI; + break; + case 4: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_SCM_U; + break; + case 8: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_SLLI; + break; + case 13: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3841smod_slot0_Slot_smod_slot0_get (insn) == 0) + return OPCODE_PUSH128; + break; + } + switch (Field_dsp340050b49a6c_fld3120smod_slot0_Slot_smod_slot0_get (insn)) + { + case 76: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_AR2CM_LN; + break; + case 77: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_AR2CM_LN_I; + break; + case 78: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_AR2CM_LN_R; + break; + case 79: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_BEQZ_N; + break; + case 82: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_BNEZ_N; + break; + } + switch (Field_dsp340050b49a6c_fld3121smod_slot0_Slot_smod_slot0_get (insn)) + { + case 40: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_MOVI_N; + break; + case 47: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld2049_Slot_smod_slot0_get (insn) == 0) + return OPCODE_POP128_2M_3; + break; + } + switch (Field_dsp340050b49a6c_fld3122smod_slot0_Slot_smod_slot0_get (insn)) + { + case 332: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_AR2CM_DUP; + break; + case 333: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_MOV_N; + break; + case 334: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_NSA; + break; + case 335: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_NSAU; + break; + case 371: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_PUSH32; + break; + } + if (Field_dsp340050b49a6c_fld3123smod_slot0_Slot_smod_slot0_get (insn) == 84 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_CM2AR_LN; + if (Field_dsp340050b49a6c_fld3125smod_slot0_Slot_smod_slot0_get (insn) == 85 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_CM2AR_LN_R; + if (Field_dsp340050b49a6c_fld3126smod_slot0_Slot_smod_slot0_get (insn) == 344 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_ABS; + if (Field_dsp340050b49a6c_fld3127smod_slot0_Slot_smod_slot0_get (insn) == 345 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_CONJ; + if (Field_dsp340050b49a6c_fld3128smod_slot0_Slot_smod_slot0_get (insn) == 346 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_MOVCM; + if (Field_dsp340050b49a6c_fld3129smod_slot0_Slot_smod_slot0_get (insn) == 347 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_MOV_R; + if (Field_dsp340050b49a6c_fld3130smod_slot0_Slot_smod_slot0_get (insn) == 348 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_MOV_I; + if (Field_dsp340050b49a6c_fld3131smod_slot0_Slot_smod_slot0_get (insn) == 349 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_NEG; + if (Field_dsp340050b49a6c_fld3132smod_slot0_Slot_smod_slot0_get (insn) == 350 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_NEGCM; + if (Field_dsp340050b49a6c_fld3133smod_slot0_Slot_smod_slot0_get (insn) == 351 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SRA; + if (Field_dsp340050b49a6c_fld3134smod_slot0_Slot_smod_slot0_get (insn) == 88 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_CM2AR_LN_I; + if (Field_dsp340050b49a6c_fld3135smod_slot0_Slot_smod_slot0_get (insn) == 356 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SRL; + if (Field_dsp340050b49a6c_fld3136smod_slot0_Slot_smod_slot0_get (insn) == 5637 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_CLRCM; + if (Field_dsp340050b49a6c_fld3137smod_slot0_Slot_smod_slot0_get (insn) == 5653 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_GET_HSAR; + if (Field_dsp340050b49a6c_fld3138smod_slot0_Slot_smod_slot0_get (insn) == 5669 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_GET_HSAR2SAR; + if (Field_dsp340050b49a6c_fld3139smod_slot0_Slot_smod_slot0_get (insn) == 5685 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld3140smod_slot0_Slot_smod_slot0_get (insn) == 5701 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_GET_SAR; + if (Field_dsp340050b49a6c_fld3141smod_slot0_Slot_smod_slot0_get (insn) == 5717 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld3142smod_slot0_Slot_smod_slot0_get (insn) == 5733 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld3143smod_slot0_Slot_smod_slot0_get (insn) == 5749 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld3144smod_slot0_Slot_smod_slot0_get (insn) == 5765 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_GET_SMOD_OFFSET_TABLE; + if (Field_dsp340050b49a6c_fld3145smod_slot0_Slot_smod_slot0_get (insn) == 5781 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_POP128_4; + if (Field_dsp340050b49a6c_fld3146smod_slot0_Slot_smod_slot0_get (insn) == 2901 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3150_Slot_smod_slot0_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld3148smod_slot0_Slot_smod_slot0_get (insn) == 1461 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_imm6_Slot_smod_slot0_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld3149smod_slot0_Slot_smod_slot0_get (insn) == 355 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3834_Slot_smod_slot0_get (insn) == 0) + return OPCODE_ANY8; + if (Field_dsp340050b49a6c_fld3152smod_slot0_Slot_smod_slot0_get (insn) == 363 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3834_Slot_smod_slot0_get (insn) == 0) + return OPCODE_GET_SMOD_BUF; + if (Field_dsp340050b49a6c_fld3153smod_slot0_Slot_smod_slot0_get (insn) == 89 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3834_Slot_smod_slot0_get (insn) == 0) + return OPCODE_GET_LLR_BUF; + if (Field_dsp340050b49a6c_fld3155smod_slot0_Slot_smod_slot0_get (insn) == 91 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3833smod_slot0_Slot_smod_slot0_get (insn) == 0) + return OPCODE_ANY4; + if (Field_dsp340050b49a6c_fld3156smod_slot0_Slot_smod_slot0_get (insn) == 184 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_POP128_2M_0; + if (Field_dsp340050b49a6c_fld3157smod_slot0_Slot_smod_slot0_get (insn) == 185 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_POP128_2M_1; + if (Field_dsp340050b49a6c_fld3158smod_slot0_Slot_smod_slot0_get (insn) == 186 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_POP128_2M_2; + if (Field_dsp340050b49a6c_fld3159smod_slot0_Slot_smod_slot0_get (insn) == 3000 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SSAI; + switch (Field_dsp340050b49a6c_fld3160smod_slot0_Slot_smod_slot0_get (insn)) + { + case 6002: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SET_LLR_POS; + break; + case 6003: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SET_PHASOR_OFFSET; + break; + case 6004: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SET_PERM_REG; + break; + case 6005: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SET_SCALE_REG; + break; + case 6006: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SET_SMOD_POS; + break; + case 6007: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SET_SOV; + break; + case 6008: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SET_PHASOR_N; + break; + case 6009: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SET_WGHT; + break; + case 6010: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SSA8B; + break; + case 6011: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SSL; + break; + } + if (Field_dsp340050b49a6c_fld3161smod_slot0_Slot_smod_slot0_get (insn) == 3006 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3832smod_slot0_Slot_smod_slot0_get (insn) == 0) + return OPCODE_SSA8L; + if (Field_dsp340050b49a6c_fld3164smod_slot0_Slot_smod_slot0_get (insn) == 3007 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3832smod_slot0_Slot_smod_slot0_get (insn) == 0) + return OPCODE_SSR; + if (Field_dsp340050b49a6c_fld3165smod_slot0_Slot_smod_slot0_get (insn) == 400 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SLL; + if (Field_dsp340050b49a6c_fld3166smod_slot0_Slot_smod_slot0_get (insn) == 3208 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SET_SMOD_BUF; + if (Field_dsp340050b49a6c_fld3168smod_slot0_Slot_smod_slot0_get (insn) == 6418 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_GET_PERM_REG; + if (Field_dsp340050b49a6c_fld3170smod_slot0_Slot_smod_slot0_get (insn) == 6419 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_GET_SCALE_REG; + if (Field_dsp340050b49a6c_fld3171smod_slot0_Slot_smod_slot0_get (insn) == 6420 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_GET_PHASOR_N; + if (Field_dsp340050b49a6c_fld3172smod_slot0_Slot_smod_slot0_get (insn) == 6421 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_GET_SMOD_POS; + if (Field_dsp340050b49a6c_fld3173smod_slot0_Slot_smod_slot0_get (insn) == 6422 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_GET_SOV; + if (Field_dsp340050b49a6c_fld3174smod_slot0_Slot_smod_slot0_get (insn) == 6423 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_GET_WGHT; + if (Field_dsp340050b49a6c_fld3175smod_slot0_Slot_smod_slot0_get (insn) == 6424 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_GET_PHASOR_OFFSET; + if (Field_dsp340050b49a6c_fld3176smod_slot0_Slot_smod_slot0_get (insn) == 6425 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld3177smod_slot0_Slot_smod_slot0_get (insn) == 6426 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld3178smod_slot0_Slot_smod_slot0_get (insn) == 6427 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld3179smod_slot0_Slot_smod_slot0_get (insn) == 6428 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld3180smod_slot0_Slot_smod_slot0_get (insn) == 6429 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SET_SAR; + if (Field_dsp340050b49a6c_fld3181smod_slot0_Slot_smod_slot0_get (insn) == 3215 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_s8_Slot_smod_slot0_get (insn) == 0) + return OPCODE_SET_SMOD_OFFSET_TABLE; + if (Field_dsp340050b49a6c_fld3182smod_slot0_Slot_smod_slot0_get (insn) == 201 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_sas_Slot_smod_slot0_get (insn) == 0) + return OPCODE_GET_INTERP_EXT_L; + if (Field_dsp340050b49a6c_fld3184smod_slot0_Slot_smod_slot0_get (insn) == 101 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3836smod_slot0_Slot_smod_slot0_get (insn) == 0) + return OPCODE_GET_INTERP_EXT_N; + if (Field_dsp340050b49a6c_fld3186smod_slot0_Slot_smod_slot0_get (insn) == 51 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3837smod_slot0_Slot_smod_slot0_get (insn) == 0) + return OPCODE_GET_LLR_POS; + if (Field_dsp340050b49a6c_fld3188smod_slot0_Slot_smod_slot0_get (insn) == 7 && + Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3838smod_slot0_Slot_smod_slot0_get (insn) == 0) + return OPCODE_SET_LLR_BUF; + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 2) + return OPCODE_EXTUI; + switch (Field_sae_Slot_smod_slot0_get (insn)) + { + case 0: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_MOVLTZ; + break; + case 1: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_MOVNEZ; + break; + case 2: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_MOVT; + break; + case 3: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SCM; + break; + case 4: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_OR; + break; + case 5: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SCM_PINC_X; + break; + case 6: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SCM_X; + break; + case 7: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SCM_XU; + break; + case 8: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_ORB; + break; + case 9: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SEXT; + break; + case 10: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_ADD; + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SRC; + break; + case 11: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SUB; + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_ADDX2; + break; + case 12: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_ADDI_N; + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SRLI; + break; + case 13: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_ADDX4; + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SUBX2; + break; + case 14: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_ADDX8; + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SUBX4; + break; + case 15: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_SUBX8; + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_AND; + break; + case 16: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_S32I_N; + break; + case 17: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_XOR; + break; + case 18: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_ANDB; + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1) + return OPCODE_XORB; + break; + case 19: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_L32I_N; + break; + case 20: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_CLAMPS; + break; + case 21: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_LCM; + break; + case 22: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_LCM_PINC_X; + break; + case 23: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_LCM_X; + break; + case 24: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_COMB_AR; + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3842smod_slot0_Slot_smod_slot0_get (insn) == 0) + return OPCODE_PUSH128_M; + break; + case 25: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_LCM_XU; + break; + case 26: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_MAX; + break; + case 27: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_MIN; + break; + case 28: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_MAXU; + break; + case 29: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_MINU; + break; + case 30: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_MOVEQZ; + break; + case 31: + if (Field_op0_s17_Slot_smod_slot0_get (insn) == 0) + return OPCODE_MOVGEZ; + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_llr_slot0_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2071_Slot_llr_slot0_get (insn)) + { + case 0: + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 4) + return OPCODE_S32I_N; + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 0) + return OPCODE_ADD; + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 6) + return OPCODE_SUB; + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 1) + return OPCODE_AND; + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 2) + return OPCODE_LCM; + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 3) + return OPCODE_LCM_XU; + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 5) + return OPCODE_SCM_X; + break; + case 1: + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 0) + return OPCODE_ADDI_N; + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 1) + return OPCODE_L32I_N; + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 3) + return OPCODE_OR; + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 6) + return OPCODE_XOR; + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 8 && + Field_dsp340050b49a6c_fld3881llr_slot0_Slot_llr_slot0_get (insn) == 0) + return OPCODE_GET_LLR_BUF; + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 2) + return OPCODE_LCM_X; + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 4) + return OPCODE_SCM; + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 5) + return OPCODE_SCM_XU; + break; + } + if (Field_dsp340050b49a6c_fld3258llr_slot0_Slot_llr_slot0_get (insn) == 0 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_MOVI_N; + if (Field_dsp340050b49a6c_fld3259llr_slot0_Slot_llr_slot0_get (insn) == 2 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_AR2CM_LN; + switch (Field_dsp340050b49a6c_fld3260llr_slot0_Slot_llr_slot0_get (insn)) + { + case 12: + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_AR2CM_DUP; + break; + case 13: + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_MOV_N; + break; + case 14: + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_PUSH128_PQ; + break; + case 15: + if (Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_PUSH32; + break; + } + if (Field_dsp340050b49a6c_fld3261llr_slot0_Slot_llr_slot0_get (insn) == 4 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_CM2AR_LN; + if (Field_dsp340050b49a6c_fld3263llr_slot0_Slot_llr_slot0_get (insn) == 20 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_CONJ; + if (Field_dsp340050b49a6c_fld3264llr_slot0_Slot_llr_slot0_get (insn) == 21 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_MOV_I; + if (Field_dsp340050b49a6c_fld3265llr_slot0_Slot_llr_slot0_get (insn) == 22 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_MOV_R; + if (Field_dsp340050b49a6c_fld3266llr_slot0_Slot_llr_slot0_get (insn) == 23 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_NEG; + if (Field_dsp340050b49a6c_fld3267llr_slot0_Slot_llr_slot0_get (insn) == 24 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_MOVCM; + if (Field_dsp340050b49a6c_fld3268llr_slot0_Slot_llr_slot0_get (insn) == 25 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_NEGCM; + if (Field_dsp340050b49a6c_fld3269llr_slot0_Slot_llr_slot0_get (insn) == 26 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_SRA; + if (Field_dsp340050b49a6c_fld3270llr_slot0_Slot_llr_slot0_get (insn) == 43 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_SET_LLR_BUF; + if (Field_dsp340050b49a6c_fld3272llr_slot0_Slot_llr_slot0_get (insn) == 283 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_GET_LLR_POS; + if (Field_dsp340050b49a6c_fld3274llr_slot0_Slot_llr_slot0_get (insn) == 315 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_GET_PERM_REG; + if (Field_dsp340050b49a6c_fld3275llr_slot0_Slot_llr_slot0_get (insn) == 347 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_GET_SCALE_REG; + if (Field_dsp340050b49a6c_fld3276llr_slot0_Slot_llr_slot0_get (insn) == 379 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_GET_WGHT; + if (Field_dsp340050b49a6c_fld3277llr_slot0_Slot_llr_slot0_get (insn) == 411 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_GET_SMOD_POS; + if (Field_dsp340050b49a6c_fld3278llr_slot0_Slot_llr_slot0_get (insn) == 443 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld3279llr_slot0_Slot_llr_slot0_get (insn) == 475 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld3280llr_slot0_Slot_llr_slot0_get (insn) == 507 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld3281llr_slot0_Slot_llr_slot0_get (insn) == 44 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_PUSH128; + if (Field_dsp340050b49a6c_fld3282llr_slot0_Slot_llr_slot0_get (insn) == 269 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld3283llr_slot0_Slot_llr_slot0_get (insn) == 301 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_SET_SAR; + if (Field_dsp340050b49a6c_fld3284llr_slot0_Slot_llr_slot0_get (insn) == 173 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld2041_Slot_llr_slot0_get (insn) == 0) + return OPCODE_SET_SMOD_OFFSET_TABLE; + if (Field_dsp340050b49a6c_fld3286llr_slot0_Slot_llr_slot0_get (insn) == 109 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld3879llr_slot0_Slot_llr_slot0_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld3288llr_slot0_Slot_llr_slot0_get (insn) == 30 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld2056_Slot_llr_slot0_get (insn) == 0) + return OPCODE_SET_SMOD_BUF; + if (Field_dsp340050b49a6c_fld3289llr_slot0_Slot_llr_slot0_get (insn) == 135 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_GET_SMOD_BUF; + if (Field_dsp340050b49a6c_fld3291llr_slot0_Slot_llr_slot0_get (insn) == 286 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_CLRCM; + if (Field_dsp340050b49a6c_fld3292llr_slot0_Slot_llr_slot0_get (insn) == 287 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_GET_SMOD_OFFSET_TABLE; + if (Field_dsp340050b49a6c_fld3293llr_slot0_Slot_llr_slot0_get (insn) == 302 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_GET_HSAR; + if (Field_dsp340050b49a6c_fld3294llr_slot0_Slot_llr_slot0_get (insn) == 303 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld3295llr_slot0_Slot_llr_slot0_get (insn) == 318 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld3296llr_slot0_Slot_llr_slot0_get (insn) == 319 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld3297llr_slot0_Slot_llr_slot0_get (insn) == 334 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_GET_HSAR2SAR; + if (Field_dsp340050b49a6c_fld3298llr_slot0_Slot_llr_slot0_get (insn) == 335 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld3299llr_slot0_Slot_llr_slot0_get (insn) == 175 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld2047_Slot_llr_slot0_get (insn) == 0) + return OPCODE_POP128_4; + if (Field_dsp340050b49a6c_fld3300llr_slot0_Slot_llr_slot0_get (insn) == 95 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld3893llr_slot0_Slot_llr_slot0_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld3302llr_slot0_Slot_llr_slot0_get (insn) == 31 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 7 && + Field_dsp340050b49a6c_fld3883llr_slot0_Slot_llr_slot0_get (insn) == 0) + return OPCODE_GET_SAR; + if (Field_dsp340050b49a6c_fld3303llr_slot0_Slot_llr_slot0_get (insn) == 0 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 8) + return OPCODE_SLL; + if (Field_dsp340050b49a6c_fld3304llr_slot0_Slot_llr_slot0_get (insn) == 1 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 8 && + Field_dsp340050b49a6c_fld3887llr_slot0_Slot_llr_slot0_get (insn) == 0) + return OPCODE_SET_PERM_REG; + if (Field_dsp340050b49a6c_fld3305llr_slot0_Slot_llr_slot0_get (insn) == 17 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 8 && + Field_dsp340050b49a6c_fld3887llr_slot0_Slot_llr_slot0_get (insn) == 0) + return OPCODE_SET_SMOD_POS; + if (Field_dsp340050b49a6c_fld3306llr_slot0_Slot_llr_slot0_get (insn) == 17 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 8 && + Field_dsp340050b49a6c_fld3890llr_slot0_Slot_llr_slot0_get (insn) == 0) + return OPCODE_SET_WGHT; + if (Field_dsp340050b49a6c_fld3308llr_slot0_Slot_llr_slot0_get (insn) == 17 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 8 && + Field_dsp340050b49a6c_fld3892llr_slot0_Slot_llr_slot0_get (insn) == 0) + return OPCODE_POP16LLR_1; + if (Field_dsp340050b49a6c_fld3310llr_slot0_Slot_llr_slot0_get (insn) == 1 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 8 && + Field_dsp340050b49a6c_fld3888llr_slot0_Slot_llr_slot0_get (insn) == 0) + return OPCODE_SET_SCALE_REG; + if (Field_dsp340050b49a6c_fld3311llr_slot0_Slot_llr_slot0_get (insn) == 1 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 8 && + Field_r_Slot_llr_slot0_get (insn) == 0) + return OPCODE_PUSH2X128_PQ; + if (Field_dsp340050b49a6c_fld3312llr_slot0_Slot_llr_slot0_get (insn) == 1 && + Field_op0_s20_Slot_llr_slot0_get (insn) == 8 && + Field_dsp340050b49a6c_fld3885llr_slot0_Slot_llr_slot0_get (insn) == 0) + return OPCODE_SET_LLR_POS; + switch (Field_op0_s20_Slot_llr_slot0_get (insn)) + { + case 9: + return OPCODE_LCM_U; + case 10: + return OPCODE_SCM_U; + case 11: + return OPCODE_SLLI; + case 12: + return OPCODE_SRAI; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_dual_slot2_decode (const xtensa_insnbuf insn) +{ + if (Field_dsp340050b49a6c_fld2044_Slot_dual_slot2_get (insn) == 0 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_EXTUI; + if (Field_dsp340050b49a6c_fld2056_Slot_dual_slot2_get (insn) == 5 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3923dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_CLRTIEP; + if (Field_dsp340050b49a6c_fld3313dual_slot2_Slot_dual_slot2_get (insn) == 1 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_BEQI; + if (Field_dsp340050b49a6c_fld3314_Slot_dual_slot2_get (insn) == 1 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3904dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_BNEZ; + if (Field_dsp340050b49a6c_fld3315dual_slot2_Slot_dual_slot2_get (insn) == 17 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_BLTUI; + if (Field_dsp340050b49a6c_fld3316dual_slot2_Slot_dual_slot2_get (insn) == 33 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_BNEI; + if (Field_dsp340050b49a6c_fld3317dual_slot2_Slot_dual_slot2_get (insn) == 769 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ADD32; + switch (Field_dsp340050b49a6c_fld3318_Slot_dual_slot2_get (insn)) + { + case 2: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_BEQZ; + break; + case 4: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_BGEZ; + break; + case 6: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2 && + Field_s_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ASRM; + break; + } + if (Field_dsp340050b49a6c_fld3319dual_slot2_Slot_dual_slot2_get (insn) == 785 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ADDCM; + if (Field_dsp340050b49a6c_fld3320dual_slot2_Slot_dual_slot2_get (insn) == 801 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ADDWRP; + if (Field_dsp340050b49a6c_fld3321dual_slot2_Slot_dual_slot2_get (insn) == 817 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ASR; + if (Field_dsp340050b49a6c_fld3322dual_slot2_Slot_dual_slot2_get (insn) == 833 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_AND128; + if (Field_dsp340050b49a6c_fld3323dual_slot2_Slot_dual_slot2_get (insn) == 849 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_EXTUI4; + if (Field_dsp340050b49a6c_fld3324dual_slot2_Slot_dual_slot2_get (insn) == 865 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_LUT; + if (Field_dsp340050b49a6c_fld3325dual_slot2_Slot_dual_slot2_get (insn) == 881 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_LUT_IEXT; + if (Field_dsp340050b49a6c_fld3326dual_slot2_Slot_dual_slot2_get (insn) == 897 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ASL; + if (Field_dsp340050b49a6c_fld3327dual_slot2_Slot_dual_slot2_get (insn) == 913 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_LUT_REXT; + if (Field_dsp340050b49a6c_fld3328dual_slot2_Slot_dual_slot2_get (insn) == 929 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MAX8; + if (Field_dsp340050b49a6c_fld3329dual_slot2_Slot_dual_slot2_get (insn) == 945 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MEAN32; + if (Field_dsp340050b49a6c_fld3330dual_slot2_Slot_dual_slot2_get (insn) == 961 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MEAN; + if (Field_dsp340050b49a6c_fld3331dual_slot2_Slot_dual_slot2_get (insn) == 977 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MIN8; + if (Field_dsp340050b49a6c_fld3332dual_slot2_Slot_dual_slot2_get (insn) == 993 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_OR128; + if (Field_dsp340050b49a6c_fld3333dual_slot2_Slot_dual_slot2_get (insn) == 1009 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SUB32; + if (Field_dsp340050b49a6c_fld3334dual_slot2_Slot_dual_slot2_get (insn) == 2 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_BGEI; + if (Field_dsp340050b49a6c_fld3335dual_slot2_Slot_dual_slot2_get (insn) == 3 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SUBCM; + if (Field_dsp340050b49a6c_fld3336dual_slot2_Slot_dual_slot2_get (insn) == 19 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_XOR128; + if (Field_dsp340050b49a6c_fld3337dual_slot2_Slot_dual_slot2_get (insn) == 560 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ABS8; + if (Field_dsp340050b49a6c_fld3339dual_slot2_Slot_dual_slot2_get (insn) == 561 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_CONJ; + if (Field_dsp340050b49a6c_fld3340dual_slot2_Slot_dual_slot2_get (insn) == 562 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_LUT_PHASOR; + if (Field_dsp340050b49a6c_fld3341dual_slot2_Slot_dual_slot2_get (insn) == 563 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_NCO_UPDATE; + if (Field_dsp340050b49a6c_fld3342dual_slot2_Slot_dual_slot2_get (insn) == 525 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_LUT_WRITE; + if (Field_dsp340050b49a6c_fld3345dual_slot2_Slot_dual_slot2_get (insn) == 9268 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SET_ARGMAX; + if (Field_dsp340050b49a6c_fld3347dual_slot2_Slot_dual_slot2_get (insn) == 9269 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SET_MAX; + if (Field_dsp340050b49a6c_fld3348dual_slot2_Slot_dual_slot2_get (insn) == 9270 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SET_NCO; + switch (Field_dsp340050b49a6c_fld3349dual_slot2_Slot_dual_slot2_get (insn)) + { + case 132151: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_1; + break; + case 136247: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_2; + break; + case 140343: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_3; + break; + case 144439: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_0; + break; + case 148535: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_4; + break; + case 152631: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_1; + break; + case 156727: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_2; + break; + case 160823: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_3; + break; + } + if (Field_dsp340050b49a6c_fld3350dual_slot2_Slot_dual_slot2_get (insn) == 42039 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3907dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_5; + if (Field_dsp340050b49a6c_fld3353dual_slot2_Slot_dual_slot2_get (insn) == 46135 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3907dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld3354dual_slot2_Slot_dual_slot2_get (insn) == 2381 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_s4_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SET_SAR; + if (Field_dsp340050b49a6c_fld3356dual_slot2_Slot_dual_slot2_get (insn) == 1229 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3924dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_0; + if (Field_dsp340050b49a6c_fld3358dual_slot2_Slot_dual_slot2_get (insn) == 333 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3918dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SET_HSAR; + if (Field_dsp340050b49a6c_fld3360dual_slot2_Slot_dual_slot2_get (insn) == 568 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVCM; + if (Field_dsp340050b49a6c_fld3361dual_slot2_Slot_dual_slot2_get (insn) == 569 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_NEGCM; + if (Field_dsp340050b49a6c_fld3362dual_slot2_Slot_dual_slot2_get (insn) == 570 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_NOT128; + if (Field_dsp340050b49a6c_fld3363dual_slot2_Slot_dual_slot2_get (insn) == 8251 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_CLRCM; + switch (Field_dsp340050b49a6c_fld3364_Slot_dual_slot2_get (insn)) + { + case 52: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_ADD; + break; + case 53: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_ADDX2; + break; + case 54: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_ADDX4; + break; + case 55: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_ADDX8; + break; + case 56: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_ADDI_N; + break; + case 57: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_AND; + break; + case 58: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_ANDB; + break; + case 59: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_LUT_AR; + break; + case 60: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_CLAMPS; + break; + case 61: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_MAX; + break; + case 62: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_MAXU; + break; + case 63: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_MIN; + break; + case 112: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_MINU; + break; + case 113: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_MOVEQZ; + break; + case 114: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_MOVGEZ; + break; + case 115: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_MOVT; + break; + case 116: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_MOVLTZ; + break; + case 117: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_OR; + break; + case 118: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_ORB; + break; + case 119: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_SEXT; + break; + case 120: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_MOVNEZ; + break; + case 121: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_SRC; + break; + case 122: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_SRLI; + break; + case 123: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_SUBX2; + break; + case 124: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_SUB; + break; + case 125: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_SUBX4; + break; + case 126: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_SUBX8; + break; + case 127: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_XOR; + break; + } + if (Field_dsp340050b49a6c_fld3365dual_slot2_Slot_dual_slot2_get (insn) == 8507 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_GET_ARGMAX; + if (Field_dsp340050b49a6c_fld3366dual_slot2_Slot_dual_slot2_get (insn) == 8763 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_GET_HSAR; + if (Field_dsp340050b49a6c_fld3367dual_slot2_Slot_dual_slot2_get (insn) == 9019 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_GET_NCO; + if (Field_dsp340050b49a6c_fld3368dual_slot2_Slot_dual_slot2_get (insn) == 9275 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_GET_HSAR2SAR; + if (Field_dsp340050b49a6c_fld3369dual_slot2_Slot_dual_slot2_get (insn) == 9531 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_GET_SAR; + if (Field_dsp340050b49a6c_fld3370dual_slot2_Slot_dual_slot2_get (insn) == 9787 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld3371dual_slot2_Slot_dual_slot2_get (insn) == 10043 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld3372dual_slot2_Slot_dual_slot2_get (insn) == 10299 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_GET_MAX; + if (Field_dsp340050b49a6c_fld3373dual_slot2_Slot_dual_slot2_get (insn) == 10555 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld3374dual_slot2_Slot_dual_slot2_get (insn) == 10811 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld3375dual_slot2_Slot_dual_slot2_get (insn) == 11067 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld3376dual_slot2_Slot_dual_slot2_get (insn) == 11323 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_POP128_4; + if (Field_dsp340050b49a6c_fld3377dual_slot2_Slot_dual_slot2_get (insn) == 11579 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld3378dual_slot2_Slot_dual_slot2_get (insn) == 11835 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld3379dual_slot2_Slot_dual_slot2_get (insn) == 12091 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld3380dual_slot2_Slot_dual_slot2_get (insn) == 572 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_TRANS; + if (Field_dsp340050b49a6c_fld3381dual_slot2_Slot_dual_slot2_get (insn) == 573 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2046_Slot_dual_slot2_get (insn) == 0) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld3382dual_slot2_Slot_dual_slot2_get (insn) == 287 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3928dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_RDTIEP; + if (Field_dsp340050b49a6c_fld3384dual_slot2_Slot_dual_slot2_get (insn) == 771 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVAR2; + if (Field_dsp340050b49a6c_fld3385dual_slot2_Slot_dual_slot2_get (insn) == 787 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SLL; + if (Field_dsp340050b49a6c_fld3386dual_slot2_Slot_dual_slot2_get (insn) == 803 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SWAPB; + switch (Field_dsp340050b49a6c_fld3387dual_slot2_Slot_dual_slot2_get (insn)) + { + case 13059: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SSA8L; + break; + case 13075: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SSL; + break; + } + if (Field_dsp340050b49a6c_fld3388dual_slot2_Slot_dual_slot2_get (insn) == 6547 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3913dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SSR; + if (Field_dsp340050b49a6c_fld3390dual_slot2_Slot_dual_slot2_get (insn) == 3283 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2049_Slot_dual_slot2_get (insn) == 0) + return OPCODE_WRTBSIGQ; + if (Field_dsp340050b49a6c_fld3392dual_slot2_Slot_dual_slot2_get (insn) == 1651 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3900_Slot_dual_slot2_get (insn) == 0) + return OPCODE_WRTSIGQ; + if (Field_dsp340050b49a6c_fld3394dual_slot2_Slot_dual_slot2_get (insn) == 211 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3920dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_AR2SAR_DUP; + if (Field_dsp340050b49a6c_fld3396dual_slot2_Slot_dual_slot2_get (insn) == 115 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3909dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SSA8B; + if (Field_dsp340050b49a6c_fld3397dual_slot2_Slot_dual_slot2_get (insn) == 19 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3919dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_AR2CM_DUP; + if (Field_dsp340050b49a6c_fld3399dual_slot2_Slot_dual_slot2_get (insn) == 19 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3931dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ARGMAX8; + if (Field_dsp340050b49a6c_fld3401dual_slot2_Slot_dual_slot2_get (insn) == 33 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3934dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SUBMEAN; + if (Field_dsp340050b49a6c_fld3403dual_slot2_Slot_dual_slot2_get (insn) == 41 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3922dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_PQ2CM; + if (Field_dsp340050b49a6c_fld3404dual_slot2_Slot_dual_slot2_get (insn) == 25 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3910dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SSAI; + if (Field_dsp340050b49a6c_fld3406dual_slot2_Slot_dual_slot2_get (insn) == 9 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3935dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SUBWRP; + if (Field_dsp340050b49a6c_fld3407_Slot_dual_slot2_get (insn) == 1 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3905dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVI; + if (Field_dsp340050b49a6c_fld3408dual_slot2_Slot_dual_slot2_get (insn) == 1 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3901dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_BGEUI; + if (Field_dsp340050b49a6c_fld3410_Slot_dual_slot2_get (insn) == 3 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3929dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SETTIEP; + if (Field_dsp340050b49a6c_fld3411dual_slot2_Slot_dual_slot2_get (insn) == 5 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3933dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ASLM32; + if (Field_dsp340050b49a6c_fld3412dual_slot2_Slot_dual_slot2_get (insn) == 18 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3927dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_QREADY; + if (Field_dsp340050b49a6c_fld3413dual_slot2_Slot_dual_slot2_get (insn) == 19 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3930dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_WRTBSIGQM; + if (Field_dsp340050b49a6c_fld3414dual_slot2_Slot_dual_slot2_get (insn) == 1 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_ADDMI; + if (Field_dsp340050b49a6c_fld3415dual_slot2_Slot_dual_slot2_get (insn) == 17 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BALL; + if (Field_dsp340050b49a6c_fld3416dual_slot2_Slot_dual_slot2_get (insn) == 33 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BANY; + if (Field_dsp340050b49a6c_fld3417dual_slot2_Slot_dual_slot2_get (insn) == 49 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BBC; + if (Field_dsp340050b49a6c_fld3418dual_slot2_Slot_dual_slot2_get (insn) == 1 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BBCI; + if (Field_dsp340050b49a6c_fld3419dual_slot2_Slot_dual_slot2_get (insn) == 18 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BBS; + if (Field_dsp340050b49a6c_fld3420dual_slot2_Slot_dual_slot2_get (insn) == 19 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BGE; + if (Field_dsp340050b49a6c_fld3421dual_slot2_Slot_dual_slot2_get (insn) == 34 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BEQ; + if (Field_dsp340050b49a6c_fld3422dual_slot2_Slot_dual_slot2_get (insn) == 35 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BGEU; + if (Field_dsp340050b49a6c_fld3423dual_slot2_Slot_dual_slot2_get (insn) == 50 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BLT; + if (Field_dsp340050b49a6c_fld3424dual_slot2_Slot_dual_slot2_get (insn) == 51 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BLTU; + if (Field_dsp340050b49a6c_fld3425dual_slot2_Slot_dual_slot2_get (insn) == 2 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BBSI; + if (Field_dsp340050b49a6c_fld3426dual_slot2_Slot_dual_slot2_get (insn) == 6 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BNALL; + if (Field_dsp340050b49a6c_fld3427dual_slot2_Slot_dual_slot2_get (insn) == 7 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_ASL32; + if (Field_dsp340050b49a6c_fld3428dual_slot2_Slot_dual_slot2_get (insn) == 23 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_ASR32; + if (Field_dsp340050b49a6c_fld3429dual_slot2_Slot_dual_slot2_get (insn) == 39 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND8_0; + if (Field_dsp340050b49a6c_fld3430dual_slot2_Slot_dual_slot2_get (insn) == 55 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND8_3; + if (Field_dsp340050b49a6c_fld3431dual_slot2_Slot_dual_slot2_get (insn) == 71 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND8_1; + if (Field_dsp340050b49a6c_fld3432dual_slot2_Slot_dual_slot2_get (insn) == 87 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND8_4; + if (Field_dsp340050b49a6c_fld3433dual_slot2_Slot_dual_slot2_get (insn) == 103 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND8_5; + if (Field_dsp340050b49a6c_fld3434dual_slot2_Slot_dual_slot2_get (insn) == 119 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND8_6; + if (Field_dsp340050b49a6c_fld3435dual_slot2_Slot_dual_slot2_get (insn) == 135 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND8_2; + if (Field_dsp340050b49a6c_fld3436dual_slot2_Slot_dual_slot2_get (insn) == 151 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND8_7; + if (Field_dsp340050b49a6c_fld3437dual_slot2_Slot_dual_slot2_get (insn) == 167 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND_0; + if (Field_dsp340050b49a6c_fld3438dual_slot2_Slot_dual_slot2_get (insn) == 183 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND_2; + if (Field_dsp340050b49a6c_fld3439dual_slot2_Slot_dual_slot2_get (insn) == 199 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND_1; + if (Field_dsp340050b49a6c_fld3440dual_slot2_Slot_dual_slot2_get (insn) == 215 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND_3; + if (Field_dsp340050b49a6c_fld3441dual_slot2_Slot_dual_slot2_get (insn) == 231 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND_4; + if (Field_dsp340050b49a6c_fld3442dual_slot2_Slot_dual_slot2_get (insn) == 247 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND_5; + if (Field_dsp340050b49a6c_fld3443dual_slot2_Slot_dual_slot2_get (insn) == 20 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BNE; + if (Field_dsp340050b49a6c_fld3444dual_slot2_Slot_dual_slot2_get (insn) == 261 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_MOVCND_6; + if (Field_dsp340050b49a6c_fld3445dual_slot2_Slot_dual_slot2_get (insn) == 277 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_PERM; + if (Field_dsp340050b49a6c_fld3446dual_slot2_Slot_dual_slot2_get (insn) == 1172 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_ADD16; + if (Field_dsp340050b49a6c_fld3448dual_slot2_Slot_dual_slot2_get (insn) == 2346 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3925dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_PUSH128; + if (Field_dsp340050b49a6c_fld3450dual_slot2_Slot_dual_slot2_get (insn) == 2347 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2046_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ANY8; + if (Field_dsp340050b49a6c_fld3451dual_slot2_Slot_dual_slot2_get (insn) == 587 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3914dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ANY4; + switch (Field_dsp340050b49a6c_fld3453dual_slot2_Slot_dual_slot2_get (insn)) + { + case 4869: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_NSA; + break; + case 4885: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_NSAU; + break; + case 4901: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_PUSH128_PQ; + break; + case 4917: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_SUBARX; + break; + } + if (Field_dsp340050b49a6c_fld3454dual_slot2_Slot_dual_slot2_get (insn) == 2469 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3466_Slot_dual_slot2_get (insn) == 0) + return OPCODE_PUSH32; + if (Field_dsp340050b49a6c_fld3456dual_slot2_Slot_dual_slot2_get (insn) == 2485 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3466_Slot_dual_slot2_get (insn) == 0) + return OPCODE_WRTIEP; + if (Field_dsp340050b49a6c_fld3457dual_slot2_Slot_dual_slot2_get (insn) == 629 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3917dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SET_EXT_REGS; + if (Field_dsp340050b49a6c_fld3458dual_slot2_Slot_dual_slot2_get (insn) == 85 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3919dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ADDAR2; + if (Field_dsp340050b49a6c_fld3459dual_slot2_Slot_dual_slot2_get (insn) == 53 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3896dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOV_N; + if (Field_dsp340050b49a6c_fld3460dual_slot2_Slot_dual_slot2_get (insn) == 11 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3921dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVCND_7; + if (Field_dsp340050b49a6c_fld3461dual_slot2_Slot_dual_slot2_get (insn) == 9 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2049_Slot_dual_slot2_get (insn) == 0) + return OPCODE_BNONE; + if (Field_dsp340050b49a6c_fld3462dual_slot2_Slot_dual_slot2_get (insn) == 49 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3894dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_AR2CM_LN; + if (Field_dsp340050b49a6c_fld3464dual_slot2_Slot_dual_slot2_get (insn) == 53 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3894dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_dsp340050b49a6c_fld3465dual_slot2_Slot_dual_slot2_get (insn) == 29 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3895dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_BNEZ_N; + if (Field_dsp340050b49a6c_fld3467dual_slot2_Slot_dual_slot2_get (insn) == 1 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3899dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ADDI; + if (Field_dsp340050b49a6c_fld3468dual_slot2_Slot_dual_slot2_get (insn) == 3 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3897dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_MOVI_N; + switch (Field_dsp340050b49a6c_fld3469dual_slot2_Slot_dual_slot2_get (insn)) + { + case 24: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_SLLI; + break; + case 25: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_SRAI; + break; + } + if (Field_dsp340050b49a6c_fld3470dual_slot2_Slot_dual_slot2_get (insn) == 80 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_ASLM; + if (Field_dsp340050b49a6c_fld3471dual_slot2_Slot_dual_slot2_get (insn) == 81 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_CMP8; + if (Field_dsp340050b49a6c_fld3472dual_slot2_Slot_dual_slot2_get (insn) == 82 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_CMP_I; + if (Field_dsp340050b49a6c_fld3473dual_slot2_Slot_dual_slot2_get (insn) == 83 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_LSRM; + if (Field_dsp340050b49a6c_fld3474dual_slot2_Slot_dual_slot2_get (insn) == 84 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2) + return OPCODE_CMP_R; + if (Field_dsp340050b49a6c_fld3475dual_slot2_Slot_dual_slot2_get (insn) == 325 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3898dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_ABS; + if (Field_dsp340050b49a6c_fld3477dual_slot2_Slot_dual_slot2_get (insn) == 341 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3898dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SRA; + if (Field_dsp340050b49a6c_fld3478dual_slot2_Slot_dual_slot2_get (insn) == 181 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3908dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_SRL; + if (Field_dsp340050b49a6c_fld3479dual_slot2_Slot_dual_slot2_get (insn) == 43 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3906dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_NEG; + if (Field_dsp340050b49a6c_fld3480dual_slot2_Slot_dual_slot2_get (insn) == 22 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2 && + Field_s4_Slot_dual_slot2_get (insn) == 0) + return OPCODE_LSLM; + if (Field_dsp340050b49a6c_fld3481dual_slot2_Slot_dual_slot2_get (insn) == 23 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld2046_Slot_dual_slot2_get (insn) == 0) + return OPCODE_CM2AR_LN; + if (Field_dsp340050b49a6c_fld3482dual_slot2_Slot_dual_slot2_get (insn) == 2 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3903dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_BLTZ; + if (Field_dsp340050b49a6c_fld3484dual_slot2_Slot_dual_slot2_get (insn) == 3 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3916dual_slot2_Slot_dual_slot2_get (insn) == 0) + return OPCODE_XORB; + if (Field_r_Slot_dual_slot2_get (insn) == 0 && + Field_op0_s21_Slot_dual_slot2_get (insn) == 1) + return OPCODE_BITFINS; + switch (Field_t_Slot_dual_slot2_get (insn)) + { + case 0: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 0) + return OPCODE_BITFEXT; + break; + case 8: + if (Field_op0_s21_Slot_dual_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3314_Slot_dual_slot2_get (insn) == 0) + return OPCODE_BLTI; + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_dual_slot0_decode (const xtensa_insnbuf insn) +{ + if (Field_dsp340050b49a6c_fld2056_Slot_dual_slot0_get (insn) == 3 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 2 && + Field_imm8_Slot_dual_slot0_get (insn) == 0) + return OPCODE_MOVCM2PQ; + switch (Field_dsp340050b49a6c_fld2057_Slot_dual_slot0_get (insn)) + { + case 2842: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_AR2CM_DUP; + break; + case 2843: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_MOV_N; + break; + case 2874: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_NSA; + break; + case 2906: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_NSAU; + break; + case 2970: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_PUSH128_PQ; + break; + } + switch (Field_dsp340050b49a6c_fld3487dual_slot0_Slot_dual_slot0_get (insn)) + { + case 0: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BBCI; + break; + case 1: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BBSI; + break; + } + switch (Field_dsp340050b49a6c_fld3488dual_slot0_Slot_dual_slot0_get (insn)) + { + case 0: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_EXTUI; + break; + case 3: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4 && + Field_sae_Slot_dual_slot0_get (insn) == 0) + return OPCODE_ULT_S; + break; + } + switch (Field_dsp340050b49a6c_fld3489dual_slot0_Slot_dual_slot0_get (insn)) + { + case 2: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_BEQZ; + break; + case 3: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_BNEZ; + break; + case 4: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_BGEZ; + break; + case 5: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4 && + Field_dsp340050b49a6c_fld2079_Slot_dual_slot0_get (insn) == 0) + return OPCODE_ULE_S; + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_LSI; + break; + case 6: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_LSIU; + break; + case 7: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_MOVI; + break; + case 8: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_BLTZ; + break; + case 9: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SSI; + break; + case 10: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SSIU; + break; + case 14: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld2037_Slot_dual_slot0_get (insn) == 0) + return OPCODE_LCM_U; + break; + } + if (Field_dsp340050b49a6c_fld3490dual_slot0_Slot_dual_slot0_get (insn) == 88 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_LAC32_R; + if (Field_dsp340050b49a6c_fld3491dual_slot0_Slot_dual_slot0_get (insn) == 177 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_LAC_IH; + if (Field_dsp340050b49a6c_fld3492dual_slot0_Slot_dual_slot0_get (insn) == 185 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_LAC_RL; + if (Field_dsp340050b49a6c_fld3493dual_slot0_Slot_dual_slot0_get (insn) == 178 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_LAC_IL; + if (Field_dsp340050b49a6c_fld3494dual_slot0_Slot_dual_slot0_get (insn) == 355 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_LAC2X64_0; + if (Field_dsp340050b49a6c_fld3496dual_slot0_Slot_dual_slot0_get (insn) == 371 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_LAC2X64_2; + if (Field_dsp340050b49a6c_fld3497dual_slot0_Slot_dual_slot0_get (insn) == 362 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_LAC2X64_1; + if (Field_dsp340050b49a6c_fld3498dual_slot0_Slot_dual_slot0_get (insn) == 363 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_LAC2X64_3; + if (Field_dsp340050b49a6c_fld3499dual_slot0_Slot_dual_slot0_get (insn) == 5750 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_LLR_BUF; + if (Field_dsp340050b49a6c_fld3500dual_slot0_Slot_dual_slot0_get (insn) == 11502 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_ANY4; + if (Field_dsp340050b49a6c_fld3502dual_slot0_Slot_dual_slot0_get (insn) == 23006 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_ANY8; + if (Field_dsp340050b49a6c_fld3504dual_slot0_Slot_dual_slot0_get (insn) == 23007 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_SMOD_BUF; + if (Field_dsp340050b49a6c_fld3505dual_slot0_Slot_dual_slot0_get (insn) == 11628 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_PUSH2X128_PQ; + switch (Field_dsp340050b49a6c_fld3506dual_slot0_Slot_dual_slot0_get (insn)) + { + case 23258: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP128_2PQ_1; + break; + case 23259: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP128_2PQ_3; + break; + case 23260: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP128_2PQ_2; + break; + case 23261: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP128_2PQ_4; + break; + case 23262: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP128_2PQ_5; + break; + case 23263: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SSAI; + break; + case 23504: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP128_2PQ_0; + break; + } + switch (Field_dsp340050b49a6c_fld3507dual_slot0_Slot_dual_slot0_get (insn)) + { + case 47010: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP2X128_2PQ_01; + break; + case 47011: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP2X128_2PQ_23; + break; + case 47012: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP2X128_2PQ_03; + break; + case 47013: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SET_LLR_POS; + break; + case 47014: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SET_PERM_REG; + break; + case 47015: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SET_PHASOR_N; + break; + case 47016: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP2X128_2PQ_21; + break; + case 47017: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SET_PHASOR_OFFSET; + break; + case 47018: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SET_SCALE_REG; + break; + case 47019: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SET_SOV; + break; + case 47020: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SET_SMOD_POS; + break; + case 47021: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SET_WGHT; + break; + case 47022: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SSA8B; + break; + case 47023: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SSA8L; + break; + } + if (Field_dsp340050b49a6c_fld3508dual_slot0_Slot_dual_slot0_get (insn) == 47024 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_CLRCM; + if (Field_dsp340050b49a6c_fld3509dual_slot0_Slot_dual_slot0_get (insn) == 47025 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_HSAR; + if (Field_dsp340050b49a6c_fld3510dual_slot0_Slot_dual_slot0_get (insn) == 47026 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_HSAR2SAR; + if (Field_dsp340050b49a6c_fld3511dual_slot0_Slot_dual_slot0_get (insn) == 47027 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld3512dual_slot0_Slot_dual_slot0_get (insn) == 47028 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_SAR; + if (Field_dsp340050b49a6c_fld3513dual_slot0_Slot_dual_slot0_get (insn) == 47029 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld3514dual_slot0_Slot_dual_slot0_get (insn) == 47030 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld3515dual_slot0_Slot_dual_slot0_get (insn) == 47031 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld3516dual_slot0_Slot_dual_slot0_get (insn) == 47032 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_SMOD_OFFSET_TABLE; + if (Field_dsp340050b49a6c_fld3517dual_slot0_Slot_dual_slot0_get (insn) == 47033 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP128_4; + if (Field_dsp340050b49a6c_fld3518dual_slot0_Slot_dual_slot0_get (insn) == 23517 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_s8_Slot_dual_slot0_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld3519dual_slot0_Slot_dual_slot0_get (insn) == 11759 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3939dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld3520dual_slot0_Slot_dual_slot0_get (insn) == 5942 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld2056_Slot_dual_slot0_get (insn) == 0) + return OPCODE_SSL; + if (Field_dsp340050b49a6c_fld3522dual_slot0_Slot_dual_slot0_get (insn) == 5943 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3950dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_POP16LLR_1; + if (Field_dsp340050b49a6c_fld3523dual_slot0_Slot_dual_slot0_get (insn) == 1501 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_bbi_Slot_dual_slot0_get (insn) == 0) + return OPCODE_SSR; + if (Field_dsp340050b49a6c_fld3524dual_slot0_Slot_dual_slot0_get (insn) == 765 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3943dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_CLRAC; + if (Field_dsp340050b49a6c_fld3527dual_slot0_Slot_dual_slot0_get (insn) == 45 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld2049_Slot_dual_slot0_get (insn) == 0) + return OPCODE_LAC_RH; + switch (Field_dsp340050b49a6c_fld3529dual_slot0_Slot_dual_slot0_get (insn)) + { + case 707: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_AR2CM_LN; + break; + case 711: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_AR2CM_LN_I; + break; + } + if (Field_dsp340050b49a6c_fld3530dual_slot0_Slot_dual_slot0_get (insn) == 359 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld2072_Slot_dual_slot0_get (insn) == 0) + return OPCODE_AR2CM_LN_R; + switch (Field_dsp340050b49a6c_fld3531_Slot_dual_slot0_get (insn)) + { + case 120: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SAC2X32; + break; + case 121: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SAC32_R; + break; + case 122: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SCM_PINC; + break; + case 123: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SLLI; + break; + case 124: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SCM_U; + break; + case 125: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SRAI; + break; + } + if (Field_dsp340050b49a6c_fld3532dual_slot0_Slot_dual_slot0_get (insn) == 183 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3602_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BEQZ_N; + if (Field_dsp340050b49a6c_fld3533dual_slot0_Slot_dual_slot0_get (insn) == 95 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3936dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BNEZ_N; + if (Field_dsp340050b49a6c_fld3535dual_slot0_Slot_dual_slot0_get (insn) == 48 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld2066_Slot_dual_slot0_get (insn) == 0) + return OPCODE_LAC2X32; + if (Field_dsp340050b49a6c_fld3536dual_slot0_Slot_dual_slot0_get (insn) == 193 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld2060_Slot_dual_slot0_get (insn) == 0) + return OPCODE_POP128_2M_0; + if (Field_dsp340050b49a6c_fld3537dual_slot0_Slot_dual_slot0_get (insn) == 197 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld2060_Slot_dual_slot0_get (insn) == 0) + return OPCODE_POP128_2M_2; + if (Field_dsp340050b49a6c_fld3538dual_slot0_Slot_dual_slot0_get (insn) == 101 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3957dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_POP128_2M_3; + if (Field_dsp340050b49a6c_fld3539dual_slot0_Slot_dual_slot0_get (insn) == 25 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3954dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_POP128_2M_1; + if (Field_dsp340050b49a6c_fld3541dual_slot0_Slot_dual_slot0_get (insn) == 104 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_LCM_PINC; + if (Field_dsp340050b49a6c_fld3542dual_slot0_Slot_dual_slot0_get (insn) == 105 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_LP; + if (Field_dsp340050b49a6c_fld3543dual_slot0_Slot_dual_slot0_get (insn) == 106 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_LQ; + if (Field_dsp340050b49a6c_fld3544dual_slot0_Slot_dual_slot0_get (insn) == 3331 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_ABS; + if (Field_dsp340050b49a6c_fld3545dual_slot0_Slot_dual_slot0_get (insn) == 3339 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_CONJ; + if (Field_dsp340050b49a6c_fld3546dual_slot0_Slot_dual_slot0_get (insn) == 3347 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_MOVCM; + if (Field_dsp340050b49a6c_fld3547dual_slot0_Slot_dual_slot0_get (insn) == 3355 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_NEGCM; + if (Field_dsp340050b49a6c_fld3548dual_slot0_Slot_dual_slot0_get (insn) == 3363 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_MOV_I; + if (Field_dsp340050b49a6c_fld3549dual_slot0_Slot_dual_slot0_get (insn) == 3371 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SRA; + if (Field_dsp340050b49a6c_fld3550dual_slot0_Slot_dual_slot0_get (insn) == 3379 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SRL; + if (Field_dsp340050b49a6c_fld3551dual_slot0_Slot_dual_slot0_get (insn) == 6763 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_CLB_C; + switch (Field_dsp340050b49a6c_fld3552_Slot_dual_slot0_get (insn)) + { + case 146: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_EXT; + break; + case 147: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_PUSH128_M; + break; + case 148: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_EXT_R; + break; + case 149: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SAC2X64_0; + break; + case 150: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SAC2X64_1; + break; + case 151: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SAC2X64_2; + break; + } + if (Field_dsp340050b49a6c_fld3553dual_slot0_Slot_dual_slot0_get (insn) == 6779 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_CLB_R; + if (Field_dsp340050b49a6c_fld3554dual_slot0_Slot_dual_slot0_get (insn) == 3395 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_MOV_R; + if (Field_dsp340050b49a6c_fld3555dual_slot0_Slot_dual_slot0_get (insn) == 6795 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_MINCLB_C; + if (Field_dsp340050b49a6c_fld3556dual_slot0_Slot_dual_slot0_get (insn) == 6811 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SMINCLB_C; + if (Field_dsp340050b49a6c_fld3557dual_slot0_Slot_dual_slot0_get (insn) == 6819 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_MINCLB_R; + if (Field_dsp340050b49a6c_fld3558dual_slot0_Slot_dual_slot0_get (insn) == 6835 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SMINCLB_R; + if (Field_dsp340050b49a6c_fld3559dual_slot0_Slot_dual_slot0_get (insn) == 6827 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SET_LLR_BUF; + if (Field_dsp340050b49a6c_fld3560dual_slot0_Slot_dual_slot0_get (insn) == 54555 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_INTERP_EXT_L; + if (Field_dsp340050b49a6c_fld3562dual_slot0_Slot_dual_slot0_get (insn) == 54587 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_INTERP_EXT_N; + if (Field_dsp340050b49a6c_fld3563dual_slot0_Slot_dual_slot0_get (insn) == 54619 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_LLR_POS; + if (Field_dsp340050b49a6c_fld3564dual_slot0_Slot_dual_slot0_get (insn) == 54651 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_PHASOR_N; + if (Field_dsp340050b49a6c_fld3565dual_slot0_Slot_dual_slot0_get (insn) == 54683 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_PERM_REG; + if (Field_dsp340050b49a6c_fld3566dual_slot0_Slot_dual_slot0_get (insn) == 54715 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_PHASOR_OFFSET; + if (Field_dsp340050b49a6c_fld3567dual_slot0_Slot_dual_slot0_get (insn) == 54747 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_SCALE_REG; + if (Field_dsp340050b49a6c_fld3568dual_slot0_Slot_dual_slot0_get (insn) == 54779 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_SMOD_POS; + if (Field_dsp340050b49a6c_fld3569dual_slot0_Slot_dual_slot0_get (insn) == 6851 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_PUSH128; + if (Field_dsp340050b49a6c_fld3570dual_slot0_Slot_dual_slot0_get (insn) == 54795 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_SOV; + if (Field_dsp340050b49a6c_fld3571dual_slot0_Slot_dual_slot0_get (insn) == 54827 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld3572dual_slot0_Slot_dual_slot0_get (insn) == 54859 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld3573dual_slot0_Slot_dual_slot0_get (insn) == 54891 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SET_SAR; + if (Field_dsp340050b49a6c_fld3574dual_slot0_Slot_dual_slot0_get (insn) == 54923 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld3575dual_slot0_Slot_dual_slot0_get (insn) == 54955 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_SET_SMOD_OFFSET_TABLE; + if (Field_dsp340050b49a6c_fld3576dual_slot0_Slot_dual_slot0_get (insn) == 109771 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_ADDAC_I2R; + if (Field_dsp340050b49a6c_fld3577dual_slot0_Slot_dual_slot0_get (insn) == 109803 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_ADDAC_R2I; + if (Field_dsp340050b49a6c_fld3578dual_slot0_Slot_dual_slot0_get (insn) == 110027 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_REDAC; + if (Field_dsp340050b49a6c_fld3579dual_slot0_Slot_dual_slot0_get (insn) == 110059 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_REDAC2; + if (Field_dsp340050b49a6c_fld3580dual_slot0_Slot_dual_slot0_get (insn) == 54803 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_GET_WGHT; + if (Field_dsp340050b49a6c_fld3581dual_slot0_Slot_dual_slot0_get (insn) == 54811 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3620dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_REDAC4; + if (Field_dsp340050b49a6c_fld3582dual_slot0_Slot_dual_slot0_get (insn) == 27419 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3959dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_REDACS; + if (Field_dsp340050b49a6c_fld3583dual_slot0_Slot_dual_slot0_get (insn) == 13723 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3960dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_SUBAC_I2R; + switch (Field_dsp340050b49a6c_fld3584_Slot_dual_slot0_get (insn)) + { + case 2: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3937dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BLTUI; + break; + case 3: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3552_Slot_dual_slot0_get (insn) == 0) + return OPCODE_ASLACM; + break; + } + if (Field_dsp340050b49a6c_fld3585dual_slot0_Slot_dual_slot0_get (insn) == 6875 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3961dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_SUBAC_R2I; + if (Field_dsp340050b49a6c_fld3587dual_slot0_Slot_dual_slot0_get (insn) == 1723 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3610_Slot_dual_slot0_get (insn) == 0) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld3588dual_slot0_Slot_dual_slot0_get (insn) == 219 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3938dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_NEG; + if (Field_dsp340050b49a6c_fld3589dual_slot0_Slot_dual_slot0_get (insn) == 106 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_s8_Slot_dual_slot0_get (insn) == 0) + return OPCODE_LCM; + if (Field_dsp340050b49a6c_fld3590dual_slot0_Slot_dual_slot0_get (insn) == 3331 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_EXT32_I; + if (Field_dsp340050b49a6c_fld3591dual_slot0_Slot_dual_slot0_get (insn) == 3335 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_EXT32_R; + if (Field_dsp340050b49a6c_fld3592dual_slot0_Slot_dual_slot0_get (insn) == 3339 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_EXT_2FIFO_0; + if (Field_dsp340050b49a6c_fld3593dual_slot0_Slot_dual_slot0_get (insn) == 3343 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_EXT_R2FIFO_0; + if (Field_dsp340050b49a6c_fld3594dual_slot0_Slot_dual_slot0_get (insn) == 3363 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_EXT_2FIFO_1; + if (Field_dsp340050b49a6c_fld3595dual_slot0_Slot_dual_slot0_get (insn) == 3367 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_EXT_R2FIFO_1; + if (Field_dsp340050b49a6c_fld3596dual_slot0_Slot_dual_slot0_get (insn) == 3371 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_EXT_R2FIFO_2; + if (Field_dsp340050b49a6c_fld3597dual_slot0_Slot_dual_slot0_get (insn) == 3375 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_EXT_R2FIFO_3; + if (Field_dsp340050b49a6c_fld3598dual_slot0_Slot_dual_slot0_get (insn) == 851 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3951dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_EXT_2FIFO_2; + if (Field_dsp340050b49a6c_fld3599dual_slot0_Slot_dual_slot0_get (insn) == 855 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3941dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_SET_SMOD_BUF; + if (Field_dsp340050b49a6c_fld3600dual_slot0_Slot_dual_slot0_get (insn) == 219 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3952dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_EXT_2FIFO_3; + if (Field_dsp340050b49a6c_fld3601dual_slot0_Slot_dual_slot0_get (insn) == 213 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3945dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_CM2AR_LN; + if (Field_dsp340050b49a6c_fld3603dual_slot0_Slot_dual_slot0_get (insn) == 215 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3945dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_CM2AR_LN_I; + if (Field_dsp340050b49a6c_fld3604dual_slot0_Slot_dual_slot0_get (insn) == 111 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 1 && + Field_dsp340050b49a6c_fld3946dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_CM2AR_LN_R; + if (Field_dsp340050b49a6c_fld3606dual_slot0_Slot_dual_slot0_get (insn) == 5 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 2) + return OPCODE_ABS_S; + if (Field_dsp340050b49a6c_fld3607dual_slot0_Slot_dual_slot0_get (insn) == 21 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 2) + return OPCODE_MOV_S; + if (Field_dsp340050b49a6c_fld3608dual_slot0_Slot_dual_slot0_get (insn) == 37 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 2) + return OPCODE_NEG_S; + if (Field_dsp340050b49a6c_fld3609dual_slot0_Slot_dual_slot0_get (insn) == 106 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3620dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_MOVAC; + if (Field_dsp340050b49a6c_fld3611dual_slot0_Slot_dual_slot0_get (insn) == 107 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3620dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_SWAPAC_RI; + if (Field_dsp340050b49a6c_fld3612dual_slot0_Slot_dual_slot0_get (insn) == 21 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3602_Slot_dual_slot0_get (insn) == 0) + return OPCODE_PUSH32; + if (Field_dsp340050b49a6c_fld3613dual_slot0_Slot_dual_slot0_get (insn) == 21 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3936dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_RFR; + if (Field_dsp340050b49a6c_fld3614dual_slot0_Slot_dual_slot0_get (insn) == 21 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld2079_Slot_dual_slot0_get (insn) == 0) + return OPCODE_SLL; + if (Field_dsp340050b49a6c_fld3615dual_slot0_Slot_dual_slot0_get (insn) == 21 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3958dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_ASRAC; + if (Field_dsp340050b49a6c_fld3616dual_slot0_Slot_dual_slot0_get (insn) == 21 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3947dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_MOV2AC32_I; + if (Field_dsp340050b49a6c_fld3618dual_slot0_Slot_dual_slot0_get (insn) == 21 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 2 && + Field_dsp340050b49a6c_fld3949dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_MOV2AC32_R; + if (Field_dsp340050b49a6c_fld3619_Slot_dual_slot0_get (insn) == 1 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 4 && + Field_dsp340050b49a6c_fld3940dual_slot0_Slot_dual_slot0_get (insn) == 0) + return OPCODE_FLOOR_S; + if (Field_dsp340050b49a6c_fld3620dual_slot0_Slot_dual_slot0_get (insn) == 1 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 3 && + Field_dsp340050b49a6c_fld2048_Slot_dual_slot0_get (insn) == 0) + return OPCODE_L32I; + if (Field_dsp340050b49a6c_fld3621dual_slot0_Slot_dual_slot0_get (insn) == 42 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SAC_IH; + if (Field_dsp340050b49a6c_fld3622dual_slot0_Slot_dual_slot0_get (insn) == 43 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SAC_RH; + if (Field_dsp340050b49a6c_fld3623dual_slot0_Slot_dual_slot0_get (insn) == 44 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SAC_IL; + if (Field_dsp340050b49a6c_fld3624dual_slot0_Slot_dual_slot0_get (insn) == 45 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SAC_RL; + if (Field_dsp340050b49a6c_fld3625dual_slot0_Slot_dual_slot0_get (insn) == 38 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 4 && + Field_dsp340050b49a6c_fld3602_Slot_dual_slot0_get (insn) == 0) + return OPCODE_MOVI_N; + if (Field_dsp340050b49a6c_fld3626dual_slot0_Slot_dual_slot0_get (insn) == 39 && + Field_op0_s23_Slot_dual_slot0_get (insn) == 4 && + Field_dsp340050b49a6c_fld3602_Slot_dual_slot0_get (insn) == 0) + return OPCODE_SAC2X64_3; + switch (Field_imm8_Slot_dual_slot0_get (insn)) + { + case 0: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_ADDX4; + break; + case 1: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_ADDX8; + break; + case 2: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_AND; + break; + case 3: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_L32I_N; + break; + case 4: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_ANDB; + break; + case 5: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_LCM_PINC_X; + break; + case 6: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_LCM_X; + break; + case 7: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_LCM_XU; + break; + case 8: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_CEIL_S; + break; + case 9: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_LP_X; + break; + case 10: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_LQ_X; + break; + case 11: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_LUT0; + break; + case 12: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_LSXU; + break; + case 13: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_LUT1; + break; + case 14: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_LUT2; + break; + case 15: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_LUT3; + break; + case 16: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_CLAMPS; + break; + case 17: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MADD_S; + break; + case 18: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MAX; + break; + case 19: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MINU; + break; + case 20: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MAXU; + break; + case 21: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MOVEQZ; + break; + case 22: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MOVEQZ_S; + break; + case 23: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MOVF_S; + break; + case 24: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MIN; + break; + case 25: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MOVGEZ; + break; + case 26: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MOVGEZ_S; + break; + case 27: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MOVLTZ_S; + break; + case 28: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MOVLTZ; + break; + case 29: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MOVNEZ; + break; + case 30: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MOVNEZ_S; + break; + case 31: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MOVT; + break; + case 32: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_COMB_AR; + break; + case 33: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MOVT_S; + break; + case 34: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MSUB_S; + break; + case 35: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_OLT_S; + break; + case 36: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_MUL_S; + break; + case 37: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_OR; + break; + case 38: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_ORB; + break; + case 39: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_ROUND_S; + break; + case 40: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_OEQ_S; + break; + case 41: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_S32I_N; + break; + case 46: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SCM; + break; + case 47: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SCM_PINC_X; + break; + case 48: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_OLE_S; + break; + case 49: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SCM_X; + break; + case 50: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SCM_XU; + break; + case 51: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SRLI; + break; + case 52: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SEXT; + break; + case 53: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SSX; + break; + case 54: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SSXU; + break; + case 55: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_STORE_P; + break; + case 56: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SRC; + break; + case 57: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_STORE_Q; + break; + case 58: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_STSWAPBM; + break; + case 59: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SUB; + break; + case 60: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_STSWAPBMU; + break; + case 61: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SUB_S; + break; + case 62: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SUBX2; + break; + case 63: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SUBX4; + break; + case 64: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_FLOAT_S; + break; + case 65: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_SUBX8; + break; + case 66: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_TRUNC_S; + break; + case 67: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_UN_S; + break; + case 68: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_UEQ_S; + break; + case 69: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_UTRUNC_S; + break; + case 70: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_XOR; + break; + case 71: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_XORB; + break; + case 72: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 4) + return OPCODE_UFLOAT_S; + break; + case 252: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_ADD; + break; + case 253: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_ADD_S; + break; + case 254: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_ADDI_N; + break; + case 255: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 1) + return OPCODE_ADDX2; + break; + } + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 5) + return OPCODE_L32R; + switch (Field_r_Slot_dual_slot0_get (insn)) + { + case 0: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 3) + return OPCODE_BNE; + break; + case 1: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 3) + return OPCODE_BNONE; + break; + case 2: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 3) + return OPCODE_L16SI; + break; + case 3: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 3) + return OPCODE_L8UI; + break; + case 4: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_ADDI; + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 3) + return OPCODE_L16UI; + break; + case 5: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BALL; + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 3) + return OPCODE_S16I; + break; + case 6: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BANY; + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 3) + return OPCODE_S32I; + break; + case 7: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BBC; + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 3) + return OPCODE_S8I; + break; + case 8: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_ADDMI; + break; + case 9: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BBS; + break; + case 10: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BEQ; + break; + case 11: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BGEU; + break; + case 12: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BGE; + break; + case 13: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BLT; + break; + case 14: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BLTU; + break; + case 15: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 0) + return OPCODE_BNALL; + break; + } + switch (Field_t_Slot_dual_slot0_get (insn)) + { + case 0: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 2) + return OPCODE_BEQI; + break; + case 1: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 2) + return OPCODE_BGEI; + break; + case 2: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 2) + return OPCODE_BGEUI; + break; + case 3: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 2) + return OPCODE_BNEI; + break; + case 4: + if (Field_op0_s23_Slot_dual_slot0_get (insn) == 2) + return OPCODE_BLTI; + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_gp_slot1_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2394gp_slot1_Slot_gp_slot1_get (insn)) + { + case 0: + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 0) + return OPCODE_CMAC; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 1) + return OPCODE_CMPY; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 2) + return OPCODE_MAC; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 3) + return OPCODE_MACS; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 4) + return OPCODE_MACXP_1; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 5) + return OPCODE_MACXP_3; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 6) + return OPCODE_MPY8; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 7) + return OPCODE_MPYXP_0; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 8) + return OPCODE_MPYXP_2; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 9) + return OPCODE_NORMACD; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 10) + return OPCODE_RCMAC; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 11) + return OPCODE_RMAC; + break; + case 1: + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 0) + return OPCODE_CMACS; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 1) + return OPCODE_CMPYS; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 2) + return OPCODE_MAC8; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 3) + return OPCODE_MACXP_0; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 4) + return OPCODE_MACXP_2; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 5) + return OPCODE_MPY; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 6) + return OPCODE_MPYS; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 7) + return OPCODE_MPYXP_1; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 8) + return OPCODE_MPYXP_3; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 9) + return OPCODE_NORMD; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 10) + return OPCODE_RCMPY; + if (Field_op0_s4_Slot_gp_slot1_get (insn) == 11) + return OPCODE_RMPY; + break; + } + if (Field_dsp340050b49a6c_fld2395gp_slot1_Slot_gp_slot1_get (insn) == 0 && + Field_op0_s4_Slot_gp_slot1_get (insn) == 12) + return OPCODE_ADD2AC; + if (Field_dsp340050b49a6c_fld2397gp_slot1_Slot_gp_slot1_get (insn) == 1 && + Field_op0_s4_Slot_gp_slot1_get (insn) == 12) + return OPCODE_MOV2AC; + if (Field_dsp340050b49a6c_fld2398gp_slot1_Slot_gp_slot1_get (insn) == 2 && + Field_op0_s4_Slot_gp_slot1_get (insn) == 12) + return OPCODE_SUB2AC; + if (Field_dsp340050b49a6c_fld2399gp_slot1_Slot_gp_slot1_get (insn) == 3 && + Field_op0_s4_Slot_gp_slot1_get (insn) == 12 && + Field_dsp340050b49a6c_fld3681gp_slot1_Slot_gp_slot1_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld2400gp_slot1_Slot_gp_slot1_get (insn) == 8 && + Field_op0_s4_Slot_gp_slot1_get (insn) == 12 && + Field_dsp340050b49a6c_fld3683gp_slot1_Slot_gp_slot1_get (insn) == 0) + return OPCODE_NORMACPQ_I; + if (Field_dsp340050b49a6c_fld2402gp_slot1_Slot_gp_slot1_get (insn) == 9 && + Field_op0_s4_Slot_gp_slot1_get (insn) == 12 && + Field_dsp340050b49a6c_fld3683gp_slot1_Slot_gp_slot1_get (insn) == 0) + return OPCODE_NORMACPQ_R; + if (Field_dsp340050b49a6c_fld2403gp_slot1_Slot_gp_slot1_get (insn) == 5 && + Field_op0_s4_Slot_gp_slot1_get (insn) == 12 && + Field_dsp340050b49a6c_fld3684gp_slot1_Slot_gp_slot1_get (insn) == 0) + return OPCODE_NORMPYPQ_I; + if (Field_dsp340050b49a6c_fld2405gp_slot1_Slot_gp_slot1_get (insn) == 3 && + Field_op0_s4_Slot_gp_slot1_get (insn) == 12 && + Field_dsp340050b49a6c_fld3686gp_slot1_Slot_gp_slot1_get (insn) == 0) + return OPCODE_NORMPYPQ_R; + switch (Field_op0_s4_Slot_gp_slot1_get (insn)) + { + case 13: + return OPCODE_CMPY2CM; + case 14: + return OPCODE_LIN_INT; + case 15: + return OPCODE_MPY2CM; + case 16: + return OPCODE_MPYADD8_2CM; + case 17: + return OPCODE_RCMPY2CM; + case 18: + return OPCODE_RMPY2CM; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_dot_slot2_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2049_Slot_dot_slot2_get (insn)) + { + case 2: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_t_Slot_dot_slot2_get (insn) == 0) + return OPCODE_OR128; + break; + case 3: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2029_Slot_dot_slot2_get (insn) == 0) + return OPCODE_PERM; + break; + } + if (Field_dsp340050b49a6c_fld2532dot_slot2_Slot_dot_slot2_get (insn) == 0 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ADD32; + if (Field_dsp340050b49a6c_fld2533dot_slot2_Slot_dot_slot2_get (insn) == 1 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ADDCM; + if (Field_dsp340050b49a6c_fld2534dot_slot2_Slot_dot_slot2_get (insn) == 2 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ADDWRP; + if (Field_dsp340050b49a6c_fld2535dot_slot2_Slot_dot_slot2_get (insn) == 3 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ASR; + if (Field_dsp340050b49a6c_fld2536dot_slot2_Slot_dot_slot2_get (insn) == 4 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_AND128; + if (Field_dsp340050b49a6c_fld2537dot_slot2_Slot_dot_slot2_get (insn) == 5 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ASR32; + if (Field_dsp340050b49a6c_fld2538dot_slot2_Slot_dot_slot2_get (insn) == 6 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_EXTUI4; + if (Field_dsp340050b49a6c_fld2539dot_slot2_Slot_dot_slot2_get (insn) == 7 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_LUT; + if (Field_dsp340050b49a6c_fld2540dot_slot2_Slot_dot_slot2_get (insn) == 8 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ASL; + if (Field_dsp340050b49a6c_fld2541dot_slot2_Slot_dot_slot2_get (insn) == 9 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_LUT_IEXT; + if (Field_dsp340050b49a6c_fld2542dot_slot2_Slot_dot_slot2_get (insn) == 10 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_LUT_REXT; + if (Field_dsp340050b49a6c_fld2543dot_slot2_Slot_dot_slot2_get (insn) == 11 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MEAN; + if (Field_dsp340050b49a6c_fld2544dot_slot2_Slot_dot_slot2_get (insn) == 12 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MAX8; + if (Field_dsp340050b49a6c_fld2545dot_slot2_Slot_dot_slot2_get (insn) == 13 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MEAN32; + if (Field_dsp340050b49a6c_fld2546dot_slot2_Slot_dot_slot2_get (insn) == 14 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MIN8; + if (Field_dsp340050b49a6c_fld2547dot_slot2_Slot_dot_slot2_get (insn) == 15 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOV2CM2PQ; + if (Field_dsp340050b49a6c_fld2548dot_slot2_Slot_dot_slot2_get (insn) == 16 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ASL32; + if (Field_dsp340050b49a6c_fld2549dot_slot2_Slot_dot_slot2_get (insn) == 17 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND8_0; + if (Field_dsp340050b49a6c_fld2550dot_slot2_Slot_dot_slot2_get (insn) == 18 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND8_1; + if (Field_dsp340050b49a6c_fld2551dot_slot2_Slot_dot_slot2_get (insn) == 19 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND8_4; + if (Field_dsp340050b49a6c_fld2552dot_slot2_Slot_dot_slot2_get (insn) == 20 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND8_2; + if (Field_dsp340050b49a6c_fld2553dot_slot2_Slot_dot_slot2_get (insn) == 21 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND8_5; + if (Field_dsp340050b49a6c_fld2554dot_slot2_Slot_dot_slot2_get (insn) == 22 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND8_6; + if (Field_dsp340050b49a6c_fld2555dot_slot2_Slot_dot_slot2_get (insn) == 23 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND8_7; + if (Field_dsp340050b49a6c_fld2556dot_slot2_Slot_dot_slot2_get (insn) == 24 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND8_3; + if (Field_dsp340050b49a6c_fld2557dot_slot2_Slot_dot_slot2_get (insn) == 25 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND_0; + if (Field_dsp340050b49a6c_fld2558dot_slot2_Slot_dot_slot2_get (insn) == 26 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND_1; + if (Field_dsp340050b49a6c_fld2559dot_slot2_Slot_dot_slot2_get (insn) == 27 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND_3; + if (Field_dsp340050b49a6c_fld2560dot_slot2_Slot_dot_slot2_get (insn) == 28 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND_2; + if (Field_dsp340050b49a6c_fld2561dot_slot2_Slot_dot_slot2_get (insn) == 29 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND_4; + if (Field_dsp340050b49a6c_fld2562dot_slot2_Slot_dot_slot2_get (insn) == 30 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND_5; + if (Field_dsp340050b49a6c_fld2563dot_slot2_Slot_dot_slot2_get (insn) == 31 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCND_6; + if (Field_dsp340050b49a6c_fld2564dot_slot2_Slot_dot_slot2_get (insn) == 32 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ASLM; + if (Field_dsp340050b49a6c_fld2565dot_slot2_Slot_dot_slot2_get (insn) == 33 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ASRM; + if (Field_dsp340050b49a6c_fld2566dot_slot2_Slot_dot_slot2_get (insn) == 34 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_CMP8; + if (Field_dsp340050b49a6c_fld2567dot_slot2_Slot_dot_slot2_get (insn) == 35 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_LSRM; + if (Field_dsp340050b49a6c_fld2568dot_slot2_Slot_dot_slot2_get (insn) == 36 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_CMP_I; + if (Field_dsp340050b49a6c_fld2569dot_slot2_Slot_dot_slot2_get (insn) == 517 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ABS8; + if (Field_dsp340050b49a6c_fld2571dot_slot2_Slot_dot_slot2_get (insn) == 533 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_CONJ; + if (Field_dsp340050b49a6c_fld2572dot_slot2_Slot_dot_slot2_get (insn) == 549 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_LUT_PHASOR; + if (Field_dsp340050b49a6c_fld2573dot_slot2_Slot_dot_slot2_get (insn) == 565 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_NEGCM; + if (Field_dsp340050b49a6c_fld2574dot_slot2_Slot_dot_slot2_get (insn) == 581 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCM; + if (Field_dsp340050b49a6c_fld2575dot_slot2_Slot_dot_slot2_get (insn) == 597 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_NOT128; + if (Field_dsp340050b49a6c_fld2576dot_slot2_Slot_dot_slot2_get (insn) == 613 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_TRANS; + if (Field_dsp340050b49a6c_fld2577dot_slot2_Slot_dot_slot2_get (insn) == 629 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_CLRCM; + if (Field_dsp340050b49a6c_fld2578_Slot_dot_slot2_get (insn) == 0 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_LUT_AR; + if (Field_dsp340050b49a6c_fld2579dot_slot2_Slot_dot_slot2_get (insn) == 1653 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_GET_ARGMAX; + if (Field_dsp340050b49a6c_fld2580dot_slot2_Slot_dot_slot2_get (insn) == 2677 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_GET_HSAR; + if (Field_dsp340050b49a6c_fld2581dot_slot2_Slot_dot_slot2_get (insn) == 3701 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_GET_NCO; + if (Field_dsp340050b49a6c_fld2582dot_slot2_Slot_dot_slot2_get (insn) == 4725 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_GET_HSAR2SAR; + if (Field_dsp340050b49a6c_fld2583dot_slot2_Slot_dot_slot2_get (insn) == 5749 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_GET_SAR; + if (Field_dsp340050b49a6c_fld2584dot_slot2_Slot_dot_slot2_get (insn) == 6773 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld2585dot_slot2_Slot_dot_slot2_get (insn) == 7797 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld2586dot_slot2_Slot_dot_slot2_get (insn) == 8821 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_GET_MAX; + if (Field_dsp340050b49a6c_fld2587dot_slot2_Slot_dot_slot2_get (insn) == 9845 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld2588dot_slot2_Slot_dot_slot2_get (insn) == 10869 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld2589dot_slot2_Slot_dot_slot2_get (insn) == 11893 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld2590dot_slot2_Slot_dot_slot2_get (insn) == 12917 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_4; + switch (Field_dsp340050b49a6c_fld2591dot_slot2_Slot_dot_slot2_get (insn)) + { + case 221301: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_0; + break; + case 221557: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_2; + break; + case 221813: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_3; + break; + case 222069: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_0; + break; + case 222325: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_4; + break; + case 222581: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_1; + break; + case 222837: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_2; + break; + case 223093: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_3; + break; + } + if (Field_dsp340050b49a6c_fld2592dot_slot2_Slot_dot_slot2_get (insn) == 55925 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3708dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_5; + if (Field_dsp340050b49a6c_fld2595dot_slot2_Slot_dot_slot2_get (insn) == 56181 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3708dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld2596dot_slot2_Slot_dot_slot2_get (insn) == 7797 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3724dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_1; + if (Field_dsp340050b49a6c_fld2598dot_slot2_Slot_dot_slot2_get (insn) == 645 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_NCO_UPDATE; + if (Field_dsp340050b49a6c_fld2599dot_slot2_Slot_dot_slot2_get (insn) == 2197 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3709dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_SET_ARGMAX; + if (Field_dsp340050b49a6c_fld2601dot_slot2_Slot_dot_slot2_get (insn) == 2453 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3709dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_SET_NCO; + if (Field_dsp340050b49a6c_fld2602dot_slot2_Slot_dot_slot2_get (insn) == 1429 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3713dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_SET_SAR; + if (Field_dsp340050b49a6c_fld2604dot_slot2_Slot_dot_slot2_get (insn) == 341 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3710dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_SET_HSAR; + if (Field_dsp340050b49a6c_fld2606dot_slot2_Slot_dot_slot2_get (insn) == 181 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3711dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_SET_MAX; + if (Field_dsp340050b49a6c_fld2608dot_slot2_Slot_dot_slot2_get (insn) == 19 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_2CMPQ_0; + if (Field_dsp340050b49a6c_fld2609dot_slot2_Slot_dot_slot2_get (insn) == 51 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_2CMPQ_1; + if (Field_dsp340050b49a6c_fld2610dot_slot2_Slot_dot_slot2_get (insn) == 83 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_2CMPQ_2; + if (Field_dsp340050b49a6c_fld2611dot_slot2_Slot_dot_slot2_get (insn) == 899 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_PUSH2X128_PQ; + if (Field_dsp340050b49a6c_fld2612_Slot_dot_slot2_get (insn) == 32 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_QREADY; + if (Field_dsp340050b49a6c_fld2613dot_slot2_Slot_dot_slot2_get (insn) == 1811 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_0; + switch (Field_dsp340050b49a6c_fld2614_Slot_dot_slot2_get (insn)) + { + case 66: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_MOVPQ2PQ; + break; + case 67: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_SET_EXT_REGS; + break; + case 68: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_PUSH128_PQ; + break; + case 69: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_SUBARX; + break; + case 70: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_SWAPB; + break; + case 71: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_WRTIEP; + break; + case 72: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_PUSH32; + break; + } + if (Field_dsp340050b49a6c_fld2615dot_slot2_Slot_dot_slot2_get (insn) == 1819 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_3; + if (Field_dsp340050b49a6c_fld2616dot_slot2_Slot_dot_slot2_get (insn) == 1827 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_1; + if (Field_dsp340050b49a6c_fld2617dot_slot2_Slot_dot_slot2_get (insn) == 1835 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_4; + if (Field_dsp340050b49a6c_fld2618dot_slot2_Slot_dot_slot2_get (insn) == 1843 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_5; + if (Field_dsp340050b49a6c_fld2619dot_slot2_Slot_dot_slot2_get (insn) == 3702 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld2620dot_slot2_Slot_dot_slot2_get (insn) == 3703 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld2621dot_slot2_Slot_dot_slot2_get (insn) == 1859 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_2; + if (Field_dsp340050b49a6c_fld2622dot_slot2_Slot_dot_slot2_get (insn) == 1867 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2047_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld2623dot_slot2_Slot_dot_slot2_get (insn) == 939 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3727dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld2624dot_slot2_Slot_dot_slot2_get (insn) == 475 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3729dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_RDTIEP; + if (Field_dsp340050b49a6c_fld2625_Slot_dot_slot2_get (insn) == 19 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3731dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_SETTIEP; + if (Field_dsp340050b49a6c_fld2626dot_slot2_Slot_dot_slot2_get (insn) == 51 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3715_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP128_2CMPQ_3; + if (Field_dsp340050b49a6c_fld2628dot_slot2_Slot_dot_slot2_get (insn) == 51 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3722_Slot_dot_slot2_get (insn) == 0) + return OPCODE_PQ2CM; + if (Field_dsp340050b49a6c_fld2630dot_slot2_Slot_dot_slot2_get (insn) == 10 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2032_Slot_dot_slot2_get (insn) == 0) + return OPCODE_CMP_R; + if (Field_dsp340050b49a6c_fld2632dot_slot2_Slot_dot_slot2_get (insn) == 11 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_t_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ADD16; + if (Field_dsp340050b49a6c_fld2633dot_slot2_Slot_dot_slot2_get (insn) == 6 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3733dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_LSLM; + if (Field_dsp340050b49a6c_fld2635dot_slot2_Slot_dot_slot2_get (insn) == 7 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3719dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_CM2AR_LN; + switch (Field_dsp340050b49a6c_fld2636dot_slot2_Slot_dot_slot2_get (insn)) + { + case 1168: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_AR2SAR_DUP; + break; + case 1169: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_POP2X128_2PQ_01; + break; + case 1170: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_POP2X128_2PQ_03; + break; + case 1171: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_WRTBSIGQ; + break; + } + if (Field_dsp340050b49a6c_fld2637dot_slot2_Slot_dot_slot2_get (insn) == 586 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3725dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP2X128_2PQ_21; + if (Field_dsp340050b49a6c_fld2640dot_slot2_Slot_dot_slot2_get (insn) == 587 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3725dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_WRTSIGQ; + if (Field_dsp340050b49a6c_fld2641dot_slot2_Slot_dot_slot2_get (insn) == 147 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3726dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_POP2X128_2PQ_23; + if (Field_dsp340050b49a6c_fld2642dot_slot2_Slot_dot_slot2_get (insn) == 74 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2605_Slot_dot_slot2_get (insn) == 0) + return OPCODE_CLRTIEP; + if (Field_dsp340050b49a6c_fld2643dot_slot2_Slot_dot_slot2_get (insn) == 75 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2605_Slot_dot_slot2_get (insn) == 0) + return OPCODE_WRTBSIGQM; + if (Field_dsp340050b49a6c_fld2644dot_slot2_Slot_dot_slot2_get (insn) == 4 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3732dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ADDAR2; + if (Field_dsp340050b49a6c_fld2645dot_slot2_Slot_dot_slot2_get (insn) == 4 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3714dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_AR2CM_DUP; + if (Field_dsp340050b49a6c_fld2646dot_slot2_Slot_dot_slot2_get (insn) == 4 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3721dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVAR2; + if (Field_dsp340050b49a6c_fld2647dot_slot2_Slot_dot_slot2_get (insn) == 16 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_MOVCND_7; + if (Field_dsp340050b49a6c_fld2648dot_slot2_Slot_dot_slot2_get (insn) == 17 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_SUB32; + if (Field_dsp340050b49a6c_fld2649dot_slot2_Slot_dot_slot2_get (insn) == 18 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_SUBCM; + if (Field_dsp340050b49a6c_fld2650dot_slot2_Slot_dot_slot2_get (insn) == 19 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_XOR128; + if (Field_dsp340050b49a6c_fld2651dot_slot2_Slot_dot_slot2_get (insn) == 20 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1) + return OPCODE_SUBMEAN; + if (Field_dsp340050b49a6c_fld2652dot_slot2_Slot_dot_slot2_get (insn) == 37 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3718_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ARGMAX8; + if (Field_dsp340050b49a6c_fld2654dot_slot2_Slot_dot_slot2_get (insn) == 53 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3728dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_PUSH128; + if (Field_dsp340050b49a6c_fld2655dot_slot2_Slot_dot_slot2_get (insn) == 11 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2029_Slot_dot_slot2_get (insn) == 0) + return OPCODE_MOVCM2PQ; + if (Field_dsp340050b49a6c_fld2656dot_slot2_Slot_dot_slot2_get (insn) == 6 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3712_Slot_dot_slot2_get (insn) == 0) + return OPCODE_SUBWRP; + if (Field_dsp340050b49a6c_fld2657dot_slot2_Slot_dot_slot2_get (insn) == 7 && + Field_op0_s6_Slot_dot_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2029_Slot_dot_slot2_get (insn) == 0) + return OPCODE_ASLM32; + switch (Field_dsp340050b49a6c_fld2658dot_slot2_Slot_dot_slot2_get (insn)) + { + case 0: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3717dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_AR2PQ_LN; + break; + case 1: + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3716dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_AR2CM_LN; + break; + } + if (Field_op0_s6_Slot_dot_slot2_get (insn) == 3 && + Field_dsp340050b49a6c_fld3723dot_slot2_Slot_dot_slot2_get (insn) == 0) + return OPCODE_LUT_WRITE; + return XTENSA_UNDEFINED; +} + +static int +Slot_dot_slot1_decode (const xtensa_insnbuf insn) +{ + switch (Field_op0_s7_Slot_dot_slot1_get (insn)) + { + case 0: + return OPCODE_CDOT; + case 1: + return OPCODE_CDOTAC; + case 2: + return OPCODE_CDOTACS; + case 3: + return OPCODE_DOT; + case 4: + return OPCODE_DOTAC; + case 5: + return OPCODE_DOTACS; + case 6: + return OPCODE_MACD8; + case 7: + return OPCODE_MACPQXP_0; + case 8: + return OPCODE_MACPQXP_1; + case 9: + return OPCODE_MACPQXP_2; + case 10: + return OPCODE_MACPQXP_3; + case 11: + return OPCODE_MACXP2_0; + case 12: + return OPCODE_MACXP2_1; + case 13: + return OPCODE_MPYD8; + case 14: + return OPCODE_MPYPQXP_0; + case 15: + return OPCODE_MPYPQXP_1; + case 16: + return OPCODE_MPYPQXP_2; + case 17: + return OPCODE_MPYPQXP_3; + case 18: + return OPCODE_MPYXP2_0; + case 19: + return OPCODE_MPYXP2_1; + case 20: + if (Field_dsp340050b49a6c_fld3734dot_slot1_Slot_dot_slot1_get (insn) == 0) + return OPCODE_NOP; + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_pq_slot1_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2825pq_slot1_Slot_pq_slot1_get (insn)) + { + case 0: + if (Field_op0_s10_Slot_pq_slot1_get (insn) == 0) + return OPCODE_CMPYXP2PQ; + break; + case 1: + if (Field_op0_s10_Slot_pq_slot1_get (insn) == 0) + return OPCODE_MPYXP2PQ; + break; + } + if (Field_dsp340050b49a6c_fld2826pq_slot1_Slot_pq_slot1_get (insn) == 1 && + Field_op0_s10_Slot_pq_slot1_get (insn) == 0 && + Field_dsp340050b49a6c_fld3761pq_slot1_Slot_pq_slot1_get (insn) == 0) + return OPCODE_NOP; + switch (Field_op0_s10_Slot_pq_slot1_get (insn)) + { + case 1: + return OPCODE_CMPY2PQ; + case 2: + return OPCODE_MPY2PQ; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_acc2_slot2_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2045_Slot_acc2_slot2_get (insn)) + { + case 0: + if (Field_op0_s12_Slot_acc2_slot2_get (insn) == 0) + return OPCODE_ARGMAX8; + break; + case 2: + if (Field_op0_s12_Slot_acc2_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2046_Slot_acc2_slot2_get (insn) == 0) + return OPCODE_POP32_0; + break; + case 3: + if (Field_op0_s12_Slot_acc2_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2046_Slot_acc2_slot2_get (insn) == 0) + return OPCODE_POP32_3; + break; + } + switch (Field_dsp340050b49a6c_fld2953acc2_slot2_Slot_acc2_slot2_get (insn)) + { + case 2: + if (Field_op0_s12_Slot_acc2_slot2_get (insn) == 0) + return OPCODE_PUSH128; + break; + case 3: + if (Field_op0_s12_Slot_acc2_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3782acc2_slot2_Slot_acc2_slot2_get (insn) == 0) + return OPCODE_NOP; + break; + } + if (Field_dsp340050b49a6c_fld2954acc2_slot2_Slot_acc2_slot2_get (insn) == 1 && + Field_op0_s12_Slot_acc2_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3786acc2_slot2_Slot_acc2_slot2_get (insn) == 0) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld2955acc2_slot2_Slot_acc2_slot2_get (insn) == 1 && + Field_op0_s12_Slot_acc2_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3788acc2_slot2_Slot_acc2_slot2_get (insn) == 0) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld2956acc2_slot2_Slot_acc2_slot2_get (insn) == 3 && + Field_op0_s12_Slot_acc2_slot2_get (insn) == 1) + return OPCODE_CLRCM; + if (Field_dsp340050b49a6c_fld2957acc2_slot2_Slot_acc2_slot2_get (insn) == 19 && + Field_op0_s12_Slot_acc2_slot2_get (insn) == 1) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld2958acc2_slot2_Slot_acc2_slot2_get (insn) == 35 && + Field_op0_s12_Slot_acc2_slot2_get (insn) == 1) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld2959acc2_slot2_Slot_acc2_slot2_get (insn) == 51 && + Field_op0_s12_Slot_acc2_slot2_get (insn) == 1) + return OPCODE_POP128_4; + if (Field_dsp340050b49a6c_fld2960acc2_slot2_Slot_acc2_slot2_get (insn) == 35 && + Field_op0_s12_Slot_acc2_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3784acc2_slot2_Slot_acc2_slot2_get (insn) == 0) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld2963acc2_slot2_Slot_acc2_slot2_get (insn) == 51 && + Field_op0_s12_Slot_acc2_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3784acc2_slot2_Slot_acc2_slot2_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld2964acc2_slot2_Slot_acc2_slot2_get (insn) == 19 && + Field_op0_s12_Slot_acc2_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3785acc2_slot2_Slot_acc2_slot2_get (insn) == 0) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld2966acc2_slot2_Slot_acc2_slot2_get (insn) == 1 && + Field_op0_s12_Slot_acc2_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3783acc2_slot2_Slot_acc2_slot2_get (insn) == 0) + return OPCODE_NCO_UPDATE; + if (Field_dsp340050b49a6c_fld2967acc2_slot2_Slot_acc2_slot2_get (insn) == 1 && + Field_op0_s12_Slot_acc2_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2056_Slot_acc2_slot2_get (insn) == 0) + return OPCODE_NEGCM; + switch (Field_op0_s12_Slot_acc2_slot2_get (insn)) + { + case 2: + if (Field_dsp340050b49a6c_fld2046_Slot_acc2_slot2_get (insn) == 0) + return OPCODE_PUSH32; + break; + case 3: + return OPCODE_ADD32; + case 4: + return OPCODE_ADDCM; + case 5: + return OPCODE_ASR; + case 6: + return OPCODE_LUT_IEXT; + case 7: + return OPCODE_PERM; + } + switch (Field_s_Slot_acc2_slot2_get (insn)) + { + case 0: + if (Field_op0_s12_Slot_acc2_slot2_get (insn) == 1) + return OPCODE_CONJ; + break; + case 1: + if (Field_op0_s12_Slot_acc2_slot2_get (insn) == 1) + return OPCODE_LUT_PHASOR; + break; + case 2: + if (Field_op0_s12_Slot_acc2_slot2_get (insn) == 1) + return OPCODE_MOVCM; + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_acc2_slot1_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2075_Slot_acc2_slot1_get (insn)) + { + case 0: + if (Field_op0_s13_Slot_acc2_slot1_get (insn) == 0 && + Field_dsp340050b49a6c_fld2031_Slot_acc2_slot1_get (insn) == 0) + return OPCODE_RFIRD; + break; + case 1: + if (Field_op0_s13_Slot_acc2_slot1_get (insn) == 0 && + Field_dsp340050b49a6c_fld2031_Slot_acc2_slot1_get (insn) == 0) + return OPCODE_RFIRDA; + break; + } + if (Field_dsp340050b49a6c_fld2968acc2_slot1_Slot_acc2_slot1_get (insn) == 1 && + Field_op0_s13_Slot_acc2_slot1_get (insn) == 0 && + Field_dsp340050b49a6c_fld3793acc2_slot1_Slot_acc2_slot1_get (insn) == 0) + return OPCODE_SWAPAC_R; + if (Field_dsp340050b49a6c_fld2969acc2_slot1_Slot_acc2_slot1_get (insn) == 1 && + Field_op0_s13_Slot_acc2_slot1_get (insn) == 0 && + Field_dsp340050b49a6c_fld3790acc2_slot1_Slot_acc2_slot1_get (insn) == 0) + return OPCODE_NOP; + switch (Field_op0_s13_Slot_acc2_slot1_get (insn)) + { + case 1: + return OPCODE_LLRPRE1; + case 2: + return OPCODE_RFIR; + case 3: + return OPCODE_RFIRA; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_smod_slot2_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2049_Slot_smod_slot2_get (insn)) + { + case 2: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_t_Slot_smod_slot2_get (insn) == 0) + return OPCODE_OR128; + break; + case 3: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2029_Slot_smod_slot2_get (insn) == 0) + return OPCODE_PERM; + break; + } + if (Field_dsp340050b49a6c_fld2991smod_slot2_Slot_smod_slot2_get (insn) == 0 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ADD32; + if (Field_dsp340050b49a6c_fld2992smod_slot2_Slot_smod_slot2_get (insn) == 1 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ADDCM; + if (Field_dsp340050b49a6c_fld2993smod_slot2_Slot_smod_slot2_get (insn) == 2 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ADDWRP; + if (Field_dsp340050b49a6c_fld2994smod_slot2_Slot_smod_slot2_get (insn) == 3 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ASR; + if (Field_dsp340050b49a6c_fld2995smod_slot2_Slot_smod_slot2_get (insn) == 4 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_AND128; + if (Field_dsp340050b49a6c_fld2996smod_slot2_Slot_smod_slot2_get (insn) == 5 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ASR32; + if (Field_dsp340050b49a6c_fld2997smod_slot2_Slot_smod_slot2_get (insn) == 6 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_EXTUI4; + if (Field_dsp340050b49a6c_fld2998smod_slot2_Slot_smod_slot2_get (insn) == 7 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_LUT; + if (Field_dsp340050b49a6c_fld2999smod_slot2_Slot_smod_slot2_get (insn) == 8 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ASL; + if (Field_dsp340050b49a6c_fld3000smod_slot2_Slot_smod_slot2_get (insn) == 9 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_LUT_IEXT; + if (Field_dsp340050b49a6c_fld3001smod_slot2_Slot_smod_slot2_get (insn) == 10 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_LUT_REXT; + if (Field_dsp340050b49a6c_fld3002smod_slot2_Slot_smod_slot2_get (insn) == 11 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MEAN; + if (Field_dsp340050b49a6c_fld3003smod_slot2_Slot_smod_slot2_get (insn) == 12 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MAX8; + if (Field_dsp340050b49a6c_fld3004smod_slot2_Slot_smod_slot2_get (insn) == 13 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MEAN32; + if (Field_dsp340050b49a6c_fld3005smod_slot2_Slot_smod_slot2_get (insn) == 14 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MIN8; + if (Field_dsp340050b49a6c_fld3006smod_slot2_Slot_smod_slot2_get (insn) == 15 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOV2CM2PQ; + if (Field_dsp340050b49a6c_fld3007smod_slot2_Slot_smod_slot2_get (insn) == 16 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ASL32; + if (Field_dsp340050b49a6c_fld3008smod_slot2_Slot_smod_slot2_get (insn) == 17 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND8_0; + if (Field_dsp340050b49a6c_fld3009smod_slot2_Slot_smod_slot2_get (insn) == 18 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND8_1; + if (Field_dsp340050b49a6c_fld3010smod_slot2_Slot_smod_slot2_get (insn) == 19 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND8_4; + if (Field_dsp340050b49a6c_fld3011smod_slot2_Slot_smod_slot2_get (insn) == 20 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND8_2; + if (Field_dsp340050b49a6c_fld3012smod_slot2_Slot_smod_slot2_get (insn) == 21 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND8_5; + if (Field_dsp340050b49a6c_fld3013smod_slot2_Slot_smod_slot2_get (insn) == 22 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND8_6; + if (Field_dsp340050b49a6c_fld3014smod_slot2_Slot_smod_slot2_get (insn) == 23 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND8_7; + if (Field_dsp340050b49a6c_fld3015smod_slot2_Slot_smod_slot2_get (insn) == 24 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND8_3; + if (Field_dsp340050b49a6c_fld3016smod_slot2_Slot_smod_slot2_get (insn) == 25 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND_0; + if (Field_dsp340050b49a6c_fld3017smod_slot2_Slot_smod_slot2_get (insn) == 26 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND_1; + if (Field_dsp340050b49a6c_fld3018smod_slot2_Slot_smod_slot2_get (insn) == 27 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND_3; + if (Field_dsp340050b49a6c_fld3019smod_slot2_Slot_smod_slot2_get (insn) == 28 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND_2; + if (Field_dsp340050b49a6c_fld3020smod_slot2_Slot_smod_slot2_get (insn) == 29 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND_4; + if (Field_dsp340050b49a6c_fld3021smod_slot2_Slot_smod_slot2_get (insn) == 30 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND_5; + if (Field_dsp340050b49a6c_fld3022smod_slot2_Slot_smod_slot2_get (insn) == 31 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCND_6; + if (Field_dsp340050b49a6c_fld3023smod_slot2_Slot_smod_slot2_get (insn) == 32 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ASLM; + if (Field_dsp340050b49a6c_fld3024smod_slot2_Slot_smod_slot2_get (insn) == 33 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ASRM; + if (Field_dsp340050b49a6c_fld3025smod_slot2_Slot_smod_slot2_get (insn) == 34 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_CMP8; + if (Field_dsp340050b49a6c_fld3026smod_slot2_Slot_smod_slot2_get (insn) == 35 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_LSRM; + if (Field_dsp340050b49a6c_fld3027smod_slot2_Slot_smod_slot2_get (insn) == 36 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_CMP_I; + if (Field_dsp340050b49a6c_fld3028smod_slot2_Slot_smod_slot2_get (insn) == 517 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ABS8; + if (Field_dsp340050b49a6c_fld3030smod_slot2_Slot_smod_slot2_get (insn) == 533 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_CONJ; + if (Field_dsp340050b49a6c_fld3031smod_slot2_Slot_smod_slot2_get (insn) == 549 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_LUT_PHASOR; + if (Field_dsp340050b49a6c_fld3032smod_slot2_Slot_smod_slot2_get (insn) == 565 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_NEGCM; + if (Field_dsp340050b49a6c_fld3033smod_slot2_Slot_smod_slot2_get (insn) == 581 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCM; + if (Field_dsp340050b49a6c_fld3034smod_slot2_Slot_smod_slot2_get (insn) == 597 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_NOT128; + if (Field_dsp340050b49a6c_fld3035smod_slot2_Slot_smod_slot2_get (insn) == 613 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_TRANS; + if (Field_dsp340050b49a6c_fld3036smod_slot2_Slot_smod_slot2_get (insn) == 1141 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_PUSH128; + switch (Field_dsp340050b49a6c_fld3038smod_slot2_Slot_smod_slot2_get (insn)) + { + case 8565: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_SET_ARGMAX; + break; + case 9077: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_SET_HSAR; + break; + case 9589: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_SET_MAX; + break; + case 10101: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_SET_SAR; + break; + case 10613: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_SET_NCO; + break; + } + switch (Field_dsp340050b49a6c_fld3039smod_slot2_Slot_smod_slot2_get (insn)) + { + case 11125: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_0; + break; + case 27509: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_2; + break; + case 43893: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_3; + break; + case 60277: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_0; + break; + case 76661: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_4; + break; + case 93045: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_1; + break; + case 109429: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_2; + break; + case 125813: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_3; + break; + } + if (Field_dsp340050b49a6c_fld3040smod_slot2_Slot_smod_slot2_get (insn) == 43893 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3805smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_5; + if (Field_dsp340050b49a6c_fld3043smod_slot2_Slot_smod_slot2_get (insn) == 60277 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3805smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld3044smod_slot2_Slot_smod_slot2_get (insn) == 6005 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3819smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_1; + if (Field_dsp340050b49a6c_fld3046smod_slot2_Slot_smod_slot2_get (insn) == 645 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_NCO_UPDATE; + if (Field_dsp340050b49a6c_fld3047smod_slot2_Slot_smod_slot2_get (insn) == 661 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_CLRCM; + if (Field_dsp340050b49a6c_fld3048_Slot_smod_slot2_get (insn) == 0 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_LUT_AR; + if (Field_dsp340050b49a6c_fld3049smod_slot2_Slot_smod_slot2_get (insn) == 1685 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_GET_HSAR2SAR; + if (Field_dsp340050b49a6c_fld3050smod_slot2_Slot_smod_slot2_get (insn) == 2709 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_GET_MAX; + if (Field_dsp340050b49a6c_fld3051smod_slot2_Slot_smod_slot2_get (insn) == 3733 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld3052smod_slot2_Slot_smod_slot2_get (insn) == 4757 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_GET_NCO; + if (Field_dsp340050b49a6c_fld3053smod_slot2_Slot_smod_slot2_get (insn) == 5781 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld3054smod_slot2_Slot_smod_slot2_get (insn) == 6805 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld3055smod_slot2_Slot_smod_slot2_get (insn) == 7829 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld3056smod_slot2_Slot_smod_slot2_get (insn) == 4757 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3809smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_GET_SAR; + if (Field_dsp340050b49a6c_fld3058smod_slot2_Slot_smod_slot2_get (insn) == 5781 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3809smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_4; + if (Field_dsp340050b49a6c_fld3059smod_slot2_Slot_smod_slot2_get (insn) == 3733 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3821smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld3061smod_slot2_Slot_smod_slot2_get (insn) == 341 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3806smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_GET_ARGMAX; + if (Field_dsp340050b49a6c_fld3063smod_slot2_Slot_smod_slot2_get (insn) == 181 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3807smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_GET_HSAR; + if (Field_dsp340050b49a6c_fld3065smod_slot2_Slot_smod_slot2_get (insn) == 19 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_2CMPQ_0; + if (Field_dsp340050b49a6c_fld3066smod_slot2_Slot_smod_slot2_get (insn) == 51 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_2CMPQ_1; + if (Field_dsp340050b49a6c_fld3067smod_slot2_Slot_smod_slot2_get (insn) == 83 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_2CMPQ_2; + if (Field_dsp340050b49a6c_fld3068smod_slot2_Slot_smod_slot2_get (insn) == 227 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_PUSH128_PQ; + if (Field_dsp340050b49a6c_fld3069smod_slot2_Slot_smod_slot2_get (insn) == 1803 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_0; + switch (Field_dsp340050b49a6c_fld3070_Slot_smod_slot2_get (insn)) + { + case 66: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_MOVPQ2PQ; + break; + case 67: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_SUBARX; + break; + case 68: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_PUSH32; + break; + case 69: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_SWAPB; + break; + case 70: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_WRTIEP; + break; + } + if (Field_dsp340050b49a6c_fld3071smod_slot2_Slot_smod_slot2_get (insn) == 1819 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_1; + if (Field_dsp340050b49a6c_fld3072smod_slot2_Slot_smod_slot2_get (insn) == 1835 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_2; + if (Field_dsp340050b49a6c_fld3073smod_slot2_Slot_smod_slot2_get (insn) == 1851 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_4; + if (Field_dsp340050b49a6c_fld3074smod_slot2_Slot_smod_slot2_get (insn) == 1867 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_3; + if (Field_dsp340050b49a6c_fld3075smod_slot2_Slot_smod_slot2_get (insn) == 1883 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_2PQ_5; + if (Field_dsp340050b49a6c_fld3076smod_slot2_Slot_smod_slot2_get (insn) == 3798 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld3077smod_slot2_Slot_smod_slot2_get (insn) == 3799 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld3078smod_slot2_Slot_smod_slot2_get (insn) == 3830 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld3079smod_slot2_Slot_smod_slot2_get (insn) == 3831 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld3080smod_slot2_Slot_smod_slot2_get (insn) == 147 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP128_2CMPQ_3; + if (Field_dsp340050b49a6c_fld3081smod_slot2_Slot_smod_slot2_get (insn) == 179 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2056_Slot_smod_slot2_get (insn) == 0) + return OPCODE_PUSH2X128_PQ; + if (Field_dsp340050b49a6c_fld3082smod_slot2_Slot_smod_slot2_get (insn) == 115 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3824smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_RDTIEP; + if (Field_dsp340050b49a6c_fld3084smod_slot2_Slot_smod_slot2_get (insn) == 51 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3817_Slot_smod_slot2_get (insn) == 0) + return OPCODE_PQ2CM; + if (Field_dsp340050b49a6c_fld3085smod_slot2_Slot_smod_slot2_get (insn) == 10 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld2032_Slot_smod_slot2_get (insn) == 0) + return OPCODE_CMP_R; + if (Field_dsp340050b49a6c_fld3087smod_slot2_Slot_smod_slot2_get (insn) == 11 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_t_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ADD16; + if (Field_dsp340050b49a6c_fld3088smod_slot2_Slot_smod_slot2_get (insn) == 6 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3828smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_LSLM; + if (Field_dsp340050b49a6c_fld3090smod_slot2_Slot_smod_slot2_get (insn) == 7 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 0 && + Field_dsp340050b49a6c_fld3814smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_CM2AR_LN; + switch (Field_dsp340050b49a6c_fld3091smod_slot2_Slot_smod_slot2_get (insn)) + { + case 32: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_QREADY; + break; + case 36: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2041_Slot_smod_slot2_get (insn) == 0) + return OPCODE_SET_EXT_REGS; + break; + } + switch (Field_dsp340050b49a6c_fld3092smod_slot2_Slot_smod_slot2_get (insn)) + { + case 1136: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_AR2SAR_DUP; + break; + case 1137: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_POP2X128_2PQ_01; + break; + case 1138: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_POP2X128_2PQ_03; + break; + case 1139: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_WRTBSIGQ; + break; + } + if (Field_dsp340050b49a6c_fld3093smod_slot2_Slot_smod_slot2_get (insn) == 570 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3822smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP2X128_2PQ_21; + if (Field_dsp340050b49a6c_fld3096smod_slot2_Slot_smod_slot2_get (insn) == 571 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3822smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_WRTSIGQ; + if (Field_dsp340050b49a6c_fld3097smod_slot2_Slot_smod_slot2_get (insn) == 143 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3823smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_POP2X128_2PQ_23; + if (Field_dsp340050b49a6c_fld3098smod_slot2_Slot_smod_slot2_get (insn) == 74 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3062_Slot_smod_slot2_get (insn) == 0) + return OPCODE_CLRTIEP; + if (Field_dsp340050b49a6c_fld3099smod_slot2_Slot_smod_slot2_get (insn) == 75 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3062_Slot_smod_slot2_get (insn) == 0) + return OPCODE_WRTBSIGQM; + if (Field_dsp340050b49a6c_fld3100smod_slot2_Slot_smod_slot2_get (insn) == 19 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3825smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_SETTIEP; + if (Field_dsp340050b49a6c_fld3101smod_slot2_Slot_smod_slot2_get (insn) == 4 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3826smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ADDAR2; + if (Field_dsp340050b49a6c_fld3102smod_slot2_Slot_smod_slot2_get (insn) == 4 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3810smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_AR2CM_DUP; + if (Field_dsp340050b49a6c_fld3104smod_slot2_Slot_smod_slot2_get (insn) == 4 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3816smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVAR2; + if (Field_dsp340050b49a6c_fld3105smod_slot2_Slot_smod_slot2_get (insn) == 16 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_MOVCND_7; + if (Field_dsp340050b49a6c_fld3106smod_slot2_Slot_smod_slot2_get (insn) == 17 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_SMOD_LUT; + if (Field_dsp340050b49a6c_fld3107smod_slot2_Slot_smod_slot2_get (insn) == 18 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_SUB32; + if (Field_dsp340050b49a6c_fld3108smod_slot2_Slot_smod_slot2_get (insn) == 19 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_SUBWRP; + if (Field_dsp340050b49a6c_fld3109smod_slot2_Slot_smod_slot2_get (insn) == 20 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_SUBCM; + if (Field_dsp340050b49a6c_fld3110smod_slot2_Slot_smod_slot2_get (insn) == 21 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1) + return OPCODE_XOR128; + if (Field_dsp340050b49a6c_fld3111smod_slot2_Slot_smod_slot2_get (insn) == 19 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2056_Slot_smod_slot2_get (insn) == 0) + return OPCODE_MOVCM2PQ; + if (Field_dsp340050b49a6c_fld3113smod_slot2_Slot_smod_slot2_get (insn) == 27 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3827smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ARGMAX8; + if (Field_dsp340050b49a6c_fld3114smod_slot2_Slot_smod_slot2_get (insn) == 6 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3808_Slot_smod_slot2_get (insn) == 0) + return OPCODE_SUBMEAN; + if (Field_dsp340050b49a6c_fld3115smod_slot2_Slot_smod_slot2_get (insn) == 7 && + Field_op0_s15_Slot_smod_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2029_Slot_smod_slot2_get (insn) == 0) + return OPCODE_ASLM32; + switch (Field_dsp340050b49a6c_fld3116smod_slot2_Slot_smod_slot2_get (insn)) + { + case 0: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3813smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_AR2PQ_LN; + break; + case 1: + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3812smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_AR2CM_LN; + break; + } + if (Field_op0_s15_Slot_smod_slot2_get (insn) == 3 && + Field_dsp340050b49a6c_fld3818smod_slot2_Slot_smod_slot2_get (insn) == 0) + return OPCODE_LUT_WRITE; + return XTENSA_UNDEFINED; +} + +static int +Slot_smod_slot1_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2080_Slot_smod_slot1_get (insn)) + { + case 0: + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 0) + return OPCODE_CMPY2CM; + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 1) + return OPCODE_RMPY2CM; + break; + case 1: + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 0) + return OPCODE_MPY2CM; + break; + case 2: + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 0) + return OPCODE_MPYADD8_2CM; + break; + case 3: + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 0) + return OPCODE_RCMPY2CM; + break; + } + switch (Field_dsp340050b49a6c_fld3117smod_slot1_Slot_smod_slot1_get (insn)) + { + case 2: + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 1) + return OPCODE_CMAC; + break; + case 3: + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 1) + return OPCODE_MAC; + break; + case 4: + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 1) + return OPCODE_CMPY; + break; + case 5: + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 1) + return OPCODE_MPY; + break; + case 6: + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 1) + return OPCODE_NORMACD; + break; + case 7: + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 1) + return OPCODE_NORMD; + break; + } + switch (Field_dsp340050b49a6c_fld3118smod_slot1_Slot_smod_slot1_get (insn)) + { + case 0: + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 2 && + Field_dsp340050b49a6c_fld3117smod_slot1_Slot_smod_slot1_get (insn) == 0) + return OPCODE_SMOD_SCR; + break; + case 1: + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 2 && + Field_dsp340050b49a6c_fld3829smod_slot1_Slot_smod_slot1_get (insn) == 0) + return OPCODE_NOP; + break; + } + if (Field_op0_s16_Slot_smod_slot1_get (insn) == 3) + return OPCODE_SMOD_ALIGN; + return XTENSA_UNDEFINED; +} + +static int +Slot_llr_slot2_decode (const xtensa_insnbuf insn) +{ + switch (Field_dsp340050b49a6c_fld2046_Slot_llr_slot2_get (insn)) + { + case 0: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 2) + return OPCODE_LUT_AR; + break; + case 2: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3230_Slot_llr_slot2_get (insn) == 0) + return OPCODE_CM2AR_LN; + break; + } + switch (Field_dsp340050b49a6c_fld3191llr_slot2_Slot_llr_slot2_get (insn)) + { + case 6: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_ABS8; + break; + case 7: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_CONJ; + break; + case 22: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_LUT_PHASOR; + break; + case 23: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_NOT128; + break; + case 38: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_MOVCM; + break; + case 39: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_TRANS; + break; + case 70: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_NCO_UPDATE; + break; + } + if (Field_dsp340050b49a6c_fld3192llr_slot2_Slot_llr_slot2_get (insn) == 54 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_CLRCM; + if (Field_dsp340050b49a6c_fld3193llr_slot2_Slot_llr_slot2_get (insn) == 55 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_GET_ARGMAX; + if (Field_dsp340050b49a6c_fld3194llr_slot2_Slot_llr_slot2_get (insn) == 310 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_GET_HSAR; + if (Field_dsp340050b49a6c_fld3195llr_slot2_Slot_llr_slot2_get (insn) == 311 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_GET_SAR; + if (Field_dsp340050b49a6c_fld3196llr_slot2_Slot_llr_slot2_get (insn) == 566 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_GET_HSAR2SAR; + if (Field_dsp340050b49a6c_fld3197llr_slot2_Slot_llr_slot2_get (insn) == 567 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_POP128_0; + if (Field_dsp340050b49a6c_fld3198llr_slot2_Slot_llr_slot2_get (insn) == 822 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_POP128_1; + if (Field_dsp340050b49a6c_fld3199llr_slot2_Slot_llr_slot2_get (insn) == 823 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_POP128_2; + if (Field_dsp340050b49a6c_fld3200llr_slot2_Slot_llr_slot2_get (insn) == 1078 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_GET_MAX; + if (Field_dsp340050b49a6c_fld3201llr_slot2_Slot_llr_slot2_get (insn) == 1079 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_POP128_3; + if (Field_dsp340050b49a6c_fld3202llr_slot2_Slot_llr_slot2_get (insn) == 1334 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_POP128_4; + switch (Field_dsp340050b49a6c_fld3203llr_slot2_Slot_llr_slot2_get (insn)) + { + case 20535: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_MOVEQ128_0; + break; + case 20791: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_MOVEQ128_1; + break; + case 21047: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_MOVEQ128_2; + break; + case 21303: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_MOVEQ128_5; + break; + case 21559: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_MOVEQ128_3; + break; + case 21815: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_MOVEQ32_0; + break; + case 22071: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_MOVEQ32_1; + break; + case 22327: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_MOVEQ32_2; + break; + } + if (Field_dsp340050b49a6c_fld3204llr_slot2_Slot_llr_slot2_get (insn) == 11319 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3844_Slot_llr_slot2_get (insn) == 0) + return OPCODE_MOVEQ128_4; + if (Field_dsp340050b49a6c_fld3205_Slot_llr_slot2_get (insn) == 7 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3847llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_SET_EXT_REGS; + switch (Field_dsp340050b49a6c_fld3206_Slot_llr_slot2_get (insn)) + { + case 71: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3225_Slot_llr_slot2_get (insn) == 0) + return OPCODE_SET_ARGMAX; + break; + case 327: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3225_Slot_llr_slot2_get (insn) == 0) + return OPCODE_SET_NCO; + break; + } + if (Field_dsp340050b49a6c_fld3207llr_slot2_Slot_llr_slot2_get (insn) == 11575 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3844_Slot_llr_slot2_get (insn) == 0) + return OPCODE_MOVEQ32_3; + if (Field_dsp340050b49a6c_fld3208llr_slot2_Slot_llr_slot2_get (insn) == 5943 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3843llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld3210llr_slot2_Slot_llr_slot2_get (insn) == 411 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3857llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_POP128_5; + if (Field_dsp340050b49a6c_fld3212_Slot_llr_slot2_get (insn) == 43 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3848llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_SET_HSAR; + if (Field_dsp340050b49a6c_fld3213llr_slot2_Slot_llr_slot2_get (insn) == 155 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3845llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_GET_NCO; + if (Field_dsp340050b49a6c_fld3214_Slot_llr_slot2_get (insn) == 1 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3863llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_QREADY; + if (Field_dsp340050b49a6c_fld3215llr_slot2_Slot_llr_slot2_get (insn) == 327 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3850llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_SET_SAR; + if (Field_dsp340050b49a6c_fld3216llr_slot2_Slot_llr_slot2_get (insn) == 27 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3849llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_SET_MAX; + if (Field_dsp340050b49a6c_fld3217_Slot_llr_slot2_get (insn) == 5 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3859llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_POP32_0; + if (Field_dsp340050b49a6c_fld3218llr_slot2_Slot_llr_slot2_get (insn) == 11 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3851llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_NEGCM; + if (Field_dsp340050b49a6c_fld3220llr_slot2_Slot_llr_slot2_get (insn) == 9 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3246_Slot_llr_slot2_get (insn) == 0) + return OPCODE_PUSH128; + if (Field_dsp340050b49a6c_fld3221llr_slot2_Slot_llr_slot2_get (insn) == 25 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld2046_Slot_llr_slot2_get (insn) == 0) + return OPCODE_POP32_1; + if (Field_dsp340050b49a6c_fld3222llr_slot2_Slot_llr_slot2_get (insn) == 25 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3860llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_POP32_2; + if (Field_dsp340050b49a6c_fld3224llr_slot2_Slot_llr_slot2_get (insn) == 25 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3861llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_POP32_3; + if (Field_dsp340050b49a6c_fld3226llr_slot2_Slot_llr_slot2_get (insn) == 25 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3864llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_RDTIEP; + if (Field_dsp340050b49a6c_fld3228llr_slot2_Slot_llr_slot2_get (insn) == 3 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3866llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_ADD16; + if (Field_dsp340050b49a6c_fld3231llr_slot2_Slot_llr_slot2_get (insn) == 7 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 1 && + Field_dsp340050b49a6c_fld3856llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_LUT_WRITE; + if (Field_dsp340050b49a6c_fld3232llr_slot2_Slot_llr_slot2_get (insn) == 4 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 2) + return OPCODE_AR2CM_LN; + switch (Field_dsp340050b49a6c_fld3233_Slot_llr_slot2_get (insn)) + { + case 2: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 4 && + Field_dsp340050b49a6c_fld2049_Slot_llr_slot2_get (insn) == 0) + return OPCODE_SUBWRP; + break; + case 3: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 4 && + Field_dsp340050b49a6c_fld2029_Slot_llr_slot2_get (insn) == 0) + return OPCODE_ASLM32; + break; + } + if (Field_dsp340050b49a6c_fld3234llr_slot2_Slot_llr_slot2_get (insn) == 20 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 2) + return OPCODE_AR2CM_DUP; + if (Field_dsp340050b49a6c_fld3235llr_slot2_Slot_llr_slot2_get (insn) == 133 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 2) + return OPCODE_SETTIEP; + if (Field_dsp340050b49a6c_fld3236_Slot_llr_slot2_get (insn) == 27 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld2074_Slot_llr_slot2_get (insn) == 0) + return OPCODE_WRTIEP; + if (Field_dsp340050b49a6c_fld3237llr_slot2_Slot_llr_slot2_get (insn) == 149 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld2074_Slot_llr_slot2_get (insn) == 0) + return OPCODE_AR2SAR_DUP; + if (Field_dsp340050b49a6c_fld3238llr_slot2_Slot_llr_slot2_get (insn) == 85 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3862_Slot_llr_slot2_get (insn) == 0) + return OPCODE_WRTBSIGQ; + if (Field_dsp340050b49a6c_fld3240llr_slot2_Slot_llr_slot2_get (insn) == 53 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3847llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_WRTSIGQ; + if (Field_dsp340050b49a6c_fld3241llr_slot2_Slot_llr_slot2_get (insn) == 11 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3865llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_WRTBSIGQM; + if (Field_dsp340050b49a6c_fld3242llr_slot2_Slot_llr_slot2_get (insn) == 3 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3855llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_CLRTIEP; + switch (Field_dsp340050b49a6c_fld3243llr_slot2_Slot_llr_slot2_get (insn)) + { + case 48: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 2) + return OPCODE_ADDAR2; + break; + case 49: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 2) + return OPCODE_MOVAR2; + break; + case 50: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 2) + return OPCODE_PUSH128_PQ; + break; + case 51: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 2) + return OPCODE_SUBARX; + break; + case 52: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 2) + return OPCODE_PUSH32; + break; + case 53: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 2) + return OPCODE_SWAPB; + break; + } + if (Field_dsp340050b49a6c_fld3244llr_slot2_Slot_llr_slot2_get (insn) == 1 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 2 && + Field_dsp340050b49a6c_fld3853llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_PQ2CM; + if (Field_dsp340050b49a6c_fld3245llr_slot2_Slot_llr_slot2_get (insn) == 2 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 4 && + Field_dsp340050b49a6c_fld3868_Slot_llr_slot2_get (insn) == 0) + return OPCODE_SUBMEAN; + if (Field_dsp340050b49a6c_fld3247llr_slot2_Slot_llr_slot2_get (insn) == 3 && + Field_op0_s18_Slot_llr_slot2_get (insn) == 4 && + Field_dsp340050b49a6c_fld3867llr_slot2_Slot_llr_slot2_get (insn) == 0) + return OPCODE_ARGMAX8; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 5 && + Field_dsp340050b49a6c_fld2029_Slot_llr_slot2_get (insn) == 0) + return OPCODE_PERM; + switch (Field_s_Slot_llr_slot2_get (insn)) + { + case 0: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_ASLM; + break; + case 1: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_ASRM; + break; + case 2: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_CMP8; + break; + case 3: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_LSLM; + break; + case 4: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_CMP_I; + break; + case 5: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_LSRM; + break; + case 8: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 1) + return OPCODE_CMP_R; + break; + } + switch (Field_t_Slot_llr_slot2_get (insn)) + { + case 0: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND8_0; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_ADD32; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 4) + return OPCODE_OR128; + break; + case 1: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND8_1; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_ADDCM; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 4) + return OPCODE_SUB32; + break; + case 2: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND8_2; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_ADDWRP; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 4) + return OPCODE_SUBCM; + break; + case 3: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND8_5; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_ASL32; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 4) + return OPCODE_XOR128; + break; + case 4: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND8_3; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_AND128; + break; + case 5: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND8_6; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_ASR; + break; + case 6: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND8_7; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_ASR32; + break; + case 7: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND_0; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_EXTUI4; + break; + case 8: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND8_4; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_ASL; + break; + case 9: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND_1; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_LUT; + break; + case 10: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND_2; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_LUT_IEXT; + break; + case 11: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND_4; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_MAX8; + break; + case 12: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND_3; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_LUT_REXT; + break; + case 13: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND_5; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_MEAN; + break; + case 14: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND_6; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_MEAN32; + break; + case 15: + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 3) + return OPCODE_MOVCND_7; + if (Field_op0_s18_Slot_llr_slot2_get (insn) == 0) + return OPCODE_MIN8; + break; + } + return XTENSA_UNDEFINED; +} + +static int +Slot_llr_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_dsp340050b49a6c_fld3248llr_slot1_Slot_llr_slot1_get (insn) == 0 && + Field_op0_s19_Slot_llr_slot1_get (insn) == 0 && + Field_dsp340050b49a6c_fld3870_Slot_llr_slot1_get (insn) == 0) + return OPCODE_WGHT32; + if (Field_dsp340050b49a6c_fld3250llr_slot1_Slot_llr_slot1_get (insn) == 1 && + Field_op0_s19_Slot_llr_slot1_get (insn) == 0 && + Field_dsp340050b49a6c_fld3869llr_slot1_Slot_llr_slot1_get (insn) == 0) + return OPCODE_NOP; + if (Field_dsp340050b49a6c_fld3251llr_slot1_Slot_llr_slot1_get (insn) == 2 && + Field_op0_s19_Slot_llr_slot1_get (insn) == 0 && + Field_dsp340050b49a6c_fld3878llr_slot1_Slot_llr_slot1_get (insn) == 0) + return OPCODE_LLRPRE2; + if (Field_dsp340050b49a6c_fld3252llr_slot1_Slot_llr_slot1_get (insn) == 3 && + Field_op0_s19_Slot_llr_slot1_get (insn) == 0 && + Field_dsp340050b49a6c_fld3875llr_slot1_Slot_llr_slot1_get (insn) == 0) + return OPCODE_MOVAC_R; + if (Field_dsp340050b49a6c_fld3253llr_slot1_Slot_llr_slot1_get (insn) == 1 && + Field_op0_s19_Slot_llr_slot1_get (insn) == 0 && + Field_dsp340050b49a6c_fld3876llr_slot1_Slot_llr_slot1_get (insn) == 0) + return OPCODE_ADDAC; + if (Field_dsp340050b49a6c_fld3254llr_slot1_Slot_llr_slot1_get (insn) == 1 && + Field_op0_s19_Slot_llr_slot1_get (insn) == 0 && + Field_dsp340050b49a6c_fld3872llr_slot1_Slot_llr_slot1_get (insn) == 0) + return OPCODE_MOVAC_I; + if (Field_op0_s19_Slot_llr_slot1_get (insn) == 1) + return OPCODE_COMB32; + return XTENSA_UNDEFINED; +} + +static int +Slot_dual_slot1_decode (const xtensa_insnbuf insn) +{ + if (Field_op0_s22_Slot_dual_slot1_get (insn) == 0) + return OPCODE_NOP; + return XTENSA_UNDEFINED; +} + + +/* Instruction slots. */ + +static void +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = (insn[0] & 0xffffff); +} + +static void +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); +} + +static void +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = (insn[0] & 0xffff); +} + +static void +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); +} + +static void +Slot_gp_Format_gp_slot2_43_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[1] & 0x3ffff800) >> 11); +} + +static void +Slot_gp_Format_gp_slot2_43_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3ffff800) | ((slotbuf[0] & 0x7ffff) << 11); +} + +static void +Slot_gp_Format_gp_slot1_26_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0xfc000000) >> 26); + slotbuf[0] = (slotbuf[0] & ~0x1ffc0) | ((insn[1] & 0x7ff) << 6); +} + +static void +Slot_gp_Format_gp_slot1_26_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfc000000) | ((slotbuf[0] & 0x3f) << 26); + insn[1] = (insn[1] & ~0x7ff) | ((slotbuf[0] & 0x1ffc0) >> 6); +} + +static void +Slot_gp_Format_gp_slot0_7_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0x3ffff80) >> 7); +} + +static void +Slot_gp_Format_gp_slot0_7_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3ffff80) | ((slotbuf[0] & 0x7ffff) << 7); +} + +static void +Slot_dot_Format_dot_slot2_44_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[1] & 0xfffff000) >> 12); +} + +static void +Slot_dot_Format_dot_slot2_44_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0xfffff000) | ((slotbuf[0] & 0xfffff) << 12); +} + +static void +Slot_dot_Format_dot_slot1_24_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0xff000000) >> 24); + slotbuf[0] = (slotbuf[0] & ~0xfff00) | ((insn[1] & 0xfff) << 8); +} + +static void +Slot_dot_Format_dot_slot1_24_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff000000) | ((slotbuf[0] & 0xff) << 24); + insn[1] = (insn[1] & ~0xfff) | ((slotbuf[0] & 0xfff00) >> 8); +} + +static void +Slot_dot_Format_dot_slot0_7_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0xffff80) >> 7); +} + +static void +Slot_dot_Format_dot_slot0_7_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff80) | ((slotbuf[0] & 0x1ffff) << 7); +} + +static void +Slot_pq_Format_pq_slot2_40_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[1] & 0x7ffff00) >> 8); +} + +static void +Slot_pq_Format_pq_slot2_40_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x7ffff00) | ((slotbuf[0] & 0x7ffff) << 8); +} + +static void +Slot_pq_Format_pq_slot1_26_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0xfc000000) >> 26); + slotbuf[0] = (slotbuf[0] & ~0x3fc0) | ((insn[1] & 0xff) << 6); +} + +static void +Slot_pq_Format_pq_slot1_26_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfc000000) | ((slotbuf[0] & 0x3f) << 26); + insn[1] = (insn[1] & ~0xff) | ((slotbuf[0] & 0x3fc0) >> 6); +} + +static void +Slot_pq_Format_pq_slot0_7_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0x3ffff80) >> 7); +} + +static void +Slot_pq_Format_pq_slot0_7_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3ffff80) | ((slotbuf[0] & 0x7ffff) << 7); +} + +static void +Slot_acc2_Format_acc2_slot2_47_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[1] & 0x3fff8000) >> 15); +} + +static void +Slot_acc2_Format_acc2_slot2_47_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3fff8000) | ((slotbuf[0] & 0x7fff) << 15); +} + +static void +Slot_acc2_Format_acc2_slot1_23_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0xff800000) >> 23); + slotbuf[0] = (slotbuf[0] & ~0xfffe00) | ((insn[1] & 0x7fff) << 9); +} + +static void +Slot_acc2_Format_acc2_slot1_23_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff800000) | ((slotbuf[0] & 0x1ff) << 23); + insn[1] = (insn[1] & ~0x7fff) | ((slotbuf[0] & 0xfffe00) >> 9); +} + +static void +Slot_acc2_Format_acc2_slot0_7_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0x7fff80) >> 7); +} + +static void +Slot_acc2_Format_acc2_slot0_7_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x7fff80) | ((slotbuf[0] & 0xffff) << 7); +} + +static void +Slot_smod_Format_smod_slot2_42_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[1] & 0x3ffffc00) >> 10); +} + +static void +Slot_smod_Format_smod_slot2_42_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x3ffffc00) | ((slotbuf[0] & 0xfffff) << 10); +} + +static void +Slot_smod_Format_smod_slot1_26_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0xfc000000) >> 26); + slotbuf[0] = (slotbuf[0] & ~0xffc0) | ((insn[1] & 0x3ff) << 6); +} + +static void +Slot_smod_Format_smod_slot1_26_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xfc000000) | ((slotbuf[0] & 0x3f) << 26); + insn[1] = (insn[1] & ~0x3ff) | ((slotbuf[0] & 0xffc0) >> 6); +} + +static void +Slot_smod_Format_smod_slot0_7_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0x3ffff80) >> 7); +} + +static void +Slot_smod_Format_smod_slot0_7_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3ffff80) | ((slotbuf[0] & 0x7ffff) << 7); +} + +static void +Slot_llr_Format_llr_slot2_44_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[1] & 0x7ffff000) >> 12); +} + +static void +Slot_llr_Format_llr_slot2_44_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[1] = (insn[1] & ~0x7ffff000) | ((slotbuf[0] & 0x7ffff) << 12); +} + +static void +Slot_llr_Format_llr_slot1_24_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0xff000000) >> 24); + slotbuf[0] = (slotbuf[0] & ~0xfff00) | ((insn[1] & 0xfff) << 8); +} + +static void +Slot_llr_Format_llr_slot1_24_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xff000000) | ((slotbuf[0] & 0xff) << 24); + insn[1] = (insn[1] & ~0xfff) | ((slotbuf[0] & 0xfff00) >> 8); +} + +static void +Slot_llr_Format_llr_slot0_7_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0xffff80) >> 7); +} + +static void +Slot_llr_Format_llr_slot0_7_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0xffff80) | ((slotbuf[0] & 0x1ffff) << 7); +} + +static void +Slot_dual_Format_dual_slot2_31_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0x80000000) >> 31); + slotbuf[0] = (slotbuf[0] & ~0xfffffe) | ((insn[1] & 0x7fffff) << 1); +} + +static void +Slot_dual_Format_dual_slot2_31_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x80000000) | ((slotbuf[0] & 0x1) << 31); + insn[1] = (insn[1] & ~0x7fffff) | ((slotbuf[0] & 0xfffffe) >> 1); +} + +static void +Slot_dual_Format_dual_slot1_30_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0x40000000) >> 30); +} + +static void +Slot_dual_Format_dual_slot1_30_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x40000000) | ((slotbuf[0] & 0x1) << 30); +} + +static void +Slot_dual_Format_dual_slot0_7_get (const xtensa_insnbuf insn, + xtensa_insnbuf slotbuf) +{ + slotbuf[1] = 0; + slotbuf[0] = ((insn[0] & 0x3fffff80) >> 7); +} + +static void +Slot_dual_Format_dual_slot0_7_set (xtensa_insnbuf insn, + const xtensa_insnbuf slotbuf) +{ + insn[0] = (insn[0] & ~0x3fffff80) | ((slotbuf[0] & 0x7fffff) << 7); +} + +static xtensa_get_field_fn +Slot_inst_get_field_fns[] = { + Field_t_Slot_inst_get, + Field_bbi4_Slot_inst_get, + Field_bbi_Slot_inst_get, + Field_imm12_Slot_inst_get, + Field_imm8_Slot_inst_get, + Field_s_Slot_inst_get, + Field_imm12b_Slot_inst_get, + Field_imm16_Slot_inst_get, + Field_m_Slot_inst_get, + Field_n_Slot_inst_get, + Field_offset_Slot_inst_get, + Field_op0_Slot_inst_get, + Field_op1_Slot_inst_get, + Field_op2_Slot_inst_get, + Field_r_Slot_inst_get, + Field_sa4_Slot_inst_get, + Field_sae4_Slot_inst_get, + Field_sae_Slot_inst_get, + Field_sal_Slot_inst_get, + Field_sargt_Slot_inst_get, + Field_sas4_Slot_inst_get, + Field_sas_Slot_inst_get, + Field_sr_Slot_inst_get, + Field_st_Slot_inst_get, + Field_thi3_Slot_inst_get, + Field_imm4_Slot_inst_get, + Field_mn_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_get, + Field_s2_Slot_inst_get, + Field_r2_Slot_inst_get, + Field_t4_Slot_inst_get, + Field_s4_Slot_inst_get, + Field_r4_Slot_inst_get, + Field_t8_Slot_inst_get, + Field_s8_Slot_inst_get, + Field_r8_Slot_inst_get, + Field_xt_wbr15_imm_Slot_inst_get, + Field_xt_wbr18_imm_Slot_inst_get, + Field_fimm8_Slot_inst_get, + Field_dsp340050b49a6c_fld2019_Slot_inst_get, + Field_dsp340050b49a6c_fld2021_Slot_inst_get, + Field_dsp340050b49a6c_fld2029_Slot_inst_get, + Field_dsp340050b49a6c_fld2030_Slot_inst_get, + Field_dsp340050b49a6c_fld2032_Slot_inst_get, + Field_dsp340050b49a6c_fld2035_Slot_inst_get, + Field_dsp340050b49a6c_fld2036_Slot_inst_get, + Field_dsp340050b49a6c_fld2037_Slot_inst_get, + Field_dsp340050b49a6c_fld2038_Slot_inst_get, + Field_dsp340050b49a6c_fld2039_Slot_inst_get, + Field_dsp340050b49a6c_fld2040_Slot_inst_get, + Field_dsp340050b49a6c_fld2041_Slot_inst_get, + Field_dsp340050b49a6c_fld2042_Slot_inst_get, + Field_dsp340050b49a6c_fld2043_Slot_inst_get, + Field_dsp340050b49a6c_fld2044_Slot_inst_get, + Field_dsp340050b49a6c_fld2045_Slot_inst_get, + Field_dsp340050b49a6c_fld2046_Slot_inst_get, + Field_dsp340050b49a6c_fld2047_Slot_inst_get, + Field_dsp340050b49a6c_fld2048_Slot_inst_get, + Field_dsp340050b49a6c_fld2049_Slot_inst_get, + Field_dsp340050b49a6c_fld2050_Slot_inst_get, + Field_dsp340050b49a6c_fld2051_Slot_inst_get, + Field_dsp340050b49a6c_fld2052_Slot_inst_get, + Field_dsp340050b49a6c_fld2053_Slot_inst_get, + Field_dsp340050b49a6c_fld2054_Slot_inst_get, + Field_dsp340050b49a6c_fld2055_Slot_inst_get, + Field_dsp340050b49a6c_fld2056_Slot_inst_get, + Field_dsp340050b49a6c_fld2082inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2083inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2084inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2085inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2086inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2088inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2089inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2090inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2091inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2092inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2094inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2095inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2096inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2098inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2099inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2100inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2101inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2102inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2103inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2104inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2105inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2106inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2107inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2108inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2109inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2110inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2111inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2112inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2113inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2114inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2115inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2116inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2117inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2118inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2119inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2120inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2122inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2123inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2124inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2125inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2126inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2127inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2128inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2129inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2131inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2132inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2133inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2134inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2136inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2137inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2138inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2139inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2140inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2141inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2142inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2143inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2144inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2145inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2146inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2147inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2149inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2151inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2153inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2154inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2155inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2156inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2157inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2158inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2159inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2160inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2161inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2162inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2163inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2164inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2165inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2166inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2167inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2168inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2169inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2171inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2172inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2173inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2174inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2175inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2177inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2178inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2179inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2180inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2181inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2182inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2183inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2184inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2185inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2186inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2187inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2188inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2189inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2190inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2191inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2192inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2193inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2194inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2195inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2196inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2197inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2198inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2199inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2200inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2201inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2202inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2203inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2204inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2205inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2206inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2207inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2208inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2209inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2210inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2211inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2212inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2213inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2214inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2215inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2216inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2217inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2218inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2219inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2220inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2221inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2222inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2223inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2224inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2225inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2226inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2227inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2228inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2229inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2230inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2231inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2232inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2234inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2235inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2236inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2237inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2238inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2239inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2240inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2241inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2242inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2243inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2244inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2245inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2246inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2247inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2248inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2249inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2250inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2251inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2252inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2253inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2254_Slot_inst_get, + Field_dsp340050b49a6c_fld2255inst_Slot_inst_get, + Field_dsp340050b49a6c_fld2257inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3627inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3630inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3631inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3633inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3634_Slot_inst_get, + Field_dsp340050b49a6c_fld3635inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3636inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3637inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3638inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3639inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3640inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3642inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3643inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3644inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3645inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3647inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3648inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3649inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3650inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3651inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3653inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3654inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3655inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3656inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3657inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3658inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3659inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3660inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3661inst_Slot_inst_get, + Field_dsp340050b49a6c_fld3662inst_Slot_inst_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst_set_field_fns[] = { + Field_t_Slot_inst_set, + Field_bbi4_Slot_inst_set, + Field_bbi_Slot_inst_set, + Field_imm12_Slot_inst_set, + Field_imm8_Slot_inst_set, + Field_s_Slot_inst_set, + Field_imm12b_Slot_inst_set, + Field_imm16_Slot_inst_set, + Field_m_Slot_inst_set, + Field_n_Slot_inst_set, + Field_offset_Slot_inst_set, + Field_op0_Slot_inst_set, + Field_op1_Slot_inst_set, + Field_op2_Slot_inst_set, + Field_r_Slot_inst_set, + Field_sa4_Slot_inst_set, + Field_sae4_Slot_inst_set, + Field_sae_Slot_inst_set, + Field_sal_Slot_inst_set, + Field_sargt_Slot_inst_set, + Field_sas4_Slot_inst_set, + Field_sas_Slot_inst_set, + Field_sr_Slot_inst_set, + Field_st_Slot_inst_set, + Field_thi3_Slot_inst_set, + Field_imm4_Slot_inst_set, + Field_mn_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_t2_Slot_inst_set, + Field_s2_Slot_inst_set, + Field_r2_Slot_inst_set, + Field_t4_Slot_inst_set, + Field_s4_Slot_inst_set, + Field_r4_Slot_inst_set, + Field_t8_Slot_inst_set, + Field_s8_Slot_inst_set, + Field_r8_Slot_inst_set, + Field_xt_wbr15_imm_Slot_inst_set, + Field_xt_wbr18_imm_Slot_inst_set, + Field_fimm8_Slot_inst_set, + Field_dsp340050b49a6c_fld2019_Slot_inst_set, + Field_dsp340050b49a6c_fld2021_Slot_inst_set, + Field_dsp340050b49a6c_fld2029_Slot_inst_set, + Field_dsp340050b49a6c_fld2030_Slot_inst_set, + Field_dsp340050b49a6c_fld2032_Slot_inst_set, + Field_dsp340050b49a6c_fld2035_Slot_inst_set, + Field_dsp340050b49a6c_fld2036_Slot_inst_set, + Field_dsp340050b49a6c_fld2037_Slot_inst_set, + Field_dsp340050b49a6c_fld2038_Slot_inst_set, + Field_dsp340050b49a6c_fld2039_Slot_inst_set, + Field_dsp340050b49a6c_fld2040_Slot_inst_set, + Field_dsp340050b49a6c_fld2041_Slot_inst_set, + Field_dsp340050b49a6c_fld2042_Slot_inst_set, + Field_dsp340050b49a6c_fld2043_Slot_inst_set, + Field_dsp340050b49a6c_fld2044_Slot_inst_set, + Field_dsp340050b49a6c_fld2045_Slot_inst_set, + Field_dsp340050b49a6c_fld2046_Slot_inst_set, + Field_dsp340050b49a6c_fld2047_Slot_inst_set, + Field_dsp340050b49a6c_fld2048_Slot_inst_set, + Field_dsp340050b49a6c_fld2049_Slot_inst_set, + Field_dsp340050b49a6c_fld2050_Slot_inst_set, + Field_dsp340050b49a6c_fld2051_Slot_inst_set, + Field_dsp340050b49a6c_fld2052_Slot_inst_set, + Field_dsp340050b49a6c_fld2053_Slot_inst_set, + Field_dsp340050b49a6c_fld2054_Slot_inst_set, + Field_dsp340050b49a6c_fld2055_Slot_inst_set, + Field_dsp340050b49a6c_fld2056_Slot_inst_set, + Field_dsp340050b49a6c_fld2082inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2083inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2084inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2085inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2086inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2088inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2089inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2090inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2091inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2092inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2094inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2095inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2096inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2098inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2099inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2100inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2101inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2102inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2103inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2104inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2105inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2106inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2107inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2108inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2109inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2110inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2111inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2112inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2113inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2114inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2115inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2116inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2117inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2118inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2119inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2120inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2122inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2123inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2124inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2125inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2126inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2127inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2128inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2129inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2131inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2132inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2133inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2134inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2136inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2137inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2138inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2139inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2140inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2141inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2142inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2143inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2144inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2145inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2146inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2147inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2149inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2151inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2153inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2154inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2155inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2156inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2157inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2158inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2159inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2160inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2161inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2162inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2163inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2164inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2165inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2166inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2167inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2168inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2169inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2171inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2172inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2173inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2174inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2175inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2177inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2178inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2179inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2180inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2181inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2182inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2183inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2184inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2185inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2186inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2187inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2188inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2189inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2190inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2191inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2192inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2193inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2194inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2195inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2196inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2197inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2198inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2199inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2200inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2201inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2202inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2203inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2204inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2205inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2206inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2207inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2208inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2209inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2210inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2211inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2212inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2213inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2214inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2215inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2216inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2217inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2218inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2219inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2220inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2221inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2222inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2223inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2224inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2225inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2226inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2227inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2228inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2229inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2230inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2231inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2232inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2234inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2235inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2236inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2237inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2238inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2239inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2240inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2241inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2242inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2243inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2244inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2245inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2246inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2247inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2248inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2249inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2250inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2251inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2252inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2253inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2254_Slot_inst_set, + Field_dsp340050b49a6c_fld2255inst_Slot_inst_set, + Field_dsp340050b49a6c_fld2257inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3627inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3630inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3631inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3633inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3634_Slot_inst_set, + Field_dsp340050b49a6c_fld3635inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3636inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3637inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3638inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3639inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3640inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3642inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3643inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3644inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3645inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3647inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3648inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3649inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3650inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3651inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3653inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3654inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3655inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3656inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3657inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3658inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3659inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3660inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3661inst_Slot_inst_set, + Field_dsp340050b49a6c_fld3662inst_Slot_inst_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16a_get_field_fns[] = { + Field_t_Slot_inst16a_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_get, + 0, + 0, + Field_r_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_get, + Field_st_Slot_inst16a_get, + 0, + Field_imm4_Slot_inst16a_get, + 0, + Field_i_Slot_inst16a_get, + Field_imm6lo_Slot_inst16a_get, + Field_imm6hi_Slot_inst16a_get, + Field_imm7lo_Slot_inst16a_get, + Field_imm7hi_Slot_inst16a_get, + Field_z_Slot_inst16a_get, + Field_imm6_Slot_inst16a_get, + Field_imm7_Slot_inst16a_get, + Field_t2_Slot_inst16a_get, + Field_s2_Slot_inst16a_get, + Field_r2_Slot_inst16a_get, + Field_t4_Slot_inst16a_get, + Field_s4_Slot_inst16a_get, + Field_r4_Slot_inst16a_get, + Field_t8_Slot_inst16a_get, + Field_s8_Slot_inst16a_get, + Field_r8_Slot_inst16a_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16a_set_field_fns[] = { + Field_t_Slot_inst16a_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16a_set, + 0, + 0, + Field_r_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16a_set, + Field_st_Slot_inst16a_set, + 0, + Field_imm4_Slot_inst16a_set, + 0, + Field_i_Slot_inst16a_set, + Field_imm6lo_Slot_inst16a_set, + Field_imm6hi_Slot_inst16a_set, + Field_imm7lo_Slot_inst16a_set, + Field_imm7hi_Slot_inst16a_set, + Field_z_Slot_inst16a_set, + Field_imm6_Slot_inst16a_set, + Field_imm7_Slot_inst16a_set, + Field_t2_Slot_inst16a_set, + Field_s2_Slot_inst16a_set, + Field_r2_Slot_inst16a_set, + Field_t4_Slot_inst16a_set, + Field_s4_Slot_inst16a_set, + Field_r4_Slot_inst16a_set, + Field_t8_Slot_inst16a_set, + Field_s8_Slot_inst16a_set, + Field_r8_Slot_inst16a_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_inst16b_get_field_fns[] = { + Field_t_Slot_inst16b_get, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_get, + 0, + 0, + Field_r_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_get, + Field_st_Slot_inst16b_get, + 0, + Field_imm4_Slot_inst16b_get, + 0, + Field_i_Slot_inst16b_get, + Field_imm6lo_Slot_inst16b_get, + Field_imm6hi_Slot_inst16b_get, + Field_imm7lo_Slot_inst16b_get, + Field_imm7hi_Slot_inst16b_get, + Field_z_Slot_inst16b_get, + Field_imm6_Slot_inst16b_get, + Field_imm7_Slot_inst16b_get, + Field_t2_Slot_inst16b_get, + Field_s2_Slot_inst16b_get, + Field_r2_Slot_inst16b_get, + Field_t4_Slot_inst16b_get, + Field_s4_Slot_inst16b_get, + Field_r4_Slot_inst16b_get, + Field_t8_Slot_inst16b_get, + Field_s8_Slot_inst16b_get, + Field_r8_Slot_inst16b_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_inst16b_set_field_fns[] = { + Field_t_Slot_inst16b_set, + 0, + 0, + 0, + 0, + Field_s_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + Field_op0_Slot_inst16b_set, + 0, + 0, + Field_r_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_sr_Slot_inst16b_set, + Field_st_Slot_inst16b_set, + 0, + Field_imm4_Slot_inst16b_set, + 0, + Field_i_Slot_inst16b_set, + Field_imm6lo_Slot_inst16b_set, + Field_imm6hi_Slot_inst16b_set, + Field_imm7lo_Slot_inst16b_set, + Field_imm7hi_Slot_inst16b_set, + Field_z_Slot_inst16b_set, + Field_imm6_Slot_inst16b_set, + Field_imm7_Slot_inst16b_set, + Field_t2_Slot_inst16b_set, + Field_s2_Slot_inst16b_set, + Field_r2_Slot_inst16b_set, + Field_t4_Slot_inst16b_set, + Field_s4_Slot_inst16b_set, + Field_r4_Slot_inst16b_set, + Field_t8_Slot_inst16b_set, + Field_s8_Slot_inst16b_set, + Field_r8_Slot_inst16b_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_gp_slot2_get_field_fns[] = { + Field_t_Slot_gp_slot2_get, + 0, + 0, + 0, + 0, + Field_s_Slot_gp_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_gp_slot2_get, + Field_r_Slot_gp_slot2_get, + 0, + 0, + Field_sae_Slot_gp_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_gp_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2030_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2032_Slot_gp_slot2_get, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2039_Slot_gp_slot2_get, + 0, + Field_dsp340050b49a6c_fld2041_Slot_gp_slot2_get, + 0, + 0, + Field_dsp340050b49a6c_fld2044_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2045_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2046_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2047_Slot_gp_slot2_get, + 0, + Field_dsp340050b49a6c_fld2049_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2050_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2051_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2052_Slot_gp_slot2_get, + 0, + 0, + Field_dsp340050b49a6c_fld2055_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2056_Slot_gp_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s3_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2025_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2027_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2258gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2259gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2260gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2261gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2262gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2263gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2264gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2266gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2267gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2268gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2269gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2270gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2271gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2272_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2273gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2274gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2275gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2277gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2278gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2279gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2280gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2281gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2282gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2283gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2284gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2286gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2287gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2288gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2289gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2290gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2291gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2292gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2293gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2294gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2295gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2296gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2297gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2298gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2299gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2300gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2301gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2302_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2303gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2304gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2305_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2306gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2308gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2309gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2310gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2312gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2313_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2314gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2316gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2317gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2318gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2319gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2320gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2321gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2322gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2323gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2324gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2325gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2326gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2327gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2328gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2329gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2330gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2331gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2332gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2333gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2334gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2335gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2336gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2337gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2338gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2339gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2340gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2341gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2342gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2343gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2344gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2345gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2346gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2347gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2348gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2349gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2350gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2351gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2352gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2353gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2354gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2355gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2356gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2357gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2358gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2359gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2361gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2362gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2364gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2366gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2368gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2369gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2370gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2371gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2372gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2373gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2374gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2375gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2376gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2378gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2379gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2381gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2383gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2384_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2385gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2386_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2387gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2388gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld2389gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3663gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3664gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3665gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3666_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3667gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3668gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3669gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3670gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3671gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3673gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3674gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3675gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3676gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3678gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3679gp_slot2_Slot_gp_slot2_get, + Field_dsp340050b49a6c_fld3680gp_slot2_Slot_gp_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_gp_slot2_set_field_fns[] = { + Field_t_Slot_gp_slot2_set, + 0, + 0, + 0, + 0, + Field_s_Slot_gp_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_gp_slot2_set, + Field_r_Slot_gp_slot2_set, + 0, + 0, + Field_sae_Slot_gp_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_gp_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2030_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2032_Slot_gp_slot2_set, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2039_Slot_gp_slot2_set, + 0, + Field_dsp340050b49a6c_fld2041_Slot_gp_slot2_set, + 0, + 0, + Field_dsp340050b49a6c_fld2044_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2045_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2046_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2047_Slot_gp_slot2_set, + 0, + Field_dsp340050b49a6c_fld2049_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2050_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2051_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2052_Slot_gp_slot2_set, + 0, + 0, + Field_dsp340050b49a6c_fld2055_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2056_Slot_gp_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s3_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2025_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2027_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2258gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2259gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2260gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2261gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2262gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2263gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2264gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2266gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2267gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2268gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2269gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2270gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2271gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2272_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2273gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2274gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2275gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2277gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2278gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2279gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2280gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2281gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2282gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2283gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2284gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2286gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2287gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2288gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2289gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2290gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2291gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2292gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2293gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2294gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2295gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2296gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2297gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2298gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2299gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2300gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2301gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2302_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2303gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2304gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2305_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2306gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2308gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2309gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2310gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2312gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2313_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2314gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2316gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2317gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2318gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2319gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2320gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2321gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2322gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2323gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2324gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2325gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2326gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2327gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2328gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2329gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2330gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2331gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2332gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2333gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2334gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2335gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2336gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2337gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2338gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2339gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2340gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2341gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2342gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2343gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2344gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2345gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2346gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2347gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2348gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2349gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2350gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2351gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2352gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2353gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2354gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2355gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2356gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2357gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2358gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2359gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2361gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2362gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2364gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2366gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2368gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2369gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2370gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2371gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2372gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2373gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2374gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2375gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2376gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2378gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2379gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2381gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2383gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2384_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2385gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2386_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2387gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2388gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld2389gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3663gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3664gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3665gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3666_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3667gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3668gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3669gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3670gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3671gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3673gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3674gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3675gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3676gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3678gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3679gp_slot2_Slot_gp_slot2_set, + Field_dsp340050b49a6c_fld3680gp_slot2_Slot_gp_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_gp_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + Field_s_Slot_gp_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2046_Slot_gp_slot1_get, + 0, + Field_dsp340050b49a6c_fld2048_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld2049_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld2050_Slot_gp_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s4_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld2026_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld2031_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld2394gp_slot1_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld2395gp_slot1_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld2397gp_slot1_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld2398gp_slot1_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld2399gp_slot1_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld2400gp_slot1_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld2402gp_slot1_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld2403gp_slot1_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld2405gp_slot1_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld3681gp_slot1_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld3683gp_slot1_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld3684gp_slot1_Slot_gp_slot1_get, + Field_dsp340050b49a6c_fld3686gp_slot1_Slot_gp_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_gp_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + Field_s_Slot_gp_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2046_Slot_gp_slot1_set, + 0, + Field_dsp340050b49a6c_fld2048_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld2049_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld2050_Slot_gp_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s4_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld2026_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld2031_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld2394gp_slot1_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld2395gp_slot1_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld2397gp_slot1_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld2398gp_slot1_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld2399gp_slot1_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld2400gp_slot1_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld2402gp_slot1_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld2403gp_slot1_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld2405gp_slot1_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld3681gp_slot1_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld3683gp_slot1_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld3684gp_slot1_Slot_gp_slot1_set, + Field_dsp340050b49a6c_fld3686gp_slot1_Slot_gp_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_gp_slot0_get_field_fns[] = { + Field_t_Slot_gp_slot0_get, + 0, + 0, + 0, + 0, + Field_s_Slot_gp_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_gp_slot0_get, + Field_r_Slot_gp_slot0_get, + 0, + 0, + Field_sae_Slot_gp_slot0_get, + Field_sal_Slot_gp_slot0_get, + Field_sargt_Slot_gp_slot0_get, + 0, + Field_sas_Slot_gp_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm6_Slot_gp_slot0_get, + Field_imm7_Slot_gp_slot0_get, + 0, + 0, + 0, + 0, + Field_s4_Slot_gp_slot0_get, + 0, + 0, + Field_s8_Slot_gp_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2030_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2032_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2035_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2036_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2037_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2038_Slot_gp_slot0_get, + 0, + Field_dsp340050b49a6c_fld2040_Slot_gp_slot0_get, + 0, + Field_dsp340050b49a6c_fld2042_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2043_Slot_gp_slot0_get, + 0, + Field_dsp340050b49a6c_fld2045_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2046_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2047_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2048_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2049_Slot_gp_slot0_get, + 0, + Field_dsp340050b49a6c_fld2051_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2052_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2053_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2054_Slot_gp_slot0_get, + 0, + Field_dsp340050b49a6c_fld2056_Slot_gp_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s5_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2058_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2067_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2407gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2409gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2410gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2411gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2412gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2413gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2415gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2416gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2417gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2418gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2419gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2420gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2422gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2423gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2424gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2425gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2426gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2427gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2429gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2430gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2431gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2432gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2433gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2434gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2435gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2436gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2437gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2438gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2439gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2440gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2441gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2443gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2444gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2445_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2447gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2448_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2449gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2451gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2452gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2453gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2454gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2455gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2456gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2457gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2458gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2459gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2460gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2461gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2462_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2463gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2464gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2465gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2466gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2467gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2468gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2470gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2471gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2472gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2473gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2474gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2475gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2477gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2479gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2480gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2481gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2482gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2483gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2484gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2485gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2486gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2487gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2488gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2489gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2490gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2491gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2492gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2493gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2494gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2495gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2496gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2497gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2498gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2499gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2500gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2501gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2502gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2503gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2504gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2505gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2506gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2507gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2508gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2509gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2510gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2512gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2514gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2515gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2516gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2517gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2518gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2519gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2520gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2521gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2523gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2524gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2526gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2527gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2528gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2529gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2530_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld2531gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3688gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3689gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3690gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3691gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3692gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3693gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3695gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3696gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3697gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3698gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3699gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3700gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3702gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3703gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3705gp_slot0_Slot_gp_slot0_get, + Field_dsp340050b49a6c_fld3706gp_slot0_Slot_gp_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_gp_slot0_set_field_fns[] = { + Field_t_Slot_gp_slot0_set, + 0, + 0, + 0, + 0, + Field_s_Slot_gp_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_gp_slot0_set, + Field_r_Slot_gp_slot0_set, + 0, + 0, + Field_sae_Slot_gp_slot0_set, + Field_sal_Slot_gp_slot0_set, + Field_sargt_Slot_gp_slot0_set, + 0, + Field_sas_Slot_gp_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm6_Slot_gp_slot0_set, + Field_imm7_Slot_gp_slot0_set, + 0, + 0, + 0, + 0, + Field_s4_Slot_gp_slot0_set, + 0, + 0, + Field_s8_Slot_gp_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2030_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2032_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2035_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2036_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2037_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2038_Slot_gp_slot0_set, + 0, + Field_dsp340050b49a6c_fld2040_Slot_gp_slot0_set, + 0, + Field_dsp340050b49a6c_fld2042_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2043_Slot_gp_slot0_set, + 0, + Field_dsp340050b49a6c_fld2045_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2046_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2047_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2048_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2049_Slot_gp_slot0_set, + 0, + Field_dsp340050b49a6c_fld2051_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2052_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2053_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2054_Slot_gp_slot0_set, + 0, + Field_dsp340050b49a6c_fld2056_Slot_gp_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s5_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2058_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2067_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2407gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2409gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2410gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2411gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2412gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2413gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2415gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2416gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2417gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2418gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2419gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2420gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2422gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2423gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2424gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2425gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2426gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2427gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2429gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2430gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2431gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2432gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2433gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2434gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2435gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2436gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2437gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2438gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2439gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2440gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2441gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2443gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2444gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2445_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2447gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2448_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2449gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2451gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2452gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2453gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2454gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2455gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2456gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2457gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2458gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2459gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2460gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2461gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2462_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2463gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2464gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2465gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2466gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2467gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2468gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2470gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2471gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2472gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2473gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2474gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2475gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2477gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2479gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2480gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2481gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2482gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2483gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2484gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2485gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2486gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2487gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2488gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2489gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2490gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2491gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2492gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2493gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2494gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2495gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2496gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2497gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2498gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2499gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2500gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2501gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2502gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2503gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2504gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2505gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2506gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2507gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2508gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2509gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2510gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2512gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2514gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2515gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2516gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2517gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2518gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2519gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2520gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2521gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2523gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2524gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2526gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2527gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2528gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2529gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2530_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld2531gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3688gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3689gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3690gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3691gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3692gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3693gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3695gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3696gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3697gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3698gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3699gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3700gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3702gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3703gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3705gp_slot0_Slot_gp_slot0_set, + Field_dsp340050b49a6c_fld3706gp_slot0_Slot_gp_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_dot_slot2_get_field_fns[] = { + Field_t_Slot_dot_slot2_get, + 0, + 0, + 0, + 0, + Field_s_Slot_dot_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_dot_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2030_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2032_Slot_dot_slot2_get, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2039_Slot_dot_slot2_get, + 0, + Field_dsp340050b49a6c_fld2041_Slot_dot_slot2_get, + 0, + 0, + Field_dsp340050b49a6c_fld2044_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2045_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2046_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2047_Slot_dot_slot2_get, + 0, + Field_dsp340050b49a6c_fld2049_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2050_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2051_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2052_Slot_dot_slot2_get, + 0, + 0, + Field_dsp340050b49a6c_fld2055_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2056_Slot_dot_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2025_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2027_Slot_dot_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s6_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2532dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2533dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2534dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2535dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2536dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2537dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2538dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2539dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2540dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2541dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2542dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2543dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2544dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2545dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2546dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2547dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2548dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2549dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2550dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2551dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2552dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2553dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2554dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2555dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2556dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2557dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2558dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2559dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2560dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2561dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2562dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2563dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2564dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2565dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2566dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2567dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2568dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2569dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2571dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2572dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2573dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2574dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2575dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2576dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2577dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2578_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2579dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2580dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2581dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2582dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2583dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2584dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2585dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2586dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2587dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2588dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2589dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2590dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2591dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2592dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2595dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2596dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2598dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2599dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2601dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2602dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2604dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2605_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2606dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2608dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2609dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2610dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2611dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2612_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2613dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2614_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2615dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2616dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2617dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2618dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2619dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2620dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2621dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2622dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2623dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2624dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2625_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2626dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2628dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2630dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2632dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2633dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2635dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2636dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2637dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2640dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2641dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2642dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2643dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2644dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2645dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2646dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2647dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2648dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2649dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2650dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2651dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2652dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2654dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2655dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2656dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2657dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld2658dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3708dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3709dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3710dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3711dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3712_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3713dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3714dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3715_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3716dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3717dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3718_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3719dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3721dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3722_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3723dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3724dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3725dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3726dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3727dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3728dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3729dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3731dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3732dot_slot2_Slot_dot_slot2_get, + Field_dsp340050b49a6c_fld3733dot_slot2_Slot_dot_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_dot_slot2_set_field_fns[] = { + Field_t_Slot_dot_slot2_set, + 0, + 0, + 0, + 0, + Field_s_Slot_dot_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_dot_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2030_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2032_Slot_dot_slot2_set, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2039_Slot_dot_slot2_set, + 0, + Field_dsp340050b49a6c_fld2041_Slot_dot_slot2_set, + 0, + 0, + Field_dsp340050b49a6c_fld2044_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2045_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2046_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2047_Slot_dot_slot2_set, + 0, + Field_dsp340050b49a6c_fld2049_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2050_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2051_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2052_Slot_dot_slot2_set, + 0, + 0, + Field_dsp340050b49a6c_fld2055_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2056_Slot_dot_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2025_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2027_Slot_dot_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s6_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2532dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2533dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2534dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2535dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2536dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2537dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2538dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2539dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2540dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2541dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2542dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2543dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2544dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2545dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2546dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2547dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2548dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2549dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2550dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2551dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2552dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2553dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2554dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2555dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2556dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2557dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2558dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2559dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2560dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2561dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2562dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2563dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2564dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2565dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2566dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2567dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2568dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2569dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2571dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2572dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2573dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2574dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2575dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2576dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2577dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2578_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2579dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2580dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2581dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2582dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2583dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2584dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2585dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2586dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2587dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2588dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2589dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2590dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2591dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2592dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2595dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2596dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2598dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2599dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2601dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2602dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2604dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2605_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2606dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2608dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2609dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2610dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2611dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2612_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2613dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2614_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2615dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2616dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2617dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2618dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2619dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2620dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2621dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2622dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2623dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2624dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2625_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2626dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2628dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2630dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2632dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2633dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2635dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2636dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2637dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2640dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2641dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2642dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2643dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2644dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2645dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2646dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2647dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2648dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2649dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2650dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2651dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2652dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2654dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2655dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2656dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2657dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld2658dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3708dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3709dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3710dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3711dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3712_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3713dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3714dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3715_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3716dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3717dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3718_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3719dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3721dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3722_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3723dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3724dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3725dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3726dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3727dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3728dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3729dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3731dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3732dot_slot2_Slot_dot_slot2_set, + Field_dsp340050b49a6c_fld3733dot_slot2_Slot_dot_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_dot_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2048_Slot_dot_slot1_get, + 0, + Field_dsp340050b49a6c_fld2050_Slot_dot_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2026_Slot_dot_slot1_get, + Field_dsp340050b49a6c_fld2031_Slot_dot_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s7_Slot_dot_slot1_get, + Field_dsp340050b49a6c_fld3734dot_slot1_Slot_dot_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_dot_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2048_Slot_dot_slot1_set, + 0, + Field_dsp340050b49a6c_fld2050_Slot_dot_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2026_Slot_dot_slot1_set, + Field_dsp340050b49a6c_fld2031_Slot_dot_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s7_Slot_dot_slot1_set, + Field_dsp340050b49a6c_fld3734dot_slot1_Slot_dot_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_dot_slot0_get_field_fns[] = { + Field_t_Slot_dot_slot0_get, + 0, + 0, + 0, + 0, + Field_s_Slot_dot_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_dot_slot0_get, + 0, + 0, + 0, + Field_sal_Slot_dot_slot0_get, + Field_sargt_Slot_dot_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_dot_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_dot_slot0_get, + 0, + Field_dsp340050b49a6c_fld2032_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2035_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2036_Slot_dot_slot0_get, + 0, + Field_dsp340050b49a6c_fld2038_Slot_dot_slot0_get, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2043_Slot_dot_slot0_get, + 0, + Field_dsp340050b49a6c_fld2045_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2046_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2047_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2048_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2049_Slot_dot_slot0_get, + 0, + 0, + Field_dsp340050b49a6c_fld2052_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2053_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2054_Slot_dot_slot0_get, + 0, + Field_dsp340050b49a6c_fld2056_Slot_dot_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s8_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2068_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2666dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2667dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2668dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2669dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2671dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2672dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2673dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2674dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2675dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2676dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2677dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2678dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2679dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2680dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2681dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2682dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2683dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2684dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2685dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2686dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2688dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2689dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2690dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2692dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2693dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2695dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2697dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2699dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2700dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2701dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2702dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2703dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2704dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld2705dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld3735dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld3736_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld3737dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld3738dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld3739dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld3740dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld3741dot_slot0_Slot_dot_slot0_get, + Field_dsp340050b49a6c_fld3742dot_slot0_Slot_dot_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_dot_slot0_set_field_fns[] = { + Field_t_Slot_dot_slot0_set, + 0, + 0, + 0, + 0, + Field_s_Slot_dot_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_dot_slot0_set, + 0, + 0, + 0, + Field_sal_Slot_dot_slot0_set, + Field_sargt_Slot_dot_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_dot_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_dot_slot0_set, + 0, + Field_dsp340050b49a6c_fld2032_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2035_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2036_Slot_dot_slot0_set, + 0, + Field_dsp340050b49a6c_fld2038_Slot_dot_slot0_set, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2043_Slot_dot_slot0_set, + 0, + Field_dsp340050b49a6c_fld2045_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2046_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2047_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2048_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2049_Slot_dot_slot0_set, + 0, + 0, + Field_dsp340050b49a6c_fld2052_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2053_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2054_Slot_dot_slot0_set, + 0, + Field_dsp340050b49a6c_fld2056_Slot_dot_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s8_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2068_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2666dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2667dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2668dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2669dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2671dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2672dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2673dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2674dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2675dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2676dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2677dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2678dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2679dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2680dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2681dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2682dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2683dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2684dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2685dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2686dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2688dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2689dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2690dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2692dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2693dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2695dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2697dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2699dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2700dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2701dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2702dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2703dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2704dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld2705dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld3735dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld3736_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld3737dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld3738dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld3739dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld3740dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld3741dot_slot0_Slot_dot_slot0_set, + Field_dsp340050b49a6c_fld3742dot_slot0_Slot_dot_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_pq_slot2_get_field_fns[] = { + Field_t_Slot_pq_slot2_get, + 0, + 0, + 0, + 0, + Field_s_Slot_pq_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_pq_slot2_get, + Field_r_Slot_pq_slot2_get, + 0, + 0, + Field_sae_Slot_pq_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_pq_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2030_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2032_Slot_pq_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2044_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2045_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2046_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2047_Slot_pq_slot2_get, + 0, + Field_dsp340050b49a6c_fld2049_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2050_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2051_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2052_Slot_pq_slot2_get, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2056_Slot_pq_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2025_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2027_Slot_pq_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s9_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2706pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2707pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2708pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2709pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2710pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2711pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2713pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2714pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2715pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2717pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2718pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2719pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2721pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2722pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2723pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2724pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2725pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2726pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2727pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2728pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2729pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2730pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2731pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2732pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2733pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2734pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2735pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2736pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2737_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2738pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2739pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2741pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2742pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2743pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2746pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2747pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2748pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2750pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2751pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2752pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2753pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2754pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2755pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2756pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2757pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2758pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2759pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2760pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2761pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2762pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2763pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2764pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2765pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2766pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2767pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2768pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2769pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2770pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2771pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2772pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2773pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2774pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2775pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2776pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2777pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2778pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2779pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2780pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2781pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2782pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2783pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2784pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2785pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2786pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2787pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2788pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2789pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2790pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2791pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2792pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2793pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2795pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2796pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2798pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2801pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2803pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2805pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2806pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2807pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2808pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2809pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2810pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2811pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2812pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2814pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2816pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2817_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2818pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2819_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2820pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2821pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld2823pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3744pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3745pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3746pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3747pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3748_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3749pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3750pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3751pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3752pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3753pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3754pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3756pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3757pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3758pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3759pq_slot2_Slot_pq_slot2_get, + Field_dsp340050b49a6c_fld3760pq_slot2_Slot_pq_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_pq_slot2_set_field_fns[] = { + Field_t_Slot_pq_slot2_set, + 0, + 0, + 0, + 0, + Field_s_Slot_pq_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_pq_slot2_set, + Field_r_Slot_pq_slot2_set, + 0, + 0, + Field_sae_Slot_pq_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_pq_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2030_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2032_Slot_pq_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2044_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2045_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2046_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2047_Slot_pq_slot2_set, + 0, + Field_dsp340050b49a6c_fld2049_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2050_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2051_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2052_Slot_pq_slot2_set, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2056_Slot_pq_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2025_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2027_Slot_pq_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s9_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2706pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2707pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2708pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2709pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2710pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2711pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2713pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2714pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2715pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2717pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2718pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2719pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2721pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2722pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2723pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2724pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2725pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2726pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2727pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2728pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2729pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2730pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2731pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2732pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2733pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2734pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2735pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2736pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2737_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2738pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2739pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2741pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2742pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2743pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2746pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2747pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2748pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2750pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2751pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2752pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2753pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2754pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2755pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2756pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2757pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2758pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2759pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2760pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2761pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2762pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2763pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2764pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2765pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2766pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2767pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2768pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2769pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2770pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2771pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2772pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2773pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2774pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2775pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2776pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2777pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2778pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2779pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2780pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2781pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2782pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2783pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2784pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2785pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2786pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2787pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2788pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2789pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2790pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2791pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2792pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2793pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2795pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2796pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2798pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2801pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2803pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2805pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2806pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2807pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2808pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2809pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2810pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2811pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2812pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2814pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2816pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2817_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2818pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2819_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2820pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2821pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld2823pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3744pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3745pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3746pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3747pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3748_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3749pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3750pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3751pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3752pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3753pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3754pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3756pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3757pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3758pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3759pq_slot2_Slot_pq_slot2_set, + Field_dsp340050b49a6c_fld3760pq_slot2_Slot_pq_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_pq_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2049_Slot_pq_slot1_get, + Field_dsp340050b49a6c_fld2050_Slot_pq_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2026_Slot_pq_slot1_get, + Field_dsp340050b49a6c_fld2031_Slot_pq_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s10_Slot_pq_slot1_get, + Field_dsp340050b49a6c_fld2825pq_slot1_Slot_pq_slot1_get, + Field_dsp340050b49a6c_fld2826pq_slot1_Slot_pq_slot1_get, + Field_dsp340050b49a6c_fld3761pq_slot1_Slot_pq_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_pq_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2049_Slot_pq_slot1_set, + Field_dsp340050b49a6c_fld2050_Slot_pq_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2026_Slot_pq_slot1_set, + Field_dsp340050b49a6c_fld2031_Slot_pq_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s10_Slot_pq_slot1_set, + Field_dsp340050b49a6c_fld2825pq_slot1_Slot_pq_slot1_set, + Field_dsp340050b49a6c_fld2826pq_slot1_Slot_pq_slot1_set, + Field_dsp340050b49a6c_fld3761pq_slot1_Slot_pq_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_pq_slot0_get_field_fns[] = { + Field_t_Slot_pq_slot0_get, + 0, + 0, + 0, + 0, + Field_s_Slot_pq_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_pq_slot0_get, + Field_r_Slot_pq_slot0_get, + 0, + 0, + Field_sae_Slot_pq_slot0_get, + Field_sal_Slot_pq_slot0_get, + Field_sargt_Slot_pq_slot0_get, + 0, + Field_sas_Slot_pq_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm6_Slot_pq_slot0_get, + Field_imm7_Slot_pq_slot0_get, + 0, + 0, + 0, + 0, + Field_s4_Slot_pq_slot0_get, + 0, + 0, + Field_s8_Slot_pq_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2030_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2032_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2035_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2036_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2037_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2038_Slot_pq_slot0_get, + 0, + Field_dsp340050b49a6c_fld2040_Slot_pq_slot0_get, + 0, + Field_dsp340050b49a6c_fld2042_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2043_Slot_pq_slot0_get, + 0, + Field_dsp340050b49a6c_fld2045_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2046_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2047_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2048_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2049_Slot_pq_slot0_get, + 0, + Field_dsp340050b49a6c_fld2051_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2052_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2053_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2054_Slot_pq_slot0_get, + 0, + Field_dsp340050b49a6c_fld2056_Slot_pq_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s11_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2059_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2069_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2827pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2829pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2830pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2831pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2832pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2833pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2835pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2836pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2837pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2838pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2839pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2840pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2842pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2843pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2844pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2845pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2846pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2847pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2849pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2850pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2851pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2852pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2853pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2854pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2855pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2856pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2857pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2858pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2859pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2860pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2861pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2863pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2864pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2865_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2867pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2869pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2871pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2872pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2873pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2874pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2875pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2876pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2877pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2878pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2879pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2880pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2881pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2882_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2883pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2884pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2885pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2886pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2887pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2888pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2890pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2891pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2892pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2893pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2894pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2895pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2897pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2899pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2900pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2901pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2902pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2903pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2904pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2905pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2906pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2907pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2908pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2909pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2910pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2911pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2912pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2913pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2914pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2915pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2916pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2917pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2918pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2919pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2920pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2921pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2922pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2923pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2924pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2925pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2926pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2927pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2928pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2929pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2930pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2932pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2934pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2935pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2936pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2937pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2939pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2940_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2941pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2942pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2943pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2945pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2946pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2947pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2948pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2949pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld2950pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3763pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3764pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3765pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3766pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3767pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3768pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3769pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3770pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3771pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3772_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3773pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3775pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3776pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3777pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3778pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3779pq_slot0_Slot_pq_slot0_get, + Field_dsp340050b49a6c_fld3780pq_slot0_Slot_pq_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_pq_slot0_set_field_fns[] = { + Field_t_Slot_pq_slot0_set, + 0, + 0, + 0, + 0, + Field_s_Slot_pq_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_pq_slot0_set, + Field_r_Slot_pq_slot0_set, + 0, + 0, + Field_sae_Slot_pq_slot0_set, + Field_sal_Slot_pq_slot0_set, + Field_sargt_Slot_pq_slot0_set, + 0, + Field_sas_Slot_pq_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm6_Slot_pq_slot0_set, + Field_imm7_Slot_pq_slot0_set, + 0, + 0, + 0, + 0, + Field_s4_Slot_pq_slot0_set, + 0, + 0, + Field_s8_Slot_pq_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2030_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2032_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2035_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2036_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2037_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2038_Slot_pq_slot0_set, + 0, + Field_dsp340050b49a6c_fld2040_Slot_pq_slot0_set, + 0, + Field_dsp340050b49a6c_fld2042_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2043_Slot_pq_slot0_set, + 0, + Field_dsp340050b49a6c_fld2045_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2046_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2047_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2048_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2049_Slot_pq_slot0_set, + 0, + Field_dsp340050b49a6c_fld2051_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2052_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2053_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2054_Slot_pq_slot0_set, + 0, + Field_dsp340050b49a6c_fld2056_Slot_pq_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s11_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2059_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2069_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2827pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2829pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2830pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2831pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2832pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2833pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2835pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2836pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2837pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2838pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2839pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2840pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2842pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2843pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2844pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2845pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2846pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2847pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2849pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2850pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2851pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2852pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2853pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2854pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2855pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2856pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2857pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2858pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2859pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2860pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2861pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2863pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2864pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2865_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2867pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2869pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2871pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2872pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2873pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2874pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2875pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2876pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2877pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2878pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2879pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2880pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2881pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2882_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2883pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2884pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2885pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2886pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2887pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2888pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2890pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2891pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2892pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2893pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2894pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2895pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2897pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2899pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2900pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2901pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2902pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2903pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2904pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2905pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2906pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2907pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2908pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2909pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2910pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2911pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2912pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2913pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2914pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2915pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2916pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2917pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2918pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2919pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2920pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2921pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2922pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2923pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2924pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2925pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2926pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2927pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2928pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2929pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2930pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2932pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2934pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2935pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2936pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2937pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2939pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2940_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2941pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2942pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2943pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2945pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2946pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2947pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2948pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2949pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld2950pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3763pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3764pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3765pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3766pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3767pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3768pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3769pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3770pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3771pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3772_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3773pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3775pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3776pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3777pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3778pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3779pq_slot0_Slot_pq_slot0_set, + Field_dsp340050b49a6c_fld3780pq_slot0_Slot_pq_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_acc2_slot2_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + Field_s_Slot_acc2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_acc2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2045_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld2046_Slot_acc2_slot2_get, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2052_Slot_acc2_slot2_get, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2056_Slot_acc2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2027_Slot_acc2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s12_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld2953acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld2954acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld2955acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld2956acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld2957acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld2958acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld2959acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld2960acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld2963acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld2964acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld2966acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld2967acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld3782acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld3783acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld3784acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld3785acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld3786acc2_slot2_Slot_acc2_slot2_get, + Field_dsp340050b49a6c_fld3788acc2_slot2_Slot_acc2_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_acc2_slot2_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + Field_s_Slot_acc2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_acc2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2045_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld2046_Slot_acc2_slot2_set, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2052_Slot_acc2_slot2_set, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2056_Slot_acc2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2027_Slot_acc2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s12_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld2953acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld2954acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld2955acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld2956acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld2957acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld2958acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld2959acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld2960acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld2963acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld2964acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld2966acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld2967acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld3782acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld3783acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld3784acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld3785acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld3786acc2_slot2_Slot_acc2_slot2_set, + Field_dsp340050b49a6c_fld3788acc2_slot2_Slot_acc2_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_acc2_slot1_get_field_fns[] = { + Field_t_Slot_acc2_slot1_get, + 0, + 0, + 0, + 0, + Field_s_Slot_acc2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2047_Slot_acc2_slot1_get, + Field_dsp340050b49a6c_fld2048_Slot_acc2_slot1_get, + 0, + Field_dsp340050b49a6c_fld2050_Slot_acc2_slot1_get, + 0, + Field_dsp340050b49a6c_fld2052_Slot_acc2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2026_Slot_acc2_slot1_get, + Field_dsp340050b49a6c_fld2031_Slot_acc2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s13_Slot_acc2_slot1_get, + Field_dsp340050b49a6c_fld2028_Slot_acc2_slot1_get, + Field_dsp340050b49a6c_fld2075_Slot_acc2_slot1_get, + Field_dsp340050b49a6c_fld2968acc2_slot1_Slot_acc2_slot1_get, + Field_dsp340050b49a6c_fld2969acc2_slot1_Slot_acc2_slot1_get, + Field_dsp340050b49a6c_fld3790acc2_slot1_Slot_acc2_slot1_get, + Field_dsp340050b49a6c_fld3793acc2_slot1_Slot_acc2_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_acc2_slot1_set_field_fns[] = { + Field_t_Slot_acc2_slot1_set, + 0, + 0, + 0, + 0, + Field_s_Slot_acc2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2047_Slot_acc2_slot1_set, + Field_dsp340050b49a6c_fld2048_Slot_acc2_slot1_set, + 0, + Field_dsp340050b49a6c_fld2050_Slot_acc2_slot1_set, + 0, + Field_dsp340050b49a6c_fld2052_Slot_acc2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2026_Slot_acc2_slot1_set, + Field_dsp340050b49a6c_fld2031_Slot_acc2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s13_Slot_acc2_slot1_set, + Field_dsp340050b49a6c_fld2028_Slot_acc2_slot1_set, + Field_dsp340050b49a6c_fld2075_Slot_acc2_slot1_set, + Field_dsp340050b49a6c_fld2968acc2_slot1_Slot_acc2_slot1_set, + Field_dsp340050b49a6c_fld2969acc2_slot1_Slot_acc2_slot1_set, + Field_dsp340050b49a6c_fld3790acc2_slot1_Slot_acc2_slot1_set, + Field_dsp340050b49a6c_fld3793acc2_slot1_Slot_acc2_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_acc2_slot0_get_field_fns[] = { + Field_t_Slot_acc2_slot0_get, + 0, + 0, + 0, + 0, + Field_s_Slot_acc2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_acc2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_acc2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2039_Slot_acc2_slot0_get, + 0, + Field_dsp340050b49a6c_fld2041_Slot_acc2_slot0_get, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2045_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2046_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2047_Slot_acc2_slot0_get, + 0, + 0, + Field_dsp340050b49a6c_fld2050_Slot_acc2_slot0_get, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2055_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2056_Slot_acc2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s14_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2973acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2974acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2975acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2976acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2977acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2980acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2981acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2982acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2984acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2985acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2987acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2989acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld2990acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld3795acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld3796acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld3797_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld3798acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld3799acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld3800acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld3801acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld3802acc2_slot0_Slot_acc2_slot0_get, + Field_dsp340050b49a6c_fld3803acc2_slot0_Slot_acc2_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_acc2_slot0_set_field_fns[] = { + Field_t_Slot_acc2_slot0_set, + 0, + 0, + 0, + 0, + Field_s_Slot_acc2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_acc2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_acc2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2039_Slot_acc2_slot0_set, + 0, + Field_dsp340050b49a6c_fld2041_Slot_acc2_slot0_set, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2045_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2046_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2047_Slot_acc2_slot0_set, + 0, + 0, + Field_dsp340050b49a6c_fld2050_Slot_acc2_slot0_set, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2055_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2056_Slot_acc2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s14_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2973acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2974acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2975acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2976acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2977acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2980acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2981acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2982acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2984acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2985acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2987acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2989acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld2990acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld3795acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld3796acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld3797_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld3798acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld3799acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld3800acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld3801acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld3802acc2_slot0_Slot_acc2_slot0_set, + Field_dsp340050b49a6c_fld3803acc2_slot0_Slot_acc2_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_smod_slot2_get_field_fns[] = { + Field_t_Slot_smod_slot2_get, + 0, + 0, + 0, + 0, + Field_s_Slot_smod_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_smod_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2030_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2032_Slot_smod_slot2_get, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2039_Slot_smod_slot2_get, + 0, + Field_dsp340050b49a6c_fld2041_Slot_smod_slot2_get, + 0, + 0, + Field_dsp340050b49a6c_fld2044_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2045_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2046_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2047_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2048_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2049_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2050_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2051_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2052_Slot_smod_slot2_get, + 0, + 0, + Field_dsp340050b49a6c_fld2055_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2056_Slot_smod_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2025_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2027_Slot_smod_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s15_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2991smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2992smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2993smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2994smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2995smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2996smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2997smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2998smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld2999smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3000smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3001smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3002smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3003smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3004smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3005smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3006smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3007smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3008smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3009smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3010smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3011smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3012smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3013smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3014smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3015smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3016smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3017smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3018smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3019smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3020smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3021smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3022smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3023smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3024smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3025smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3026smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3027smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3028smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3030smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3031smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3032smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3033smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3034smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3035smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3036smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3038smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3039smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3040smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3043smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3044smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3046smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3047smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3048_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3049smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3050smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3051smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3052smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3053smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3054smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3055smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3056smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3058smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3059smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3061smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3062_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3063smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3065smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3066smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3067smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3068smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3069smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3070_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3071smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3072smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3073smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3074smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3075smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3076smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3077smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3078smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3079smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3080smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3081smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3082smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3084smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3085smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3087smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3088smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3090smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3091smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3092smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3093smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3096smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3097smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3098smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3099smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3100smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3101smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3102smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3104smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3105smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3106smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3107smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3108smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3109smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3110smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3111smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3113smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3114smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3115smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3116smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3805smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3806smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3807smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3808_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3809smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3810smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3812smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3813smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3814smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3816smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3817_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3818smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3819smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3821smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3822smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3823smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3824smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3825smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3826smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3827smod_slot2_Slot_smod_slot2_get, + Field_dsp340050b49a6c_fld3828smod_slot2_Slot_smod_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_smod_slot2_set_field_fns[] = { + Field_t_Slot_smod_slot2_set, + 0, + 0, + 0, + 0, + Field_s_Slot_smod_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_smod_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2030_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2032_Slot_smod_slot2_set, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2039_Slot_smod_slot2_set, + 0, + Field_dsp340050b49a6c_fld2041_Slot_smod_slot2_set, + 0, + 0, + Field_dsp340050b49a6c_fld2044_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2045_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2046_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2047_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2048_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2049_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2050_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2051_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2052_Slot_smod_slot2_set, + 0, + 0, + Field_dsp340050b49a6c_fld2055_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2056_Slot_smod_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2025_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2027_Slot_smod_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s15_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2991smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2992smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2993smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2994smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2995smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2996smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2997smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2998smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld2999smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3000smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3001smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3002smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3003smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3004smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3005smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3006smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3007smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3008smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3009smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3010smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3011smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3012smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3013smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3014smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3015smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3016smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3017smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3018smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3019smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3020smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3021smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3022smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3023smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3024smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3025smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3026smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3027smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3028smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3030smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3031smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3032smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3033smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3034smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3035smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3036smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3038smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3039smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3040smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3043smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3044smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3046smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3047smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3048_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3049smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3050smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3051smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3052smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3053smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3054smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3055smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3056smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3058smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3059smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3061smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3062_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3063smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3065smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3066smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3067smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3068smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3069smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3070_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3071smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3072smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3073smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3074smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3075smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3076smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3077smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3078smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3079smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3080smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3081smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3082smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3084smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3085smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3087smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3088smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3090smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3091smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3092smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3093smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3096smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3097smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3098smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3099smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3100smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3101smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3102smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3104smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3105smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3106smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3107smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3108smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3109smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3110smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3111smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3113smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3114smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3115smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3116smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3805smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3806smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3807smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3808_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3809smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3810smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3812smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3813smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3814smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3816smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3817_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3818smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3819smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3821smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3822smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3823smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3824smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3825smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3826smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3827smod_slot2_Slot_smod_slot2_set, + Field_dsp340050b49a6c_fld3828smod_slot2_Slot_smod_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_smod_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + Field_s_Slot_smod_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2046_Slot_smod_slot1_get, + 0, + Field_dsp340050b49a6c_fld2048_Slot_smod_slot1_get, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2054_Slot_smod_slot1_get, + 0, + Field_dsp340050b49a6c_fld2056_Slot_smod_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2026_Slot_smod_slot1_get, + Field_dsp340050b49a6c_fld2031_Slot_smod_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s16_Slot_smod_slot1_get, + Field_dsp340050b49a6c_fld2033_Slot_smod_slot1_get, + Field_dsp340050b49a6c_fld2080_Slot_smod_slot1_get, + Field_dsp340050b49a6c_fld3117smod_slot1_Slot_smod_slot1_get, + Field_dsp340050b49a6c_fld3118smod_slot1_Slot_smod_slot1_get, + Field_dsp340050b49a6c_fld3829smod_slot1_Slot_smod_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_smod_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + Field_s_Slot_smod_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2046_Slot_smod_slot1_set, + 0, + Field_dsp340050b49a6c_fld2048_Slot_smod_slot1_set, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2054_Slot_smod_slot1_set, + 0, + Field_dsp340050b49a6c_fld2056_Slot_smod_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2026_Slot_smod_slot1_set, + Field_dsp340050b49a6c_fld2031_Slot_smod_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s16_Slot_smod_slot1_set, + Field_dsp340050b49a6c_fld2033_Slot_smod_slot1_set, + Field_dsp340050b49a6c_fld2080_Slot_smod_slot1_set, + Field_dsp340050b49a6c_fld3117smod_slot1_Slot_smod_slot1_set, + Field_dsp340050b49a6c_fld3118smod_slot1_Slot_smod_slot1_set, + Field_dsp340050b49a6c_fld3829smod_slot1_Slot_smod_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_smod_slot0_get_field_fns[] = { + Field_t_Slot_smod_slot0_get, + 0, + 0, + 0, + 0, + Field_s_Slot_smod_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_smod_slot0_get, + Field_r_Slot_smod_slot0_get, + 0, + 0, + Field_sae_Slot_smod_slot0_get, + Field_sal_Slot_smod_slot0_get, + Field_sargt_Slot_smod_slot0_get, + 0, + Field_sas_Slot_smod_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm6_Slot_smod_slot0_get, + Field_imm7_Slot_smod_slot0_get, + 0, + 0, + 0, + 0, + Field_s4_Slot_smod_slot0_get, + 0, + 0, + Field_s8_Slot_smod_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_smod_slot0_get, + 0, + Field_dsp340050b49a6c_fld2032_Slot_smod_slot0_get, + 0, + 0, + Field_dsp340050b49a6c_fld2037_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld2038_Slot_smod_slot0_get, + 0, + Field_dsp340050b49a6c_fld2040_Slot_smod_slot0_get, + 0, + 0, + Field_dsp340050b49a6c_fld2043_Slot_smod_slot0_get, + 0, + Field_dsp340050b49a6c_fld2045_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld2046_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld2047_Slot_smod_slot0_get, + 0, + Field_dsp340050b49a6c_fld2049_Slot_smod_slot0_get, + 0, + 0, + Field_dsp340050b49a6c_fld2052_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld2053_Slot_smod_slot0_get, + 0, + 0, + Field_dsp340050b49a6c_fld2056_Slot_smod_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s17_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3119smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3120smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3121smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3122smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3123smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3125smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3126smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3127smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3128smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3129smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3130smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3131smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3132smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3133smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3134smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3135smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3136smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3137smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3138smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3139smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3140smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3141smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3142smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3143smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3144smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3145smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3146smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3148smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3149smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3150_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3152smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3153smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3155smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3156smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3157smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3158smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3159smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3160smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3161smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3164smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3165smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3166smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3168smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3170smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3171smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3172smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3173smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3174smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3175smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3176smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3177smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3178smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3179smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3180smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3181smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3182smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3184smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3186smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3188smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3832smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3833smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3834_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3836smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3837smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3838smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3841smod_slot0_Slot_smod_slot0_get, + Field_dsp340050b49a6c_fld3842smod_slot0_Slot_smod_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_smod_slot0_set_field_fns[] = { + Field_t_Slot_smod_slot0_set, + 0, + 0, + 0, + 0, + Field_s_Slot_smod_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_smod_slot0_set, + Field_r_Slot_smod_slot0_set, + 0, + 0, + Field_sae_Slot_smod_slot0_set, + Field_sal_Slot_smod_slot0_set, + Field_sargt_Slot_smod_slot0_set, + 0, + Field_sas_Slot_smod_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm6_Slot_smod_slot0_set, + Field_imm7_Slot_smod_slot0_set, + 0, + 0, + 0, + 0, + Field_s4_Slot_smod_slot0_set, + 0, + 0, + Field_s8_Slot_smod_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_smod_slot0_set, + 0, + Field_dsp340050b49a6c_fld2032_Slot_smod_slot0_set, + 0, + 0, + Field_dsp340050b49a6c_fld2037_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld2038_Slot_smod_slot0_set, + 0, + Field_dsp340050b49a6c_fld2040_Slot_smod_slot0_set, + 0, + 0, + Field_dsp340050b49a6c_fld2043_Slot_smod_slot0_set, + 0, + Field_dsp340050b49a6c_fld2045_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld2046_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld2047_Slot_smod_slot0_set, + 0, + Field_dsp340050b49a6c_fld2049_Slot_smod_slot0_set, + 0, + 0, + Field_dsp340050b49a6c_fld2052_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld2053_Slot_smod_slot0_set, + 0, + 0, + Field_dsp340050b49a6c_fld2056_Slot_smod_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s17_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3119smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3120smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3121smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3122smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3123smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3125smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3126smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3127smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3128smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3129smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3130smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3131smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3132smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3133smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3134smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3135smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3136smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3137smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3138smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3139smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3140smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3141smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3142smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3143smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3144smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3145smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3146smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3148smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3149smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3150_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3152smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3153smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3155smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3156smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3157smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3158smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3159smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3160smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3161smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3164smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3165smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3166smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3168smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3170smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3171smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3172smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3173smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3174smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3175smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3176smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3177smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3178smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3179smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3180smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3181smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3182smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3184smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3186smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3188smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3832smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3833smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3834_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3836smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3837smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3838smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3841smod_slot0_Slot_smod_slot0_set, + Field_dsp340050b49a6c_fld3842smod_slot0_Slot_smod_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_llr_slot2_get_field_fns[] = { + Field_t_Slot_llr_slot2_get, + 0, + 0, + 0, + 0, + Field_s_Slot_llr_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_llr_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld2030_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld2032_Slot_llr_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2044_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld2045_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld2046_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld2047_Slot_llr_slot2_get, + 0, + Field_dsp340050b49a6c_fld2049_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld2050_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld2051_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld2052_Slot_llr_slot2_get, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2056_Slot_llr_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2025_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld2027_Slot_llr_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s18_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld2074_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3191llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3192llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3193llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3194llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3195llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3196llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3197llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3198llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3199llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3200llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3201llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3202llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3203llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3204llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3205_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3206_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3207llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3208llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3210llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3212_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3213llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3214_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3215llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3216llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3217_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3218llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3220llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3221llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3222llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3224llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3225_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3226llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3228llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3230_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3231llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3232llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3233_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3234llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3235llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3236_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3237llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3238llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3240llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3241llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3242llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3243llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3244llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3245llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3246_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3247llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3843llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3844_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3845llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3847llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3848llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3849llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3850llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3851llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3853llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3855llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3856llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3857llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3859llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3860llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3861llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3862_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3863llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3864llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3865llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3866llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3867llr_slot2_Slot_llr_slot2_get, + Field_dsp340050b49a6c_fld3868_Slot_llr_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_llr_slot2_set_field_fns[] = { + Field_t_Slot_llr_slot2_set, + 0, + 0, + 0, + 0, + Field_s_Slot_llr_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_llr_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld2030_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld2032_Slot_llr_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2044_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld2045_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld2046_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld2047_Slot_llr_slot2_set, + 0, + Field_dsp340050b49a6c_fld2049_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld2050_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld2051_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld2052_Slot_llr_slot2_set, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2056_Slot_llr_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2025_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld2027_Slot_llr_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s18_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld2074_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3191llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3192llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3193llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3194llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3195llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3196llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3197llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3198llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3199llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3200llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3201llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3202llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3203llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3204llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3205_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3206_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3207llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3208llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3210llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3212_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3213llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3214_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3215llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3216llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3217_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3218llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3220llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3221llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3222llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3224llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3225_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3226llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3228llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3230_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3231llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3232llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3233_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3234llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3235llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3236_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3237llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3238llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3240llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3241llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3242llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3243llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3244llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3245llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3246_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3247llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3843llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3844_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3845llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3847llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3848llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3849llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3850llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3851llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3853llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3855llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3856llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3857llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3859llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3860llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3861llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3862_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3863llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3864llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3865llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3866llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3867llr_slot2_Slot_llr_slot2_set, + Field_dsp340050b49a6c_fld3868_Slot_llr_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_llr_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2047_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld2048_Slot_llr_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2055_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld2056_Slot_llr_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2026_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld2031_Slot_llr_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2028_Slot_llr_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2033_Slot_llr_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s19_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld2034_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld3248llr_slot1_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld3250llr_slot1_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld3251llr_slot1_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld3252llr_slot1_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld3253llr_slot1_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld3254llr_slot1_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld3869llr_slot1_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld3870_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld3872llr_slot1_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld3875llr_slot1_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld3876llr_slot1_Slot_llr_slot1_get, + Field_dsp340050b49a6c_fld3878llr_slot1_Slot_llr_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_llr_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2047_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld2048_Slot_llr_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2055_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld2056_Slot_llr_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2026_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld2031_Slot_llr_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2028_Slot_llr_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2033_Slot_llr_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s19_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld2034_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld3248llr_slot1_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld3250llr_slot1_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld3251llr_slot1_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld3252llr_slot1_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld3253llr_slot1_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld3254llr_slot1_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld3869llr_slot1_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld3870_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld3872llr_slot1_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld3875llr_slot1_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld3876llr_slot1_Slot_llr_slot1_set, + Field_dsp340050b49a6c_fld3878llr_slot1_Slot_llr_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_llr_slot0_get_field_fns[] = { + Field_t_Slot_llr_slot0_get, + 0, + 0, + 0, + 0, + Field_s_Slot_llr_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_llr_slot0_get, + 0, + 0, + 0, + Field_sal_Slot_llr_slot0_get, + Field_sargt_Slot_llr_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_llr_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_llr_slot0_get, + 0, + Field_dsp340050b49a6c_fld2032_Slot_llr_slot0_get, + 0, + 0, + Field_dsp340050b49a6c_fld2037_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld2038_Slot_llr_slot0_get, + 0, + 0, + Field_dsp340050b49a6c_fld2041_Slot_llr_slot0_get, + 0, + Field_dsp340050b49a6c_fld2043_Slot_llr_slot0_get, + 0, + Field_dsp340050b49a6c_fld2045_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld2046_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld2047_Slot_llr_slot0_get, + 0, + Field_dsp340050b49a6c_fld2049_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld2050_Slot_llr_slot0_get, + 0, + Field_dsp340050b49a6c_fld2052_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld2053_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld2054_Slot_llr_slot0_get, + 0, + Field_dsp340050b49a6c_fld2056_Slot_llr_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s20_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld2071_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3258llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3259llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3260llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3261llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3263llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3264llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3265llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3266llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3267llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3268llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3269llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3270llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3272llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3274llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3275llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3276llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3277llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3278llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3279llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3280llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3281llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3282llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3283llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3284llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3286llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3288llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3289llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3291llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3292llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3293llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3294llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3295llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3296llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3297llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3298llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3299llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3300llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3302llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3303llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3304llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3305llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3306llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3308llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3310llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3311llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3312llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3879llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3881llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3883llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3885llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3887llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3888llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3890llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3892llr_slot0_Slot_llr_slot0_get, + Field_dsp340050b49a6c_fld3893llr_slot0_Slot_llr_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_llr_slot0_set_field_fns[] = { + Field_t_Slot_llr_slot0_set, + 0, + 0, + 0, + 0, + Field_s_Slot_llr_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_r_Slot_llr_slot0_set, + 0, + 0, + 0, + Field_sal_Slot_llr_slot0_set, + Field_sargt_Slot_llr_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm7_Slot_llr_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_llr_slot0_set, + 0, + Field_dsp340050b49a6c_fld2032_Slot_llr_slot0_set, + 0, + 0, + Field_dsp340050b49a6c_fld2037_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld2038_Slot_llr_slot0_set, + 0, + 0, + Field_dsp340050b49a6c_fld2041_Slot_llr_slot0_set, + 0, + Field_dsp340050b49a6c_fld2043_Slot_llr_slot0_set, + 0, + Field_dsp340050b49a6c_fld2045_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld2046_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld2047_Slot_llr_slot0_set, + 0, + Field_dsp340050b49a6c_fld2049_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld2050_Slot_llr_slot0_set, + 0, + Field_dsp340050b49a6c_fld2052_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld2053_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld2054_Slot_llr_slot0_set, + 0, + Field_dsp340050b49a6c_fld2056_Slot_llr_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s20_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld2071_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3258llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3259llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3260llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3261llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3263llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3264llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3265llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3266llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3267llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3268llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3269llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3270llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3272llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3274llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3275llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3276llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3277llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3278llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3279llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3280llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3281llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3282llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3283llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3284llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3286llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3288llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3289llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3291llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3292llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3293llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3294llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3295llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3296llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3297llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3298llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3299llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3300llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3302llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3303llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3304llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3305llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3306llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3308llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3310llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3311llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3312llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3879llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3881llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3883llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3885llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3887llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3888llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3890llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3892llr_slot0_Slot_llr_slot0_set, + Field_dsp340050b49a6c_fld3893llr_slot0_Slot_llr_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_dual_slot2_get_field_fns[] = { + Field_t_Slot_dual_slot2_get, + 0, + Field_bbi_Slot_dual_slot2_get, + Field_imm12_Slot_dual_slot2_get, + Field_imm8_Slot_dual_slot2_get, + Field_s_Slot_dual_slot2_get, + Field_imm12b_Slot_dual_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_dual_slot2_get, + Field_r_Slot_dual_slot2_get, + 0, + 0, + Field_sae_Slot_dual_slot2_get, + Field_sal_Slot_dual_slot2_get, + Field_sargt_Slot_dual_slot2_get, + 0, + Field_sas_Slot_dual_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm6_Slot_dual_slot2_get, + Field_imm7_Slot_dual_slot2_get, + 0, + 0, + 0, + 0, + Field_s4_Slot_dual_slot2_get, + 0, + 0, + Field_s8_Slot_dual_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld2030_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld2032_Slot_dual_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2044_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld2045_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld2046_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld2047_Slot_dual_slot2_get, + 0, + Field_dsp340050b49a6c_fld2049_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld2050_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld2051_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld2052_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld2053_Slot_dual_slot2_get, + 0, + 0, + Field_dsp340050b49a6c_fld2056_Slot_dual_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2025_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld2027_Slot_dual_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s21_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3313dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3314_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3315dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3316dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3317dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3318_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3319dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3320dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3321dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3322dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3323dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3324dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3325dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3326dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3327dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3328dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3329dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3330dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3331dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3332dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3333dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3334dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3335dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3336dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3337dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3339dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3340dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3341dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3342dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3345dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3347dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3348dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3349dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3350dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3353dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3354dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3356dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3358dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3360dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3361dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3362dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3363dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3364_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3365dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3366dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3367dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3368dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3369dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3370dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3371dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3372dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3373dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3374dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3375dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3376dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3377dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3378dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3379dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3380dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3381dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3382dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3384dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3385dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3386dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3387dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3388dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3390dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3392dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3394dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3396dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3397dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3399dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3401dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3403dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3404dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3406dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3407_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3408dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3410_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3411dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3412dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3413dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3414dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3415dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3416dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3417dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3418dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3419dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3420dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3421dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3422dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3423dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3424dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3425dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3426dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3427dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3428dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3429dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3430dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3431dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3432dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3433dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3434dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3435dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3436dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3437dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3438dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3439dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3440dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3441dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3442dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3443dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3444dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3445dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3446dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3448dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3450dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3451dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3453dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3454dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3456dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3457dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3458dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3459dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3460dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3461dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3462dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3464dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3465dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3466_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3467dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3468dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3469dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3470dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3471dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3472dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3473dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3474dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3475dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3477dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3478dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3479dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3480dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3481dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3482dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3484dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3894dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3895dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3896dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3897dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3898dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3899dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3900_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3901dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3903dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3904dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3905dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3906dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3907dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3908dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3909dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3910dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3913dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3914dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3916dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3917dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3918dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3919dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3920dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3921dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3922dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3923dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3924dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3925dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3927dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3928dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3929dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3930dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3931dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3933dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3934dual_slot2_Slot_dual_slot2_get, + Field_dsp340050b49a6c_fld3935dual_slot2_Slot_dual_slot2_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_dual_slot2_set_field_fns[] = { + Field_t_Slot_dual_slot2_set, + 0, + Field_bbi_Slot_dual_slot2_set, + Field_imm12_Slot_dual_slot2_set, + Field_imm8_Slot_dual_slot2_set, + Field_s_Slot_dual_slot2_set, + Field_imm12b_Slot_dual_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_dual_slot2_set, + Field_r_Slot_dual_slot2_set, + 0, + 0, + Field_sae_Slot_dual_slot2_set, + Field_sal_Slot_dual_slot2_set, + Field_sargt_Slot_dual_slot2_set, + 0, + Field_sas_Slot_dual_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm6_Slot_dual_slot2_set, + Field_imm7_Slot_dual_slot2_set, + 0, + 0, + 0, + 0, + Field_s4_Slot_dual_slot2_set, + 0, + 0, + Field_s8_Slot_dual_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld2030_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld2032_Slot_dual_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2044_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld2045_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld2046_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld2047_Slot_dual_slot2_set, + 0, + Field_dsp340050b49a6c_fld2049_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld2050_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld2051_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld2052_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld2053_Slot_dual_slot2_set, + 0, + 0, + Field_dsp340050b49a6c_fld2056_Slot_dual_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_dsp340050b49a6c_fld2025_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld2027_Slot_dual_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s21_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3313dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3314_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3315dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3316dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3317dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3318_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3319dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3320dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3321dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3322dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3323dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3324dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3325dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3326dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3327dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3328dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3329dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3330dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3331dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3332dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3333dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3334dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3335dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3336dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3337dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3339dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3340dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3341dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3342dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3345dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3347dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3348dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3349dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3350dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3353dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3354dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3356dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3358dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3360dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3361dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3362dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3363dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3364_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3365dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3366dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3367dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3368dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3369dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3370dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3371dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3372dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3373dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3374dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3375dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3376dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3377dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3378dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3379dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3380dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3381dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3382dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3384dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3385dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3386dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3387dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3388dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3390dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3392dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3394dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3396dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3397dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3399dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3401dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3403dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3404dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3406dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3407_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3408dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3410_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3411dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3412dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3413dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3414dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3415dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3416dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3417dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3418dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3419dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3420dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3421dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3422dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3423dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3424dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3425dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3426dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3427dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3428dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3429dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3430dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3431dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3432dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3433dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3434dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3435dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3436dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3437dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3438dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3439dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3440dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3441dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3442dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3443dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3444dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3445dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3446dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3448dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3450dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3451dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3453dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3454dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3456dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3457dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3458dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3459dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3460dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3461dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3462dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3464dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3465dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3466_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3467dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3468dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3469dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3470dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3471dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3472dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3473dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3474dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3475dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3477dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3478dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3479dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3480dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3481dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3482dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3484dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3894dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3895dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3896dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3897dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3898dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3899dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3900_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3901dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3903dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3904dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3905dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3906dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3907dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3908dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3909dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3910dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3913dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3914dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3916dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3917dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3918dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3919dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3920dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3921dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3922dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3923dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3924dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3925dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3927dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3928dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3929dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3930dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3931dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3933dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3934dual_slot2_Slot_dual_slot2_set, + Field_dsp340050b49a6c_fld3935dual_slot2_Slot_dual_slot2_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_dual_slot1_get_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s22_Slot_dual_slot1_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_dual_slot1_set_field_fns[] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s22_Slot_dual_slot1_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_get_field_fn +Slot_dual_slot0_get_field_fns[] = { + Field_t_Slot_dual_slot0_get, + 0, + Field_bbi_Slot_dual_slot0_get, + Field_imm12_Slot_dual_slot0_get, + Field_imm8_Slot_dual_slot0_get, + Field_s_Slot_dual_slot0_get, + Field_imm12b_Slot_dual_slot0_get, + Field_imm16_Slot_dual_slot0_get, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_dual_slot0_get, + Field_r_Slot_dual_slot0_get, + 0, + 0, + Field_sae_Slot_dual_slot0_get, + Field_sal_Slot_dual_slot0_get, + Field_sargt_Slot_dual_slot0_get, + 0, + Field_sas_Slot_dual_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm6_Slot_dual_slot0_get, + Field_imm7_Slot_dual_slot0_get, + 0, + 0, + 0, + 0, + Field_s4_Slot_dual_slot0_get, + 0, + 0, + Field_s8_Slot_dual_slot0_get, + 0, + 0, + 0, + Field_fimm8_Slot_dual_slot0_get, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2030_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2032_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2035_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2036_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2037_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2038_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2039_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2040_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2041_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2042_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2043_Slot_dual_slot0_get, + 0, + Field_dsp340050b49a6c_fld2045_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2046_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2047_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2048_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2049_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2050_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2051_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2052_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2053_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2054_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2055_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2056_Slot_dual_slot0_get, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s23_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2057_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2060_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2066_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2072_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld2079_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3487dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3488dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3489dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3490dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3491dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3492dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3493dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3494dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3496dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3497dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3498dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3499dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3500dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3502dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3504dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3505dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3506dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3507dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3508dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3509dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3510dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3511dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3512dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3513dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3514dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3515dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3516dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3517dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3518dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3519dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3520dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3522dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3523dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3524dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3527dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3529dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3530dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3531_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3532dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3533dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3535dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3536dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3537dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3538dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3539dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3541dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3542dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3543dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3544dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3545dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3546dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3547dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3548dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3549dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3550dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3551dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3552_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3553dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3554dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3555dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3556dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3557dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3558dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3559dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3560dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3562dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3563dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3564dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3565dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3566dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3567dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3568dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3569dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3570dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3571dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3572dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3573dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3574dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3575dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3576dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3577dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3578dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3579dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3580dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3581dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3582dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3583dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3584_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3585dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3587dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3588dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3589dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3590dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3591dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3592dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3593dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3594dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3595dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3596dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3597dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3598dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3599dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3600dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3601dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3602_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3603dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3604dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3606dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3607dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3608dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3609dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3610_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3611dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3612dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3613dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3614dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3615dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3616dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3618dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3619_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3620dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3621dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3622dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3623dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3624dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3625dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3626dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3936dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3937dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3938dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3939dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3940dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3941dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3943dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3945dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3946dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3947dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3949dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3950dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3951dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3952dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3954dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3957dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3958dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3959dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3960dual_slot0_Slot_dual_slot0_get, + Field_dsp340050b49a6c_fld3961dual_slot0_Slot_dual_slot0_get, + Implicit_Field_ar0_get, + Implicit_Field_ar4_get, + Implicit_Field_ar8_get, + Implicit_Field_ar12_get, + Implicit_Field_bt16_get, + Implicit_Field_bs16_get, + Implicit_Field_br16_get, + Implicit_Field_brall_get +}; + +static xtensa_set_field_fn +Slot_dual_slot0_set_field_fns[] = { + Field_t_Slot_dual_slot0_set, + 0, + Field_bbi_Slot_dual_slot0_set, + Field_imm12_Slot_dual_slot0_set, + Field_imm8_Slot_dual_slot0_set, + Field_s_Slot_dual_slot0_set, + Field_imm12b_Slot_dual_slot0_set, + Field_imm16_Slot_dual_slot0_set, + 0, + 0, + 0, + 0, + 0, + Field_op2_Slot_dual_slot0_set, + Field_r_Slot_dual_slot0_set, + 0, + 0, + Field_sae_Slot_dual_slot0_set, + Field_sal_Slot_dual_slot0_set, + Field_sargt_Slot_dual_slot0_set, + 0, + Field_sas_Slot_dual_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_imm6_Slot_dual_slot0_set, + Field_imm7_Slot_dual_slot0_set, + 0, + 0, + 0, + 0, + Field_s4_Slot_dual_slot0_set, + 0, + 0, + Field_s8_Slot_dual_slot0_set, + 0, + 0, + 0, + Field_fimm8_Slot_dual_slot0_set, + 0, + 0, + Field_dsp340050b49a6c_fld2029_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2030_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2032_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2035_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2036_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2037_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2038_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2039_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2040_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2041_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2042_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2043_Slot_dual_slot0_set, + 0, + Field_dsp340050b49a6c_fld2045_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2046_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2047_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2048_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2049_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2050_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2051_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2052_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2053_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2054_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2055_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2056_Slot_dual_slot0_set, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + Field_op0_s23_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2057_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2060_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2066_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2072_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld2079_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3487dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3488dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3489dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3490dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3491dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3492dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3493dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3494dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3496dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3497dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3498dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3499dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3500dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3502dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3504dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3505dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3506dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3507dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3508dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3509dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3510dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3511dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3512dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3513dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3514dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3515dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3516dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3517dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3518dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3519dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3520dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3522dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3523dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3524dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3527dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3529dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3530dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3531_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3532dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3533dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3535dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3536dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3537dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3538dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3539dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3541dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3542dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3543dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3544dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3545dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3546dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3547dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3548dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3549dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3550dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3551dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3552_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3553dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3554dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3555dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3556dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3557dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3558dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3559dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3560dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3562dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3563dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3564dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3565dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3566dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3567dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3568dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3569dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3570dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3571dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3572dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3573dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3574dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3575dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3576dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3577dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3578dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3579dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3580dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3581dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3582dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3583dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3584_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3585dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3587dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3588dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3589dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3590dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3591dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3592dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3593dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3594dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3595dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3596dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3597dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3598dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3599dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3600dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3601dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3602_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3603dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3604dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3606dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3607dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3608dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3609dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3610_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3611dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3612dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3613dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3614dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3615dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3616dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3618dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3619_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3620dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3621dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3622dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3623dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3624dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3625dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3626dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3936dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3937dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3938dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3939dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3940dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3941dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3943dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3945dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3946dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3947dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3949dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3950dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3951dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3952dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3954dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3957dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3958dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3959dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3960dual_slot0_Slot_dual_slot0_set, + Field_dsp340050b49a6c_fld3961dual_slot0_Slot_dual_slot0_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set, + Implicit_Field_set +}; + +static xtensa_slot_internal slots[] = { + { "Inst", "x24", 0, + Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, + Slot_inst_get_field_fns, Slot_inst_set_field_fns, + Slot_inst_decode, "nop" }, + { "Inst16a", "x16a", 0, + Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, + Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, + Slot_inst16a_decode, "" }, + { "Inst16b", "x16b", 0, + Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, + Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, + Slot_inst16b_decode, "nop.n" }, + { "GP_slot2", "GP", 2, + Slot_gp_Format_gp_slot2_43_get, Slot_gp_Format_gp_slot2_43_set, + Slot_gp_slot2_get_field_fns, Slot_gp_slot2_set_field_fns, + Slot_gp_slot2_decode, "nop" }, + { "GP_slot1", "GP", 1, + Slot_gp_Format_gp_slot1_26_get, Slot_gp_Format_gp_slot1_26_set, + Slot_gp_slot1_get_field_fns, Slot_gp_slot1_set_field_fns, + Slot_gp_slot1_decode, "nop" }, + { "GP_slot0", "GP", 0, + Slot_gp_Format_gp_slot0_7_get, Slot_gp_Format_gp_slot0_7_set, + Slot_gp_slot0_get_field_fns, Slot_gp_slot0_set_field_fns, + Slot_gp_slot0_decode, "nop" }, + { "DOT_slot2", "DOT", 2, + Slot_dot_Format_dot_slot2_44_get, Slot_dot_Format_dot_slot2_44_set, + Slot_dot_slot2_get_field_fns, Slot_dot_slot2_set_field_fns, + Slot_dot_slot2_decode, "nop" }, + { "DOT_slot1", "DOT", 1, + Slot_dot_Format_dot_slot1_24_get, Slot_dot_Format_dot_slot1_24_set, + Slot_dot_slot1_get_field_fns, Slot_dot_slot1_set_field_fns, + Slot_dot_slot1_decode, "nop" }, + { "DOT_slot0", "DOT", 0, + Slot_dot_Format_dot_slot0_7_get, Slot_dot_Format_dot_slot0_7_set, + Slot_dot_slot0_get_field_fns, Slot_dot_slot0_set_field_fns, + Slot_dot_slot0_decode, "nop" }, + { "PQ_slot2", "PQ", 2, + Slot_pq_Format_pq_slot2_40_get, Slot_pq_Format_pq_slot2_40_set, + Slot_pq_slot2_get_field_fns, Slot_pq_slot2_set_field_fns, + Slot_pq_slot2_decode, "nop" }, + { "PQ_slot1", "PQ", 1, + Slot_pq_Format_pq_slot1_26_get, Slot_pq_Format_pq_slot1_26_set, + Slot_pq_slot1_get_field_fns, Slot_pq_slot1_set_field_fns, + Slot_pq_slot1_decode, "nop" }, + { "PQ_slot0", "PQ", 0, + Slot_pq_Format_pq_slot0_7_get, Slot_pq_Format_pq_slot0_7_set, + Slot_pq_slot0_get_field_fns, Slot_pq_slot0_set_field_fns, + Slot_pq_slot0_decode, "nop" }, + { "ACC2_slot2", "ACC2", 2, + Slot_acc2_Format_acc2_slot2_47_get, Slot_acc2_Format_acc2_slot2_47_set, + Slot_acc2_slot2_get_field_fns, Slot_acc2_slot2_set_field_fns, + Slot_acc2_slot2_decode, "nop" }, + { "ACC2_slot1", "ACC2", 1, + Slot_acc2_Format_acc2_slot1_23_get, Slot_acc2_Format_acc2_slot1_23_set, + Slot_acc2_slot1_get_field_fns, Slot_acc2_slot1_set_field_fns, + Slot_acc2_slot1_decode, "nop" }, + { "ACC2_slot0", "ACC2", 0, + Slot_acc2_Format_acc2_slot0_7_get, Slot_acc2_Format_acc2_slot0_7_set, + Slot_acc2_slot0_get_field_fns, Slot_acc2_slot0_set_field_fns, + Slot_acc2_slot0_decode, "nop" }, + { "SMOD_slot2", "SMOD", 2, + Slot_smod_Format_smod_slot2_42_get, Slot_smod_Format_smod_slot2_42_set, + Slot_smod_slot2_get_field_fns, Slot_smod_slot2_set_field_fns, + Slot_smod_slot2_decode, "nop" }, + { "SMOD_slot1", "SMOD", 1, + Slot_smod_Format_smod_slot1_26_get, Slot_smod_Format_smod_slot1_26_set, + Slot_smod_slot1_get_field_fns, Slot_smod_slot1_set_field_fns, + Slot_smod_slot1_decode, "nop" }, + { "SMOD_slot0", "SMOD", 0, + Slot_smod_Format_smod_slot0_7_get, Slot_smod_Format_smod_slot0_7_set, + Slot_smod_slot0_get_field_fns, Slot_smod_slot0_set_field_fns, + Slot_smod_slot0_decode, "nop" }, + { "LLR_slot2", "LLR", 2, + Slot_llr_Format_llr_slot2_44_get, Slot_llr_Format_llr_slot2_44_set, + Slot_llr_slot2_get_field_fns, Slot_llr_slot2_set_field_fns, + Slot_llr_slot2_decode, "nop" }, + { "LLR_slot1", "LLR", 1, + Slot_llr_Format_llr_slot1_24_get, Slot_llr_Format_llr_slot1_24_set, + Slot_llr_slot1_get_field_fns, Slot_llr_slot1_set_field_fns, + Slot_llr_slot1_decode, "nop" }, + { "LLR_slot0", "LLR", 0, + Slot_llr_Format_llr_slot0_7_get, Slot_llr_Format_llr_slot0_7_set, + Slot_llr_slot0_get_field_fns, Slot_llr_slot0_set_field_fns, + Slot_llr_slot0_decode, "nop" }, + { "DUAL_slot2", "DUAL", 2, + Slot_dual_Format_dual_slot2_31_get, Slot_dual_Format_dual_slot2_31_set, + Slot_dual_slot2_get_field_fns, Slot_dual_slot2_set_field_fns, + Slot_dual_slot2_decode, "nop" }, + { "DUAL_slot1", "DUAL", 1, + Slot_dual_Format_dual_slot1_30_get, Slot_dual_Format_dual_slot1_30_set, + Slot_dual_slot1_get_field_fns, Slot_dual_slot1_set_field_fns, + Slot_dual_slot1_decode, "nop" }, + { "DUAL_slot0", "DUAL", 0, + Slot_dual_Format_dual_slot0_7_get, Slot_dual_Format_dual_slot0_7_set, + Slot_dual_slot0_get_field_fns, Slot_dual_slot0_set_field_fns, + Slot_dual_slot0_decode, "nop" } +}; + + +/* Instruction formats. */ + +static void +Format_x24_encode (xtensa_insnbuf insn) +{ + insn[0] = 0; + insn[1] = 0; +} + +static void +Format_x16a_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x8; + insn[1] = 0; +} + +static void +Format_x16b_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xc; + insn[1] = 0; +} + +static void +Format_GP_encode (xtensa_insnbuf insn) +{ + insn[0] = 0xf; + insn[1] = 0; +} + +static void +Format_DOT_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x1f; + insn[1] = 0; +} + +static void +Format_PQ_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x2f; + insn[1] = 0; +} + +static void +Format_ACC2_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x3f; + insn[1] = 0; +} + +static void +Format_SMOD_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x4f; + insn[1] = 0; +} + +static void +Format_LLR_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x5f; + insn[1] = 0; +} + +static void +Format_DUAL_encode (xtensa_insnbuf insn) +{ + insn[0] = 0x6f; + insn[1] = 0; +} + +static int Format_x24_slots[] = { 0 }; + +static int Format_x16a_slots[] = { 1 }; + +static int Format_x16b_slots[] = { 2 }; + +static int Format_GP_slots[] = { 5, 4, 3 }; + +static int Format_DOT_slots[] = { 8, 7, 6 }; + +static int Format_PQ_slots[] = { 11, 10, 9 }; + +static int Format_ACC2_slots[] = { 14, 13, 12 }; + +static int Format_SMOD_slots[] = { 17, 16, 15 }; + +static int Format_LLR_slots[] = { 20, 19, 18 }; + +static int Format_DUAL_slots[] = { 23, 22, 21 }; + +static xtensa_format_internal formats[] = { + { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, + { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, + { "GP", 8, Format_GP_encode, 3, Format_GP_slots }, + { "DOT", 8, Format_DOT_encode, 3, Format_DOT_slots }, + { "PQ", 8, Format_PQ_encode, 3, Format_PQ_slots }, + { "ACC2", 8, Format_ACC2_encode, 3, Format_ACC2_slots }, + { "SMOD", 8, Format_SMOD_encode, 3, Format_SMOD_slots }, + { "LLR", 8, Format_LLR_encode, 3, Format_LLR_slots }, + { "DUAL", 8, Format_DUAL_encode, 3, Format_DUAL_slots } +}; + + +static int +format_decoder (const xtensa_insnbuf insn) +{ + if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0) + return 0; /* x24 */ + if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0) + return 1; /* x16a */ + if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0) + return 2; /* x16b */ + if ((insn[0] & 0x7f) == 0xf && (insn[1] & 0) == 0) + return 3; /* GP */ + if ((insn[0] & 0x7f) == 0x1f && (insn[1] & 0) == 0) + return 4; /* DOT */ + if ((insn[0] & 0x7f) == 0x2f && (insn[1] & 0) == 0) + return 5; /* PQ */ + if ((insn[0] & 0x7f) == 0x3f && (insn[1] & 0) == 0) + return 6; /* ACC2 */ + if ((insn[0] & 0x7f) == 0x4f && (insn[1] & 0) == 0) + return 7; /* SMOD */ + if ((insn[0] & 0x7f) == 0x5f && (insn[1] & 0) == 0) + return 8; /* LLR */ + if ((insn[0] & 0x7f) == 0x6f && (insn[1] & 0) == 0) + return 9; /* DUAL */ + return -1; +} + +static int length_table[16] = { + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 3, + 2, + 2, + 2, + 2, + 2, + 2, + -1, + 8 +}; + +static int +length_decoder (const unsigned char *insn) +{ + int op0 = insn[0] & 0xf; + return length_table[op0]; +} + + +/* Top-level ISA structure. */ + +xtensa_isa_internal xtensa_modules = { + 0 /* little-endian */, + 8 /* insn_size */, 0, + 10, formats, format_decoder, length_decoder, + 24, slots, + 1733 /* num_fields */, + 1828, operands, + 747, iclasses, + 839, opcodes, 0, + 10, regfiles, + NUM_STATES, states, 0, + NUM_SYSREGS, sysregs, 0, + { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, + 95, interfaces, 0, + 0, funcUnits, 0 +};