From patchwork Wed Jul 8 15:34:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11651801 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A6169913 for ; Wed, 8 Jul 2020 15:34:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8E397207DF for ; Wed, 8 Jul 2020 15:34:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730283AbgGHPeq (ORCPT ); Wed, 8 Jul 2020 11:34:46 -0400 Received: from foss.arm.com ([217.140.110.172]:47166 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730028AbgGHPep (ORCPT ); Wed, 8 Jul 2020 11:34:45 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 21AB61045; Wed, 8 Jul 2020 08:34:45 -0700 (PDT) Received: from e123648.arm.com (unknown [10.37.12.67]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AFCD23F237; Wed, 8 Jul 2020 08:34:40 -0700 (PDT) From: Lukasz Luba To: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Cc: lukasz.luba@arm.com, willy.mh.wolff.ml@gmail.com, k.konieczny@samsung.com, cw00.choi@samsung.com, b.zolnierkie@samsung.com, krzk@kernel.org, chanwoo@kernel.org, myungjoo.ham@samsung.com, kyungmin.park@samsung.com, s.nawrocki@samsung.com, kgene@kernel.org Subject: [PATCH 1/2] memory: samsung: exynos5422-dmc: Adjust polling interval and uptreshold Date: Wed, 8 Jul 2020 16:34:19 +0100 Message-Id: <20200708153420.29484-2-lukasz.luba@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708153420.29484-1-lukasz.luba@arm.com> References: <20200708153420.29484-1-lukasz.luba@arm.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org In order to react faster and make better decisions under some workloads, benchmarking the memory subsystem behavior, adjust the polling interval and upthreshold value used by the simple_ondemand governor. Reported-by: Willy Wolff Signed-off-by: Lukasz Luba Reviewed-by: Chanwoo Choi --- drivers/memory/samsung/exynos5422-dmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c index 93e9c2429c0d..e03ee35f0ab5 100644 --- a/drivers/memory/samsung/exynos5422-dmc.c +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -1466,10 +1466,10 @@ static int exynos5_dmc_probe(struct platform_device *pdev) * Setup default thresholds for the devfreq governor. * The values are chosen based on experiments. */ - dmc->gov_data.upthreshold = 30; + dmc->gov_data.upthreshold = 10; dmc->gov_data.downdifferential = 5; - exynos5_dmc_df_profile.polling_ms = 500; + exynos5_dmc_df_profile.polling_ms = 100; } From patchwork Wed Jul 8 15:34:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 11651805 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6BD4E13B1 for ; Wed, 8 Jul 2020 15:34:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5CFA8206DF for ; Wed, 8 Jul 2020 15:34:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730299AbgGHPeu (ORCPT ); Wed, 8 Jul 2020 11:34:50 -0400 Received: from foss.arm.com ([217.140.110.172]:47186 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730028AbgGHPeu (ORCPT ); Wed, 8 Jul 2020 11:34:50 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CDC281FB; Wed, 8 Jul 2020 08:34:49 -0700 (PDT) Received: from e123648.arm.com (unknown [10.37.12.67]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9C1083F237; Wed, 8 Jul 2020 08:34:45 -0700 (PDT) From: Lukasz Luba To: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Cc: lukasz.luba@arm.com, willy.mh.wolff.ml@gmail.com, k.konieczny@samsung.com, cw00.choi@samsung.com, b.zolnierkie@samsung.com, krzk@kernel.org, chanwoo@kernel.org, myungjoo.ham@samsung.com, kyungmin.park@samsung.com, s.nawrocki@samsung.com, kgene@kernel.org Subject: [PATCH 2/2] ARM: dts: exynos: Remove interrupts from DMC controller in Exynos5422 Date: Wed, 8 Jul 2020 16:34:20 +0100 Message-Id: <20200708153420.29484-3-lukasz.luba@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200708153420.29484-1-lukasz.luba@arm.com> References: <20200708153420.29484-1-lukasz.luba@arm.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The interrupts in Dynamic Memory Controller in Exynos5422 and Odroid XU3-family boards are no longer needed. They have been used in order to workaround some issues in scheduled work in devfreq. Now when the devfreq framework design is improved, remove the interrupt driven approach and rely on devfreq monitoring mechanism with fixed intervals. Reported-by: Willy Wolff Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c76460b70532..967868cc8211 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -240,9 +240,6 @@ dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; - interrupt-parent = <&combiner>; - interrupts = <16 0>, <16 1>; - interrupt-names = "drex_0", "drex_1"; clocks = <&clock CLK_FOUT_SPLL>, <&clock CLK_MOUT_SCLK_SPLL>, <&clock CLK_FF_DOUT_SPLL2>,