From patchwork Thu Jul 9 05:01:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11653327 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 689BC14B7 for ; Thu, 9 Jul 2020 05:01:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5086F2074A for ; Thu, 9 Jul 2020 05:01:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="AOLHWt2G" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726064AbgGIFBp (ORCPT ); Thu, 9 Jul 2020 01:01:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726119AbgGIFBm (ORCPT ); Thu, 9 Jul 2020 01:01:42 -0400 Received: from mail-pj1-x1043.google.com (mail-pj1-x1043.google.com [IPv6:2607:f8b0:4864:20::1043]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38BD9C08C5DC for ; Wed, 8 Jul 2020 22:01:42 -0700 (PDT) Received: by mail-pj1-x1043.google.com with SMTP id cv18so2902885pjb.1 for ; Wed, 08 Jul 2020 22:01:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T+6WxJ1O6k89NNQZzhHWgQkm03zUeIAl0iKHL4vPlUk=; b=AOLHWt2GPk9pGPq6HPxBOiLg8IkaE8fySTF+79CaOlFbY/Ii9OChxP90kbGu1Kpp4g 1geiQB3FJADTo1pUFgW3Sxa65geoU2CT5za4/L0HfEdsLOAuiS/hjjGJAhLd5WpirmZf FtqNIv1CQKnyDdPXdmuFBCNC6yhLvo2cYc6qSM5QnmTXkmdX5EeDxnIrVvTmG4ZIadtN 9Wc0sp5jXMyQsZ3p/wY2QYy7Ht2049b7nCZwdk1eGIpkU//mzH2EjylQGA8lOiKrtshJ LlRfr/5BOfigasYH241F2AoEDk2ymoYdc1UD+9rYiSk5J9TrKnHdKxLfuGL8+sE3Lbxw Lrdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T+6WxJ1O6k89NNQZzhHWgQkm03zUeIAl0iKHL4vPlUk=; b=qFQTf0Ni6I4jy1mU35Ly892RhXHctA+VjNhDwOPTe3n6opT25CBnLstdZOqsjwSZ10 R0MGU5Hq0HpeMKruqlwHggTA99Qa6uWk0RStCmLHNtUUPq6EOiRpsohTAOzbdYrLbdkc MvE1KKWTx6herwLgySaI6F3k9cBuOQGYQi+3SlU0yh77UpgPnOWfm1I3Xg15cZA7YzDN kM1776LdOgbVh7og1F8VAlTV+cEZIhiy9WZ8K2HEaQdk4gVsSr2dJb4YLVNRsy6Dgtn4 UAo2J38WLKHcud5aPi5j6zZOg1UIxft07ge/qpoiUzH0KCoWoBpB+9eqWXNxR6uJD+zt BssA== X-Gm-Message-State: AOAM530ZsBrtiBOUEktHq1SBy/5nyA3UvbSv3fBvE/7HR3jYAtuNuP1z Pxnc2WYf71fsVWGeRF3GhTnuHw== X-Google-Smtp-Source: ABdhPJxF4d+sWu8w2NwzlZP7r/VFELTU9n5hnbo5rdODjHR0wnwyVgaX97f2R3IqlZFh0Lej268MjA== X-Received: by 2002:a17:90b:4d08:: with SMTP id mw8mr12970883pjb.119.1594270901682; Wed, 08 Jul 2020 22:01:41 -0700 (PDT) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id h15sm999974pjc.14.2020.07.08.22.01.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2020 22:01:41 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org Subject: [PATCH 1/5] iommu/arm-smmu: Make all valid stream mappings BYPASS Date: Wed, 8 Jul 2020 22:01:41 -0700 Message-Id: <20200709050145.3520931-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200709050145.3520931-1-bjorn.andersson@linaro.org> References: <20200709050145.3520931-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Turn all stream mappings marked as valid into BYPASS. This allows the platform specific implementation to configure stream mappings to match the boot loader's configuration for e.g. display to continue to function through the reset of the SMMU. Suggested-by: Robin Murphy Signed-off-by: Bjorn Andersson Reported-by: kernel test robot Reported-by: kernel test robot --- drivers/iommu/arm-smmu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 243bc4cb2705..2e27cf9815ab 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1924,6 +1924,22 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) return 0; } +int arm_smmu_setup_identity(struct arm_smmu_device *smmu) +{ + int i; + + for (i = 0; i < smmu->num_mapping_groups; i++) { + if (smmu->smrs[i].valid) { + smmu->s2crs[i].type = S2CR_TYPE_BYPASS; + smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; + smmu->s2crs[i].cbndx = 0xff; + smmu->s2crs[i].count++; + } + } + + return 0; +} + struct arm_smmu_match_data { enum arm_smmu_arch_version version; enum arm_smmu_implementation model; @@ -2181,6 +2197,10 @@ static int arm_smmu_device_probe(struct platform_device *pdev) if (err) return err; + err = arm_smmu_setup_identity(smmu); + if (err) + return err; + if (smmu->version == ARM_SMMU_V2) { if (smmu->num_context_banks > smmu->num_context_irqs) { dev_err(dev, From patchwork Thu Jul 9 05:01:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11653337 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A4F614DD for ; Thu, 9 Jul 2020 05:02:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 039712070E for ; Thu, 9 Jul 2020 05:02:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="YQWuQBQH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726327AbgGIFCD (ORCPT ); Thu, 9 Jul 2020 01:02:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726196AbgGIFBo (ORCPT ); Thu, 9 Jul 2020 01:01:44 -0400 Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A587EC08C5CE for ; Wed, 8 Jul 2020 22:01:43 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id j20so494079pfe.5 for ; Wed, 08 Jul 2020 22:01:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fL1oj/82czdR0WXUznCgbOV1KIBa6gJW0wdl0Fe8bqk=; b=YQWuQBQH2GSEZE8K4EI/Gew9fg1AI6MpHL0uRHUylnIff9sxijznzxDBhh0+EguiC3 nPQaHnHAyeNKdx99gIzgFq3df+1a/ehZVV2I6ySRKyX3IfkQUfRsGNWC0w/WeiKfU6oi yzyYjpbROlG19Zuw4csOp62AY8ifnBblwcGo4ZHdYoUriQ3cGGw8mBKSAk+zOXqPJdFV MLjR1dq/Yv3w3bS11+j4uGeq0PZfwU88ItxE5IY5qbW/nMGO90Mk4xQjbm7W6Y8QozWe E+KYwEDC4Af+CwQl+dbh/ewI/SNpahBBYVME/IKZnlzjYbjUMqBTFdzzERsOBo1iCZuJ p7sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fL1oj/82czdR0WXUznCgbOV1KIBa6gJW0wdl0Fe8bqk=; b=f3sjLN5pEHth6YBHvbf9pBGp5DrisRv2c5G/G53QBt9iawSesolJX6uberl2psrbuq FNl4MQlakd3eyLnf4ShY/QMdJ3w2c+yaST7xmC79hmBG5urhWtM5r0roCMzPjZCyv38Y KFd4o1cm8kUp9JXxuvbbAiYVVLoKRm5/gfS4IOX/Cjvxn/JuMhZl8I2NL9v0Dz98cTH7 5Ynv+LBdjGf4wwGSZXOlQ1K3MD73RV0C5vWHtpIo+HMsbX82FfFEE97STvoDH6ctRi4L /yt0fZqJnvuYkcuxO7d15xIcI6c3aKbYdm4A6f88J7bxilnq9r2V9FV5zN6IIAnVESG5 L3Ng== X-Gm-Message-State: AOAM5319w5uAoyP34jf1q70UZ5OPFVMKLit0rMTaPPKf+fhDCw6C3Ior RkgONx1hsr/jivFOIvLm0e+gtw== X-Google-Smtp-Source: ABdhPJyCvUhg3Z54pWl5PZR4ipfWmNp9zxcFYtuOj/BIJz3aWWsj8AWlwbK8reSTeGRPCPOiYOhZpQ== X-Received: by 2002:a05:6a00:807:: with SMTP id m7mr58259929pfk.246.1594270903096; Wed, 08 Jul 2020 22:01:43 -0700 (PDT) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id h15sm999974pjc.14.2020.07.08.22.01.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2020 22:01:42 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org Subject: [PATCH 2/5] iommu/arm-smmu: Emulate bypass by using context banks Date: Wed, 8 Jul 2020 22:01:42 -0700 Message-Id: <20200709050145.3520931-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200709050145.3520931-1-bjorn.andersson@linaro.org> References: <20200709050145.3520931-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some firmware found on various Qualcomm platforms traps writes to S2CR of type BYPASS and writes FAULT into the register. This prevents us from marking the streams for the display controller as BYPASS to allow continued scanout of the screen through the initialization of the ARM SMMU. This adds a Qualcomm specific cfg_probe function, which probes the behavior of the S2CR registers and if found faulty enables the related quirk. Based on this quirk context banks are allocated for IDENTITY domains as well, but with ARM_SMMU_SCTLR_M omitted. The result is valid stream mappings, without translation. Signed-off-by: Bjorn Andersson --- drivers/iommu/arm-smmu-qcom.c | 21 +++++++++++++++++++++ drivers/iommu/arm-smmu.c | 14 ++++++++++++-- drivers/iommu/arm-smmu.h | 3 +++ 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c index cf01d0215a39..e8a36054e912 100644 --- a/drivers/iommu/arm-smmu-qcom.c +++ b/drivers/iommu/arm-smmu-qcom.c @@ -23,6 +23,26 @@ static const struct of_device_id qcom_smmu_client_of_match[] = { { } }; +static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) +{ + unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); + u32 reg; + + /* + * With some firmware writes to S2CR of type FAULT are ignored, and + * writing BYPASS will end up as FAULT in the register. Perform a write + * to S2CR to detect if this is the case with the current firmware. + */ + arm_smmu_gr0_write(smmu, last_s2cr, FIELD_PREP(ARM_SMMU_S2CR_TYPE, S2CR_TYPE_BYPASS) | + FIELD_PREP(ARM_SMMU_S2CR_CBNDX, 0xff) | + FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, S2CR_PRIVCFG_DEFAULT)); + reg = arm_smmu_gr0_read(smmu, last_s2cr); + if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) + smmu->qcom_bypass_quirk = true; + + return 0; +} + static int qcom_smmu_def_domain_type(struct device *dev) { const struct of_device_id *match = @@ -61,6 +81,7 @@ static int qcom_smmu500_reset(struct arm_smmu_device *smmu) } static const struct arm_smmu_impl qcom_smmu_impl = { + .cfg_probe = qcom_smmu_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, .reset = qcom_smmu500_reset, }; diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 2e27cf9815ab..f33eda3117fa 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -654,7 +654,9 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) /* SCTLR */ reg = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE | ARM_SMMU_SCTLR_AFE | - ARM_SMMU_SCTLR_TRE | ARM_SMMU_SCTLR_M; + ARM_SMMU_SCTLR_TRE; + if (cfg->m) + reg |= ARM_SMMU_SCTLR_M; if (stage1) reg |= ARM_SMMU_SCTLR_S1_ASIDPNE; if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) @@ -678,7 +680,11 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, if (smmu_domain->smmu) goto out_unlock; - if (domain->type == IOMMU_DOMAIN_IDENTITY) { + /* + * Nothing to do for IDENTITY domains,unless disabled context banks are + * used to emulate bypass mappings on Qualcomm platforms. + */ + if (domain->type == IOMMU_DOMAIN_IDENTITY && !smmu->qcom_bypass_quirk) { smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS; smmu_domain->smmu = smmu; goto out_unlock; @@ -826,6 +832,10 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, domain->geometry.aperture_end = (1UL << ias) - 1; domain->geometry.force_aperture = true; + /* Enable translation for non-identity context banks */ + if (domain->type != IOMMU_DOMAIN_IDENTITY) + cfg->m = true; + /* Initialise the context bank with our page table cfg */ arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg); arm_smmu_write_context_bank(smmu, cfg->cbndx); diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index d172c024be61..a71d193073e4 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -305,6 +305,8 @@ struct arm_smmu_device { /* IOMMU core code handle */ struct iommu_device iommu; + + bool qcom_bypass_quirk; }; enum arm_smmu_context_fmt { @@ -323,6 +325,7 @@ struct arm_smmu_cfg { }; enum arm_smmu_cbar_type cbar; enum arm_smmu_context_fmt fmt; + bool m; }; #define ARM_SMMU_INVALID_IRPTNDX 0xff From patchwork Thu Jul 9 05:01:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11653333 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CE26414B7 for ; Thu, 9 Jul 2020 05:02:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B75822074A for ; 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id h15sm999974pjc.14.2020.07.08.22.01.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2020 22:01:43 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org Subject: [PATCH 3/5] iommu/arm-smmu: Move SMR and S2CR definitions to header file Date: Wed, 8 Jul 2020 22:01:43 -0700 Message-Id: <20200709050145.3520931-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200709050145.3520931-1-bjorn.andersson@linaro.org> References: <20200709050145.3520931-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Expose the SMR and S2CR structs in the header file, to allow platform specific implementations to populate/initialize the smrs and s2cr arrays. Signed-off-by: Bjorn Andersson --- drivers/iommu/arm-smmu.c | 14 -------------- drivers/iommu/arm-smmu.h | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index f33eda3117fa..e2d6c0aaf1ea 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -68,24 +68,10 @@ module_param(disable_bypass, bool, S_IRUGO); MODULE_PARM_DESC(disable_bypass, "Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU."); -struct arm_smmu_s2cr { - struct iommu_group *group; - int count; - enum arm_smmu_s2cr_type type; - enum arm_smmu_s2cr_privcfg privcfg; - u8 cbndx; -}; - #define s2cr_init_val (struct arm_smmu_s2cr){ \ .type = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS, \ } -struct arm_smmu_smr { - u16 mask; - u16 id; - bool valid; -}; - struct arm_smmu_cb { u64 ttbr[2]; u32 tcr[2]; diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index a71d193073e4..bcd160d01c53 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -251,6 +251,21 @@ enum arm_smmu_implementation { QCOM_SMMUV2, }; +struct arm_smmu_s2cr { + struct iommu_group *group; + int count; + enum arm_smmu_s2cr_type type; + enum arm_smmu_s2cr_privcfg privcfg; + u8 cbndx; +}; + +struct arm_smmu_smr { + u16 mask; + u16 id; + bool valid; + bool pinned; +}; + struct arm_smmu_device { struct device *dev; From patchwork Thu Jul 9 05:01:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 11653331 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 532D16C1 for ; Thu, 9 Jul 2020 05:01:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2FC682073A for ; Thu, 9 Jul 2020 05:01:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="sJK6emFs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726345AbgGIFBu (ORCPT ); Thu, 9 Jul 2020 01:01:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726342AbgGIFBt (ORCPT ); Thu, 9 Jul 2020 01:01:49 -0400 Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89480C08C5CE for ; Wed, 8 Jul 2020 22:01:49 -0700 (PDT) Received: by mail-pf1-x443.google.com with SMTP id m9so504284pfh.0 for ; Wed, 08 Jul 2020 22:01:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fpwjVW7Z+irWop7fAETDGc/ua6yC0KP+NMCvyoQB9RI=; b=sJK6emFsSGA7psgbjAjtw3CRMaGl/+7BOiQ4h4025c9G/rVWUt0A6aJm2gjrW8i7Wy Yrym08TuQl9dY0zvkSbZ2r1/VkMl4GOvHkhCCCatBhYTHgqUtf3X/9W37MpGiTG7Ktqy BbCRqZIA9yjdjCFauiLj1eh/8Zc525Iq225fyNlSNCU3zACQgRcYzKxpgK5hJOf17Juy F/VEaHTOmE4WWQxzVIloHzKMBszVPgWKskOtDFsQo9NG/9EL3K8OFict6ASYJSd0JOfE Wuthn6aw7DFI318hoKqJBVPR0kKzmuVqmDzwrfqlYB1YhNi++hQtjUHpmC8jwlJllPsm X4Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fpwjVW7Z+irWop7fAETDGc/ua6yC0KP+NMCvyoQB9RI=; b=Pn8QDnbd6Iv6KR4jwmkFhLToSWQEp2zsQCHPyAlDdFn2ybxsO8TQTla9/8Z9nyc/rR HBz81t9cGOjQ/yqNA+byuDYi6KP9TQKW9dzLbVdcQ3wVaFb/4cXTwwpUtsk7OVWmmO+t bmMF5DAAmMK9zWWPEoQ5DZUm1X7q/2/ZnOjH1rpVmLBF1o5M/R2HdnfTZ3+O+84ZhdeA M0IjwS9SvpSo8wz80UVJ9H2MKiSLTOorm9OjytkQev/EDPu2vUkgv3CkvM9wJoXaalkq mtP0uuIb+NsWtDOTF4rXzMuubfzme7yx4guChYgC9ZcUE7pynUbSrHPn33hekc4Yz5bY rDbw== X-Gm-Message-State: AOAM533rhgXx6Idv1tCRaznPSfl2WlgBDYFqvSOYZO/EjXxZrVBtHtrO Qr36twputM6MgOw6VanECwJp6A== X-Google-Smtp-Source: ABdhPJzN6OwP8GTvSH4ENnFiwWNlVHQa4IJ6tTaqVk88twX1CJ1jwT8Jvpf9n9tYDT6X1OX3iMcKTA== X-Received: by 2002:a63:e114:: with SMTP id z20mr45873953pgh.300.1594270907500; Wed, 08 Jul 2020 22:01:47 -0700 (PDT) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id h15sm999974pjc.14.2020.07.08.22.01.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2020 22:01:46 -0700 (PDT) From: Bjorn Andersson To: Will Deacon , Robin Murphy , Joerg Roedel , Thierry Reding , Laurentiu Tudor Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jonathan Marek , linux-arm-msm@vger.kernel.org Subject: [PATCH 5/5] iommu/arm-smmu: Setup identity domain for boot mappings Date: Wed, 8 Jul 2020 22:01:45 -0700 Message-Id: <20200709050145.3520931-6-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200709050145.3520931-1-bjorn.andersson@linaro.org> References: <20200709050145.3520931-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org With many Qualcomm platforms not having functional S2CR BYPASS a temporary IOMMU domain, without translation, needs to be allocated in order to allow these memory transactions. Unfortunately the boot loader uses the first few context banks, so rather than overwriting a active bank the last context bank is used and streams are diverted here during initialization. This also performs the readback of SMR registers for the Qualcomm platform, to trigger the mechanism. This is based on prior work by Thierry Reding and Laurentiu Tudor. Signed-off-by: Bjorn Andersson Tested-by: Laurentiu Tudor --- drivers/iommu/arm-smmu-qcom.c | 11 +++++ drivers/iommu/arm-smmu.c | 80 +++++++++++++++++++++++++++++++++-- drivers/iommu/arm-smmu.h | 3 ++ 3 files changed, 90 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c index 86b1917459a4..397df27c1d69 100644 --- a/drivers/iommu/arm-smmu-qcom.c +++ b/drivers/iommu/arm-smmu-qcom.c @@ -26,6 +26,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] = { static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) { unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); + u32 smr; u32 reg; int i; @@ -56,6 +57,16 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) } } + for (i = 0; i < smmu->num_mapping_groups; i++) { + smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); + + if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) { + smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); + smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); + smmu->smrs[i].valid = true; + } + } + return 0; } diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index e2d6c0aaf1ea..a7cb27c1a49e 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -652,7 +652,8 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) } static int arm_smmu_init_domain_context(struct iommu_domain *domain, - struct arm_smmu_device *smmu) + struct arm_smmu_device *smmu, + bool boot_domain) { int irq, start, ret = 0; unsigned long ias, oas; @@ -770,6 +771,15 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, ret = -EINVAL; goto out_unlock; } + + /* + * Use the last context bank for identity mappings during boot, to + * avoid overwriting in-use bank configuration while we're setting up + * the new mappings. + */ + if (boot_domain) + start = smmu->num_context_banks - 1; + ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); if (ret < 0) @@ -1149,7 +1159,10 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct arm_smmu_master_cfg *cfg; struct arm_smmu_device *smmu; + bool free_identity_domain = false; + int idx; int ret; + int i; if (!fwspec || fwspec->ops != &arm_smmu_ops) { dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); @@ -1174,7 +1187,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) return ret; /* Ensure that the domain is finalised */ - ret = arm_smmu_init_domain_context(domain, smmu); + ret = arm_smmu_init_domain_context(domain, smmu, false); if (ret < 0) goto rpm_put; @@ -1190,9 +1203,34 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) goto rpm_put; } + /* Decrement use counter for any references to the identity domain */ + mutex_lock(&smmu->stream_map_mutex); + if (smmu->identity) { + struct arm_smmu_domain *identity = to_smmu_domain(smmu->identity); + + for_each_cfg_sme(cfg, fwspec, i, idx) { + dev_err(smmu->dev, "%s() %#x\n", __func__, smmu->smrs[idx].id); + if (smmu->s2crs[idx].cbndx == identity->cfg.cbndx) { + smmu->num_identity_masters--; + if (smmu->num_identity_masters == 0) + free_identity_domain = true; + } + } + } + mutex_unlock(&smmu->stream_map_mutex); + /* Looks ok, so add the device to the domain */ ret = arm_smmu_domain_add_master(smmu_domain, cfg, fwspec); + /* + * The last stream map to reference the identity domain has been + * overwritten, so it's now okay to free it. + */ + if (free_identity_domain) { + arm_smmu_domain_free(smmu->identity); + smmu->identity = NULL; + } + /* * Setup an autosuspend delay to avoid bouncing runpm state. * Otherwise, if a driver for a suspended consumer device @@ -1922,17 +1960,51 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) int arm_smmu_setup_identity(struct arm_smmu_device *smmu) { + struct device *dev = smmu->dev; + int cbndx = 0xff; + int type = S2CR_TYPE_BYPASS; + int ret; int i; + if (smmu->qcom_bypass_quirk) { + /* Create a IDENTITY domain to use for all inherited streams */ + smmu->identity = arm_smmu_domain_alloc(IOMMU_DOMAIN_IDENTITY); + if (!smmu->identity) { + dev_err(dev, "failed to create identity domain\n"); + return -ENOMEM; + } + + smmu->identity->pgsize_bitmap = smmu->pgsize_bitmap; + smmu->identity->type = IOMMU_DOMAIN_IDENTITY; + smmu->identity->ops = &arm_smmu_ops; + + ret = arm_smmu_init_domain_context(smmu->identity, smmu, true); + if (ret < 0) { + dev_err(dev, "failed to initialize identity domain: %d\n", ret); + return ret; + } + + type = S2CR_TYPE_TRANS; + cbndx = to_smmu_domain(smmu->identity)->cfg.cbndx; + } + for (i = 0; i < smmu->num_mapping_groups; i++) { if (smmu->smrs[i].valid) { - smmu->s2crs[i].type = S2CR_TYPE_BYPASS; + smmu->s2crs[i].type = type; smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; - smmu->s2crs[i].cbndx = 0xff; + smmu->s2crs[i].cbndx = cbndx; smmu->s2crs[i].count++; + + smmu->num_identity_masters++; } } + /* If no mappings where found, free the identiy domain again */ + if (smmu->identity && !smmu->num_identity_masters) { + arm_smmu_domain_free(smmu->identity); + smmu->identity = NULL; + } + return 0; } diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index bcd160d01c53..37257ede86fa 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -321,6 +321,9 @@ struct arm_smmu_device { /* IOMMU core code handle */ struct iommu_device iommu; + struct iommu_domain *identity; + unsigned int num_identity_masters; + bool qcom_bypass_quirk; };