From patchwork Thu Jul 9 20:00:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 11655029 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F012D913 for ; Thu, 9 Jul 2020 20:01:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CC577207FF for ; Thu, 9 Jul 2020 20:01:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="QuD5u3E/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CC577207FF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8DB876EB25; Thu, 9 Jul 2020 20:01:20 +0000 (UTC) X-Original-To: dri-devel@freedesktop.org Delivered-To: dri-devel@freedesktop.org Received: from mail29.static.mailgun.info (mail29.static.mailgun.info [104.130.122.29]) by gabe.freedesktop.org (Postfix) with ESMTPS id F24E76EB24 for ; Thu, 9 Jul 2020 20:01:16 +0000 (UTC) DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1594324879; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=qvFYV5gSdJN7uGe/5cfb+tk9FUbHSiqsuZE2Uf3f6Vs=; b=QuD5u3E/KSS5Ti7l1Rpk+kv2rMo8yy2GjgFxYDVSmZDzBQsEDObYbsCKMk79gEu2rszJ6ySO Ghx/GOnJ8pwGkWlCHABWiSfpedbvaX1IJtF1dUDlBzZE9TTBCjKAlDkiYScZgL9BVkoJQGMy /pvLCOfuJBn3OBkL52eL9PI7uP4= X-Mailgun-Sending-Ip: 104.130.122.29 X-Mailgun-Sid: WyIxOTRiMSIsICJkcmktZGV2ZWxAZnJlZWRlc2t0b3Aub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n12.prod.us-west-2.postgun.com with SMTP id 5f077777f97e988aab47109d (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 09 Jul 2020 20:00:55 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 2931DC4339C; Thu, 9 Jul 2020 20:00:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from akhilpo-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akhilpo) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1BB36C433C6; Thu, 9 Jul 2020 20:00:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1BB36C433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akhilpo@codeaurora.org From: Akhil P Oommen To: freedreno@lists.freedesktop.org Subject: [PATCH v4 1/7] dt-bindings: drm/msm/gpu: Document gpu opp table Date: Fri, 10 Jul 2020 01:30:21 +0530 Message-Id: <1594324828-9571-2-git-send-email-akhilpo@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> References: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, jonathan@marek.ca, saravanak@google.com, linux-arm-msm@vger.kernel.org, smasetty@codeaurora.org, linux-kernel@vger.kernel.org, mka@chromium.org, dri-devel@freedesktop.org, viresh.kumar@linaro.org, sibis@codeaurora.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Sharat Masetty Update documentation to list the gpu opp table bindings including the newly added "opp-peak-kBps" needed for GPU-DDR bandwidth scaling. Signed-off-by: Sharat Masetty Acked-by: Rob Herring Signed-off-by: Akhil P Oommen --- .../devicetree/bindings/display/msm/gpu.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index fd779cd..1af0ff1 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -112,6 +112,34 @@ Example a6xx (with GMU): interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; interconnect-names = "gfx-mem"; + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = ; + opp-peak-kBps = <5412000>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = ; + opp-peak-kBps = <3072000>; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = ; + opp-peak-kBps = <3072000>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = ; + opp-peak-kBps = <1804000>; + }; + }; + qcom,gmu = <&gmu>; zap-shader { From patchwork Thu Jul 9 20:00:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 11655035 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5D58F739 for ; Thu, 9 Jul 2020 20:01:47 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3A6D1207DD for ; Thu, 9 Jul 2020 20:01:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="DOMg4Jn8" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3A6D1207DD Authentication-Results: mail.kernel.org; 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spf=none smtp.mailfrom=akhilpo@codeaurora.org From: Akhil P Oommen To: freedreno@lists.freedesktop.org Subject: [PATCH v4 2/7] drm: msm: a6xx: send opp instead of a frequency Date: Fri, 10 Jul 2020 01:30:22 +0530 Message-Id: <1594324828-9571-3-git-send-email-akhilpo@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> References: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, jonathan@marek.ca, saravanak@google.com, linux-arm-msm@vger.kernel.org, smasetty@codeaurora.org, linux-kernel@vger.kernel.org, mka@chromium.org, dri-devel@freedesktop.org, viresh.kumar@linaro.org, sibis@codeaurora.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Sharat Masetty This patch changes the plumbing to send the devfreq recommended opp rather than the frequency. Also consolidate and rearrange the code in a6xx to set the GPU frequency and the icc vote in preparation for the upcoming changes for GPU->DDR scaling votes. Signed-off-by: Sharat Masetty Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 73 ++++++++++++++++------------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/msm_gpu.c | 3 +- drivers/gpu/drm/msm/msm_gpu.h | 3 +- 4 files changed, 38 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 21e77d6..233afea 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -103,17 +103,31 @@ bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); } -static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) +void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) { - struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); - struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; - struct msm_gpu *gpu = &adreno_gpu->base; - int ret; + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; + u32 perf_index; + unsigned long gpu_freq; + int ret = 0; + + gpu_freq = dev_pm_opp_get_freq(opp); + + if (gpu_freq == gmu->freq) + return; + + for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) + if (gpu_freq == gmu->gpu_freqs[perf_index]) + break; + + gmu->current_perf_index = perf_index; + gmu->freq = gmu->gpu_freqs[perf_index]; gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, - ((3 & 0xf) << 28) | index); + ((3 & 0xf) << 28) | perf_index); /* * Send an invalid index as a vote for the bus bandwidth and let the @@ -136,38 +150,6 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); } -void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq) -{ - struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - struct a6xx_gmu *gmu = &a6xx_gpu->gmu; - u32 perf_index = 0; - - if (freq == gmu->freq) - return; - - for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) - if (freq == gmu->gpu_freqs[perf_index]) - break; - - gmu->current_perf_index = perf_index; - gmu->freq = gmu->gpu_freqs[perf_index]; - - /* - * This can get called from devfreq while the hardware is idle. Don't - * bring up the power if it isn't already active - */ - if (pm_runtime_get_if_in_use(gmu->dev) == 0) - return; - - if (gmu->legacy) - __a6xx_gmu_set_freq(gmu, perf_index); - else - a6xx_hfi_set_freq(gmu, perf_index); - - pm_runtime_put(gmu->dev); -} - unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -839,6 +821,19 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) a6xx_gmu_rpmh_off(gmu); } +static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) +{ + struct dev_pm_opp *gpu_opp; + unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; + + gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); + if (IS_ERR_OR_NULL(gpu_opp)) + return; + + a6xx_gmu_set_freq(gpu, gpu_opp); + dev_pm_opp_put(gpu_opp); +} + int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; @@ -899,7 +894,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) /* Set the GPU to the current freq */ if (gmu->legacy) - __a6xx_gmu_set_freq(gmu, gmu->current_perf_index); + a6xx_gmu_set_initial_freq(gpu, gmu); else a6xx_hfi_set_freq(gmu, gmu->current_perf_index); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 7239b8b..03ba60d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -63,7 +63,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); -void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq); +void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp); unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index a22d306..82eb727 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -13,7 +13,6 @@ #include #include -#include #include #include #include @@ -34,7 +33,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq, return PTR_ERR(opp); if (gpu->funcs->gpu_set_freq) - gpu->funcs->gpu_set_freq(gpu, (u64)*freq); + gpu->funcs->gpu_set_freq(gpu, opp); else clk_set_rate(gpu->core_clk, *freq); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 429cb40..0db117a 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -9,6 +9,7 @@ #include #include +#include #include #include "msm_drv.h" @@ -61,7 +62,7 @@ struct msm_gpu_funcs { struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu); int (*gpu_state_put)(struct msm_gpu_state *state); unsigned long (*gpu_get_freq)(struct msm_gpu *gpu); - void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq); + void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp); struct msm_gem_address_space *(*create_address_space) (struct msm_gpu *gpu, struct platform_device *pdev); }; From patchwork Thu Jul 9 20:00:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 11655053 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1626A739 for ; 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Thu, 9 Jul 2020 20:00:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 381B0C433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akhilpo@codeaurora.org From: Akhil P Oommen To: freedreno@lists.freedesktop.org Subject: [PATCH v4 3/7] drm: msm: a6xx: set gpu freq through hfi Date: Fri, 10 Jul 2020 01:30:23 +0530 Message-Id: <1594324828-9571-4-git-send-email-akhilpo@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> References: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, jonathan@marek.ca, saravanak@google.com, linux-arm-msm@vger.kernel.org, smasetty@codeaurora.org, linux-kernel@vger.kernel.org, mka@chromium.org, dri-devel@freedesktop.org, viresh.kumar@linaro.org, sibis@codeaurora.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Newer targets support changing gpu frequency through HFI. So use that wherever supported instead of the legacy method. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 233afea..b547339 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -121,6 +121,12 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) if (gpu_freq == gmu->gpu_freqs[perf_index]) break; + if (!gmu->legacy) { + a6xx_hfi_set_freq(gmu, gmu->current_perf_index); + icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); + return; + } + gmu->current_perf_index = perf_index; gmu->freq = gmu->gpu_freqs[perf_index]; @@ -893,10 +899,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) enable_irq(gmu->hfi_irq); /* Set the GPU to the current freq */ - if (gmu->legacy) - a6xx_gmu_set_initial_freq(gpu, gmu); - else - a6xx_hfi_set_freq(gmu, gmu->current_perf_index); + a6xx_gmu_set_initial_freq(gpu, gmu); /* * "enable" the GX power domain which won't actually do anything but it From patchwork Thu Jul 9 20:00:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 11655045 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D4718739 for ; Thu, 9 Jul 2020 20:01:58 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B0F93207DA for ; Thu, 9 Jul 2020 20:01:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="J9XRO5vA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B0F93207DA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: mail.kernel.org; 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spf=none smtp.mailfrom=akhilpo@codeaurora.org From: Akhil P Oommen To: freedreno@lists.freedesktop.org Subject: [PATCH v4 4/7] drm: msm: a6xx: use dev_pm_opp_set_bw to scale DDR Date: Fri, 10 Jul 2020 01:30:24 +0530 Message-Id: <1594324828-9571-5-git-send-email-akhilpo@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> References: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, jonathan@marek.ca, saravanak@google.com, linux-arm-msm@vger.kernel.org, smasetty@codeaurora.org, linux-kernel@vger.kernel.org, mka@chromium.org, dri-devel@freedesktop.org, viresh.kumar@linaro.org, sibis@codeaurora.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Sharat Masetty This patches replaces the previously used static DDR vote and uses dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling GPU frequency. Also since the icc path voting is handled completely in the opp driver, remove the icc_path handle and its usage in the drm driver. Signed-off-by: Sharat Masetty Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index b547339..6fbfd7d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -123,7 +123,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) if (!gmu->legacy) { a6xx_hfi_set_freq(gmu, gmu->current_perf_index); - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); + dev_pm_opp_set_bw(&gpu->pdev->dev, opp); return; } @@ -149,11 +149,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) if (ret) dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); - /* - * Eventually we will want to scale the path vote with the frequency but - * for now leave it at max so that the performance is nominal. - */ - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); + dev_pm_opp_set_bw(&gpu->pdev->dev, opp); } unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) @@ -840,6 +836,19 @@ static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) dev_pm_opp_put(gpu_opp); } +static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) +{ + struct dev_pm_opp *gpu_opp; + unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; + + gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); + if (IS_ERR_OR_NULL(gpu_opp)) + return; + + dev_pm_opp_set_bw(&gpu->pdev->dev, gpu_opp); + dev_pm_opp_put(gpu_opp); +} + int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; @@ -864,7 +873,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) } /* Set the bus quota to a reasonable value for boot */ - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072)); + a6xx_gmu_set_initial_bw(gpu, gmu); /* Enable the GMU interrupt */ gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); @@ -1040,7 +1049,7 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) a6xx_gmu_shutdown(gmu); /* Remove the bus vote */ - icc_set_bw(gpu->icc_path, 0, 0); + dev_pm_opp_set_bw(&gpu->pdev->dev, NULL); /* * Make sure the GX domain is off before turning off the GMU (CX) From patchwork Thu Jul 9 20:00:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 11655047 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D59C2739 for ; Thu, 9 Jul 2020 20:02:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B37E1207DF for ; Thu, 9 Jul 2020 20:02:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="hp/Q0cih" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B37E1207DF Authentication-Results: mail.kernel.org; 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Thu, 09 Jul 2020 20:01:14 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 9C97DC43395; Thu, 9 Jul 2020 20:01:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=ham autolearn_force=no version=3.4.0 Received: from akhilpo-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akhilpo) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5BC24C433CA; Thu, 9 Jul 2020 20:01:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5BC24C433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akhilpo@codeaurora.org From: Akhil P Oommen To: freedreno@lists.freedesktop.org Subject: [PATCH v4 5/7] arm64: dts: qcom: SDM845: Enable GPU DDR bw scaling Date: Fri, 10 Jul 2020 01:30:25 +0530 Message-Id: <1594324828-9571-6-git-send-email-akhilpo@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> References: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, jonathan@marek.ca, saravanak@google.com, linux-arm-msm@vger.kernel.org, smasetty@codeaurora.org, linux-kernel@vger.kernel.org, mka@chromium.org, dri-devel@freedesktop.org, viresh.kumar@linaro.org, sibis@codeaurora.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Sharat Masetty This patch adds the interconnects property for the gpu node and the opp-peak-kBps property to the opps of the gpu opp table. This should help enable DDR bandwidth scaling dynamically and proportionally to the GPU frequency. Signed-off-by: Sharat Masetty Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 8eb5a31..5e9561a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3515,42 +3515,51 @@ qcom,gmu = <&gmu>; + interconnects = <&mem_noc MASTER_GFX3D &mem_noc SLAVE_EBI1>; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-710000000 { opp-hz = /bits/ 64 <710000000>; opp-level = ; + opp-peak-kBps = <7216000>; }; opp-675000000 { opp-hz = /bits/ 64 <675000000>; opp-level = ; + opp-peak-kBps = <7216000>; }; opp-596000000 { opp-hz = /bits/ 64 <596000000>; opp-level = ; + opp-peak-kBps = <6220000>; }; opp-520000000 { opp-hz = /bits/ 64 <520000000>; opp-level = ; + opp-peak-kBps = <6220000>; }; opp-414000000 { opp-hz = /bits/ 64 <414000000>; opp-level = ; + opp-peak-kBps = <4068000>; }; opp-342000000 { opp-hz = /bits/ 64 <342000000>; opp-level = ; + opp-peak-kBps = <2724000>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; opp-level = ; + opp-peak-kBps = <1648000>; }; }; }; From patchwork Thu Jul 9 20:00:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 11655043 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2FCBE739 for ; Thu, 9 Jul 2020 20:01:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D6FF207DA for ; Thu, 9 Jul 2020 20:01:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="qDI2fSF4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0D6FF207DA Authentication-Results: mail.kernel.org; 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spf=none smtp.mailfrom=akhilpo@codeaurora.org From: Akhil P Oommen To: freedreno@lists.freedesktop.org Subject: [PATCH v4 6/7] arm64: dts: qcom: sc7180: Add interconnects property for GPU Date: Fri, 10 Jul 2020 01:30:26 +0530 Message-Id: <1594324828-9571-7-git-send-email-akhilpo@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> References: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, jonathan@marek.ca, saravanak@google.com, linux-arm-msm@vger.kernel.org, smasetty@codeaurora.org, linux-kernel@vger.kernel.org, mka@chromium.org, dri-devel@freedesktop.org, viresh.kumar@linaro.org, sibis@codeaurora.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Sharat Masetty This patch adds the interconnects property to the GPU node. This enables the GPU->DDR path bandwidth voting. Signed-off-by: Sharat Masetty Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 31b9217..a567297 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1470,6 +1470,8 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; From patchwork Thu Jul 9 20:00:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 11655055 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1F4D2913 for ; Thu, 9 Jul 2020 20:02:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F0420207DF for ; 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Thu, 9 Jul 2020 20:01:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9DA52C433A1 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akhilpo@codeaurora.org From: Akhil P Oommen To: freedreno@lists.freedesktop.org Subject: [PATCH v4 7/7] arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp Date: Fri, 10 Jul 2020 01:30:27 +0530 Message-Id: <1594324828-9571-8-git-send-email-akhilpo@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> References: <1594324828-9571-1-git-send-email-akhilpo@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, jonathan@marek.ca, saravanak@google.com, linux-arm-msm@vger.kernel.org, smasetty@codeaurora.org, linux-kernel@vger.kernel.org, mka@chromium.org, dri-devel@freedesktop.org, viresh.kumar@linaro.org, sibis@codeaurora.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Sharat Masetty Add opp-peak-kBps bindings to the GPU opp table, listing the peak GPU -> DDR bandwidth requirement for each opp level. This will be used to scale the DDR bandwidth along with the GPU frequency dynamically. Signed-off-by: Sharat Masetty Reviewed-by: Matthias Kaehlcke Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a567297..8567e9e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1478,36 +1478,43 @@ opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-level = ; + opp-peak-kBps = <8532000>; }; opp-650000000 { opp-hz = /bits/ 64 <650000000>; opp-level = ; + opp-peak-kBps = <7216000>; }; opp-565000000 { opp-hz = /bits/ 64 <565000000>; opp-level = ; + opp-peak-kBps = <5412000>; }; opp-430000000 { opp-hz = /bits/ 64 <430000000>; opp-level = ; + opp-peak-kBps = <5412000>; }; opp-355000000 { opp-hz = /bits/ 64 <355000000>; opp-level = ; + opp-peak-kBps = <3072000>; }; opp-267000000 { opp-hz = /bits/ 64 <267000000>; opp-level = ; + opp-peak-kBps = <3072000>; }; opp-180000000 { opp-hz = /bits/ 64 <180000000>; opp-level = ; + opp-peak-kBps = <1804000>; }; }; };