From patchwork Thu Jul 9 23:19:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11655283 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 93B5A60D for ; Thu, 9 Jul 2020 23:20:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 756B520786 for ; Thu, 9 Jul 2020 23:20:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="YDfq/PKy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726725AbgGIXUJ (ORCPT ); Thu, 9 Jul 2020 19:20:09 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:34582 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726446AbgGIXUI (ORCPT ); Thu, 9 Jul 2020 19:20:08 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NK3aE053728; Thu, 9 Jul 2020 18:20:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336803; bh=bj6nkinvxoUBEjdlWJZuVGG0GefCFyrmKPpAuJeavTc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=YDfq/PKytLFJRXryu9Ga+CbOjFfCBU4OF2i2KTEzETIPvlxnZRW4CGS2Qf66ziQuL soAcyv4iUOc2fg2ilND/xv7hdCl+ZL63wSmc0E/BwZSrMhe5XiXIkyCLi2qY9kl/1N 8Eb9OpCgfhMBgEJFuDNnCPUfH/HLiU0/9aP5AA9I= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK3HK098998; Thu, 9 Jul 2020 18:20:03 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:03 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:02 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK2PF118701; Thu, 9 Jul 2020 18:20:02 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NK2d5124356; Thu, 9 Jul 2020 18:20:02 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 01/13] ARM: dts: omap4: Add timer_sys_ck clocks for timers Date: Thu, 9 Jul 2020 18:19:42 -0500 Message-ID: <20200709231954.1973-2-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The commit 1c7de9f27a65 ("clk: ti: omap4: cleanup unnecessary clock aliases") has cleaned up all timer_sys_ck clock aliases and retained only the timer_32k_ck clock alias. The OMAP clocksource timer driver though still uses this clock alias when reconfiguring the parent clock source for the timer functional clocks, so add these clocks to all the timer nodes. This is required by the OMAP remoteproc driver to successfully acquire a timer and configure the source clock to be driven from timer_sys_ck clock. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap4-l4-abe.dtsi | 20 ++++++++++------- arch/arm/boot/dts/omap4-l4.dtsi | 35 +++++++++++++++++------------ 2 files changed, 33 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/omap4-l4-abe.dtsi b/arch/arm/boot/dts/omap4-l4-abe.dtsi index a6feb201c569..b2cf5f41e222 100644 --- a/arch/arm/boot/dts/omap4-l4-abe.dtsi +++ b/arch/arm/boot/dts/omap4-l4-abe.dtsi @@ -333,8 +333,9 @@ timer5: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x00000000 0x80>, <0x49038000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>, + <&syc_clk_div_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-dsp; }; @@ -363,8 +364,9 @@ timer6: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x00000000 0x80>, <0x4903a000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>, + <&syc_clk_div_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-dsp; }; @@ -393,8 +395,9 @@ timer7: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x00000000 0x80>, <0x4903c000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>, + <&syc_clk_div_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-dsp; }; @@ -423,8 +426,9 @@ timer8: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x00000000 0x80>, <0x4903e000 0x80>; - clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>, + <&syc_clk_div_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-pwm; ti,timer-dsp; diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi index fcc52121ff09..bf90a683d7b8 100644 --- a/arch/arm/boot/dts/omap4-l4.dtsi +++ b/arch/arm/boot/dts/omap4-l4.dtsi @@ -1163,8 +1163,9 @@ SYSC_OMAP2_SOFTRESET | timer1: timer@0 { compatible = "ti,omap3430-timer"; reg = <0x0 0x80>; - clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-alwon; }; @@ -1439,8 +1440,9 @@ SYSC_OMAP2_SOFTRESET | timer2: timer@0 { compatible = "ti,omap3430-timer"; reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -1466,8 +1468,9 @@ target-module@34000 { /* 0x48034000, ap 7 04.0 */ timer3: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -1493,8 +1496,9 @@ target-module@36000 { /* 0x48036000, ap 9 0e.0 */ timer4: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -1520,8 +1524,9 @@ target-module@3e000 { /* 0x4803e000, ap 11 08.0 */ timer9: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-pwm; }; @@ -1954,8 +1959,9 @@ SYSC_OMAP2_SOFTRESET | timer10: timer@0 { compatible = "ti,omap3430-timer"; reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-pwm; }; @@ -1982,8 +1988,9 @@ target-module@88000 { /* 0x48088000, ap 45 2e.0 */ timer11: timer@0 { compatible = "ti,omap4430-timer"; reg = <0x0 0x80>; - clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>, + <&sys_clkin_ck>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-pwm; }; From patchwork Thu Jul 9 23:19:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11655295 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 80A5B739 for ; Thu, 9 Jul 2020 23:20:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E71D2078B for ; Thu, 9 Jul 2020 23:20:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="qsqkk/y7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726446AbgGIXUO (ORCPT ); Thu, 9 Jul 2020 19:20:14 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:47042 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726828AbgGIXUN (ORCPT ); Thu, 9 Jul 2020 19:20:13 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NK4r7038453; Thu, 9 Jul 2020 18:20:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336804; bh=c0U/6UXwkjm96QgVwEXr+Y99qTURmUnIxiiCuECGvik=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qsqkk/y7uOV3in98PC1/xYuP038z7MhEE6m0wjq3v8BEqWU2xLPWJCFxWAwRW9dFt YYqL44+lgodeAhBSV5bYznK9BSX3/77m5kX5nZWj/eaRBsbBEJVDAPsdmfc3YU1Utw TpfhX3qYKdYOQ9nuf3uENGagEUoylp9qP5N4Ot8w= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 069NK4Yo011912 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 9 Jul 2020 18:20:04 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:04 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:04 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK4B3119019; Thu, 9 Jul 2020 18:20:04 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NK3qT124367; Thu, 9 Jul 2020 18:20:03 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 02/13] ARM: dts: omap5: Add timer_sys_ck clocks for timers Date: Thu, 9 Jul 2020 18:19:43 -0500 Message-ID: <20200709231954.1973-3-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The commit d41e53040926 ("clk: ti: omap5: cleanup unnecessary clock aliases") has cleaned up all timer_sys_ck clock aliases and retained only the timer_32k_ck clock alias. The OMAP clocksource timer driver though still uses this clock alias when reconfiguring the parent clock source for the timer functional clocks, so add these clocks to all the timer nodes except for the always-on timers 1 and 12. This is required by the OMAP remoteproc driver to successfully acquire a timer and configure the source clock to be driven from timer_sys_ck clock. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap5-l4-abe.dtsi | 20 ++++++++++------- arch/arm/boot/dts/omap5-l4.dtsi | 35 +++++++++++++++++------------ 2 files changed, 33 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/omap5-l4-abe.dtsi b/arch/arm/boot/dts/omap5-l4-abe.dtsi index bafd6adf9f45..25b7fce8de2d 100644 --- a/arch/arm/boot/dts/omap5-l4-abe.dtsi +++ b/arch/arm/boot/dts/omap5-l4-abe.dtsi @@ -298,8 +298,9 @@ timer5: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>, <0x49038000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>, + <&dss_syc_gfclk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-dsp; ti,timer-pwm; @@ -329,8 +330,9 @@ timer6: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>, <0x4903a000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>, + <&dss_syc_gfclk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-dsp; ti,timer-pwm; @@ -360,8 +362,9 @@ timer7: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>, <0x4903c000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>, + <&dss_syc_gfclk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-dsp; }; @@ -390,8 +393,9 @@ timer8: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>, <0x4903e000 0x80>; - clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>, + <&dss_syc_gfclk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-dsp; ti,timer-pwm; diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index 5217805bf126..683394d1e4d6 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -1082,8 +1082,9 @@ target-module@32000 { /* 0x48032000, ap 5 3e.0 */ timer2: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -1109,8 +1110,9 @@ target-module@34000 { /* 0x48034000, ap 7 46.0 */ timer3: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -1136,8 +1138,9 @@ target-module@36000 { /* 0x48036000, ap 9 4e.0 */ timer4: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -1163,8 +1166,9 @@ target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ timer9: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-pwm; }; @@ -1730,8 +1734,9 @@ target-module@86000 { /* 0x48086000, ap 41 5e.0 */ timer10: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-pwm; }; @@ -1758,8 +1763,9 @@ target-module@88000 { /* 0x48088000, ap 43 66.0 */ timer11: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-pwm; }; @@ -2387,8 +2393,9 @@ timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ timer1: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>, + <&sys_clkin>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-alwon; }; From patchwork Thu Jul 9 23:19:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11655291 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D9F8560D for ; Thu, 9 Jul 2020 23:20:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C04B32078B for ; Thu, 9 Jul 2020 23:20:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="vB6whN1e" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726831AbgGIXUN (ORCPT ); Thu, 9 Jul 2020 19:20:13 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49288 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726778AbgGIXUM (ORCPT ); Thu, 9 Jul 2020 19:20:12 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NK4IW122916; Thu, 9 Jul 2020 18:20:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336804; bh=zGwp7kf/6vGSBcqJKvT87gomlb9Jc7VbFtUnbKFhyuI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vB6whN1ey/S1kK6AsIww0TVF5zNxwP6LkFTG3Xsk/+LV1nITqJUR7PIA7rDuBYwal 9+sJifSyUjgR021HRdKFMKoV1n3y0NHI6Mm5/Byhzo6l/tYalGv7oh6JlW6GXj4czh UvuX0PoLTiLK+e/hFrckAt5/O9qZ03ezPFgY4UAQ= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 069NK4go023734 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 9 Jul 2020 18:20:04 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:04 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:04 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK3oX118932; Thu, 9 Jul 2020 18:20:04 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NK3wx124406; Thu, 9 Jul 2020 18:20:03 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 03/13] ARM: dts: omap4: Update the DSP node Date: Thu, 9 Jul 2020 18:19:44 -0500 Message-ID: <20200709231954.1973-4-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The compatible property for the DSP node is updated to match the OMAP remoteproc bindings. The node is moved from the soc node to the ocp node to better reflect the connectivity from MPU side. The node is updated with the 'ti,bootreg', 'clocks', 'resets', 'iommus', 'mboxes' and 'firmware' properties. Note that the node does not have any 'reg' or 'reg-names' properties since it doesn't have any L2 RAM memory, but only Unicaches. The node is disabled for now, and should be enabled as per the individual product configuration in the corresponding board dts files. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap4.dtsi | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 4400f5f8e099..8f6b38bb5753 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -106,10 +106,6 @@ mpu { sram = <&ocmcram>; }; - dsp { - compatible = "ti,omap3-c64"; - }; - iva { compatible = "ti,ivahd"; ti,hwmods = "iva"; @@ -277,6 +273,17 @@ emif2: emif@4d000000 { hw-caps-temp-alert; }; + dsp: dsp { + compatible = "ti,omap4-dsp"; + ti,bootreg = <&scm_conf 0x304 0>; + iommus = <&mmu_dsp>; + resets = <&prm_tesla 0>; + clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; + firmware-name = "omap4-dsp-fw.xe64T"; + mboxes = <&mailbox &mbox_dsp>; + status = "disabled"; + }; + aes1_target: target-module@4b501000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x4b501080 0x4>, From patchwork Thu Jul 9 23:19:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11655285 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3258460D for ; Thu, 9 Jul 2020 23:20:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 103152078B for ; Thu, 9 Jul 2020 23:20:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="pP0UbUwv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726774AbgGIXUK (ORCPT ); Thu, 9 Jul 2020 19:20:10 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49280 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726446AbgGIXUK (ORCPT ); Thu, 9 Jul 2020 19:20:10 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NK5HP122925; Thu, 9 Jul 2020 18:20:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336806; bh=bTbO7tKvhum5luzqsKRZJs6tS+jmpYvKHI4pzaAiS9w=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pP0UbUwvvLDPY+nqCHOEHtvohVoePS+OwAkOUoyX6rJxzRFcMg6k7JmHawiBeRCTA eGfv2iSmVdR1o0gpk04PhHTZb6X3iezWPPuDIuClLf4z91DoYKQvQaOwdRb5dxbgj+ F+s6WRTvQ7hZmLkPY8Jjnh2ETfvS32w0CTU/pPgk= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK5Sg099173; Thu, 9 Jul 2020 18:20:05 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:04 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:04 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK43s052548; Thu, 9 Jul 2020 18:20:04 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NK4t5124425; Thu, 9 Jul 2020 18:20:04 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 04/13] ARM: dts: omap4: Add IPU DT node Date: Thu, 9 Jul 2020 18:19:45 -0500 Message-ID: <20200709231954.1973-5-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The DT node for the Dual-Cortex M3 IPU processor sub-system has been added for OMAP4 SoCs. The L2RAM memory region information has been added to the node through the 'reg' and 'reg-names' properties. The node has the 'iommus', 'clocks', 'resets', 'mboxes' and 'firmware' properties also added, and is disabled for now. It should be enabled as per the individual product configuration in the corresponding board dts files. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap4.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 8f6b38bb5753..4928951ad9db 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -284,6 +284,18 @@ dsp: dsp { status = "disabled"; }; + ipu: ipu@55020000 { + compatible = "ti,omap4-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu>; + resets = <&prm_core 0>, <&prm_core 1>; + clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>; + firmware-name = "omap4-ipu-fw.xem3"; + mboxes = <&mailbox &mbox_ipu>; + status = "disabled"; + }; + aes1_target: target-module@4b501000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x4b501080 0x4>, From patchwork Thu Jul 9 23:19:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11655293 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6294513B6 for ; Thu, 9 Jul 2020 23:20:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3F66C2078B for ; Thu, 9 Jul 2020 23:20:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="yFoI9KYV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726836AbgGIXUN (ORCPT ); Thu, 9 Jul 2020 19:20:13 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:47040 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726446AbgGIXUM (ORCPT ); Thu, 9 Jul 2020 19:20:12 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NK6dS038462; Thu, 9 Jul 2020 18:20:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336806; bh=4NEaJ+o/Rdfi/1ONnr+25cH1gYQsbvGjOaeF9dyNuSg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yFoI9KYVaPhM71Uob3JJvXvt56aE7h4B63n5YX0jRt/OsS7X9gU3N2Q6w8oXVasND TjtRdgoPKgKwwgaJh6qn68a5zOvZ4Q27FjA9dJgkGJpJyk7J1SuBWxjmDsvM+pFWJN kP0yXE/MvGIB2YnUxnT6lZHh7w2pvJV+fuiQMu7c= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 069NK5BN051495 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 9 Jul 2020 18:20:06 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:05 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:05 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK5Ms095981; Thu, 9 Jul 2020 18:20:05 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NK5us124429; Thu, 9 Jul 2020 18:20:05 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 05/13] ARM: dts: omap4: Add aliases for rproc nodes Date: Thu, 9 Jul 2020 18:19:46 -0500 Message-ID: <20200709231954.1973-6-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add aliases for the DSP and IPU remoteproc processor nodes common to all OMAP4 boards. The aliases uses the stem "rproc". The aliases can be overridden, if needed, in the respective board files. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap4.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 4928951ad9db..3fd26b22c4f3 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -26,6 +26,8 @@ aliases { serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; + rproc0 = &dsp; + rproc1 = &ipu; }; cpus { From patchwork Thu Jul 9 23:19:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11655287 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE257739 for ; Thu, 9 Jul 2020 23:20:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C59882080D for ; Thu, 9 Jul 2020 23:20:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="sEEFG/7g" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726821AbgGIXUM (ORCPT ); Thu, 9 Jul 2020 19:20:12 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49290 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726793AbgGIXUL (ORCPT ); Thu, 9 Jul 2020 19:20:11 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NK6Og122930; Thu, 9 Jul 2020 18:20:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336806; bh=CNBtCJ1QxYrYPVuB3zh0QajQVwCm8p+F9zhXyfSPlEI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sEEFG/7g8zTe4Q4neAkITmtjd6ZijNs2c194Rlt7Smbc1cYIrA5qhB1yB11lMSbFg nDs8+mIPK2L0c1TIvKZm4Bs3hUEocxRlj7f3TKs+pGOFE2uR16gHAMB4Zt5uc5LaIA p45coctb/QSIGQq003vofMvOjfN/7l3wh9Vz916I= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK6PG099341; Thu, 9 Jul 2020 18:20:06 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:06 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:06 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK6s1096031; Thu, 9 Jul 2020 18:20:06 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NK6tx124433; Thu, 9 Jul 2020 18:20:06 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 06/13] ARM: dts: omap4-panda-common: Add CMA pools and enable IPU & DSP Date: Thu, 9 Jul 2020 18:19:47 -0500 Message-ID: <20200709231954.1973-7-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The CMA reserved memory nodes have been added for the IPU and DSP remoteproc devices on all the OMAP4-based Panda boards. These nodes are assigned to the respective rproc device nodes, and both the IPU and DSP remote processors are enabled for all these boards. The current CMA pools and sizes are defined statically for each device. The starting addresses are fixed to meet current dependencies on the remote processor firmwares, and will go away when the remote-side code has been improved to gather this information runtime during its initialization. An associated pair of the rproc node and its CMA node can be disabled later on if there is no use-case defined to use that remote processor. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap4-panda-common.dtsi | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 55ea8b6189af..ef79028fc95f 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -12,6 +12,26 @@ memory@80000000 { reg = <0x80000000 0x40000000>; /* 1 GB */ }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dsp_memory_region: dsp-memory@98000000 { + compatible = "shared-dma-pool"; + reg = <0x98000000 0x800000>; + reusable; + status = "okay"; + }; + + ipu_memory_region: ipu-memory@98800000 { + compatible = "shared-dma-pool"; + reg = <0x98800000 0x7000000>; + reusable; + status = "okay"; + }; + }; + chosen { stdout-path = &uart3; }; @@ -571,3 +591,13 @@ hdmi_out: endpoint { }; }; }; + +&dsp { + status = "okay"; + memory-region = <&dsp_memory_region>; +}; + +&ipu { + status = "okay"; + memory-region = <&ipu_memory_region>; +}; From patchwork Thu Jul 9 23:19:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11655299 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F69913B6 for ; Thu, 9 Jul 2020 23:20:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 75EDD2064B for ; Thu, 9 Jul 2020 23:20:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xQFv0l7E" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726848AbgGIXUQ (ORCPT ); Thu, 9 Jul 2020 19:20:16 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49312 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726852AbgGIXUP (ORCPT ); Thu, 9 Jul 2020 19:20:15 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NK7px122934; Thu, 9 Jul 2020 18:20:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336807; bh=N+YPQiYfbFNBgXuAu/fQKZpj4xm9HZyt3OSvcyZWSpc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xQFv0l7EnEZq8iUhXRPo+XXw0aUUqUkTtZF9D9cEpsMvJxcwuCWncWK3FJo397xgo S4pYXTIT2xx5qXa4f2Ew5aKLHX6pp4vz8ghBfS/31LbRka2JZ3ZO5A97Ny7xQf1EdU SwDReNJTsfAuY9XUzr6KGCLnga3SvF1qsTmiuKy0= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 069NK75S012024 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 9 Jul 2020 18:20:07 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:06 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:06 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK6Y7096058; Thu, 9 Jul 2020 18:20:06 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NK6CO124440; Thu, 9 Jul 2020 18:20:06 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 07/13] ARM: dts: omap4-panda-common:: Add system timers to DSP and IPU Date: Thu, 9 Jul 2020 18:19:48 -0500 Message-ID: <20200709231954.1973-8-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The BIOS System Tick timers have been added for the IPU and DSP remoteproc devices on all the OMAP4-based Panda boards. The following DMTimers are chosen: IPU : GPT3 (SMP-mode) DSP : GPT5 IPU has two Cortex-M3 processors, and is currently expected to be running in SMP-mode, so only a single timer suffices to provide the BIOS tick timer. An additional timer should be added for the second processor in IPU if it were to be run in non-SMP mode. The timer value also needs to be unique from the ones used by other processors so that they can be run simultaneously. The timers are optional, but are mandatory to support device management features such as power management and watchdog support. The above are added to successfully boot and execute firmware images configured with the respective timers, images that use internal processor subsystem timers are not affected. The timers can be changed or removed as per the system integration needs, alongside equivalent changes on the firmware side. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap4-panda-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index ef79028fc95f..db0b7e9264f9 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -595,9 +595,11 @@ hdmi_out: endpoint { &dsp { status = "okay"; memory-region = <&dsp_memory_region>; + ti,timers = <&timer5>; }; &ipu { status = "okay"; memory-region = <&ipu_memory_region>; + ti,timers = <&timer3>; }; From patchwork Thu Jul 9 23:19:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11655289 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 83FDF13B6 for ; Thu, 9 Jul 2020 23:20:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6BC9F2078B for ; Thu, 9 Jul 2020 23:20:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="RlLmUo9a" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726793AbgGIXUM (ORCPT ); Thu, 9 Jul 2020 19:20:12 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:34592 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726809AbgGIXUM (ORCPT ); Thu, 9 Jul 2020 19:20:12 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NK763053748; Thu, 9 Jul 2020 18:20:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336807; bh=UgAdMugjQH9zepDiXJKzHbCjKp+TW08nB/thQHWUeAg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RlLmUo9aScgSG3Ri0j6KhzcZPrgR9XrEnJEFBnKjUZx50rErm/CUkKgckgzKohYjb lZV2cEnlaSIa++NYIXRRl63YyTwTbkgnEpAeiOSnQfzgGw+9KiR4Q+zfxl5y27fhEd 3+HASQx8S7PewtcTqK9YTO9q8enqBTvfHm4WrJ2c= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 069NK7Tx051608 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 9 Jul 2020 18:20:07 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:07 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:07 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK7ol096085; Thu, 9 Jul 2020 18:20:07 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NK7Nj124447; Thu, 9 Jul 2020 18:20:07 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 08/13] ARM: dts: omap5: Add DSP and IPU nodes Date: Thu, 9 Jul 2020 18:19:49 -0500 Message-ID: <20200709231954.1973-9-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org OMAP5, like OMAP4, also has two remote processor subsystems, DSP and IPU. The IPU subsystem though has dual Cortex-M4 processors instead of the dual Cortex-M3 processors in OMAP4, but otherwise has almost the same set of features. Add the DT nodes for these two processor sub-systems for all OMAP5 SoCs. The nodes have the 'iommus', 'clocks', 'resets', 'firmware' and 'mboxes' properties added, and are disabled for now. The IPU node has its L2 RAM memory specified through the 'reg' and 'reg-names' properties. The DSP node doesn't have these since it doesn't have any L2 RAM memories, but has an additional 'ti,bootreg' property instead as it has a specific boot register that needs to be programmed for booting. These nodes should be enabled as per the individual product configuration in the corresponding board dts files. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap5.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index fb889c5b00c9..116150ded018 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -216,6 +216,29 @@ mmu_ipu: mmu@0 { }; }; + dsp: dsp { + compatible = "ti,omap5-dsp"; + ti,bootreg = <&scm_conf 0x304 0>; + iommus = <&mmu_dsp>; + resets = <&prm_dsp 0>; + clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; + firmware-name = "omap5-dsp-fw.xe64T"; + mboxes = <&mailbox &mbox_dsp>; + status = "disabled"; + }; + + ipu: ipu@55020000 { + compatible = "ti,omap5-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu>; + resets = <&prm_core 0>, <&prm_core 1>; + clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; + firmware-name = "omap5-ipu-fw.xem4"; + mboxes = <&mailbox &mbox_ipu>; + status = "disabled"; + }; + dmm@4e000000 { compatible = "ti,omap5-dmm"; reg = <0x4e000000 0x800>; From patchwork Thu Jul 9 23:19:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11655301 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0D9F960D for ; Thu, 9 Jul 2020 23:20:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E985D207DA for ; Thu, 9 Jul 2020 23:20:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="CGgXIqVA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726890AbgGIXUR (ORCPT ); Thu, 9 Jul 2020 19:20:17 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49314 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726856AbgGIXUQ (ORCPT ); Thu, 9 Jul 2020 19:20:16 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NK9dI122954; Thu, 9 Jul 2020 18:20:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336809; bh=Q2UknZFZp0eYO410jfQeNU8OelHDDnS7sGKVXVirJAw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CGgXIqVAYgv0t9mlMOJSAhp3bcCTAObcPuolH/YYwPfRndyjIEd19nZkY+RFi5RtO e9nT4yrN9LmMgaiHyq2fZwIUptudm5aT9+KqXmz+lErU9IIAVStR9TM42hMZhGfCUf alkRlgoppxtOTjpcn7Qe+auyAEYjyOcBXKvuw77I= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK9ZP099442; Thu, 9 Jul 2020 18:20:09 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:08 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:08 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK7Ds119283; Thu, 9 Jul 2020 18:20:08 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NK7ex124457; Thu, 9 Jul 2020 18:20:07 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 09/13] ARM: dts: omap5: Add aliases for rproc nodes Date: Thu, 9 Jul 2020 18:19:50 -0500 Message-ID: <20200709231954.1973-10-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add aliases for the DSP and IPU remoteproc processor nodes common to all OMAP5 boards. The aliases uses the stem "rproc", and are identical to the values chosen on OMAP4 boards. The aliases can be overridden, if needed, in the respective board files. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap5.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 116150ded018..adffc48a6d55 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -31,6 +31,8 @@ aliases { serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; + rproc0 = &dsp; + rproc1 = &ipu; }; cpus { From patchwork Thu Jul 9 23:19:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11655297 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0697160D for ; Thu, 9 Jul 2020 23:20:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD1C72078B for ; Thu, 9 Jul 2020 23:20:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xrAeqnR5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726867AbgGIXUQ (ORCPT ); Thu, 9 Jul 2020 19:20:16 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:34598 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726848AbgGIXUP (ORCPT ); Thu, 9 Jul 2020 19:20:15 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NK8hi053753; Thu, 9 Jul 2020 18:20:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336808; bh=CyiHZQsfhTO5vLN7NiKzVMU247TNjDR4ol5AODJOUfg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xrAeqnR5nstmWpZGyl8R2kLPaRLti6sxwL19BxmncbPoV7WJ9rTaPx/FDtf7dOnSn PVA6AVup20WR+YFJuKjsy0LZu1Mq6fLEofc3Xw66IIuE7KrgeT6kg6jhzgApIr0sPM qgynQJY+Sx7z0zhp3SK30opSOTwSH1Z3GSynVgO4= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 069NK82L012077 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 9 Jul 2020 18:20:08 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:08 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:08 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK8HW096124; Thu, 9 Jul 2020 18:20:08 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NK8QA124469; Thu, 9 Jul 2020 18:20:08 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 10/13] ARM: dts: omap5-uevm: Add CMA pools and enable IPU & DSP Date: Thu, 9 Jul 2020 18:19:51 -0500 Message-ID: <20200709231954.1973-11-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The CMA reserved memory nodes have been added for the IPU and DSP remoteproc devices on the OMAP5 uEVM board. These nodes are assigned to the respective rproc device nodes, and both the IPU and DSP remote processors are enabled for this board. The current CMA pools and sizes are defined statically for each device. The starting addresses are fixed to meet current dependencies on the remote processor firmwares, and will go away when the remote-side code has been improved to gather this information runtime during its initialization. An associated pair of the rproc node and its CMA node can be disabled later on if there is no use-case defined to use that remote processor. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap5-uevm.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 9441e9a572ad..251885656697 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -15,6 +15,26 @@ memory@80000000 { reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_memory_region: dsp-memory@95000000 { + compatible = "shared-dma-pool"; + reg = <0 0x95000000 0 0x800000>; + reusable; + status = "okay"; + }; + + ipu_memory_region: ipu-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0 0x95800000 0 0x3800000>; + reusable; + status = "okay"; + }; + }; + aliases { ethernet = ðernet; }; @@ -198,3 +218,13 @@ ethernet: usbether@3 { &wlcore { compatible = "ti,wl1837"; }; + +&dsp { + status = "okay"; + memory-region = <&dsp_memory_region>; +}; + +&ipu { + status = "okay"; + memory-region = <&ipu_memory_region>; +}; From patchwork Thu Jul 9 23:19:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11655303 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 95B2113B6 for ; Thu, 9 Jul 2020 23:20:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B16D207F9 for ; Thu, 9 Jul 2020 23:20:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="EI1DT7UC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726880AbgGIXUR (ORCPT ); Thu, 9 Jul 2020 19:20:17 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49310 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726828AbgGIXUP (ORCPT ); Thu, 9 Jul 2020 19:20:15 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NK92I122950; Thu, 9 Jul 2020 18:20:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336809; bh=9DEjoc4nTb8pIGGuDBB5IWvIfClSK8JgplovScBDMdE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EI1DT7UCQe+5y2Z2H0H3Ms6mWNwnsOmiNqNZrQfmXai4vdSHIytN+/4vgKUru0E+X O6jRE4r/LbvMpwfBOx3JInzdQCC6dTdG3DhC+TmFowc8r0pB8A2peEjX/Ty8sqohbz sxtMt354IkXx6hNSd3WjtOYa7ikHHicYe4OfEavA= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 069NK9CA051639 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 9 Jul 2020 18:20:09 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:08 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:08 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NK8WX096146; Thu, 9 Jul 2020 18:20:08 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NK8oc124475; Thu, 9 Jul 2020 18:20:08 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 11/13] ARM: dts: omap5-uevm: Add system timers to DSP and IPU Date: Thu, 9 Jul 2020 18:19:52 -0500 Message-ID: <20200709231954.1973-12-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The BIOS System Tick timers have been added for the IPU and DSP remoteproc devices for the OMAP5 uEVM boards. The following timers (same as the timers on OMAP4 Panda boards) are chosen: IPU : GPT3 (SMP-mode) DSP : GPT5 IPU has two Cortex-M4 processors, and is currently expected to be running in SMP-mode, so only a single timer suffices to provide the BIOS tick timer. An additional timer should be added for the second processor in IPU if it were to be run in non-SMP mode. The timer value also needs to be unique from the ones used by other processors so that they can be run simultaneously. The timers are optional, but are mandatory to support device management features such as power management and watchdog support. The above are added to successfully boot and execute firmware images configured with the respective timers, images that use internal processor subsystem timers are not affected. The timers can be changed or removed as per the system integration needs, alongside equivalent changes on the firmware side. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap5-uevm.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 251885656697..bb016419ef61 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -222,9 +222,11 @@ &wlcore { &dsp { status = "okay"; memory-region = <&dsp_memory_region>; + ti,timers = <&timer5>; }; &ipu { status = "okay"; memory-region = <&ipu_memory_region>; + ti,timers = <&timer3>; }; From patchwork Thu Jul 9 23:19:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11655307 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BF65013B6 for ; Thu, 9 Jul 2020 23:20:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A08F6207F9 for ; Thu, 9 Jul 2020 23:20:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="IBOg/QN+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726856AbgGIXUS (ORCPT ); Thu, 9 Jul 2020 19:20:18 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49318 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726896AbgGIXUR (ORCPT ); Thu, 9 Jul 2020 19:20:17 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NKAF4122959; Thu, 9 Jul 2020 18:20:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336810; bh=u3p1npC2557z4sLt7pkiAxqgy+7rym2HrvMf1wembWw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IBOg/QN+aoXjhpU/t5LE6tJIgWUECQCOtRYAfmqwHfUx1I1RG+weVeiRZ02m+FGHX LjMyGPo06hhvZwGkim7yBuBfYWEAiI30NGS/w5JmaShJBmbtGt6iOPou6SM8JUYVgE XqgC3phDPhVA85/BasR+KFBsas69QT8SbhYFs3mo= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 069NKABg012122 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 9 Jul 2020 18:20:10 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:10 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:10 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NKAi3096163; Thu, 9 Jul 2020 18:20:10 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NKAMD124482; Thu, 9 Jul 2020 18:20:10 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 12/13] ARM: dts: omap4-panda-common: Add watchdog timers for IPU and DSP Date: Thu, 9 Jul 2020 18:19:53 -0500 Message-ID: <20200709231954.1973-13-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The watchdog timers have been added for the IPU and DSP remoteproc devices on all the OMAP4-based Panda boards. The following timers are used as the watchdog timers, DSP : GPT6 IPU : GPT9 & GPT11 (one for each Cortex-M3 core) The MPU-side drivers will use this data to initialize the watchdog timers, and listen for any watchdog triggers. The BIOS-side code needs to configure and refresh these timers properly to not throw a watchdog error. These timers can be changed or removed as per the system integration needs, alongside appropriate equivalent changes on the firmware side. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap4-panda-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index db0b7e9264f9..a6a0c7b832dd 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -596,10 +596,12 @@ &dsp { status = "okay"; memory-region = <&dsp_memory_region>; ti,timers = <&timer5>; + ti,watchdog-timers = <&timer6>; }; &ipu { status = "okay"; memory-region = <&ipu_memory_region>; ti,timers = <&timer3>; + ti,watchdog-timers = <&timer9>, <&timer11>; }; From patchwork Thu Jul 9 23:19:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 11655305 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9AE2B739 for ; Thu, 9 Jul 2020 23:20:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 83A69207BB for ; Thu, 9 Jul 2020 23:20:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="uQrDfkRX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726896AbgGIXUS (ORCPT ); Thu, 9 Jul 2020 19:20:18 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:55410 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726894AbgGIXUS (ORCPT ); Thu, 9 Jul 2020 19:20:18 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 069NKB28019098; Thu, 9 Jul 2020 18:20:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1594336811; bh=hoL0x9O1kvkaT4prL5tfXltZY55PUwkw/Roc9kLuZoA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uQrDfkRX1E7dRRpd+FVkx8e9aDd0eG5JNkddM8kTRSJcGB8SYCakzom7KEQaasN6P z+8aqRnjO5MOOA7bgMXm+ROFz96mOjsz4MAn7ESQ0ppXy9m60CayKsFPRsUiiiO1jZ kGr85dwwFamhgdNTrFHDMDz605ciqbUQNwhrdqrE= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 069NKBoo012138 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 9 Jul 2020 18:20:11 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 9 Jul 2020 18:20:10 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 9 Jul 2020 18:20:10 -0500 Received: from fllv0103.dal.design.ti.com (fllv0103.dal.design.ti.com [10.247.120.73]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 069NKAtp032199; Thu, 9 Jul 2020 18:20:10 -0500 Received: from localhost ([10.250.34.57]) by fllv0103.dal.design.ti.com (8.14.7/8.14.7) with ESMTP id 069NKAmV124485; Thu, 9 Jul 2020 18:20:10 -0500 From: Suman Anna To: Tony Lindgren CC: , , , Tero Kristo , Suman Anna Subject: [PATCH 13/13] ARM: dts: omap5-uevm: Add watchdog timers for IPU and DSP Date: Thu, 9 Jul 2020 18:19:54 -0500 Message-ID: <20200709231954.1973-14-s-anna@ti.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200709231954.1973-1-s-anna@ti.com> References: <20200709231954.1973-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The watchdog timers have been added for the IPU and DSP remoteproc devices for the OMAP5 uEVM board. The following timers (same as the timers on OMAP4 Panda boards) are used as the watchdog timers, DSP : GPT6 IPU : GPT9 & GPT11 (one for each Cortex-M4 core) The MPU-side drivers will use this data to initialize the watchdog timers, and listen for any watchdog triggers. The BIOS-side code needs to configure and refresh these timers properly to not throw a watchdog error. These timers can be changed or removed as per the system integration needs, alongside appropriate equivalent changes on the firmware side. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap5-uevm.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index bb016419ef61..9b9e9ee51b5c 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -223,10 +223,12 @@ &dsp { status = "okay"; memory-region = <&dsp_memory_region>; ti,timers = <&timer5>; + ti,watchdog-timers = <&timer6>; }; &ipu { status = "okay"; memory-region = <&ipu_memory_region>; ti,timers = <&timer3>; + ti,watchdog-timers = <&timer9>, <&timer11>; };