From patchwork Fri Jul 10 21:20:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11657431 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 048F0739 for ; Fri, 10 Jul 2020 22:20:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DF717207DF for ; Fri, 10 Jul 2020 22:20:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="s5cw7rCE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726319AbgGJWUQ (ORCPT ); Fri, 10 Jul 2020 18:20:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726624AbgGJWUQ (ORCPT ); Fri, 10 Jul 2020 18:20:16 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FEE5C08C5DC; Fri, 10 Jul 2020 15:20:15 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id o11so7350274wrv.9; Fri, 10 Jul 2020 15:20:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4W35ujYJlxKgHmJjOxh/l83E+9wVDyy9zXN8EsZkeBk=; b=s5cw7rCE0EWbF55kNa6MNaVUq9gxiw+DyerLx6J8txZcNXN19MIjAyBDqnoBlEoP1h OV4Jf4zPg4eoXxh6lRNIg//4gI/0L4lpCXVaKg5TBN6L/9m+NiW8BwXmYlbEzuabJ0te jLOZiyK1vLPR9AiJmAiEZeCWWxf8niZ1CEI90IICoBeecmKquzqhTb1PltP2NHM98Sob iIIlbZMhMCt3Ylsgi/MEpQujQAYKFP49Dk7kQkX//ko9E6xQs24vUmNBF397HgFDKadZ g9eVCpQO3O6FhhbMsdJrFi1Ufvy7Mfr1Xbev5QW4v2Y1ZBAWUEP5gqmyE9qse3fqBdfQ zCgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4W35ujYJlxKgHmJjOxh/l83E+9wVDyy9zXN8EsZkeBk=; b=TxOfyD0zDrt/dMQyrKkj2McBX9/9m+VOBtxNOdk24fiZc2A8dMt8oNdNQIMr3rg/A4 Nk5oP1HNkPoPqGuhtOlyykW77voK170kDa/fBexSVOC0DWP0BzX95QZ+EpJ8DTyMDPDD av3RNuydhWti1KJwnIuUh5dhTCjbo6dc/XUNJE1zoFobvVhHj4P0G5QeULr3TpiYPsYK XyrBM47dZhYGhhVG8cRWph84UnllZFKsprQytJ+3W3Q1ohvjftKQPp+j3lzTEfojw4uL PnAytchskRKvJ3TMn8pzcELktOm7VBUFDI7dVDuMsWVt/I4up3zNwOF0hj2bhrVFaTCY TvmQ== X-Gm-Message-State: AOAM5332iffJetQlB0hlJvORA8nWP1p2YWt/vgmZZ34PzNqFTbmae14a UR/Pbkaj8VAObFV417H8kuk= X-Google-Smtp-Source: ABdhPJzPwatony6Cjt8uiw1I+bb2q4igHjoQj2S+/ZwwO9vnHpqlg5m64LJZADjKjjMfX4mcscdugQ== X-Received: by 2002:a5d:464e:: with SMTP id j14mr69427633wrs.393.1594419614348; Fri, 10 Jul 2020 15:20:14 -0700 (PDT) Received: from net.saheed (54007186.dsl.pool.telekom.hu. [84.0.113.134]) by smtp.gmail.com with ESMTPSA id l18sm12170281wrm.52.2020.07.10.15.20.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 15:20:13 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, Lukas Wunner , skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/14 v3] PCI: pciehp: Check the return value of pcie_capability_read_*() Date: Fri, 10 Jul 2020 23:20:17 +0200 Message-Id: <20200710212026.27136-6-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200710212026.27136-1-refactormyself@gmail.com> References: <20200710212026.27136-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On any failure pcie_capability_read_word() sets it's last parameter, *val to 0, this value may have be earlier set by pci_config_read_word() to ~0. So, any function which check only for a frabricated ~0 will fail in this case. Checking for the return value of pcie_capability_read_dword() will help assert failure or success of this function. But more checks may be needed to assure the validity of the value. Include a check on the return value of pcie_capability_read_word() to confirm success or failure. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/hotplug/pciehp_hpc.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 53433b37e181..5af281d97d4f 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -86,10 +86,11 @@ static int pcie_poll_cmd(struct controller *ctrl, int timeout) { struct pci_dev *pdev = ctrl_dev(ctrl); u16 slot_status; + int ret; do { - pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); - if (slot_status == (u16) ~0) { + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); + if (ret || (slot_status == (u16) ~0)) { ctrl_info(ctrl, "%s: no response from device\n", __func__); return 0; @@ -156,6 +157,7 @@ static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, { struct pci_dev *pdev = ctrl_dev(ctrl); u16 slot_ctrl_orig, slot_ctrl; + int ret; mutex_lock(&ctrl->ctrl_lock); @@ -164,8 +166,8 @@ static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, */ pcie_wait_cmd(ctrl); - pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); - if (slot_ctrl == (u16) ~0) { + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); + if (ret || (slot_ctrl == (u16) ~0)) { ctrl_info(ctrl, "%s: no response from device\n", __func__); goto out; } @@ -430,7 +432,7 @@ void pciehp_get_latch_status(struct controller *ctrl, u8 *status) * removed immediately after the check so the caller may need to take * this into account. * - * It the hotplug controller itself is not available anymore returns + * If the hotplug controller itself is not available anymore returns * %-ENODEV. */ int pciehp_card_present(struct controller *ctrl) @@ -591,8 +593,8 @@ static irqreturn_t pciehp_isr(int irq, void *dev_id) } read_status: - pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status); - if (status == (u16) ~0) { + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status); + if (ret || (status == (u16) ~0)) { ctrl_info(ctrl, "%s: no response from device\n", __func__); if (parent) pm_runtime_put(parent); From patchwork Fri Jul 10 21:20:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11657433 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D54BA6C1 for ; Fri, 10 Jul 2020 22:20:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BC7A620674 for ; Fri, 10 Jul 2020 22:20:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="px4x+Ir1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726670AbgGJWUS (ORCPT ); Fri, 10 Jul 2020 18:20:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726631AbgGJWUR (ORCPT ); Fri, 10 Jul 2020 18:20:17 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2B2CC08C5DC; Fri, 10 Jul 2020 15:20:16 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id z13so7340756wrw.5; Fri, 10 Jul 2020 15:20:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tdpe9RfhxuAkiRZlM5Mq/vRi1xQi0fp5aVSqheR5YGw=; b=px4x+Ir1Hmqt/RIHHKLA49y3QyLmG2TCU6SADKNZHStWzUpoQU6bVSjIaM7sHXrbgl qDzy2e4Z17ZzItXeZdT6HSFTlJXeU1FU2vH0nff6XJf2oFctdr4zH2hKnf/H70zLMUYZ fhe+ON8/guj9R7yGx2KvlNibtktRd8YwMjGUSGQ338kNk/6u74wgHiUKVy8qnjMEfocr 15BUijBnxgqYv3Pch8DeXLnNIjTg8UPTC3SJDcT4FEzNLda4h8vp56xsdcsXwN7HXwgN AQBeFjjDfNXxoGE9/Fvro5okM26H+66moYBDNdTkANlv2C+LDDp1Lys2SmmGP63eYfH6 wJ/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tdpe9RfhxuAkiRZlM5Mq/vRi1xQi0fp5aVSqheR5YGw=; b=jXxDRThxnQ83IGrQYVVfdjx+4LQppN5czuwSub2IkeD06Eg9IJdT0JnENLvWxcHM/I roAbydizd4AX2lzHQiYFVDh/jfEVYKf+Eh/F1IlR0HGpv6y+pHEb/WjuuajhpZmCRmxQ IaelZN75+JlOiVAvOecQij1xQi6FDPEBaIhSwQUHOIjqBwfG2FQmC3ssABKya3vkQPNJ wnhUDMEcoqf/AsZSelwnpZuBQQck8U+THe+n5JOfRn/Up1RNVEeRyJMZOs6B/h6ppwo3 RJXfdKKgZQFLEKEayHT8hh+hQBGe6caMLAYsrmwkBEDJNK+ieMXNYj9O55LJdDowq4cA L1qg== X-Gm-Message-State: AOAM531PHBfDZvC4DMT3CzTe7ElNN8Bv8KkRdQ/O4AgApN/2FUe1O2LQ 6IqcEH/GmTFqtGSeFENPF0g= X-Google-Smtp-Source: ABdhPJwTRSLucrdEPJQmfs0y7Ck7+PkTy56iEk1AKAT5c0w1w8yRotpSUquRw9umBX/oIIntquItLA== X-Received: by 2002:adf:8b18:: with SMTP id n24mr73874175wra.372.1594419615686; Fri, 10 Jul 2020 15:20:15 -0700 (PDT) Received: from net.saheed (54007186.dsl.pool.telekom.hu. [84.0.113.134]) by smtp.gmail.com with ESMTPSA id l18sm12170281wrm.52.2020.07.10.15.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 15:20:15 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/14 v3] PCI: pciehp: Make "Power On" the default Date: Fri, 10 Jul 2020 23:20:18 +0200 Message-Id: <20200710212026.27136-7-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200710212026.27136-1-refactormyself@gmail.com> References: <20200710212026.27136-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed The default case of the switch statement is redundant since PCI_EXP_SLTCTL_PCC is only a single bit. pcie_capability_read_word() currently causes "On" value to be set if it fails. Make the switch-statement set status to "Power On" by default or when (slot_ctrl & PCI_EXP_SLTCTL_PCC) == PCI_EXP_SLTCTL_PWR_ON. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/hotplug/pciehp_hpc.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 0b691e37fd04..78f806a9c6f1 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -399,22 +399,16 @@ void pciehp_get_power_status(struct controller *ctrl, u8 *status) { struct pci_dev *pdev = ctrl_dev(ctrl); u16 slot_ctrl; + int ret; - pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); + *status = 1; /* On */ + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); - switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { - case PCI_EXP_SLTCTL_PWR_ON: - *status = 1; /* On */ - break; - case PCI_EXP_SLTCTL_PWR_OFF: + if (!ret && + ((slot_ctrl & PCI_EXP_SLTCTL_PCC) == PCI_EXP_SLTCTL_PWR_OFF)) *status = 0; /* Off */ - break; - default: - *status = 0xFF; - break; - } } void pciehp_get_latch_status(struct controller *ctrl, u8 *status) From patchwork Fri Jul 10 21:20:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11657451 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EE1EA739 for ; Fri, 10 Jul 2020 22:20:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D5CD120857 for ; Fri, 10 Jul 2020 22:20:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="vBecEFbh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726624AbgGJWUU (ORCPT ); Fri, 10 Jul 2020 18:20:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726693AbgGJWUS (ORCPT ); Fri, 10 Jul 2020 18:20:18 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F2DDC08C5DC; Fri, 10 Jul 2020 15:20:18 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id o2so7333253wmh.2; Fri, 10 Jul 2020 15:20:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zBfQN+vRaGSFliSIC9sUYYBlJBWdf+Mc3nVjYABa6uc=; b=vBecEFbh/d0jSef2GGDkawA1rYeo7al4di1WqcRGBfvnRrTP2sQxtQ0PJwcAgiO5qe MGsc06bJHFGxcuKxJEQnwXXsbhVhwXOIFkM7N/BdSw7KytVkbUqwRgCgR0jvV4AXKVCM mNRjwHqEUbOHu7JVc+2DOTngEfZFUvsXnoFl99OezVwXeJ+rXwhReatDgo1Ck2JO/kxY UZ11NYvdsJyVUZJKJSsdFaD8sfkVHxddqoSvWwfDuAQZt6rXeBv1fUkNJRmaR3d9rvUQ 1wa5IR6Xo1ZY7GKo7UgBdWpgkGe3f+hZpgf596QE3g6SXnBHKtk8tP0bakSwc4saynAE fqdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zBfQN+vRaGSFliSIC9sUYYBlJBWdf+Mc3nVjYABa6uc=; b=RCAB86vdOv/lJ+qq7BPvtI8I7JSdMKXabcuog0MgKtqLWDv0zIyW7aKLHUKdHe5Fc1 mT8bVfelxZDm3fEzdZl9Krkus1SeZAjH/lGXSAaaKocn25Ct5yVwQh6m2uORxPdA4dH0 6syb8pN5MDBzjtkhysRfOb5LV6Tne6nT+zn1dUbhaJAqSWJzIUw94OGbPdCaTh1nA4jz u3nKr3UayS3ZJc7CElaAqGU/hxwZPkQ/y8kbeCn+uBEqPFV+hVGHG54Xe0pWKlHfXzJx tjq7n7du0St4OVfV15uKqjnHdNlfi0EiVKI6liUnuzq0tR+cbyAZaabifDOLJKBIQxk6 S9Og== X-Gm-Message-State: AOAM530kIlzH+7q8FtL5sWrWPwbZlNas8jH27yonhjJgaky6F9+sq0OA 4c2FR28AyxqjuGErIQF/Pj0= X-Google-Smtp-Source: ABdhPJyfeh9pQCHsK+AR0ZiTfubZZSMON0PFLNp3rQLm4JcDpLNUMt2j2BpVH5xqfzX/lX304gQmIg== X-Received: by 2002:a1c:4086:: with SMTP id n128mr7445658wma.118.1594419616792; Fri, 10 Jul 2020 15:20:16 -0700 (PDT) Received: from net.saheed (54007186.dsl.pool.telekom.hu. [84.0.113.134]) by smtp.gmail.com with ESMTPSA id l18sm12170281wrm.52.2020.07.10.15.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 15:20:16 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/14 v3] PCI: pciehp: Check the return value of pcie_capability_read_*() Date: Fri, 10 Jul 2020 23:20:19 +0200 Message-Id: <20200710212026.27136-8-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200710212026.27136-1-refactormyself@gmail.com> References: <20200710212026.27136-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed If pcie_capability_read_word() fail, slot_ctrl will be 0 and the switch expression evaluates to 0. So *status = 1 "ON". However, with Patch 14/14 it is possible that slot_ctrl is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x), so the switch expression evaluates to PCI_EXP_SLTCTL_PCC. This means that on failure *status = 1 "OFF", since PCI_EXP_SLTCTL_PCC = PCI_EXP_SLTCTL_PWR_OFF. Use an if-statement and include a check on the return value of pcie_capability_read_word() to confirm success or failure. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/hotplug/pciehp_hpc.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index b89c9ee4a3b5..f5ef3fbace69 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -394,20 +394,16 @@ void pciehp_get_power_status(struct controller *ctrl, u8 *status) { struct pci_dev *pdev = ctrl_dev(ctrl); u16 slot_ctrl; + int ret; - pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); + *status = 1; /* On */ + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); - switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { - case PCI_EXP_SLTCTL_PWR_OFF: + if (!ret && + ((slot_ctrl & PCI_EXP_SLTCTL_PCC) == PCI_EXP_SLTCTL_PWR_OFF)) *status = 0; /* Off */ - break; - case PCI_EXP_SLTCTL_PWR_ON: - default: - *status = 1; /* On */ - break; - } } void pciehp_get_latch_status(struct controller *ctrl, u8 *status) From patchwork Fri Jul 10 21:20:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11657449 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B67906C1 for ; Fri, 10 Jul 2020 22:20:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9BDDC207F9 for ; Fri, 10 Jul 2020 22:20:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aG717Mh+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726729AbgGJWUV (ORCPT ); Fri, 10 Jul 2020 18:20:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726715AbgGJWUU (ORCPT ); Fri, 10 Jul 2020 18:20:20 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41AAFC08C5DC; Fri, 10 Jul 2020 15:20:20 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id o11so7350365wrv.9; Fri, 10 Jul 2020 15:20:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Aw1VsrtSYtcq2poBq51sXMfz6dSvwXJUJRkwZAWrd10=; b=aG717Mh+yfnVzffccC3T0g+foEBFsfS7f2qjhmFbKfu/ee4DvajkEXLibWdoOSN7Gy O2NlqE/yED1WCoVri14mxo1nA/DhbC4TfFlh+gDBhkTm1i++nEIvYhUnzX75RuLHVhxn N5qjIWWQTLGympOy6JJWc3WCP5U9JJE8x4rilTRv6CObWA2Npbxl8MILdn1cGUsg8uSf IcFSnILXaC+/DetMjFrcZg99zlfx/4nMgcNCPUU1OEUwYVeKbACTIARFV52P8VyaIUjL xRZYffbDwY9H9ssJZP1M7fjNvV9Hb7XepWAyzFgoN8RL4oGs+tKFrYDoFvFNAalnk/1b xxtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Aw1VsrtSYtcq2poBq51sXMfz6dSvwXJUJRkwZAWrd10=; b=iVVqeHAizx2Kvp3Pyl+syFjEYMKCt8j2ASEjJHSF33ZXAzuoZNrKaLG6nzGkzrDmiW Mh6dXzYjswdLQSC2sbDbJ9dWZUpPcOVfk/0wAhcsBj/EUTbtOyC4JZ6K0r6RD8+Xi58x oZ+HHCUHh3u9bfjtHhiVIpo8fdt4juGxrsyylf1QSzF6AJVKkcxy34mRdy/5jDpt29Ev /cTN7D0Wr9OV0kMXfwQjTDw+7COWw7TctB5pRqNfexz/PwhNn8OHC/WX14iKY/NFDxH+ /G/Un3LuJ6QUpiCzIyvZ3TN4VHVcYMvz9zRiKPFjy0r09j6YhHp+a3ZIAYnPJifCm5vg vQPg== X-Gm-Message-State: AOAM531ZEdFq0ei0A21hWCFYVKKh0vLW3MbmBXXngKJR06qN5ZLK8dSy NsoGNnb3rFleZvqyhBOvivE= X-Google-Smtp-Source: ABdhPJyv0JZcNwPCwOQC9NfYv6P2Yb1NOOR9kLooOJDcTnXEuQTTkqbzAPMkpAORzJE7k8uyZ+FXmg== X-Received: by 2002:a5d:66ca:: with SMTP id k10mr58545944wrw.244.1594419619001; Fri, 10 Jul 2020 15:20:19 -0700 (PDT) Received: from net.saheed (54007186.dsl.pool.telekom.hu. [84.0.113.134]) by smtp.gmail.com with ESMTPSA id l18sm12170281wrm.52.2020.07.10.15.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 15:20:18 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 9/14 v3] PCI: pciehp: Check return value of pcie_capability_read_*() Date: Fri, 10 Jul 2020 23:20:21 +0200 Message-Id: <20200710212026.27136-10-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200710212026.27136-1-refactormyself@gmail.com> References: <20200710212026.27136-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On failure pcie_capability_read_dword() sets it's last parameter, val to 0. However, with Patch 14/14, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). This bug can be avoided if the return value of pcie_capability_read_word is checked to confirm success. Check the return value of pcie_capability_read_dword() to ensure success. Return a value that indicate the result of pcie_capability_read_word(). Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/hotplug/pciehp_hpc.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 5af281d97d4f..0b691e37fd04 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -277,10 +277,11 @@ static void pcie_wait_for_presence(struct pci_dev *pdev) { int timeout = 1250; u16 slot_status; + int ret; do { - pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); - if (slot_status & PCI_EXP_SLTSTA_PDS) + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); + if (!ret && (slot_status & PCI_EXP_SLTSTA_PDS)) return; msleep(10); timeout -= 10; @@ -354,12 +355,13 @@ int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot, struct controller *ctrl = to_ctrl(hotplug_slot); struct pci_dev *pdev = ctrl_dev(ctrl); u16 slot_ctrl; + int ret; pci_config_pm_runtime_get(pdev); - pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); pci_config_pm_runtime_put(pdev); *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6; - return 0; + return pcibios_err_to_errno(ret); } int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status) @@ -367,9 +369,10 @@ int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status) struct controller *ctrl = to_ctrl(hotplug_slot); struct pci_dev *pdev = ctrl_dev(ctrl); u16 slot_ctrl; + int ret; pci_config_pm_runtime_get(pdev); - pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); + ret = pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); pci_config_pm_runtime_put(pdev); ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); @@ -389,7 +392,7 @@ int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status) break; } - return 0; + return pcibios_err_to_errno(ret); } void pciehp_get_power_status(struct controller *ctrl, u8 *status) From patchwork Fri Jul 10 21:20:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11657435 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 488826C1 for ; Fri, 10 Jul 2020 22:20:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 30E5E207D0 for ; Fri, 10 Jul 2020 22:20:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="V+ktR0g5" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726746AbgGJWUW (ORCPT ); Fri, 10 Jul 2020 18:20:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726724AbgGJWUV (ORCPT ); Fri, 10 Jul 2020 18:20:21 -0400 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CABDC08C5DC; Fri, 10 Jul 2020 15:20:21 -0700 (PDT) Received: by mail-wm1-x343.google.com with SMTP id g75so7582455wme.5; Fri, 10 Jul 2020 15:20:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9beKaVLBUAv2GkNWPso7Jo1sgUnYoNc43mKbz9aG4JE=; b=V+ktR0g5nmWzPHnEburi8Ox+p9ZismGnFac6ev3M/D6f9aFDUBsfwCp1T1QDWpmHlP Z/Xl0iU1MpoZ2rUgQMQSqUezYo+oZZqpTyOHWDtnXrkj8Ydsx38jxAYBT0duw/uH3Qva CPO0KpUoBO0D+7tdrIddSZJdVKXRB8YIivOZBQGQzCvob9bIkUKRAAuOjAXkhMcIeByo PC/U01RPp5qsWR45L7R2rAxAMR5ogxmOqtdtNYWfTSgUaaPmI/Lu+qv7gkI8El2iyJtD 9+e2RL6i59GRhaX7EOB/5Upli1fbFv6+NNfPI9nqeXWEXr1IrBw17Eiro7dOYwanqMy8 4hUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9beKaVLBUAv2GkNWPso7Jo1sgUnYoNc43mKbz9aG4JE=; b=ewMu4SwomG4XvUeKCoKUSKryVhpiAYk+2oGBKcryLvWi6OCwwXHrb0g+aUsjLm5iHS ymheAe/oMJprhwmtqmaky0xOZdXKN3/zbmku1PlyZJCbohUvulyAQ+lh0+mtK0/NV44s 4QoFGL8m0LD+5/XME6ePpcjyqONvG397lO6Q2ofEWjoSm8yTdbZWnw+tBTwVhKLZOmJk MI81tAwG0993jQwMq4CbEJXwhrF+1+D2fg56ypUeSl/x6D49Qzjkqv7PA3DjSt66QEFO njBLybDWTKJ1C7/Azszk7g34Ut0ZbRdvYSwmUcI+ETvr7NRmrLJ13TC1lATRFBkE3aMN KVfQ== X-Gm-Message-State: AOAM530hAfASELBbsCZ2zHrJ3pCfqHac4qLP2GBzB1AVDHEFvQBbNkYp I49mtuuBRggEBkKcuysiNBHqcKvTsnippA== X-Google-Smtp-Source: ABdhPJya776BQ7eTEUkYXuIJxLe0w2DKQXM0/eH13WiSIo6NquF35aXbWVwW1ITUhwemsH0Nd+vv4A== X-Received: by 2002:a1c:e4d4:: with SMTP id b203mr7611314wmh.49.1594419620087; Fri, 10 Jul 2020 15:20:20 -0700 (PDT) Received: from net.saheed (54007186.dsl.pool.telekom.hu. [84.0.113.134]) by smtp.gmail.com with ESMTPSA id l18sm12170281wrm.52.2020.07.10.15.20.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 15:20:19 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/14 v3] PCI: Check return value of pcie_capability_read_*() Date: Fri, 10 Jul 2020 23:20:22 +0200 Message-Id: <20200710212026.27136-11-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200710212026.27136-1-refactormyself@gmail.com> References: <20200710212026.27136-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On failure pcie_capability_read_dword() sets it's last parameter, val to 0. However, with Patch 14/14, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). This bug can be avoided if the return value of pcie_capability_read_word is checked to confirm success. Check the return value of pcie_capability_read_word() to ensure success. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/probe.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 2f66988cea25..3c87a8a1d4b5 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1121,10 +1121,11 @@ EXPORT_SYMBOL(pci_add_new_bus); static void pci_enable_crs(struct pci_dev *pdev) { u16 root_cap = 0; + int ret; /* Enable CRS Software Visibility if supported */ - pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); - if (root_cap & PCI_EXP_RTCAP_CRSVIS) + ret = pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); + if (!ret && (root_cap & PCI_EXP_RTCAP_CRSVIS)) pcie_capability_set_word(pdev, PCI_EXP_RTCTL, PCI_EXP_RTCTL_CRSSVE); } @@ -1519,9 +1520,10 @@ void set_pcie_port_type(struct pci_dev *pdev) void set_pcie_hotplug_bridge(struct pci_dev *pdev) { u32 reg32; + int ret; - pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); - if (reg32 & PCI_EXP_SLTCAP_HPC) + ret = pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); + if (!ret && (reg32 & PCI_EXP_SLTCAP_HPC)) pdev->is_hotplug_bridge = 1; } @@ -2057,10 +2059,11 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign) bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) { u16 v; + int ret; - pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); + ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); - return !!(v & PCI_EXP_DEVCTL_RELAX_EN); + return (!ret && !!(v & PCI_EXP_DEVCTL_RELAX_EN)); } EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); @@ -2096,16 +2099,17 @@ static void pci_configure_ltr(struct pci_dev *dev) struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); struct pci_dev *bridge; u32 cap, ctl; + int ret; if (!pci_is_pcie(dev)) return; - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_LTR)) + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); + if (ret || !(cap & PCI_EXP_DEVCAP2_LTR)) return; - pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); - if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); + if (!ret && (ctl & PCI_EXP_DEVCTL2_LTR_EN)) { if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { dev->ltr_path = 1; return; @@ -2142,12 +2146,13 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev) struct pci_dev *bridge; int pcie_type; u32 cap; + int ret; if (!pci_is_pcie(dev)) return; - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); + if (ret || !(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) return; pcie_type = pci_pcie_type(dev); From patchwork Fri Jul 10 21:20:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11657447 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C49256C1 for ; Fri, 10 Jul 2020 22:20:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A6E87207F9 for ; Fri, 10 Jul 2020 22:20:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ed5gwn4T" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726815AbgGJWUo (ORCPT ); Fri, 10 Jul 2020 18:20:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726751AbgGJWUX (ORCPT ); Fri, 10 Jul 2020 18:20:23 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97B08C08C5DC; Fri, 10 Jul 2020 15:20:22 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id a6so9340992wmm.0; Fri, 10 Jul 2020 15:20:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/DGPoUKfitACThlLV4LP7NGjasXKQ1tYflzyCbCjHy8=; b=ed5gwn4TL9l6C2hiNge5RZpFsA3eH8Iphd/yN7KO/OEDmm0/OSkvJI4TCYu/rzQnYy 0hyFq0ogXey3cZKxUvgeTPTs/hHUXW9/Vra3kb4T7oqh4Rq0PKSYLKAZZVD7N0/YdZri o4pY0AafSoWv/ld1mPCMM40Ysb1qqNrorEylEsXqfbi8jrrBBvpZkgioI+UbW+pX3KOy UGp1uGHS+r5gJJ9cvYLS5usc37+cPk7luqVtbwn9usBa+1oGAAyG+JHvt8mx1q71xuS5 Qf7uWVrXkrai9JcSXa2KhvDd2u1heIIhby4m4sVfaqwry1ZxAw9wUIQmnDzShMn0ukX3 PFKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/DGPoUKfitACThlLV4LP7NGjasXKQ1tYflzyCbCjHy8=; b=mrn68kyFKAIue/UbqL6a5WdLNuXSkhCKj94MYL8voZ5X4JxelyD9G2jmlt42wYSiZi O0DUGr5x8pnnHTtR+rXCyvQo5c9Ptl5F1q4MXs4uN6O90mV6xlKv6P387jRavRyOF2Dl AKjBblQmI+ghwq9KgoP1NcG+AxRn7tO0ANGoyI8TFWBEq9Nlc5e2gE2CwXm/J9BbqmsY uu9Or1/hgBiHP/Y6R+5A6Bkwj4PGzxwvjj4MTNJySvrraYuRESG2QgPfDcMiSLXZlZpS G1Z3t/lSDShwvCDogr7pKaJVWNvlp38cWqLJI4cfH5HYV++gGpVoZXzIUbUzSghEnS9N jSBA== X-Gm-Message-State: AOAM531FOcYvmkzTTT+7c/z3K+jvNVlefXInaIIOLz9Ac3/OKVP+aJQb UjoYxOefR1qHKnzOQTaBpdk= X-Google-Smtp-Source: ABdhPJx1ZcaQfkFJ2dxuru9m9ZjdAi9ZYjp4N9+6ITauNzxYltGNvZLsptAH6OhVGB2ky+/up1DUQQ== X-Received: by 2002:a1c:6706:: with SMTP id b6mr6726758wmc.167.1594419621287; Fri, 10 Jul 2020 15:20:21 -0700 (PDT) Received: from net.saheed (54007186.dsl.pool.telekom.hu. [84.0.113.134]) by smtp.gmail.com with ESMTPSA id l18sm12170281wrm.52.2020.07.10.15.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 15:20:20 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/14 v3] PCI/PM: Check return value of pcie_capability_read_*() Date: Fri, 10 Jul 2020 23:20:23 +0200 Message-Id: <20200710212026.27136-12-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200710212026.27136-1-refactormyself@gmail.com> References: <20200710212026.27136-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On failure pcie_capability_read_dword() sets it's last parameter, val to 0. However, with Patch 14/14, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). This bug can be avoided if the return value of pcie_capability_read_dword is checked to confirm success. Check the return value of pcie_capability_read_dword() to ensure success. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/pci.c | 52 ++++++++++++++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index ce096272f52b..9f18ffbf7bd4 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3207,6 +3207,7 @@ void pci_configure_ari(struct pci_dev *dev) { u32 cap; struct pci_dev *bridge; + int ret; if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) return; @@ -3215,8 +3216,8 @@ void pci_configure_ari(struct pci_dev *dev) if (!bridge) return; - pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_ARI)) + ret = pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); + if (ret || !(cap & PCI_EXP_DEVCAP2_ARI)) return; if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { @@ -3606,6 +3607,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) struct pci_bus *bus = dev->bus; struct pci_dev *bridge; u32 cap, ctl2; + int ret; if (!pci_is_pcie(dev)) return -EINVAL; @@ -3629,28 +3631,29 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) while (bus->parent) { bridge = bus->self; - pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); + ret = pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, + &cap); switch (pci_pcie_type(bridge)) { /* Ensure switch ports support AtomicOp routing */ case PCI_EXP_TYPE_UPSTREAM: case PCI_EXP_TYPE_DOWNSTREAM: - if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) + if (ret || !(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) return -EINVAL; break; /* Ensure root port supports all the sizes we care about */ case PCI_EXP_TYPE_ROOT_PORT: - if ((cap & cap_mask) != cap_mask) + if (ret || ((cap & cap_mask) != cap_mask)) return -EINVAL; break; } /* Ensure upstream ports don't block AtomicOps on egress */ if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) { - pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, - &ctl2); - if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) + ret = pcie_capability_read_dword(bridge, + PCI_EXP_DEVCTL2, &ctl2); + if (!ret && (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) return -EINVAL; } @@ -4507,12 +4510,13 @@ EXPORT_SYMBOL(pci_wait_for_pending_transaction); bool pcie_has_flr(struct pci_dev *dev) { u32 cap; + int ret; if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) return false; - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); - return cap & PCI_EXP_DEVCAP_FLR; + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); + return (!ret && !!(cap & PCI_EXP_DEVCAP_FLR)); } EXPORT_SYMBOL_GPL(pcie_has_flr); @@ -4672,7 +4676,7 @@ static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, msleep(20); for (;;) { pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); - ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); + ret = !!(!ret && (lnk_status & PCI_EXP_LNKSTA_DLLLA)); if (ret == active) break; if (timeout <= 0) @@ -5774,6 +5778,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed next_speed; enum pcie_link_width next_width; u32 bw, next_bw; + int ret; if (speed) *speed = PCI_SPEED_UNKNOWN; @@ -5783,7 +5788,12 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, bw = 0; while (dev) { - pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); + ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); + + if (ret) { + dev = pci_upstream_bridge(dev); + continue; + } next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> @@ -5820,6 +5830,7 @@ EXPORT_SYMBOL(pcie_bandwidth_available); enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) { u32 lnkcap2, lnkcap; + int ret; /* * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The @@ -5830,16 +5841,18 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) * should use the Supported Link Speeds field in Link Capabilities, * where only 2.5 GT/s and 5.0 GT/s speeds were defined. */ - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); + ret = pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); /* PCIe r3.0-compliant */ - if (lnkcap2) + if (!ret && lnkcap2) return PCIE_LNKCAP2_SLS2SPEED(lnkcap2); - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); - if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB) + ret = pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (!ret && + ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)) return PCIE_SPEED_5_0GT; - else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB) + else if (!ret && + ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)) return PCIE_SPEED_2_5GT; return PCI_SPEED_UNKNOWN; @@ -5856,9 +5869,10 @@ EXPORT_SYMBOL(pcie_get_speed_cap); enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) { u32 lnkcap; + int ret; - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); - if (lnkcap) + ret = pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (!ret && lnkcap) return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; return PCIE_LNK_WIDTH_UNKNOWN; From patchwork Fri Jul 10 21:20:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11657445 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4ED576C1 for ; Fri, 10 Jul 2020 22:20:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D0B9207DF for ; Fri, 10 Jul 2020 22:20:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="igXknrAx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726777AbgGJWU0 (ORCPT ); Fri, 10 Jul 2020 18:20:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726772AbgGJWUZ (ORCPT ); Fri, 10 Jul 2020 18:20:25 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E45E4C08C5DC; Fri, 10 Jul 2020 15:20:24 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id j18so7599114wmi.3; Fri, 10 Jul 2020 15:20:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RPlXxwxC87uaq64nnqw5MANvLol+4JOrpjsVdPBxD3o=; b=igXknrAx+ieLXkXBcEVFyoWfoYs+N5dQQI59AiDzZ1RrQb2nMVrxJB3zRBeI5nLuP0 xiQ+T1T30ezIW8OnSvFK8+//wKnlQDz7NjoE+g3+5UWx9KODFbIMb6vTsi8Y4tRi1wDH CmWoJfru5cZ/yAaIZc7sNTHKl8keBtYbmZLuHZRNyV6v/0R05rkDitki9YMfdSOTG61j Ru/MJmcLzXsKbMe9gRKUnFajnt/kNutKehlRM2ZGzB63l85mPpADGL9tXAt1oTS4hb8O MeHpRsE86DJf/E5NSkfQWwLoI8gNcwh2hwt8Y8r5+g2KZ0moALU1wlXRl0H4ZkZiMsS9 WY5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RPlXxwxC87uaq64nnqw5MANvLol+4JOrpjsVdPBxD3o=; b=ThnCTcTi+034XwAsX0Lq76Tt+jHnvbHxrm11curFgsPnuh1gzW4rat88hFpAnzLxA/ DYTQMTstOb1mNB/hLOwXOdEVmtVIR4mC7TiXKyu4rWjYqwbSRK+bgXdF24/JhPjsoLBw 27kWEWO4x/f/8sdf2KirfQBINSfvzIsacLuhFpWJpcq9n3DqCfZUhqB8OfVJhzpNqzBG Pso+gSshQijHXHWcR2yiosXxE2aXACGlKYqua7n47acBeLO0vD6ZTw1xHq38x77vkCSi 7bwjDh8FmGhjbDBV0QBqSPPzbdgw95Wgsd7DYYm96wxvwviAbc+v0wICBIb9qchURPHT 5Wyw== X-Gm-Message-State: AOAM532wK6NVjnSpGIinsvKSpVMBBuMFHSbenSHda2/iVCnWrQwnJtIe juHn0p4auIHtlDosWzHr+HY= X-Google-Smtp-Source: ABdhPJw7prCE9OQvuQ0E1c9jwZDnLvGW1QVsVB0xRmxoIUNhwpjMs85LIeoQU/ueNJLJo1JwN/DhIw== X-Received: by 2002:a7b:ca52:: with SMTP id m18mr7036373wml.92.1594419623608; Fri, 10 Jul 2020 15:20:23 -0700 (PDT) Received: from net.saheed (54007186.dsl.pool.telekom.hu. [84.0.113.134]) by smtp.gmail.com with ESMTPSA id l18sm12170281wrm.52.2020.07.10.15.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 15:20:23 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/14] PCI/ASPM: Check the return value of pcie_capability_read_*() Date: Fri, 10 Jul 2020 23:20:25 +0200 Message-Id: <20200710212026.27136-14-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200710212026.27136-1-refactormyself@gmail.com> References: <20200710212026.27136-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed On failure pcie_capability_read_dword() sets it's last parameter, val to 0. However, with Patch 14/14, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). This bug can be avoided if the return value of pcie_capability_read_dword is checked to confirm success. Check the return value of pcie_capability_read_dword() to ensure success. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- drivers/pci/pcie/aspm.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index b17e5ffd31b1..32aa9d57672a 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -176,7 +176,7 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable) static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) { - int capable = 1, enabled = 1; + int ret, capable = 1, enabled = 1; u32 reg32; u16 reg16; struct pci_dev *child; @@ -184,14 +184,14 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) /* All functions should have the same cap and state, take the worst */ list_for_each_entry(child, &linkbus->devices, bus_list) { - pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); - if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { + ret = pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); + if (ret || !(reg32 & PCI_EXP_LNKCAP_CLKPM)) { capable = 0; enabled = 0; break; } - pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); - if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) + ret = pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); + if (ret || !(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) enabled = 0; } link->clkpm_enabled = enabled; @@ -205,6 +205,7 @@ static bool pcie_retrain_link(struct pcie_link_state *link) struct pci_dev *parent = link->pdev; unsigned long end_jiffies; u16 reg16; + int ret; pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); reg16 |= PCI_EXP_LNKCTL_RL; @@ -222,8 +223,8 @@ static bool pcie_retrain_link(struct pcie_link_state *link) /* Wait for link training end. Break out after waiting for timeout */ end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; do { - pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_LT)) + ret = pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); + if (ret || !(reg16 & PCI_EXP_LNKSTA_LT)) break; msleep(1); } while (time_before(jiffies, end_jiffies)); @@ -237,7 +238,7 @@ static bool pcie_retrain_link(struct pcie_link_state *link) */ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) { - int same_clock = 1; + int ret, same_clock = 1; u16 reg16, parent_reg, child_reg[8]; struct pci_dev *child, *parent = link->pdev; struct pci_bus *linkbus = parent->subordinate; @@ -249,24 +250,24 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) BUG_ON(!pci_is_pcie(child)); /* Check downstream component if bit Slot Clock Configuration is 1 */ - pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_SLC)) + ret = pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); + if (ret || !(reg16 & PCI_EXP_LNKSTA_SLC)) same_clock = 0; /* Check upstream component if bit Slot Clock Configuration is 1 */ - pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_SLC)) + ret = pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); + if (ret || !(reg16 & PCI_EXP_LNKSTA_SLC)) same_clock = 0; /* Port might be already in common clock mode */ - pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); - if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) { + ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); + if (!ret && same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) { bool consistent = true; list_for_each_entry(child, &linkbus->devices, bus_list) { - pcie_capability_read_word(child, PCI_EXP_LNKCTL, + ret = pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); - if (!(reg16 & PCI_EXP_LNKCTL_CCC)) { + if (ret || !(reg16 & PCI_EXP_LNKCTL_CCC)) { consistent = false; break; } From patchwork Fri Jul 10 21:20:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. 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[84.0.113.134]) by smtp.gmail.com with ESMTPSA id l18sm12170281wrm.52.2020.07.10.15.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 15:20:25 -0700 (PDT) From: Saheed Olayemi Bolarinwa To: helgaas@kernel.org Cc: Bolarinwa Olayemi Saheed , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org, Russell Currey , Sam Bobroff , "Oliver O'Halloran" , linuxppc-dev@lists.ozlabs.org, "Rafael J. Wysocki" , Len Brown , Lukas Wunner , linux-acpi@vger.kernel.org, Mike Marciniszyn , Dennis Dalessandro , Doug Ledford , Jason Gunthorpe , linux-rdma@vger.kernel.org, Arnd Bergmann , Greg Kroah-Hartman , "David S. Miller" , Kalle Valo , Jakub Kicinski , QCA ath9k Development , linux-wireless@vger.kernel.org, netdev@vger.kernel.org, Stanislaw Gruszka Subject: [PATCH 14/14 v3] PCI: Remove '*val = 0' from pcie_capability_read_*() Date: Fri, 10 Jul 2020 23:20:26 +0200 Message-Id: <20200710212026.27136-15-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20200710212026.27136-1-refactormyself@gmail.com> References: <20200710212026.27136-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bolarinwa Olayemi Saheed There are several reasons why a PCI capability read may fail whether the device is present or not. If this happens, pcie_capability_read_*() will return -EINVAL/PCIBIOS_BAD_REGISTER_NUMBER or PCIBIOS_DEVICE_NOT_FOUND and *val is set to 0. This behaviour if further ensured by this code inside pcie_capability_read_*() ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); /* * Reset *val to 0 if pci_read_config_dword() fails, it may * have been written as 0xFFFFFFFF if hardware error happens * during pci_read_config_dword(). */ if (ret) *val = 0; return ret; a) Since all pci_generic_config_read() does is read a register value, it may return success after reading a ~0 which *may* have been fabricated by the PCI host bridge due to a read timeout. Hence pci_read_config_*() will return success with a fabricated ~0 in *val, indicating a problem. In this case, the assumed behaviour of pcie_capability_read_*() will be wrong. To avoid error slipping through, more checks are necessary. b) pci_read_config_*() will return PCIBIOS_DEVICE_NOT_FOUND only if dev->error_state = pci_channel_io_perm_failure (i.e. pci_dev_is_disconnected()) or if pci_generic_config_read() can't find the device. In both cases *val is initially set to ~0 but as shown in the code above pcie_capability_read_*() resets it back to 0. Even with this effort, drivers still have to perform validation checks more so if 0 is a valid value. Most drivers only consider the case (b) and in some cases, there is the expectation that on timeout *val has a fabricated value of ~0, which *may* not always be true as explained in (a). In any case, checks need to be done to validate the value read and maybe confirm which error has occurred. It is better left to the drivers to do. Remove the reset of *val to 0 when pci_read_config_*() fails. Suggested-by: Bjorn Helgaas Signed-off-by: Bolarinwa Olayemi Saheed --- This patch depends on all of the preceeding patches in this series, otherwise it will introduce bugs as pointed out in the commit message of each. drivers/pci/access.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/drivers/pci/access.c b/drivers/pci/access.c index 79c4a2ef269a..ec95edbb1ac8 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -413,13 +413,6 @@ int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) if (pcie_capability_reg_implemented(dev, pos)) { ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); - /* - * Reset *val to 0 if pci_read_config_word() fails, it may - * have been written as 0xFFFF if hardware error happens - * during pci_read_config_word(). - */ - if (ret) - *val = 0; return ret; } @@ -448,13 +441,6 @@ int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val) if (pcie_capability_reg_implemented(dev, pos)) { ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); - /* - * Reset *val to 0 if pci_read_config_dword() fails, it may - * have been written as 0xFFFFFFFF if hardware error happens - * during pci_read_config_dword(). - */ - if (ret) - *val = 0; return ret; }