From patchwork Sat Jul 11 16:16:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11657939 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 514A560D for ; Sat, 11 Jul 2020 16:23:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3124A207D4 for ; Sat, 11 Jul 2020 16:23:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3124A207D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:45940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIHE-0007PW-DQ for patchwork-qemu-devel@patchwork.kernel.org; Sat, 11 Jul 2020 12:23:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54690) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDY-0007fX-Rf; Sat, 11 Jul 2020 12:19:12 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:38873) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDW-0001Ln-9Z; Sat, 11 Jul 2020 12:19:12 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.531228-0.000452356-0.46832; FP=0|0|0|0|0|-1|-1|-1; HT=e01l07447; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:38 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 01/11] riscv: Add RV64I instructions description Date: Sun, 12 Jul 2020 00:16:45 +0800 Message-Id: <20200711161655.2856-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Avoid using stack pointer(x2), thread pointer(x3), global pointer(x4), as they are not under control of risu. Besides, avoid using x0 as base address register, because we can't emit a valid random address by setting x0. Signed-off-by: LIU Zhiwei --- rv64.risu | 141 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 rv64.risu diff --git a/rv64.risu b/rv64.risu new file mode 100644 index 0000000..edf0d1f --- /dev/null +++ b/rv64.risu @@ -0,0 +1,141 @@ +# Input file for risugen defining RISC-V instructions +.mode riscv.rv64 +@RV64I + +# x2 stack pointer, x3 global pointer, x4 thread pointer +# These registers should be reserved for signal handler. + +LUI RISCV imm:20 rd:5 0110111 \ +!constraints { greg($rd); } + +AUIPC RISCV imm:20 rd:5 0110111 \ +!constraints { greg($rd); } + +# Limit to current implementation, the base address register will be overide +LB RISCV imm:12 rs1:5 000 rd:5 0000011 \ +!constraints { greg($rd) && gbase($rs1); } \ +!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12), $rd); } + +LH RISCV imm:12 rs1:5 001 rd:5 0000011 \ +!constraints { greg($rd) && gbase($rs1); } \ +!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12), $rd); } + +LW RISCV imm:12 rs1:5 010 rd:5 0000011 \ +!constraints { greg($rd) && gbase($rs1); } \ +!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12), $rd); } + +LBU RISCV imm:12 rs1:5 100 rd:5 0000011 \ +!constraints { greg($rd) && gbase($rs1); } \ +!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12), $rd); } + +LHU RISCV imm:12 rs1:5 101 rd:5 0000011 \ +!constraints { greg($rd) && gbase($rs1); } \ +!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12), $rd); } + +SB RISCV imm5:7 rs2:5 rs1:5 000 imm:5 0100011 \ +!constraints { greg($rs2) && gbase($rs1) && $rs2 != $rs1; } \ +!memory { align(1); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); } + +SH RISCV imm5:7 rs2:5 rs1:5 001 imm:5 0100011 \ +!constraints { greg($rs2) && gbase($rs1) && $rs2 != $rs1; } \ +!memory { align(2); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); } + +SW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0100011 \ +!constraints { greg($rs2) && gbase($rs1) && $rs2 != $rs1; } \ +!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); } + +ADDI RISCV imm:12 rs1:5 000 rd:5 0010011 \ +!constraints { greg($rd) && greg($rs1); } + +SLTI RISCV imm:12 rs1:5 010 rd:5 0010011 \ +!constraints { greg($rd) && greg($rs1); } + +SLTIU RISCV imm:12 rs1:5 011 rd:5 0010011 \ +!constraints { greg($rd) && greg($rs1); } + +XORI RISCV imm:12 rs1:5 100 rd:5 0010011 \ +!constraints { greg($rd) && greg($rs1); } + +ORI RISCV imm:12 rs1:5 110 rd:5 0010011 \ +!constraints { greg($rd) && greg($rs1); } + +ANDI RISCV imm:12 rs1:5 111 rd:5 0010011 \ +!constraints { greg($rd) && greg($rs1); } + +ADD RISCV 0000000 rs2:5 rs1:5 000 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +SUB RISCV 0100000 rs2:5 rs1:5 000 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +SLL RISCV 0000000 rs2:5 rs1:5 001 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +SLT RISCV 0000000 rs2:5 rs1:5 010 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +SLTU RISCV 0000000 rs2:5 rs1:5 011 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +XOR RISCV 0000000 rs2:5 rs1:5 100 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +SRL RISCV 0000000 rs2:5 rs1:5 101 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +SRA RISCV 0100000 rs2:5 rs1:5 101 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +OR RISCV 0000000 rs2:5 rs1:5 110 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +AND RISCV 0000000 rs2:5 rs1:5 111 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +LWU RISCV imm:12 rs1:5 110 rd:5 0000011 \ +!constraints { greg($rd) && gbase($rs1); } \ +!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12), $rd); } + +LD RISCV imm:12 rs1:5 011 rd:5 0000011 \ +!constraints { greg($rd) && gbase($rs1); } \ +!memory { align(8); reg_plus_imm($rs1, sextract($imm, 12), $rd); } + +SD RISCV imm5:7 rs2:5 rs1:5 011 imm:5 0100011 \ +!constraints { greg($rs2) && gbase($rs1) && $rs2 != $rs1; } \ +!memory { align(8); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); } + +SLLI RISCV 00000 sham5:7 rs1:5 001 rd:5 0010011 \ +!constraints { greg($rd) && greg($rs1); } + +SRLI RISCV 00000 sham5:7 rs1:5 101 rd:5 0010011 \ +!constraints { greg($rd) && greg($rs1); } + +SRAI RISCV 01000 sham5:7 rs1:5 101 rd:5 0010011 \ +!constraints { greg($rd) && greg($rs1); } + +ADDIW RISCV imm:12 rs1:5 000 rd:5 0011011 \ +!constraints { greg($rd) && greg($rs1); } + +SLLIW RISCV 0000000 shamt:5 rs1:5 001 rd:5 0011011 \ +!constraints { greg($rd) && greg($rs1); } + +SRLIW RISCV 0000000 shamt:5 rs1:5 101 rd:5 0011011 \ +!constraints { greg($rd) && greg($rs1); } + +SRAIW RISCV 0100000 shamt:5 rs1:5 101 rd:5 0011011 \ +!constraints { greg($rd) && greg($rs1); } + +ADDW RISCV 0000000 rs2:5 rs1:5 000 rd:5 0011011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +SUBW RISCV 0100000 rs2:5 rs1:5 000 rd:5 0011011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +SLLW RISCV 0000000 rs2:5 rs1:5 001 rd:5 0011011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } From patchwork Sat Jul 11 16:16:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11657929 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2872D60D for ; Sat, 11 Jul 2020 16:21:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C9323207D4 for ; Sat, 11 Jul 2020 16:21:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C9323207D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:37398 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIFe-0003y7-S3 for patchwork-qemu-devel@patchwork.kernel.org; Sat, 11 Jul 2020 12:21:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDH-0007Ep-DM; Sat, 11 Jul 2020 12:18:55 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:47937) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDD-0001Lo-Jo; Sat, 11 Jul 2020 12:18:55 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436779|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.499597-0.0016009-0.498802; FP=0|0|0|0|0|-1|-1|-1; HT=e01a16378; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:39 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 02/11] riscv: Add RV64M instructions description Date: Sun, 12 Jul 2020 00:16:46 +0800 Message-Id: <20200711161655.2856-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei --- rv64.risu | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/rv64.risu b/rv64.risu index edf0d1f..2c4154e 100644 --- a/rv64.risu +++ b/rv64.risu @@ -139,3 +139,44 @@ SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \ SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \ !constraints { greg($rd) && greg($rs1) && greg($rs2); } + +@RV64M + +MUL RISCV 0000001 rs2:5 rs1:5 000 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +MULH RISCV 0000001 rs2:5 rs1:5 001 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +MULHSU RISCV 0000001 rs2:5 rs1:5 010 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +MULHU RISCV 0000001 rs2:5 rs1:5 011 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +DIV RISCV 0000001 rs2:5 rs1:5 100 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +DIVU RISCV 0000001 rs2:5 rs1:5 101 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +REM RISCV 0000001 rs2:5 rs1:5 110 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +REMU RISCV 0000001 rs2:5 rs1:5 111 rd:5 0110011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +MULW RISCV 0000001 rs2:5 rs1:5 000 rd:5 0111011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +DIVW RISCV 0000001 rs2:5 rs1:5 100 rd:5 0111011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +DIVUW RISCV 0000001 rs2:5 rs1:5 101 rd:5 0111011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } + +REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \ +!constraints { greg($rd) && greg($rs1) && greg($rs2); } From patchwork Sat Jul 11 16:16:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11657931 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5F60960D for ; Sat, 11 Jul 2020 16:21:25 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3FAE1207D4 for ; Sat, 11 Jul 2020 16:21:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3FAE1207D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:37502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIFg-00040a-Br for patchwork-qemu-devel@patchwork.kernel.org; Sat, 11 Jul 2020 12:21:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDI-0007FZ-TM; Sat, 11 Jul 2020 12:18:56 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:57681) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDD-0001Lw-Tt; Sat, 11 Jul 2020 12:18:56 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.669281-0.0017065-0.329012; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03301; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:39 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 03/11] riscv: Add RV64A instructions description Date: Sun, 12 Jul 2020 00:16:47 +0800 Message-Id: <20200711161655.2856-4-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Ensure $rs2 != $rs1, so that the $rs2 register's value will not be covered when setting the $rs1 register's value to get a valid address. Signed-off-by: LIU Zhiwei --- rv64.risu | 90 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/rv64.risu b/rv64.risu index 2c4154e..ad5dee9 100644 --- a/rv64.risu +++ b/rv64.risu @@ -180,3 +180,93 @@ REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \ REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \ !constraints { greg($rd) && greg($rs1) && greg($rs2); } + +@RV64A + +LR_W RISCV 00010 imm:2 00000 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && gbase($rs1); } \ +!memory { align(4); reg($rs1, $rd); } + +SC_W RISCV 00011 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOSWAP_W RISCV 00001 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOADD_W RISCV 00000 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOXOR_W RISCV 00100 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOAND_W RISCV 01100 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOOR_W RISCV 01000 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOMIN_W RISCV 10000 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOMAX_W RISCV 10100 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOMINU_W RISCV 11000 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +AMOMAXU_W RISCV 11100 imm:2 rs2:5 rs1:5 010 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(4); reg($rs1, $rd); } + +LR_D RISCV 00010 imm:2 00000 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && gbase($rs1); } \ +!memory { align(8); reg($rs1, $rd); } + +SC_D RISCV 00011 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOSWAP_D RISCV 00001 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOADD_D RISCV 00000 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOXOR_D RISCV 00100 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOAND_D RISCV 01100 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOOR_D RISCV 01000 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOMIN_D RISCV 10000 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOMAX_D RISCV 10100 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOMINU_D RISCV 11000 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } + +AMOMAXU_D RISCV 11100 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ +!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ +!memory { align(8); reg($rs1, $rd); } From patchwork Sat Jul 11 16:16:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11657921 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 95B286C1 for ; Sat, 11 Jul 2020 16:19:56 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 75A8E207DD for ; Sat, 11 Jul 2020 16:19:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 75A8E207DD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:57154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIEF-0000U8-Lh for patchwork-qemu-devel@patchwork.kernel.org; Sat, 11 Jul 2020 12:19:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54508) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDH-0007Ei-4J; Sat, 11 Jul 2020 12:18:55 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:58191) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDC-0001Lp-QS; Sat, 11 Jul 2020 12:18:54 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0026535-0.000506006-0.99684; FP=0|0|0|0|0|-1|-1|-1; HT=e01l10422; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:39 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 04/11] riscv: Add RV64F instructions description Date: Sun, 12 Jul 2020 00:16:48 +0800 Message-Id: <20200711161655.2856-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" For supporting multi-precision, split all 32 fp registers into two groups. The RV64F instructions will use only 16 fp registers selected by gfp32(). Signed-off-by: LIU Zhiwei --- rv64.risu | 94 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/rv64.risu b/rv64.risu index ad5dee9..0dcc9a1 100644 --- a/rv64.risu +++ b/rv64.risu @@ -270,3 +270,97 @@ AMOMINU_D RISCV 11000 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ AMOMAXU_D RISCV 11100 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \ !constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\ !memory { align(8); reg($rs1, $rd); } + +@RV64F + +FLW RISCV imm:12 rs1:5 010 rd:5 0000111 \ +!constraints { gbase($rs1) && gfp32($rd); } \ +!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); } + +FSW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0100111 \ +!constraints { gbase($rs1) && gfp32($rs2); } \ +!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); } + +FMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000111 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FNMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FNMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001111 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FADD_S RISCV 0000000 rs2:5 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FSUB_S RISCV 0000100 rs2:5 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FMUL_S RISCV 0001000 rs2:5 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FDIV_S RISCV 0001100 rs2:5 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); } + +FSQRT_S RISCV 0101100 00000 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rd) && grm($rm); } + +FSGNJ_S RISCV 0010000 rs2:5 rs1:5 000 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); } + +FSGNJN_S RISCV 0010000 rs2:5 rs1:5 001 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); } + +FSGNJX_S RISCV 0010000 rs2:5 rs1:5 010 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); } + +FMIN_S RISCV 0010100 rs2:5 rs1:5 000 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); } + +FMAX_S RISCV 0010100 rs2:5 rs1:5 001 rd:5 1010011 \ +!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); } + +FCVT_W_S RISCV 1100000 00000 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && grm($rm); } + +FCVT_WU_S RISCV 1100000 00001 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && grm($rm); } + +FMV_X_W RISCV 1110000 00000 rs1:5 000 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1); } + +FEQ_S RISCV 1010000 rs2:5 rs1:5 010 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && gfp32($rs2); } + +FLT_S RISCV 1010000 rs2:5 rs1:5 001 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && gfp32($rs2); } + +FLE_S RISCV 1010000 rs2:5 rs1:5 000 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && gfp32($rs2); } + +FCLASS_S RISCV 1110000 00000 rs1:5 001 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1); } + +FCVT_S_W RISCV 1101000 00000 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rs1) && gfp32($rd) && grm($rm); } + +FCVT_S_WU RISCV 1101000 00001 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rs1) && gfp32($rd) && grm($rm); } + +FMV_W_X RISCV 1111000 00000 rs1:5 000 rd:5 1010011 \ +!constraints { greg($rs1) && gfp32($rd); } + +FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && grm($rm); } + +FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rd) && gfp32($rs1) && grm($rm); } + +FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rs1) && gfp32($rd) && grm($rm); } + +FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rs1) && gfp32($rd) && grm($rm); } From patchwork Sat Jul 11 16:16:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11657943 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A357B618 for ; Sat, 11 Jul 2020 16:24:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 82E7D207D4 for ; Sat, 11 Jul 2020 16:24:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 82E7D207D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:50558 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIID-0000rm-Qm for patchwork-qemu-devel@patchwork.kernel.org; Sat, 11 Jul 2020 12:24:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54552) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDI-0007FT-Ke; Sat, 11 Jul 2020 12:18:56 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:40247) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDD-0001Lq-Ku; Sat, 11 Jul 2020 12:18:56 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0023182-0.000295609-0.997386; FP=0|0|0|0|0|-1|-1|-1; HT=e01l07381; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:40 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 05/11] riscv: Add RV64D instructions description Date: Sun, 12 Jul 2020 00:16:49 +0800 Message-Id: <20200711161655.2856-6-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" For supporting multi-precison, split all 32 fp registers into two groups. The RV64D instructions will use only the 16 fp registers selected by gfp64(). Signed-off-by: LIU Zhiwei --- rv64.risu | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/rv64.risu b/rv64.risu index 0dcc9a1..a6fa9fc 100644 --- a/rv64.risu +++ b/rv64.risu @@ -364,3 +364,103 @@ FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \ FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \ !constraints { greg($rs1) && gfp32($rd) && grm($rm); } + +@RV64D + +FLD RISCV imm:12 rs1:5 011 rd:5 0000111 \ +!constraints { gbase($rs1) && gfp64($rd); } \ +!memory { align(8); reg_plus_imm($rs1, sextract($imm, 12)); } + +FSD RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0100111 \ +!constraints { gbase($rs1) && gfp64($rs2); } \ +!memory { align(8); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); } + +FMADD_D RISCV rs3:5 01 rs2:5 rs1:5 rm:3 rd:5 1000011 \ +!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); } + +FMSUB_D RISCV rs3:5 01 rs2:5 rs1:5 rm:3 rd:5 1000111 \ +!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); } + +FNMSUB_D RISCV rs3:5 01 rs2:5 rs1:5 rm:3 rd:5 1001011 \ +!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); } + +FNMADD_D RISCV rs3:5 01 rs2:5 rs1:5 rm:3 rd:5 1001111 \ +!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); } + +FADD_D RISCV 0000001 rs2:5 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); } + +FSUB_D RISCV 0000101 rs2:5 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); } + +FMUL_D RISCV 0001001 rs2:5 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); } + +FDIV_D RISCV 0001101 rs2:5 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd) && grm($rm); } + +FSQRT_D RISCV 0101101 00000 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp64($rs1) && gfp64($rd) && grm($rm); } + +FSGNJ_D RISCV 0010001 rs2:5 rs1:5 000 rd:5 1010011 \ +!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd); } + +FSGNJN_D RISCV 0010001 rs2:5 rs1:5 001 rd:5 1010011 \ +!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd); } + +FSGNJX_D RISCV 0010001 rs2:5 rs1:5 010 rd:5 1010011 \ +!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd); } + +FMIN_D RISCV 0010101 rs2:5 rs1:5 000 rd:5 1010011 \ +!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd); } + +FMAX_D RISCV 0010101 rs2:5 rs1:5 001 rd:5 1010011 \ +!constraints { gfp64($rs1) && gfp64($rs2) && gfp64($rd); } + +FCVT_S_D RISCV 0100000 00001 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp64($rs1) && gfp64($rd) && grm($rm); } + +FCVT_D_S RISCV 0100001 00000 rs1:5 rm:3 rd:5 1010011 \ +!constraints { gfp64($rs1) && gfp64($rd) && grm($rm); } + +FEQ_D RISCV 1010001 rs2:5 rs1:5 010 rd:5 1010011 \ +!constraints { greg($rd) && gfp64($rs1) && gfp64($rs1); } + +FLT_D RISCV 1010001 rs2:5 rs1:5 001 rd:5 1010011 \ +!constraints { greg($rd) && gfp64($rs1) && gfp64($rs1); } + +FLE_D RISCV 1010001 rs2:5 rs1:5 000 rd:5 1010011 \ +!constraints { greg($rd) && gfp64($rs1) && gfp64($rs1); } + +FCLASS_D RISCV 1110001 00000 rs1:5 001 rd:5 1010011 \ +!constraints { greg($rd) && gfp64($rs1); } + +FCVT_W_D RISCV 1100001 00000 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rd) && gfp64($rs1) && grm($rm); } + +FCVT_WU_D RISCV 1100001 00001 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rd) && gfp64($rs1) && grm($rm); } + +FCVT_D_W RISCV 1101001 00000 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rs1) && gfp64($rd) && grm($rm); } + +FCVT_D_WU RISCV 1101001 00001 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rs1) && gfp64($rd) && grm($rm); } + +FCVT_L_D RISCV 1100001 00010 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rd) && gfp64($rs1) && grm($rm); } + +FCVT_LU_D RISCV 1100001 00011 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rd) && gfp64($rs1) && grm($rm); } + +FCVT_D_L RISCV 1101001 00010 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rs1) && gfp64($rd) && grm($rm); } + +FCVT_D_LU RISCV 1101001 00011 rs1:5 rm:3 rd:5 1010011 \ +!constraints { greg($rs1) && gfp64($rd) && grm($rm); } + +FMV_D_X RISCV 1111001 00000 rs1:5 000 rd:5 1010011 \ +!constraints { greg($rs1) && gfp64($rd); } + +FMV_X_D RISCV 1110001 00000 rs1:5 000 rd:5 1010011 \ +!constraints { greg($rd) && gfp64($rs1); } From patchwork Sat Jul 11 16:16:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11657925 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D9A366C1 for ; Sat, 11 Jul 2020 16:19:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B9CEB2075F for ; Sat, 11 Jul 2020 16:19:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B9CEB2075F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:57542 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIEI-0000e4-P3 for patchwork-qemu-devel@patchwork.kernel.org; Sat, 11 Jul 2020 12:19:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54586) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDK-0007H2-9H; Sat, 11 Jul 2020 12:18:58 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:53984) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDE-0001Lx-AU; Sat, 11 Jul 2020 12:18:57 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07460231|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.252457-0.00103191-0.746511; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03299; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:40 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 06/11] riscv: Add RV64C instructions description Date: Sun, 12 Jul 2020 00:16:50 +0800 Message-Id: <20200711161655.2856-7-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Make it a separate file, so that we can get subarch to recgonize the instrcution length. Signed-off-by: LIU Zhiwei --- rv64c.risu | 97 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 rv64c.risu diff --git a/rv64c.risu b/rv64c.risu new file mode 100644 index 0000000..fdd8afb --- /dev/null +++ b/rv64c.risu @@ -0,0 +1,97 @@ +# Input file for risugen defining RISC-V instructions +.mode riscv.rv64c + +@RV64C + +# we borrow X11 to store stack register +C_LWSP RISCV 010 imm5:1 rd:5 imm2:3 imm6:2 10 \ +!constraints { greg($rd) && $rd != 0 && $rd != 11; } \ +!memory { align(4); stack_plus_imm($imm5 * 32 + $imm2 * 4 + $imm6 * 64, $rd); } + +C_LDSP RISCV 011 imm5:1 rd:5 imm3:2 imm6:3 10 \ +!constraints { greg($rd) && $rd != 0 && $rd != 11; } \ +!memory { align(8); stack_plus_imm($imm5 * 32 + $imm3 * 8 + $imm6 * 64, $rd); } + +C_FLDSP RISCV 001 imm5:1 rd:5 imm3:2 imm6:3 10 \ +!memory { align(8); stack_plus_imm($imm5 * 32 + $imm3 * 8 + $imm6 * 64); } + +C_SWSP RISCV 110 imm2:4 imm6:2 rs2:5 10 \ +!constraints { greg($rs2) && $rs2 != 11; } \ +!memory { align(4); stack_plus_imm($imm2 * 4 + $imm6 * 64); } + +C_SDSP RISCV 111 imm3:3 imm6:3 rs2:5 10 \ +!constraints { greg($rs2) && $rs2 != 11; } \ +!memory { align(8); stack_plus_imm($imm3 * 8 + $imm6 * 64); } + +C_FSDSP RISCV 101 imm3:3 imm6:3 rs2:5 10 \ +!memory { align(8); stack_plus_imm($imm3 * 8 + $imm6 * 64); } + +# encode x11 into 0b011 in CL format +C_LW RISCV 010 imm3:3 rs1:3 imm2:1 imm6:1 rd:3 00 \ +!memory { align(4); reg_plus_imm($rs1 + 8, $imm2 * 4 + $imm3 * 8 + $imm6 * 64, $rd + 8); } + +C_LD RISCV 011 imm3:3 rs1:3 imm6:2 rd:3 00 \ +!memory { align(8); reg_plus_imm($rs1 + 8, $imm3 * 8 + $imm6 * 64, $rd + 8); } + +C_FLD RISCV 001 imm3:3 rs1:3 imm6:2 rd:3 00 \ +!memory { align(8); reg_plus_imm($rs1 + 8, $imm3 * 8 + $imm6 * 64); } + +C_SW RISCV 110 imm3:3 rs1:3 imm2:1 imm6:1 rs2:3 00 \ +!constraints { $rs2 != $rs1; } \ +!memory { align(4); reg_plus_imm($rs1 + 8, $imm2 * 4 + $imm3 * 8 + $imm6 * 64); } + +C_SD RISCV 111 imm3:3 rs1:3 imm6:2 rs2:3 00 \ +!constraints { $rs2 != $rs1; } \ +!memory { align(8); reg_plus_imm($rs1 + 8, $imm3 * 8 + $imm6 * 64); } + +C_FSD RISCV 101 imm3:3 rs1:3 imm6:2 rs2:3 00 \ +!memory { align(8); reg_plus_imm($rs1 + 8, $imm3 * 8 + $imm6 * 64); } + +C_LI RISCV 010 imm5:1 rd:5 imm:5 01 \ +!constraints { gbase($rd); } + +C_LUI RISCV 011 imm17:1 rd:5 imm12:5 01 \ +!constraints { gbase($rd) && ($imm17 != 0 || $imm12 != 0); } + +C_ADDI RISCV 000 imm5:1 rd:5 imm:5 01 \ +!constraints { gbase($rd) && ($imm5 != 0 || $imm != 0); } + +C_ADDIW RISCV 001 imm5:1 rd:5 imm:5 01 \ +!constraints { gbase($rd); } + +# Todo C_ADDI16SP, as it need stack as destination +# Move sp to aother register through the memory address function. + +# C_ADDI4SPN RISCV 000 imm4:2 imm6:4 imm2:1 imm3:1 rd:3 00 \ +# !constraints { $imm4 != 0 || $imm6 != 0 || $imm2 != 0 || $imm3 != 0; } + +C_SLLI RISCV 000 shamt5:1 rd:5 shamt:5 10 \ +!constraints { gbase($rd) && ($shamt5 != 0 || $shamt != 0); } + +C_SRLI RISCV 100 shamt5:1 00 rd:3 shamt:5 01 \ +!constraints { ($shamt5 != 0 || $shamt != 0); } + +C_SRAI RISCV 100 shamt5:1 01 rd:3 shamt:5 01 \ +!constraints { ($shamt5 != 0 || $shamt != 0); } + +C_ANDI RISCV 100 imm5:1 10 rd:3 imm:5 01 + +C_MV RISCV 100 0 rd:5 rs2:5 10 \ +!constraints { gbase($rd) && gbase($rs2); } + +C_ADD RISCV 100 1 rd:5 rs2:5 10 \ +!constraints { gbase($rd) && gbase($rs2); } + +C_AND RISCV 100 0 11 rd:3 11 rs2:3 01 + +C_OR RISCV 100 0 11 rd:3 10 rs2:3 01 + +C_XOR RISCV 100 0 11 rd:3 01 rs2:3 01 + +C_SUB RISCV 100 0 11 rd:3 01 rs2:3 01 + +C_SUBW RISCV 100 1 11 rd:3 00 rs2:3 01 + +C_ADDW RISCV 100 1 11 rd:3 01 rs2:3 01 + +C_NOP RISCV 0000000000000001 From patchwork Sat Jul 11 16:16:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11657933 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 590A160D for ; Sat, 11 Jul 2020 16:21:31 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 27C10207D4 for ; Sat, 11 Jul 2020 16:21:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 27C10207D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:38164 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIFm-0004Gn-A2 for patchwork-qemu-devel@patchwork.kernel.org; Sat, 11 Jul 2020 12:21:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDS-0007VD-AO; Sat, 11 Jul 2020 12:19:06 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:42387) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDD-0001M5-Jo; Sat, 11 Jul 2020 12:19:06 -0400 X-Alimail-AntiSpam: AC=PASS; BC=0.07436282|-1; BR=01201311R161ee; CH=green; DM=|CONTINUE|false|; DS=SPAM|spam_ad|0.923774-6.91251e-05-0.076157; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03273; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:41 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 07/11] riscv: Generate payload scripts Date: Sun, 12 Jul 2020 00:16:51 +0800 Message-Id: <20200711161655.2856-8-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" In general, generate payload. 1. Setup memory for load/store instructions. 2. Initialize the registers. 3. Emit instructions according to instruction format description. Specially, modify according to RISC-V ISA. 1. Support multi-precision by dividing fp registers into two groups. 2. Use $bytecount to locate special float point values. 3. Use x10 as the special register pointing to the memory block. Signed-off-by: LIU Zhiwei --- risugen_riscv.pm | 643 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 643 insertions(+) create mode 100644 risugen_riscv.pm diff --git a/risugen_riscv.pm b/risugen_riscv.pm new file mode 100644 index 0000000..79f7a67 --- /dev/null +++ b/risugen_riscv.pm @@ -0,0 +1,643 @@ +#!/usr/bin/perl -w +############################################################################### +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# LIU Zhiwei (T-Head) - RISC-V implementation +# based on Peter Maydell (Linaro) - initial implementation +############################################################################### + +# risugen -- generate a test binary file for use with risu +# See 'risugen --help' for usage information. +package risugen_riscv; + +use strict; +use warnings; + +use risugen_common; + +require Exporter; + +our @ISA = qw(Exporter); +our @EXPORT = qw(write_test_code); + +my $periodic_reg_random = 1; +my $is_rvc = 0; # are we currently in RVC mode? + +# +# Maximum alignment restriction permitted for a memory op. +my $MAXALIGN = 64; +sub ctz($) +{ + my ($imm) = @_; + my $cnt = 0; + + if ($imm == 0) { + return 0; + } + while (($imm & 1) == 0) { + $cnt++; + $imm = $imm >> 1; + } + return $cnt; +} + +sub decode_li($) +{ + my ($imm) = @_; + my $cnt = 0; + my $idx = 0; + my $part = 0; + my $next = 0; + my %result; + + $next = $imm; + # only one lui can not hold + while ((($next >> 12) != sextract(($next >> 12) & 0xfffff, 20)) || + (($next & 0xfff) != 0)) { + # at the first time, just eat the least 12 bits + if ($idx == 0) { + $part = sextract($imm & 0xfff, 12); + $result{"first"} = $part; + } else { + $imm = $imm - $part; # clear the part before it + $cnt = ctz($imm); # add a shift + $imm >>= $cnt; + $part = sextract($imm & 0xfff, 12); + $result{"mid"}{$idx}{"part"} = $part; + $result{"mid"}{$idx}{"cnt"} = $cnt; + $next = $imm - $part; + } + $idx++; + } + # output a lui + $result{"lui"} = sextract(($next >> 12) & 0xfffff, 20); + return %result; +} + +# li is implements as Myraid sequences, just the common way here +sub write_mov_ri($$) +{ + my ($rd, $imm) = @_; + + # sequence of li rd, 0x1234567887654321 + # + # 0: 002471b7 lui rd,0x247 + # 4: 8ad1819b addiw rd,rd,-1875 + # 8: 00c19193 slli rd,rd,0xc + # c: f1118193 addi rd,rd,-239 # 0x246f11 + # 10: 00d19193 slli rd,rd,0xd + # 14: d9518193 addi rd,rd,-619 + # 18: 00e19193 slli rd,rd,0xe + # 1c: 32118193 addi rd,rd,801 + my %result = decode_li($imm); + + my $len = keys %{$result{"mid"}}; + my $i = 0; + + # output the last lui + insn32(0x00000037 | $rd << 7 | $result{"lui"} << 12); + # output the sequence of slli and addi + foreach my $key (reverse sort keys %{$result{"mid"}}) { + $i++; + if ($i == 1) { + # output the last addiw + insn32(0x0000001b | $rd << 7 | $rd << 15 | + $result{"mid"}{$key}{"part"} << 20); + # slli rd, rd, $result{"mid"}{$key}{"part"} + insn32(0x00001013 | $rd << 7 | $rd << 15 | + $result{"mid"}{$key}{"cnt"} << 20); + } else { + insn32(0x00000013 | $rd << 7 | $rd << 15 | + ($result{"mid"}{$key}{"part"} & 0xfff) << 20); + # slli rd, rd, $result{"mid"}{$key}{"part"} + insn32(0x00001013 | $rd << 7 | $rd << 15 | + $result{"mid"}{$key}{"cnt"} << 20); + } + } + # addi rd, rd, $result{"first"} + insn32(0x00000013 | $rd << 7 | $rd << 15 | ($imm & 0xfff) << 20); +} + +sub write_mov_rr($$) +{ + my ($rd, $rs1) = @_; + + # addi $rd, $rs1, 0 + insn32(0x00000013 | $rd << 7 | $rs1 << 15); +} + +sub write_sub_rrr($$$) +{ + my ($rd, $rs1, $rs2) = @_; + + # sub $rd, $rs1, $rs2 + insn32(0x40000033 |$rd << 7 | $rs1 << 15 | $rs2 << 20); +} + +my $OP_COMPARE = 0; # compare registers +my $OP_TESTEND = 1; # end of test, stop +my $OP_SETMEMBLOCK = 2; # x10 is address of memory block (8192 bytes) +my $OP_GETMEMBLOCK = 3; # add the address of memory block to x10 +my $OP_COMPAREMEM = 4; # compare memory block + +# write random fp value of passed precision (1=single, 2=double) +sub write_random_fpreg_var($) +{ + my ($precision) = @_; + my $randomize_low = 0; + + if ($precision != 1 && $precision != 2) { + die "write_random_fpreg: invalid precision.\n"; + } + + my ($low, $high); + my $r = rand(100); + if ($r < 5) { + # +-0 (5%) + $low = $high = 0; + $high |= 0x80000000 if (rand() < 0.5); + } elsif ($r < 10) { + # NaN (5%) + # (plus a tiny chance of generating +-Inf) + $randomize_low = 1; + $high = rand(0xffffffff) | 0x7ff00000; + } elsif ($r < 15) { + # Infinity (5%) + $low = 0; + $high = 0x7ff00000; + $high |= 0x80000000 if (rand() < 0.5); + } elsif ($r < 30) { + # Denormalized number (15%) + # (plus tiny chance of +-0) + $randomize_low = 1; + $high = rand(0xffffffff) & ~0x7ff00000; + } else { + # Normalized number (70%) + # (plus a small chance of the other cases) + $randomize_low = 1; + $high = rand(0xffffffff); + } + + for (my $i = 1; $i < $precision; $i++) { + if ($randomize_low) { + $low = rand(0xffffffff); + } + insn32($low); + } + insn32($high); +} + +my %fpregs; +my $GROUP_RVF = 1; # fp registers for RVF insns. +my $GROUP_RVD = 2; # fp registers for RVD insns. + +# split fp regs into two sets, one for RVF, another for RVD +sub init_fp_groups() +{ + # all allocated to RVF + for (0..31) { + $fpregs{$_} = $GROUP_RVF; + } + + # allocate 16 regs to RVD + my $count = 0; + while ($count < 16) { + my $idx = int rand(31); + if ($fpregs{$idx} == $GROUP_RVF) { + $fpregs{$idx} = $GROUP_RVD; + $count++; + } + } +} + +# random initialize $GROUP_RVF registers. +sub write_random_fp32() +{ + # load floating point registers + my $align = 16; + my $padding = $align - ($bytecount % $align); + my $datalen = 16 * 4 + $padding; + + write_pc_adr(10, (4 * 4) + ($align - 1)); # insn 1 + write_align_reg(10, $align); # insn 2 + write_jump_fwd($datalen + 4); # insn 3 + + # align safety + for (my $i = 0; $i < ($padding / 4); $i++) { + insn32(rand(0xffffffff)); + } + + for (my $rt = 0; $rt <= 15; $rt++) { + write_random_fpreg_var(1); # single + } + + for (my ($rt, $imm) = (0, 0); $rt < 32; $rt++) { + if ($fpregs{$rt} == 1) { + # flw rt, x10, imm + insn32(0x00002007 | ($imm << 20) | (10 << 15) | ($rt << 7)); + $imm += 4; + } + } +} + +# random initialize $GROUP_RVD registers. +sub write_random_fp64() +{ + # load floating point registers + my $align = 16; + my $padding = $align - ($bytecount % $align); + my $datalen = 16 * 8 + $padding; + + write_pc_adr(10, (4 * 4) + ($align - 1)); # insn 1 + write_align_reg(10, $align); # insn 2 + write_jump_fwd($datalen + 4); # insn 3 + + # align safety + for (my $i = 0; $i < ($padding / 4); $i++) { + insn32(rand(0xffffffff)); + } + + for (my $rt = 0; $rt <= 15; $rt++) { + write_random_fpreg_var(2); # double + } + + for (my ($rt, $imm) = (0, 0); $rt < 32; $rt++) { + if ($fpregs{$rt} == 2) { + # fld rt, x10, imm + insn32(0x00003007 | ($imm << 20) | (10 << 15) | ($rt << 7)); + $imm += 8; + } + } +} + +sub write_random_register_data($) +{ + my ($fp_enabled) = @_; + + if ($fp_enabled) { + # load floating point + init_fp_groups(); + write_random_fp32(); + write_random_fp64(); + } + + # general purpose registers + for (my $i = 1; $i < 32; $i++) { + if ($i != 2 && $i != 3 && $i!= 4) { + # TODO full 64 bit pattern instead of 32 + write_mov_ri($i, rand(0xffffffff)); + } + } + write_risuop($OP_COMPARE); +} + +# put PC + offset into a register. +# this must emit an instruction of 8 bytes. +sub write_pc_adr($$) +{ + my ($rd, $imm) = @_; + + # auipc rd, 0 + # addi rd, rd, imm + insn32(0x00000017 | $rd << 7); + insn32(0x00000013 | $imm << 20 | $rd << 15 | $rd << 7); +} + +# clear bits in register to satisfy alignment. +# Must use exactly 4 instruction-bytes +sub write_align_reg($$) +{ + my ($rd, $align) = @_; + my $imm = (-$align) & 0xfff; + die "bad alignment!" if ($align < 2); + + # andi rd, rd, ~(align - 1) + insn32(0x00007013 | $imm << 20 | $rd << 15 | $rd << 7); +} + +# jump ahead of n bytes starting from next instruction +sub write_jump_fwd($) +{ + my ($len) = @_; + + # 31 30 21 20 19 12 11 7 6 0 + # imm[20] imm[10:1] imm[11] imm[19:12] rd opcode + # 1 10 1 8 5 7 + # offset[20:1] dest JAL + my ($imm20, $imm1, $imm11, $imm12) = (($len & 0x100000) >> 20, ($len & 0x7fe) >> 1, + ($len & 0x800) >> 11, ($len & 0xff000) >> 12); + + # jal x0, len + insn32(0x0000006f | $imm20 << 31 | $imm1 << 21 | $imm11 << 20 | + $imm12 << 12); +} + +sub write_memblock_setup() +{ + # Write code which sets up the memory block for loads and stores. + # We set x10 to point to a block of 8K length + # of random data, aligned to the maximum desired alignment. + + my $align = $MAXALIGN; + my $datalen = 8192 + $align; + if (($align > 255) || !is_pow_of_2($align) || $align < 4) { + die "bad alignment!"; + } + + # set x10 to (datablock + (align-1)) & ~(align-1) + # datablock is at PC + (4 * 5 instructions) = PC + 20 + write_pc_adr(10, (4 * 5) + ($align - 1)); # insn 1 + write_align_reg(10, $align); # insn 2 + write_risuop($OP_SETMEMBLOCK); # insn 3 + write_jump_fwd($datalen + 4); # insn 4 + + for (my $i = 0; $i < $datalen / 4; $i++) { + insn32(rand(0xffffffff)); + } + # next: +} + +# Functions used in memory blocks to handle addressing modes. +# These all have the same basic API: they get called with parameters +# corresponding to the interesting fields of the instruction, +# and should generate code to set up the base register to be +# valid. They must return the register number of the base register. +# The last (array) parameter lists the registers which are trashed +# by the instruction (ie which are the targets of the load). +# This is used to avoid problems when the base reg is a load target. + +# Global used to communicate between align(x) and reg() etc. +my $alignment_restriction; + +sub align($) +{ + my ($a) = @_; + if (!is_pow_of_2($a) || ($a < 0) || ($a > $MAXALIGN)) { + die "bad align() value $a\n"; + } + $alignment_restriction = $a; +} + +sub write_get_offset() +{ + # Emit code to get a random offset within the memory block, of the + # right alignment, into x10. + # We require the offset to not be within 512 bytes of either + # end, to (more than) allow for the worst case data transfer, which is + # 8 * 512 bit regs + my $offset = (rand(8192 - 4096) + 2048) & ~($alignment_restriction - 1); + write_mov_ri(10, $offset); + write_risuop($OP_GETMEMBLOCK); +} + +sub reg($@) +{ + my ($base, @trashed) = @_; + write_get_offset(); + # Now x10 is the address we want to do the access to, + # so just move it into the basereg + if ($base != 10) { + write_mov_rr($base, 10); + write_mov_ri(10, 0); + } + if (grep $_ == $base, @trashed) { + return -1; + } + return $base; +} + +sub reg_plus_imm($$@) +{ + # Handle reg + immediate addressing mode + my ($base, $imm, @trashed) = @_; + if ($imm == 0) { + return reg($base, @trashed); + } + + write_get_offset(); + # Now x10 is the address we want to do the access to, + # so set the basereg by doing the inverse of the + # addressing mode calculation, ie base = x10 - imm + # We could do this more cleverly with a sub immediate. + if ($base != 10) { + write_mov_ri($base, $imm); + write_sub_rrr($base, 10, $base); + # Clear x10 to avoid register compare mismatches + # when the memory block location differs between machines. + write_mov_ri(10, 0); + } else { + # We borrow x11 as a temporary (not a problem + # as long as we don't leave anything in a register + # which depends on the location of the memory block) + write_mov_ri(11, $imm); + write_sub_rrr($base, 10, 11); + } + if (grep $_ == $base, @trashed) { + return -1; + } + return $base; +} + +sub stack_plus_imm($@) +{ + # Handle stack + immediate addressing mode + my ($imm, @trashed) = @_; + my $base = 2; + + # We borrow x11 as a temporary + write_mov_rr(11, $base); + + write_get_offset(); + # Now x10 is the address we want to do the access to, + # so set the basereg by doing the inverse of the + # addressing mode calculation, ie base = x10 - imm + # We could do this more cleverly with a sub immediate. + write_mov_ri($base, $imm); + write_sub_rrr($base, 10, $base); + # Clear x10 to avoid register compare mismatches + # when the memory block location differs between machines. + write_mov_ri(10, 0); + + if (grep $_ == $base, @trashed) { + return -1; + } + return $base; +} + +# X2 stack pointer, x3 global pointer, x4 thread pointer +# These registers should be reserved for signal handler. +sub greg($) +{ + my ($reg) = @_; + return $reg != 2 && $reg != 3 && $reg != 4; +} + +# Limit to current implementation, the base address register will be overide +sub gbase($) +{ + my ($reg) = @_; + return $reg != 2 && $reg != 3 && $reg != 4 && $reg != 0; +} + +# Fp registers only visiable to RVF +sub gfp32($) +{ + my ($reg) = @_; + return $fpregs{$reg} == $GROUP_RVF; +} + +# FP registers only visible to RVD +sub gfp64($) +{ + my ($reg) = @_; + return $fpregs{$reg} == $GROUP_RVD; +} + +# Legal round mode +sub grm($) +{ + my ($rm) = @_; + return $rm != 5 && $rm != 6; +} + +sub gen_one_insn($) +{ + # Given an instruction-details array, generate an instruction + my $constraintfailures = 0; + + INSN: while(1) { + my ($rec) = @_; + my $insn = int(rand(0xffffffff)); + my $insnname = $rec->{name}; + my $insnwidth = $rec->{width}; + my $fixedbits = $rec->{fixedbits}; + my $fixedbitmask = $rec->{fixedbitmask}; + my $constraint = $rec->{blocks}{"constraints"}; + my $memblock = $rec->{blocks}{"memory"}; + + $insn &= ~$fixedbitmask; + $insn |= $fixedbits; + + if (defined $constraint) { + # user-specified constraint: evaluate in an environment + # with variables set corresponding to the variable fields. + my $v = eval_with_fields($insnname, $insn, $rec, "constraints", $constraint); + if (!$v) { + $constraintfailures++; + if ($constraintfailures > 10000) { + print "10000 consecutive constraint failures for $insnname constraints string:\n$constraint\n"; + exit (1); + } + next INSN; + } + } + + # OK, we got a good one + $constraintfailures = 0; + + my $basereg; + + if (defined $memblock) { + # This is a load or store. We simply evaluate the block, + # which is expected to be a call to a function which emits + # the code to set up the base register and returns the + # number of the base register. + # we use 16 for riscv64, although often unnecessary and overkill. + align(16); + $basereg = eval_with_fields($insnname, $insn, $rec, "memory", $memblock); + } + + if ($is_rvc) { + insn16($insn >> 16); + # emits a nop to algin. + insn16(0x0001); + } else { + insn32($insn); + } + + if (defined $memblock) { + # only in stack_plus_imm mode, restore sp register + if ($basereg == 2) { + write_mov_rr($basereg, 11); + write_mov_ri(11, 0); + } elsif ($basereg != -1) { + # Clean up following a memory access instruction: + # we need to turn the (possibly written-back) basereg + # into an offset from the base of the memory block, + # to avoid making register values depend on memory layout. + # $basereg -1 means the basereg was a target of a load + # (and so it doesn't contain a memory address after the op) + write_mov_ri(10, 0); + write_risuop($OP_GETMEMBLOCK); + write_sub_rrr($basereg, $basereg, 10); + write_mov_ri(10, 0); + } + write_risuop($OP_COMPAREMEM); + } + return; + } +} + +sub write_risuop($) +{ + # instr with bits (6:0) == 1 1 0 1 0 1 1 are UNALLOCATED + my ($op) = @_; + insn32(0x0000006b | $op << 8); +} + +sub write_test_code($) +{ + my ($params) = @_; + + my $arch = $params->{ 'arch' }; + my $subarch = $params->{ 'subarch' }; + + if ($subarch && $subarch eq 'rv64c') { + $is_rvc = 1; + } + + my $numinsns = $params->{ 'numinsns' }; + my $fp_enabled = $params->{ 'fp_enabled' }; + my $outfile = $params->{ 'outfile' }; + + my %insn_details = %{ $params->{ 'details' } }; + my @keys = @{ $params->{ 'keys' } }; + + print "Enter write code", "\n"; + open_bin($outfile); + + # TODO better random number generator? + srand(0); + + print "Generating code using patterns: @keys...\n"; + progress_start(78, $numinsns); + + if (grep { defined($insn_details{$_}->{blocks}->{"memory"}) } @keys) { + write_memblock_setup(); + } + + # memblock setup doesn't clean its registers, so this must come afterwards. + write_random_register_data($fp_enabled); + + for my $i (1..$numinsns) { + my $insn_enc = $keys[int rand (@keys)]; + #dump_insn_details($insn_enc, $insn_details{$insn_enc}); + gen_one_insn($insn_details{$insn_enc}); + write_risuop($OP_COMPARE); + # Rewrite the registers periodically. This avoids the tendency + # for the fp registers to decay to NaNs and zeroes. + if ($periodic_reg_random && ($i % 100) == 0) { + write_random_register_data($fp_enabled); + } + progress_update($i); + } + write_risuop($OP_TESTEND); + progress_end(); + close_bin(); +} + +1; From patchwork Sat Jul 11 16:16:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11657937 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 95338618 for ; Sat, 11 Jul 2020 16:22:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 74827207D4 for ; Sat, 11 Jul 2020 16:22:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 74827207D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:45210 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIH5-00077c-Mw for patchwork-qemu-devel@patchwork.kernel.org; Sat, 11 Jul 2020 12:22:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54516) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDH-0007Eu-IZ; Sat, 11 Jul 2020 12:18:55 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:46455) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDD-0001M1-K4; Sat, 11 Jul 2020 12:18:55 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436351|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.194827-0.000235336-0.804938; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03297; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:42 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 08/11] riscv: Add standard test case Date: Sun, 12 Jul 2020 00:16:52 +0800 Message-Id: <20200711161655.2856-9-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- test_riscv64.s | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 test_riscv64.s diff --git a/test_riscv64.s b/test_riscv64.s new file mode 100644 index 0000000..22a22b6 --- /dev/null +++ b/test_riscv64.s @@ -0,0 +1,85 @@ +/***************************************************************************** + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei (T-Head) - initial implementation + * based on test_arm.s by Peter Maydell + *****************************************************************************/ + +/* Initialise the gp regs */ +li x1, 1 +#li x2, 2 # stack pointer +#li x3, 3 # global pointer +#li x4, 4 # thread pointer +li x5, 5 +li x6, 6 +li x7, 7 +li x8, 8 +li x9, 9 +li x10, 10 +li x11, 11 +li x12, 12 +li x13, 13 +li x14, 14 +li x15, 15 +li x16, 16 +li x17, 17 +li x18, 18 +li x19, 19 +li x20, 20 +li x21, 21 +li x22, 22 +li x23, 23 +li x24, 24 +li x25, 25 +li x26, 26 +li x27, 27 +li x28, 28 +li x29, 29 +li x30, 30 +li x31, 30 + +/* Initialise the fp regs */ +fcvt.d.lu f0, x0 +fcvt.d.lu f1, x1 +fcvt.d.lu f2, x2 +fcvt.d.lu f3, x3 +fcvt.d.lu f4, x4 +fcvt.d.lu f5, x5 +fcvt.d.lu f6, x6 +fcvt.d.lu f7, x7 +fcvt.d.lu f8, x8 +fcvt.d.lu f9, x9 +fcvt.d.lu f10, x10 +fcvt.d.lu f11, x11 +fcvt.d.lu f12, x12 +fcvt.d.lu f13, x13 +fcvt.d.lu f14, x14 +fcvt.d.lu f15, x15 +fcvt.d.lu f16, x16 +fcvt.d.lu f17, x17 +fcvt.d.lu f18, x18 +fcvt.d.lu f19, x19 +fcvt.d.lu f20, x20 +fcvt.d.lu f21, x21 +fcvt.d.lu f22, x22 +fcvt.d.lu f23, x23 +fcvt.d.lu f24, x24 +fcvt.d.lu f25, x25 +fcvt.d.lu f26, x26 +fcvt.d.lu f27, x27 +fcvt.d.lu f28, x28 +fcvt.d.lu f29, x29 +fcvt.d.lu f30, x30 +fcvt.d.lu f31, x31 + +/* do compare. + * The manual says instr with bits (6:0) == 1 1 0 1 0 1 1 are UNALLOCATED + */ +.int 0x0000006b +/* exit test */ +.int 0x0000016b From patchwork Sat Jul 11 16:16:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11657941 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6351D60D for ; Sat, 11 Jul 2020 16:23:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 42EDA207D4 for ; Sat, 11 Jul 2020 16:23:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 42EDA207D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:46558 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIHL-0007eo-Gd for patchwork-qemu-devel@patchwork.kernel.org; Sat, 11 Jul 2020 12:23:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDX-0007cS-O5; Sat, 11 Jul 2020 12:19:11 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:41426) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDV-0001M3-Ke; Sat, 11 Jul 2020 12:19:11 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1356943|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0178803-0.00146885-0.980651; FP=0|0|0|0|0|-1|-1|-1; HT=e01a16384; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:42 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 09/11] riscv: Define riscv struct reginfo Date: Sun, 12 Jul 2020 00:16:53 +0800 Message-Id: <20200711161655.2856-10-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: LIU Zhiwei --- risu_reginfo_riscv64.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 risu_reginfo_riscv64.h diff --git a/risu_reginfo_riscv64.h b/risu_reginfo_riscv64.h new file mode 100644 index 0000000..4536480 --- /dev/null +++ b/risu_reginfo_riscv64.h @@ -0,0 +1,28 @@ +/****************************************************************************** + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei(T-Head) - initial implementation + * based on Peter Maydell's risu_arm.c + *****************************************************************************/ + +#ifndef RISU_REGINFO_RISCV64_H +#define RISU_REGINFO_RISCV64_H + +struct reginfo { + uint64_t fault_address; + uint64_t regs[32]; + uint64_t fregs[32]; + uint64_t pc; + uint32_t flags; + uint32_t faulting_insn; + + /* FP */ + uint32_t fcsr; +}; + +#endif /* RISU_REGINFO_RISCV64_H */ From patchwork Sat Jul 11 16:16:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11657927 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 027F160D for ; Sat, 11 Jul 2020 16:20:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D6CD62075F for ; Sat, 11 Jul 2020 16:20:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D6CD62075F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:57566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIEK-0000em-1s for patchwork-qemu-devel@patchwork.kernel.org; Sat, 11 Jul 2020 12:20:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54526) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDH-0007F6-Qb; Sat, 11 Jul 2020 12:18:55 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:44399) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDD-0001M9-FD; Sat, 11 Jul 2020 12:18:55 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436318|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0983034-0.000812451-0.900884; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03307; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:43 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 10/11] riscv: Implement payload load interfaces Date: Sun, 12 Jul 2020 00:16:54 +0800 Message-Id: <20200711161655.2856-11-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" When a risu op emits, the signal handler wll take over execution before running the payload again. The signal handler need some interfaces, such as setting struct reginfo and the comparison of struct reginfo. Signed-off-by: LIU Zhiwei --- risu_reginfo_riscv64.c | 132 +++++++++++++++++++++++++++++++++++++++++ risu_riscv64.c | 47 +++++++++++++++ 2 files changed, 179 insertions(+) create mode 100644 risu_reginfo_riscv64.c create mode 100644 risu_riscv64.c diff --git a/risu_reginfo_riscv64.c b/risu_reginfo_riscv64.c new file mode 100644 index 0000000..763001f --- /dev/null +++ b/risu_reginfo_riscv64.c @@ -0,0 +1,132 @@ +/****************************************************************************** + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei (T-Head) - initial implementation + * based on Peter Maydell's risu_arm.c + *****************************************************************************/ + +#include +#include +#include +#include /* for FPSIMD_MAGIC */ +#include +#include +#include +#include +#include +#include + +#include "risu.h" +#include "risu_reginfo_riscv64.h" + +const struct option * const arch_long_opts; +const char * const arch_extra_help; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} + +const int reginfo_size(void) +{ + return sizeof(struct reginfo); +} + +/* reginfo_init: initialize with a ucontext */ +void reginfo_init(struct reginfo *ri, ucontext_t *uc) +{ + int i; + union __riscv_mc_fp_state *fp; + /* necessary to be able to compare with memcmp later */ + memset(ri, 0, sizeof(*ri)); + + for (i = 0; i < 32; i++) { + ri->regs[i] = uc->uc_mcontext.__gregs[i]; + } + + ri->regs[2] = 0xdeadbeefdeadbeef; + ri->regs[3] = 0xdeadbeefdeadbeef; + ri->regs[4] = 0xdeadbeefdeadbeef; + ri->pc = uc->uc_mcontext.__gregs[0] - image_start_address; + ri->regs[0] = ri->pc; + ri->faulting_insn = *((uint32_t *) uc->uc_mcontext.__gregs[0]); + fp = &uc->uc_mcontext.__fpregs; +#if __riscv_flen == 64 + ri->fcsr = fp->__d.__fcsr; + + for (i = 0; i < 32; i++) { + ri->fregs[i] = fp->__d.__f[i]; + } +#else +# error "Unsupported fp length" +#endif +} + +/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ +int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2) +{ + return memcmp(r1, r2, reginfo_size()) == 0; +} + +/* reginfo_dump: print state to a stream, returns nonzero on success */ +int reginfo_dump(struct reginfo *ri, FILE * f) +{ + int i; + fprintf(f, " faulting insn %08x\n", ri->faulting_insn); + + for (i = 1; i < 32; i++) { + fprintf(f, " X%-2d : %016" PRIx64 "\n", i, ri->regs[i]); + } + + fprintf(f, " pc : %016" PRIx64 "\n", ri->pc); + fprintf(f, " fcsr : %08x\n", ri->fcsr); + + for (i = 0; i < 32; i++) { + fprintf(f, " F%-2d : %016" PRIx64 "\n", i, ri->fregs[i]); + } + + return !ferror(f); +} + +/* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero=ok */ +int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) +{ + int i; + fprintf(f, "mismatch detail (master : apprentice):\n"); + if (m->faulting_insn != a->faulting_insn) { + fprintf(f, " faulting insn mismatch %08x vs %08x\n", + m->faulting_insn, a->faulting_insn); + } + for (i = 1; i < 32; i++) { + if (m->regs[i] != a->regs[i]) { + fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n", + i, m->regs[i], a->regs[i]); + } + } + + if (m->pc != a->pc) { + fprintf(f, " pc : %016" PRIx64 " vs %016" PRIx64 "\n", + m->pc, a->pc); + } + + if (m->fcsr != a->fcsr) { + fprintf(f, " fcsr : %08x vs %08x\n", m->fcsr, a->fcsr); + } + + for (i = 0; i < 32; i++) { + if (m->fregs[i] != a->fregs[i]) { + fprintf(f, " F%-2d : " + "%016" PRIx64 " vs " + "%016" PRIx64 "\n", i, + (uint64_t) m->fregs[i], + (uint64_t) a->fregs[i]); + } + } + + return !ferror(f); +} diff --git a/risu_riscv64.c b/risu_riscv64.c new file mode 100644 index 0000000..06dbb2d --- /dev/null +++ b/risu_riscv64.c @@ -0,0 +1,47 @@ +/****************************************************************************** + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei(Linaro) - initial implementation + * based on Peter Maydell's risu_arm.c + *****************************************************************************/ + +#include "risu.h" + +void advance_pc(void *vuc) +{ + ucontext_t *uc = vuc; + uc->uc_mcontext.__gregs[0] += 4; +} + +void set_ucontext_paramreg(void *vuc, uint64_t value) +{ + ucontext_t *uc = vuc; + uc->uc_mcontext.__gregs[10] = value; +} + +uint64_t get_reginfo_paramreg(struct reginfo *ri) +{ + return ri->regs[10]; +} + +int get_risuop(struct reginfo *ri) +{ + /* Return the risuop we have been asked to do + * (or -1 if this was a SIGILL for a non-risuop insn) + */ + uint32_t insn = ri->faulting_insn; + uint32_t op = (insn & 0xf00) >> 8; + uint32_t key = insn & ~0xf00; + uint32_t risukey = 0x0000006b; + return (key != risukey) ? -1 : op; +} + +uintptr_t get_pc(struct reginfo *ri) +{ + return ri->pc; +} From patchwork Sat Jul 11 16:16:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 11657935 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A4A2618 for ; Sat, 11 Jul 2020 16:21:35 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EEB56207DD for ; Sat, 11 Jul 2020 16:21:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EEB56207DD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:38584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1juIFq-0004R3-40 for patchwork-qemu-devel@patchwork.kernel.org; Sat, 11 Jul 2020 12:21:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54548) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDI-0007FN-C5; Sat, 11 Jul 2020 12:18:56 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:60698) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1juIDD-0001M7-Ix; Sat, 11 Jul 2020 12:18:56 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07440338|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.325301-0.00391217-0.670787; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03268; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.I0GMGMe_1594484317; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.I0GMGMe_1594484317) by smtp.aliyun-inc.com(10.147.44.129); Sun, 12 Jul 2020 00:18:43 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 11/11] riscv: Add configure script Date: Sun, 12 Jul 2020 00:16:55 +0800 Message-Id: <20200711161655.2856-12-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> References: <20200711161655.2856-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/11 12:18:40 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" For RV64 risu, make CFLAGS="-march=rv64g" Signed-off-by: LIU Zhiwei --- configure | 4 +- upstream/configure | 204 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 207 insertions(+), 1 deletion(-) create mode 100644 upstream/configure diff --git a/configure b/configure index ca2d7db..00624d3 100755 --- a/configure +++ b/configure @@ -58,6 +58,8 @@ guess_arch() { ARCH="m68k" elif check_define __powerpc64__ ; then ARCH="ppc64" + elif check_define __riscv && check_define _LP64; then + ARCH="riscv64" else echo "This cpu is not supported by risu. Try -h. " >&2 exit 1 @@ -139,7 +141,7 @@ Some influential environment variables: prefixed with the given string. ARCH force target architecture instead of trying to detect it. - Valid values=[arm|aarch64|ppc64|ppc64le|m68k] + Valid values=[arm|aarch64|ppc64|ppc64le|m68k|riscv64] CC C compiler command CFLAGS C compiler flags diff --git a/upstream/configure b/upstream/configure new file mode 100644 index 0000000..297cd3a --- /dev/null +++ b/upstream/configure @@ -0,0 +1,204 @@ +#!/bin/sh +# simple risu configure script +# +# Copyright (c) 2013 Linaro Limited +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# Claudio Fontana (Linaro) - initial implementation + +# Locate the directory where this configure script is +SRCDIR="$(cd "$(dirname "$0")"; pwd)" + +# Temporary directory used for files created by this script. +# Like autoconf (and like QEMU) we put this directory in the +# build directory, which means we can just give it a fixed name and +# blow it away when configure is run, and we don't need to jump +# through complicated hoops to delete it when configure exits +# abnormally (it may be useful for debug purposes on an +# abnormal exit). +tmp_dir="config-temp" +rm -rf "$tmp_dir" +mkdir -p "$tmp_dir" +if [ $? -ne 0 ]; then + echo "ERROR: could not create temporary directory" + exit 1 +fi + +compile() { + $CC $CFLAGS -c -o ${1}.o ${1}.c 2>/dev/null +} + +link() { + $LD $LDFLAGS -l${2} -o ${1} ${1}.o 2>/dev/null +} + +check_define() { + c=${tmp_dir}/check_define_${1} + cat > ${c}.c <&2 + exit 1 + fi + else + echo "This cpu is not supported by risu. Try -h. " >&2 + exit 1 + fi +} + +check_type() { + c=${tmp_dir}/check_type_${1} + cat > ${c}.c < +#include +#include +#include + +int main(void) { $1 thisone; return 0; } +EOF + compile $c +} + +check_lib() { + c=${tmp_dir}/check_lib${1} + cat > ${c}.c < +#include <$2.h> + +int main(void) { $3; return 0; } +EOF + compile $c && link $c $1 +} + +generate_config() { + cfg=config.h + echo "generating config.h..." + + echo "/* config.h - generated by the 'configure' script */" > $cfg + echo "#ifndef CONFIG_H" >> $cfg + echo "#define CONFIG_H 1" >> $cfg + + if check_lib z zlib "zlibVersion()"; then + echo "#define HAVE_ZLIB 1" >> $cfg + LDFLAGS=-lz + fi + + echo "#endif /* CONFIG_H */" >> $cfg + + echo "...done" +} + +generate_makefilein() { + m=Makefile.in + echo "generating Makefile.in..." + + echo "# Makefile.in - generated by the 'configure' script" > $m + echo "ARCH:=${ARCH}" >> $m + echo "CC:=${CC}" >> $m + echo "CPPFLAGS:=${CPPFLAGS}" >> $m + echo "LDFLAGS:=${LDFLAGS}" >> $m + echo "AS:=${AS}" >> $m + echo "OBJCOPY:=${OBJCOPY}" >> $m + echo "OBJDUMP:=${OBJDUMP}" >> $m + echo "STATIC:=${STATIC}" >> $m + echo "SRCDIR:=${SRCDIR}" >> $m + echo "BUILD_INC:=${BUILD_INC}" >> $m + + echo "...done" +} + +usage() { + cat < + + AS assembler command + OBJCOPY object copy utility command + OBJDUMP object dump utility command + +EOF +} + +# STARTUP: entry point +STATIC="" + +for opt do + case "$opt" in + --help | -h) + usage; + exit 0;; + --static | -s) + STATIC="-static" + ;; + + esac +done + +CC="${CC-${CROSS_PREFIX}gcc}" +AS="${AS-${CROSS_PREFIX}as}" +LD="${LD-${CROSS_PREFIX}ld}" +OBJCOPY="${OBJCOPY-${CROSS_PREFIX}objcopy}" +OBJDUMP="${OBJDUMP-${CROSS_PREFIX}objdump}" + +if test "x${ARCH}" = "x"; then + guess_arch +fi + +# Are we in a separate build tree? If so, link the Makefile +# so that 'make' works. +if test ! -e Makefile || test -s Makefile; then + echo "linking Makefile..." + BUILD_INC="-I $(pwd)" + ln -sf "${SRCDIR}/Makefile" . +fi + +generate_config +generate_makefilein + +rm -r "$tmp_dir" + +echo "type 'make' to start the build" +exit 0 +