From patchwork Wed Jul 15 22:44:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666369 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 99344138C for ; Wed, 15 Jul 2020 22:45:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7CA23206F4 for ; Wed, 15 Jul 2020 22:45:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Cc3Q0Mhl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727780AbgGOWph (ORCPT ); Wed, 15 Jul 2020 18:45:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726660AbgGOWpg (ORCPT ); Wed, 15 Jul 2020 18:45:36 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BDC8C061755; Wed, 15 Jul 2020 15:45:35 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id a6so4707833wrm.4; Wed, 15 Jul 2020 15:45:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yQxWpRgQb3Xq+P5ehR8ew7q9vK97Ab3OJ4StJNb/DKE=; b=Cc3Q0MhlbMUqI2mmJ4bjZ179I+46uu9zKgkpNPgpJOm3L/hq/V0QhAJdofKy6Z2OVT eL+NI6Nl9UeopwhGW+y7+LPnEJjBE2wi4hri9+3ivsQ+LoBV7yxSWNFCogPIlVcWAfCi pArSktSFfGpBXCXIIQzVOMUrh41iHsFQin8wP1ep2mhNzAB9h9oJDDVssuyUVe5aSAMA bSkP9E8pPkJ1d4A38mwCK6THKgNXYBj9hbw+OHYiKQZvTFOc63rXufRT9DGc4OBTfXUh TwQ+cLWaKUYkXRbIHGiBeaND5vfo4jGERYu5MUGeOspSoWVi1kH0vyV7a/EBhykNVUu0 U8Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yQxWpRgQb3Xq+P5ehR8ew7q9vK97Ab3OJ4StJNb/DKE=; b=saRxwr8MjYBbUN66wYevt4LptoYoqN5Mh2c76qu7HtaVPKbpZh3deevooSf4MSS2B2 jVVSLqlRBlgVC4LHlNiCInZffrFu3IACBkrGHgA3J5nHOHGtCFLBGcZMHqR3eE8nlt7G pOBv2zaMkspygT8S2Vj9bH3hoxxv6Ca77NY/AnTu48jo2QAxXtn1YMw+mM/jjtUuuFgg nFZAB9a29ES3ldz6ItrzzM6ynLrQvHsLqrteayJpctCa9KN7E1nUvrJUkdaRlWnicgP0 fV9PscJcPfKkvll+zMohddmGRI74RZe0ofNGXt9hxUkrvoY2d+cedjjoWThhlpZSS4gK ewfA== X-Gm-Message-State: AOAM5337E+u6valFzzKtrwxWLbff7Xt3tSUbqllzRdC2KZ32Jpj1t/16 HnIEL5SeiyWdN2Bh4YSZ/zU= X-Google-Smtp-Source: ABdhPJynPlfZ8E65vRGR15Zc/F3arwLCSga7YwW6ZqouIkPDIQavfVH4Qflw3E24rqBWyWnXdKz/EQ== X-Received: by 2002:adf:ed47:: with SMTP id u7mr1939480wro.201.1594853134203; Wed, 15 Jul 2020 15:45:34 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-7-31-173.retail.telecomitalia.it. [87.7.31.173]) by smtp.googlemail.com with ESMTPSA id b186sm5759898wme.1.2020.07.15.15.45.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 15:45:33 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Amit Kucheria , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 1/7] ipq806x: gcc: add support for child probe Date: Thu, 16 Jul 2020 00:44:56 +0200 Message-Id: <20200715224503.30462-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200715224503.30462-1-ansuelsmth@gmail.com> References: <20200715224503.30462-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for child probing needed for tsens driver that share the seme regs of gcc for this platform. Signed-off-by: Ansuel Smith --- drivers/clk/qcom/gcc-ipq806x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index a8456e09c44d..d6b7adb4be38 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -3089,7 +3089,7 @@ static int gcc_ipq806x_probe(struct platform_device *pdev) regmap_write(regmap, 0x3cf8, 8); regmap_write(regmap, 0x3d18, 8); - return 0; + return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); } static struct platform_driver gcc_ipq806x_driver = { From patchwork Wed Jul 15 22:44:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666405 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CFFA7138C for ; Wed, 15 Jul 2020 22:46:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B6D8E2075B for ; Wed, 15 Jul 2020 22:46:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VTw/Eenj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727829AbgGOWpj (ORCPT ); Wed, 15 Jul 2020 18:45:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727810AbgGOWpi (ORCPT ); Wed, 15 Jul 2020 18:45:38 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16125C061755; Wed, 15 Jul 2020 15:45:38 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id o8so7542946wmh.4; Wed, 15 Jul 2020 15:45:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NMGpsGsTomyvbhuxUBbF2KBZ5U7/Gj4W0Zm7Cz/Tuck=; b=VTw/EenjHg9eQcYDVFcDf6W2uX4oCqGrAXTDlOI8To0QXZsCmYqI6r7ZhbfoxjYbmF swyUDZGSHBSmFm2JhU+HSTUL12xeRcGr2qkorbYZt7bzSNDJHlUVwoNPZxHiDL8Dra2k qyGfNXnq1fWXJbrVOrl/L5888J+5EY7VBlSN1PnvemkkV6WN1alozCgxq1k5uws7GDcE 8ZKQ251dbm5POrpVYMdG9kuYyGyJiF1Dq8/s5c28fZAV5vxi7eP8zGFuGBUhdhVPTGnh lV2km3WmnNSaK18uD/FbZB9uYkmXcp8VaMS6BJNgq4/89Hf8vuC2JMuuS7VeJw1o3nqQ ykqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NMGpsGsTomyvbhuxUBbF2KBZ5U7/Gj4W0Zm7Cz/Tuck=; b=Xkb8Wb1FixSHcjAzN/pVDu76Zgfa/e+ognMMdtEVQKsnrOOgEwt4DDnumGKuD8Gtyo wsNW1G+Agd7WpBxrgWaM6/IMBJ2GcFZZuksppOSpapJE4Z4e+/rMt4yEeIaFk+YtISYF uCJ5kDrAmOcLxEcE3PUDGWS/CZtY8URUDHARpBpZ4zfIp0jC/Vbpr78RNxoM2d/IpJ+q vLS+n2GCt2Itbw9LdwLEM+4LwSBgbQ8Es2+05TRyrSxITCDXMyusbtVZZBqWLUIvXeT8 Zo7+QktJKPPqylVBTuHLQMAAZj8UXPDwFT/hXI3NRhTanGT/R+1IF+6hmn/g2YJ9cGi0 oRHw== X-Gm-Message-State: AOAM531YYyZLc3ByjFS1zuNBsWF8wmNEeVUgt7O0Hdx6FO+tcsbbcY+4 RW9JZhrTBCMl6+vC1AiUv7c= X-Google-Smtp-Source: ABdhPJyTSJas4sCv/QyWfka6X6q0Nu+BkSg5RVP351kIoFh7+8x30AHm/OJUHCm7Cq2r3Oaib39pzA== X-Received: by 2002:a1c:c3c5:: with SMTP id t188mr1760579wmf.53.1594853136767; Wed, 15 Jul 2020 15:45:36 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-7-31-173.retail.telecomitalia.it. [87.7.31.173]) by smtp.googlemail.com with ESMTPSA id b186sm5759898wme.1.2020.07.15.15.45.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 15:45:36 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Amit Kucheria , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 2/7] drivers: thermal: tsens: try load regmap from parent for 8960 Date: Thu, 16 Jul 2020 00:44:57 +0200 Message-Id: <20200715224503.30462-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200715224503.30462-1-ansuelsmth@gmail.com> References: <20200715224503.30462-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Devices based on 8060 tsens driver (ipq8064) use the reg of the gcc driver. Try to load the regmap of the parent as they share the same regs. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 2a28a5af209e..45788eb3c666 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "tsens.h" @@ -168,8 +169,17 @@ static int init_8960(struct tsens_priv *priv) u32 reg_cntl; priv->tm_map = dev_get_regmap(priv->dev, NULL); - if (!priv->tm_map) + if (!priv->tm_map) { + struct device *parent = priv->dev->parent; + + if (parent) + priv->tm_map = syscon_node_to_regmap(parent->of_node); + } + + if (!priv->tm_map || IS_ERR(priv->tm_map)) { + dev_err(priv->dev, "failed to get tsens regmap\n"); return -ENODEV; + } /* * The status registers for each sensor are discontiguous From patchwork Wed Jul 15 22:44:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666371 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 27D3E138C for ; Wed, 15 Jul 2020 22:45:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E10D20791 for ; Wed, 15 Jul 2020 22:45:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KZL24XKz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727886AbgGOWpn (ORCPT ); Wed, 15 Jul 2020 18:45:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727858AbgGOWpk (ORCPT ); Wed, 15 Jul 2020 18:45:40 -0400 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B0CFC061755; Wed, 15 Jul 2020 15:45:40 -0700 (PDT) Received: by mail-wr1-x443.google.com with SMTP id f7so4734237wrw.1; Wed, 15 Jul 2020 15:45:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z7hfnd49qzQu+v3pW4+QTWy4zDs6kHByKCCdtVpj2B8=; b=KZL24XKzrPPkNZ0tREld/Dbmj74vqwi5XukLRQ5rcwQNCfFXJfCSQ58+hQjGwrdXbo iuE8GSCK0zU2MiIA5xGh/akZIEtip9ryXt3LBPTBlNogZ7TOR3oVoC0v3bKdmll2AppC Nngf/VXC8C4N4fmliCl2s+8xr6p47SbUUhLO/2oCIjY2qfrc5wXueNB17zDsYbHjfQZq O6HvxHXBxrQ4l6Ri/5EH3TD/3xr61QypVbTOV2zTjNteWfSc76vlfystMcLBfeWfM1zx 0RcwZKvYVxBoGwmvsKXqy9348B1s8Q8hlXe8hWsXv+Li5c1Penhw6aVea0MBYHuGs1IV MA8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z7hfnd49qzQu+v3pW4+QTWy4zDs6kHByKCCdtVpj2B8=; b=qfi5TW4PtI09fI/pgmDYt9fqTcUiq6LLTz+qvE//EipOZkp/2vR+YPeo4gRakAtZp/ QfGOgmPoTGADY/yNPfpNrOIDotdVvFcXBHll4BAY2yykOyLKFfh6RSFLwGzYrzWnsgzd eKHT3pRULPytwf/YsdCRbZ06gReWDI76ohbraqQaFg7nG4LYXx2vNEioXAdi4N5pQAV6 6pf1xtEpqC1bVH1pLTg+AhonTiyN8rQmAaPb9zycUm1N0/w+OQNxjHTdY9Tw/c87Qfyu WIRYaKh4IxXNoHN6MteipEveiOqzyoX2mMGBiAoWE9dYkSGLXXIzWB6hQT8aQafKeU7f X2Uw== X-Gm-Message-State: AOAM5315Lg10k6XBI0b4grpna+Mt+RhmfiAmu8hoXJUKZKWNjmlntwtH gUhPdWo/xwL8ujP/sGGBegA= X-Google-Smtp-Source: ABdhPJw+sRw023UQ9OoaCzEgBNyuSx+iXUOQt5tFvnnXqskiKzHH09rtVQzDd0XDIphacs5qhkvlMw== X-Received: by 2002:a5d:43d0:: with SMTP id v16mr1934547wrr.296.1594853139122; Wed, 15 Jul 2020 15:45:39 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-7-31-173.retail.telecomitalia.it. [87.7.31.173]) by smtp.googlemail.com with ESMTPSA id b186sm5759898wme.1.2020.07.15.15.45.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 15:45:38 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Amit Kucheria , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 3/7] drivers: thermal: tsens: add ipq8064 support Date: Thu, 16 Jul 2020 00:44:58 +0200 Message-Id: <20200715224503.30462-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200715224503.30462-1-ansuelsmth@gmail.com> References: <20200715224503.30462-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Ipq8064 SoCs based use the same 8960 driver. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 39c4462e38f6..2985a064a0d1 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -907,6 +907,9 @@ static const struct of_device_id tsens_table[] = { .compatible = "qcom,msm8996-tsens", .data = &data_8996, }, { + .compatible = "qcom,ipq8064-tsens", + .data = &data_8060, + } { .compatible = "qcom,tsens-v1", .data = &data_tsens_v1, }, { From patchwork Wed Jul 15 22:44:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666377 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D629A13B1 for ; Wed, 15 Jul 2020 22:45:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BACCF20787 for ; Wed, 15 Jul 2020 22:45:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WkvYi7Xi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727924AbgGOWpr (ORCPT ); Wed, 15 Jul 2020 18:45:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727883AbgGOWpn (ORCPT ); Wed, 15 Jul 2020 18:45:43 -0400 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEB73C061755; Wed, 15 Jul 2020 15:45:42 -0700 (PDT) Received: by mail-wr1-x443.google.com with SMTP id z13so4698342wrw.5; Wed, 15 Jul 2020 15:45:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ouNkdpPb5LfjBppsBgr8ZNpXkvCcGxxnoBprAfZ1JeY=; b=WkvYi7XiWtbYrL8OIwO2ySAi4bbVdFrqWaPKgt5mr4TGslG/hzJxVYYaWz9txApQ2G KnqfvOZCslX9mwQ/bUvGwxlNHZ9wRnmCGTs5E/17oOCj68pQEyh9JcTKC9BU52BZfHAG Y8KeeQiVPfxRVqIQwDmY47UUPn/XdmSAFgOtxuQnVWWbKBU7b5G8k9OLhlwCMpPzCrt7 b/uRn1/bjetlBVzSU+3D3CLWoVKgXX1hBpl1J9en1lt3k7aAiKSd+J+uraFiDFdhIKZ8 DJISwqzbfafpPfrQcmb/iCpmljmU9tYClz4wPUlrCF/UhPNEREH0KH3EoYS+F/ypbTl8 EGog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ouNkdpPb5LfjBppsBgr8ZNpXkvCcGxxnoBprAfZ1JeY=; b=g22vMvQ/Rvso1k4ijFf5iYY+1ZLDT1ZgCG8Hi4hno0sv0JsvMfXI9IsTxb3ntrHWFu XWGFy4IWAcRqVY6Dxyli3u67KY8rUYj1SShDA1a/fi9ixW4WfKM4NDLXvoRj1gb4HPFT IqkdFIxZYUyLcGqqykM1I4LG0AWXPdD9EuYdj1xJmGUV335TaUr59FXw6gujFCVFsO1c WN7rW6DS0V2sUt1ZtQhmCUs3zcybewujjw+/9jrvFfY5ayNkocUIolVN/FNkX7jVZ/n7 Y7bgb1OPwH53qcggKIwdA/5oNxYwlaDmQ/+C7FWKTi+sjRMYZ8Ya3eZLTHM2UKyswUZh bvLA== X-Gm-Message-State: AOAM531crwCIZ2WZuj5cPfngOUe57y/x49pkNq3JI24Wuzf2VA/XTxxG UVhyBm8ebRXduxgIHxFV2eQ= X-Google-Smtp-Source: ABdhPJyHK36hRpG+DsS7IJV19gbkMKsXNP3bpxDwfjN74paH23yKdgo2TfAZiJ1Jl0Do2oDteSp8Zg== X-Received: by 2002:a5d:68c3:: with SMTP id p3mr1898881wrw.386.1594853141525; Wed, 15 Jul 2020 15:45:41 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-7-31-173.retail.telecomitalia.it. [87.7.31.173]) by smtp.googlemail.com with ESMTPSA id b186sm5759898wme.1.2020.07.15.15.45.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 15:45:40 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Amit Kucheria , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 4/7] dt-bindings: thermal: tsens: document ipq8064 bindings Date: Thu, 16 Jul 2020 00:44:59 +0200 Message-Id: <20200715224503.30462-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200715224503.30462-1-ansuelsmth@gmail.com> References: <20200715224503.30462-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the use of bindings used for ipq8064 SoCs tsens. ipq8064 use the same gcc regs and is set as a child of the qcom gcc. Signed-off-by: Ansuel Smith --- .../bindings/thermal/qcom-tsens.yaml | 50 ++++++++++++++++--- 1 file changed, 43 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index d7be931b42d2..9d480e3943a2 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -19,6 +19,11 @@ description: | properties: compatible: oneOf: + - description: msm9860 TSENS based + items: + - enum: + - qcom,ipq8064-tsens + - description: v0.1 of TSENS items: - enum: @@ -85,12 +90,18 @@ properties: Number of cells required to uniquely identify the thermal sensors. Since we have multiple sensors this is set to 1 +required: + - compatible + - interrupts + - "#thermal-sensor-cells" + allOf: - if: properties: compatible: contains: enum: + - qcom,ipq8064-tsens - qcom,msm8916-tsens - qcom,msm8974-tsens - qcom,msm8976-tsens @@ -111,17 +122,42 @@ allOf: interrupt-names: minItems: 2 -required: - - compatible - - reg - - "#qcom,sensors" - - interrupts - - interrupt-names - - "#thermal-sensor-cells" + - if: + properties: + compatible: + contains: + enum: + - qcom,tsens-v0_1 + - qcom,tsens-v1 + - qcom,tsens-v2 + + then: + required: + - reg + - interrupt-names + - "#qcom,sensors" additionalProperties: false examples: + - | + #include + // Example msm9860 based SoC (ipq8064): + gcc: clock-controller { + + /* ... */ + + tsens: thermal-sensor { + compatible = "qcom,ipq8064-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_calsel>; + nvmem-cell-names = "calib", "calib_sel"; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + - | #include // Example 1 (legacy: for pre v1 IP): From patchwork Wed Jul 15 22:45:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666397 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C896A138C for ; Wed, 15 Jul 2020 22:46:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AB8112075B for ; Wed, 15 Jul 2020 22:46:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="B1tiYIV/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727925AbgGOWpr (ORCPT ); Wed, 15 Jul 2020 18:45:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727858AbgGOWpp (ORCPT ); Wed, 15 Jul 2020 18:45:45 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E0C9C061755; Wed, 15 Jul 2020 15:45:45 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id z13so4698495wrw.5; Wed, 15 Jul 2020 15:45:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O+FmZM4sbG++/Lg/X0btfSIQeydpuUi98YpggK+AxGs=; b=B1tiYIV/QuvHXnO1khWcLPxyV7kTmVRvQLCkFwuVBjhHtdqbHR7bf0qf0m9DtXk9iB DY+VsO9luCU0s5OQSxWIbUjAFuce4mFPU7xqbH8ZJV2vVEUIORbL9AyJEIeAeEyjoxwV It7LOlIfvQmX1AQeSQsSkKqj4E8nYFwOJMK41ItNvmEVPsoCzDi4+mpV3W1/1fg6S9yg y3beXaO59DnLrOxnFC4Gx9aTmqic7nz91LaDFEQihirs3sMahzLnVNnuV8oX4uMHgdPs 43TUBTFNPw4N4bd3rdyKdiQvwt2qlwawuoIf8i7odtxmoYAEG5GLfU/I+dn99U8RN3yk gC6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O+FmZM4sbG++/Lg/X0btfSIQeydpuUi98YpggK+AxGs=; b=bXdH+y5XDAg+oU0CygdDlWaECmBnP8DH3u2wDIw383Riy314Dy28GhpsXDRXNthArb qKBr2WSBp5Gu3Zxo9lFcCUpLZo4XrKq9WcstIIbV2kYW0HS2jFjTDc6NqHva095FYRr5 jsrDwm+z2RKsElKN7iU8IOBFPA7K4BUeZTmsGMQchgY9w9ce4CnVzLgCWZ3i1lCteIUE TZpd7pcNpyJjeVeA7785psOPMCKiHRnkiUYsH22VDLLFNd4Xd2QteYVLNK3iRu0GHB/H Hsgg/242Iw5v2SvrZ+sO17BeFu3Dhixp8ISo773uR/9PjJlEgDM2Zc7FZ3d3Y6YV9n4J Ky3w== X-Gm-Message-State: AOAM530kbTR4f7fAeoO8IC39P2CGyi+J22guvImXHFiQSTieam0nIQgN C+0ktWjm1gyTyxtIjCVxLqE= X-Google-Smtp-Source: ABdhPJwqLcCmzkURTdWdyDOQm22RvWu7BckFtWmYrmmm9nIhNWwBsa1Npq39KmgJ28O221BzJVpx6Q== X-Received: by 2002:adf:f445:: with SMTP id f5mr1853033wrp.339.1594853144024; Wed, 15 Jul 2020 15:45:44 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-7-31-173.retail.telecomitalia.it. [87.7.31.173]) by smtp.googlemail.com with ESMTPSA id b186sm5759898wme.1.2020.07.15.15.45.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 15:45:43 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Amit Kucheria , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 5/7] drivers: thermal: tsens: add interrupt support for 9860 driver Date: Thu, 16 Jul 2020 00:45:00 +0200 Message-Id: <20200715224503.30462-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200715224503.30462-1-ansuelsmth@gmail.com> References: <20200715224503.30462-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add interrupt support for 9860 tsens driver used to set thermal trip point for the system. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 196 +++++++++++++++++++++++++++--- drivers/thermal/qcom/tsens.h | 1 + 2 files changed, 183 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 45788eb3c666..b302bfb924a6 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "tsens.h" @@ -27,7 +28,6 @@ /* CNTL_ADDR bitmasks */ #define EN BIT(0) #define SW_RST BIT(1) -#define SENSOR0_EN BIT(3) #define SLP_CLK_ENA BIT(26) #define SLP_CLK_ENA_8660 BIT(24) #define MEASURE_PERIOD 1 @@ -41,14 +41,26 @@ #define THRESHOLD_ADDR 0x3624 /* THRESHOLD_ADDR bitmasks */ +#define THRESHOLD_MAX_CODE 0x20000 +#define THRESHOLD_MIN_CODE 0 #define THRESHOLD_MAX_LIMIT_SHIFT 24 #define THRESHOLD_MIN_LIMIT_SHIFT 16 #define THRESHOLD_UPPER_LIMIT_SHIFT 8 #define THRESHOLD_LOWER_LIMIT_SHIFT 0 +#define THRESHOLD_MAX_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_MAX_LIMIT_SHIFT) +#define THRESHOLD_MIN_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_MIN_LIMIT_SHIFT) +#define THRESHOLD_UPPER_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_UPPER_LIMIT_SHIFT) +#define THRESHOLD_LOWER_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_LOWER_LIMIT_SHIFT) /* Initial temperature threshold values */ -#define LOWER_LIMIT_TH 0x50 -#define UPPER_LIMIT_TH 0xdf +#define LOWER_LIMIT_TH_8960 0x50 +#define UPPER_LIMIT_TH_8960 0xdf +#define LOWER_LIMIT_TH_8064 0x9d /* 95C */ +#define UPPER_LIMIT_TH_8064 0xa6 /* 105C */ #define MIN_LIMIT_TH 0x0 #define MAX_LIMIT_TH 0xff @@ -57,6 +69,169 @@ #define TRDY_MASK BIT(7) #define TIMEOUT_US 100 +#define TSENS_EN BIT(0) +#define TSENS_SW_RST BIT(1) +#define TSENS_ADC_CLK_SEL BIT(2) +#define SENSOR0_EN BIT(3) +#define SENSOR1_EN BIT(4) +#define SENSOR2_EN BIT(5) +#define SENSOR3_EN BIT(6) +#define SENSOR4_EN BIT(7) +#define SENSORS_EN (SENSOR0_EN | SENSOR1_EN | \ + SENSOR2_EN | SENSOR3_EN | SENSOR4_EN) +#define TSENS_8064_SENSOR5_EN BIT(8) +#define TSENS_8064_SENSOR6_EN BIT(9) +#define TSENS_8064_SENSOR7_EN BIT(10) +#define TSENS_8064_SENSOR8_EN BIT(11) +#define TSENS_8064_SENSOR9_EN BIT(12) +#define TSENS_8064_SENSOR10_EN BIT(13) +#define TSENS_8064_SENSORS_EN (SENSORS_EN | \ + TSENS_8064_SENSOR5_EN | \ + TSENS_8064_SENSOR6_EN | \ + TSENS_8064_SENSOR7_EN | \ + TSENS_8064_SENSOR8_EN | \ + TSENS_8064_SENSOR9_EN | \ + TSENS_8064_SENSOR10_EN) + +u32 tsens_8960_slope[] = { + 1176, 1176, 1154, 1176, + 1111, 1132, 1132, 1199, + 1132, 1199, 1132 + }; + +/* Temperature on y axis and ADC-code on x-axis */ +static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) +{ + int slope, offset; + + slope = thermal_zone_get_slope(s->tzd); + offset = CAL_MDEGC - slope * s->offset; + + return adc_code * slope + offset; +} + +static void notify_uspace_tsens_fn(struct work_struct *work) +{ + struct tsens_sensor *s = container_of(work, struct tsens_sensor, + notify_work); + + sysfs_notify(&s->tzd->device.kobj, NULL, "type"); +} + +static void tsens_scheduler_fn(struct work_struct *work) +{ + struct tsens_priv *priv = + container_of(work, struct tsens_priv, tsens_work); + unsigned int threshold, threshold_low, code, reg, sensor, mask; + bool upper_th_x, lower_th_x; + int ret; + + ret = regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®); + if (ret) + return; + reg = reg | LOWER_STATUS_CLR | UPPER_STATUS_CLR; + ret = regmap_write(priv->tm_map, STATUS_CNTL_ADDR_8064, reg); + if (ret) + return; + + mask = ~(LOWER_STATUS_CLR | UPPER_STATUS_CLR); + ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, &threshold); + if (ret) + return; + threshold_low = (threshold & THRESHOLD_LOWER_LIMIT_MASK) >> + THRESHOLD_LOWER_LIMIT_SHIFT; + threshold = (threshold & THRESHOLD_UPPER_LIMIT_MASK) >> + THRESHOLD_UPPER_LIMIT_SHIFT; + + ret = regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®); + if (ret) + return; + + ret = regmap_read(priv->tm_map, CNTL_ADDR, &sensor); + if (ret) + return; + sensor &= (uint32_t)TSENS_8064_SENSORS_EN; + sensor >>= SENSOR0_SHIFT; + + /* Constraint: There is only 1 interrupt control register for all + * 11 temperature sensor. So monitoring more than 1 sensor based + * on interrupts will yield inconsistent result. To overcome this + * issue we will monitor only sensor 0 which is the master sensor. + */ + + /* Skip if the sensor is disabled */ + if (sensor & 1) { + ret = regmap_read(priv->tm_map, priv->sensor[0].status, &code); + if (ret) + return; + upper_th_x = code >= threshold; + lower_th_x = code <= threshold_low; + if (upper_th_x) + mask |= UPPER_STATUS_CLR; + if (lower_th_x) + mask |= LOWER_STATUS_CLR; + if (upper_th_x || lower_th_x) { + /* Notify user space */ + schedule_work(&priv->sensor[0].notify_work); + pr_debug("Trigger (%d degrees) for sensor %d\n", + code_to_mdegC(code, &priv->sensor[0]), 0); + } + } + regmap_write(priv->tm_map, STATUS_CNTL_ADDR_8064, reg & mask); +} + +static irqreturn_t tsens_isr(int irq, void *data) +{ + struct tsens_priv *priv = data; + + schedule_work(&priv->tsens_work); + return IRQ_HANDLED; +} + +static void hw_init(struct tsens_priv *priv) +{ + int ret; + unsigned int reg_cntl = 0, reg_cfg = 0, reg_thr = 0; + unsigned int reg_status_cntl = 0; + + regmap_read(priv->tm_map, CNTL_ADDR, ®_cntl); + regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl | TSENS_SW_RST); + + reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18) | + (((1 << priv->num_sensors) - 1) << SENSOR0_SHIFT); + regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); + regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®_status_cntl); + reg_status_cntl |= LOWER_STATUS_CLR | UPPER_STATUS_CLR | + MIN_STATUS_MASK | MAX_STATUS_MASK; + regmap_write(priv->tm_map, STATUS_CNTL_ADDR_8064, reg_status_cntl); + reg_cntl |= TSENS_EN; + regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); + + regmap_read(priv->tm_map, CONFIG_ADDR, ®_cfg); + if (priv->num_sensors > 1) + reg_cfg = (reg_cfg & ~CONFIG_MASK) | CONFIG; + else + reg_cfg = (reg_cfg & ~CONFIG_MASK) | + (CONFIG << CONFIG_SHIFT_8660); + regmap_write(priv->tm_map, CONFIG_ADDR, reg_cfg); + + reg_thr |= (LOWER_LIMIT_TH_8064 << THRESHOLD_LOWER_LIMIT_SHIFT) | + (UPPER_LIMIT_TH_8064 << THRESHOLD_UPPER_LIMIT_SHIFT) | + (MIN_LIMIT_TH << THRESHOLD_MIN_LIMIT_SHIFT) | + (MAX_LIMIT_TH << THRESHOLD_MAX_LIMIT_SHIFT); + + regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_thr); + + ret = devm_request_irq(priv->dev, priv->tsens_irq, tsens_isr, + IRQF_TRIGGER_RISING, "tsens_interrupt", priv); + if (ret < 0) { + dev_err(priv->dev, "request_irq FAIL: %d", ret); + return; + } + + INIT_WORK(&priv->tsens_work, tsens_scheduler_fn); +} + static int suspend_8960(struct tsens_priv *priv) { int ret; @@ -191,6 +366,8 @@ static int init_8960(struct tsens_priv *priv) if (i >= 5) priv->sensor[i].status = S0_STATUS_ADDR + 40; priv->sensor[i].status += i * 4; + priv->sensor[i].slope = tsens_8960_slope[i]; + INIT_WORK(&priv->sensor[i].notify_work, notify_uspace_tsens_fn); } reg_cntl = SW_RST; @@ -241,18 +418,9 @@ static int calibrate_8960(struct tsens_priv *priv) kfree(data); - return 0; -} - -/* Temperature on y axis and ADC-code on x-axis */ -static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) -{ - int slope, offset; + hw_init(priv); - slope = thermal_zone_get_slope(s->tzd); - offset = CAL_MDEGC - slope * s->offset; - - return adc_code * slope + offset; + return 0; } static int get_temp_8960(const struct tsens_sensor *s, int *temp) diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 59d01162c66a..2f145001e4d5 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -48,6 +48,7 @@ enum tsens_irq_type { struct tsens_sensor { struct tsens_priv *priv; struct thermal_zone_device *tzd; + struct work_struct notify_work; int offset; unsigned int hw_id; int slope; From patchwork Wed Jul 15 22:45:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666387 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B9F2E13B1 for ; Wed, 15 Jul 2020 22:46:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A27C12076C for ; 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[87.7.31.173]) by smtp.googlemail.com with ESMTPSA id b186sm5759898wme.1.2020.07.15.15.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 15:45:45 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Amit Kucheria , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 6/7] drivers: thermal: tsens: add support for custom set_trip function Date: Thu, 16 Jul 2020 00:45:01 +0200 Message-Id: <20200715224503.30462-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200715224503.30462-1-ansuelsmth@gmail.com> References: <20200715224503.30462-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org 8960 tsens driver have a custom implementation to set set_trip function. Permit the generic driver to use the custom function if provided. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens.c | 4 ++++ drivers/thermal/qcom/tsens.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 2985a064a0d1..2b55b34d66fb 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -530,6 +530,10 @@ static int tsens_set_trips(void *_sensor, int low, int high) int high_val, low_val, cl_high, cl_low; u32 hw_id = s->hw_id; + // Use the driver set_trips if present + if (priv->ops->set_trip_temp) + return priv->ops->set_trip_temp(_sensor, low, high); + dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", hw_id, __func__, low, high); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 2f145001e4d5..c27fae39d542 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -65,6 +65,7 @@ struct tsens_sensor { * @suspend: Function to suspend the tsens device * @resume: Function to resume the tsens device * @get_trend: Function to get the thermal/temp trend + * @set_trip_temp: Function to get trip temp */ struct tsens_ops { /* mandatory callbacks */ @@ -77,6 +78,7 @@ struct tsens_ops { int (*suspend)(struct tsens_priv *priv); int (*resume)(struct tsens_priv *priv); int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend); + int (*set_trip_temp)(void *data, int trip, int temp); }; #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ From patchwork Wed Jul 15 22:45:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11666379 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8435F138C for ; Wed, 15 Jul 2020 22:45:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 621E82075B for ; Wed, 15 Jul 2020 22:45:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="l7yPardr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728036AbgGOWpy (ORCPT ); Wed, 15 Jul 2020 18:45:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727883AbgGOWpu (ORCPT ); Wed, 15 Jul 2020 18:45:50 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50914C061755; Wed, 15 Jul 2020 15:45:50 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id 17so7877517wmo.1; Wed, 15 Jul 2020 15:45:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZSHTL/qZogSjk1wO7b+ejuOIxDcTABgsaA2ehIcOuNQ=; b=l7yPardrrhmbRMrWutIl+KhLaS2AJhZTE6aDuLh3xW9EEadz2rOHI4ADjDfkMcSx0u ot5xXWPIgoyu8AE+aOPTWHgERdbH0cjioqmvPaeOk0Zrz52NSBhdDkoNiI6FFS80WJlR z8PZyuX/eZhIeJQdETXtQcTwigc+CmpzY1ETtdG1cJYQbTnzOekFS3Sd7zz+0WtTXQrM WOHLrskI5lP5iPuruQL7Qa8bjtMRI7WVkOG820qLxSWKEkCZ3rzgq5mrFqI8cisqtaiQ JDMXSnTodNGY4N5+YL49tvQb2gMaZEWcBSZqny5Aw2nfYjx6eXEjMXuMWrRYHQNEDI6u 7Chw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZSHTL/qZogSjk1wO7b+ejuOIxDcTABgsaA2ehIcOuNQ=; b=slpYsN4CDbhNOTdmYWSf2OArXtIIt0IQ6STfuJTZNRbs+4LZM27oGZ2+nn7DDbv0YS v19vFmkqvG+/FIkJi5D6IWxga8yGRhFLHKKeKs/0r2T+rbpynIyyJ5MvtI8oa+uiVlxw 15ytkcRA5wBgGGkClm54iBTbxhjqHcWtXyH38OxubPxpDCOCL51aQe97aurwkXupL3QG UQHh4+tez8qnDSiqzr3rItHAUgOsQi+1Rycr7PkwrPog0XKemT2EXgZ/VOoBNWiInrWY oOamBPNPzm9yPUXs0gwKn4WLLyWvCcBtWhMt1jR72JYuAsuuLaelO/xPWr4mB+LvuhEi 1jAg== X-Gm-Message-State: AOAM533olszVWbJBMh73g+O0UIMrePPATRi+BhwYeW4E6zhvOi/auBnD RRwaRkdsB/YR7UItPXPy5mk= X-Google-Smtp-Source: ABdhPJyEpeU+85g0hQNr/pmFERueh6E8y4wDvOslPNIfjQ78xD4IVyzkF5MQ4O5454OT2dami8jC0Q== X-Received: by 2002:a05:600c:2202:: with SMTP id z2mr1777495wml.13.1594853149012; Wed, 15 Jul 2020 15:45:49 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-7-31-173.retail.telecomitalia.it. [87.7.31.173]) by smtp.googlemail.com with ESMTPSA id b186sm5759898wme.1.2020.07.15.15.45.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2020 15:45:48 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Ansuel Smith , Amit Kucheria , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Michael Turquette , Stephen Boyd , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 7/7] drivers: thermal: tsens: add set_trip support for 8960 Date: Thu, 16 Jul 2020 00:45:02 +0200 Message-Id: <20200715224503.30462-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200715224503.30462-1-ansuelsmth@gmail.com> References: <20200715224503.30462-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add custom set_trip function for 8960 needed to set trip point to the tsens driver for 8960 driver. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 78 +++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index b302bfb924a6..f6ed2450a7ba 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -93,6 +93,15 @@ TSENS_8064_SENSOR9_EN | \ TSENS_8064_SENSOR10_EN) +/* Trips: from very hot to very cold */ +enum tsens_trip_type { + TSENS_TRIP_STAGE3 = 0, + TSENS_TRIP_STAGE2, + TSENS_TRIP_STAGE1, + TSENS_TRIP_STAGE0, + TSENS_TRIP_NUM, +}; + u32 tsens_8960_slope[] = { 1176, 1176, 1154, 1176, 1111, 1132, 1132, 1199, @@ -110,6 +119,16 @@ static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) return adc_code * slope + offset; } +static int mdegC_to_code(int degC, const struct tsens_sensor *s) +{ + int slope, offset; + + slope = thermal_zone_get_slope(s->tzd); + offset = CAL_MDEGC - slope * s->offset; + + return degC / slope - offset; +} + static void notify_uspace_tsens_fn(struct work_struct *work) { struct tsens_sensor *s = container_of(work, struct tsens_sensor, @@ -447,6 +466,64 @@ static int get_temp_8960(const struct tsens_sensor *s, int *temp) return -ETIMEDOUT; } +static int set_trip_temp_ipq8064(void *data, int trip, int temp) +{ + unsigned int reg_th, reg_cntl; + int ret, code, code_chk, hi_code, lo_code; + const struct tsens_sensor *s = data; + struct tsens_priv *priv = s->priv; + + code = mdegC_to_code(temp, s); + code_chk = code; + + if (code < THRESHOLD_MIN_CODE || code > THRESHOLD_MAX_CODE) + return -EINVAL; + + ret = regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®_cntl); + if (ret) + return ret; + + ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, ®_th); + if (ret) + return ret; + + hi_code = (reg_th & THRESHOLD_UPPER_LIMIT_MASK) + >> THRESHOLD_UPPER_LIMIT_SHIFT; + lo_code = (reg_th & THRESHOLD_LOWER_LIMIT_MASK) + >> THRESHOLD_LOWER_LIMIT_SHIFT; + + switch (trip) { + case TSENS_TRIP_STAGE3: + code <<= THRESHOLD_MAX_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_MAX_LIMIT_MASK; + break; + case TSENS_TRIP_STAGE2: + if (code_chk <= lo_code) + return -EINVAL; + code <<= THRESHOLD_UPPER_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_UPPER_LIMIT_MASK; + break; + case TSENS_TRIP_STAGE1: + if (code_chk >= hi_code) + return -EINVAL; + code <<= THRESHOLD_LOWER_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_LOWER_LIMIT_MASK; + break; + case TSENS_TRIP_STAGE0: + code <<= THRESHOLD_MIN_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_MIN_LIMIT_MASK; + break; + default: + return -EINVAL; + } + + ret = regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_th | code); + if (ret) + return ret; + + return 0; +} + static const struct tsens_ops ops_8960 = { .init = init_8960, .calibrate = calibrate_8960, @@ -455,6 +532,7 @@ static const struct tsens_ops ops_8960 = { .disable = disable_8960, .suspend = suspend_8960, .resume = resume_8960, + .set_trip_temp = set_trip_temp_ipq8064, }; struct tsens_plat_data data_8960 = {