From patchwork Fri Jul 17 01:48:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668757 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F2CAC1392 for ; Fri, 17 Jul 2020 01:49:36 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CA2BE2070E for ; Fri, 17 Jul 2020 01:49:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="twYB7iQp" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CA2BE2070E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=AEFenF95REyPzBySKAR0f+zv2l1eXtlcWV/5UXE1zxM=; b=twYB7iQpcoU0zNxbKHAKJc6arG 8VEr++ywOfEtbkVxliCAEv7iHfZs+YDTuYRPta5z7cOOlSttPdm8N7oOSQaUX03zw2HxYGzSbRdZT i3X95YPW31FD67FA1DQIyY03Yz0EjG06osQbFfJl51iwd6dyIJAwBf4EsJnaPimBwOnpl4aftHfFh ov8evD4mEnoZALb0ItsLi4t6BOF31LW4IJkuc+nQXtx86NhYn9JydH9a0WjJzHz1ncJDCHfd8vKX/ OTffXz2FYhIC70TqyTodRRRc1g94kLhQOpwP0Cjs7wqeD6V2c/c2gttMcSZUf0PAb4uT86cqXWB2G JppAofxA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFVC-0003hT-Lu; Fri, 17 Jul 2020 01:49:30 +0000 Received: from lucky1.263xmail.com ([211.157.147.130]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFV5-0003YK-Nb for linux-rockchip@lists.infradead.org; Fri, 17 Jul 2020 01:49:26 +0000 Received: from localhost (unknown [192.168.167.13]) by lucky1.263xmail.com (Postfix) with ESMTP id 97FFACA856; Fri, 17 Jul 2020 09:49:12 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P17843T139819799787264S1594950550837667_; Fri, 17 Jul 2020 09:49:12 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 01/13] pinctrl: rockchip: add nr_pins to rockchip_pin_ctrl Date: Fri, 17 Jul 2020 09:48:56 +0800 Message-Id: <20200717014908.13914-2-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_214924_266857_5E22A145 X-CRM114-Status: UNSURE ( 9.96 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.130 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.130 listed in wl.mailspike.net] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Add nr_pins to rockchip_pin_ctrl by hand, instead of calculating during driver probe. This patch is prepare work for making rockchip_pin_ctrl to be const type. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index c07324d1f265..bc465da68f26 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3573,6 +3573,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( struct rockchip_pin_ctrl *ctrl; struct rockchip_pin_bank *bank; int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; + u32 nr_pins; match = of_match_node(rockchip_pinctrl_dt_match, node); ctrl = (struct rockchip_pin_ctrl *)match->data; @@ -3599,13 +3600,14 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( drv_pmu_offs = ctrl->pmu_drv_offset; drv_grf_offs = ctrl->grf_drv_offset; bank = ctrl->pin_banks; + nr_pins = 0; for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { int bank_pins = 0; raw_spin_lock_init(&bank->slock); bank->drvdata = d; - bank->pin_base = ctrl->nr_pins; - ctrl->nr_pins += bank->nr_pins; + bank->pin_base = nr_pins; + nr_pins += bank->nr_pins; /* calculate iomux and drv offsets */ for (j = 0; j < 4; j++) { @@ -3692,6 +3694,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( } } + WARN_ON(nr_pins != ctrl->nr_pins); + return ctrl; } @@ -3852,6 +3856,7 @@ static struct rockchip_pin_bank px30_pin_banks[] = { static struct rockchip_pin_ctrl px30_pin_ctrl = { .pin_banks = px30_pin_banks, .nr_banks = ARRAY_SIZE(px30_pin_banks), + .nr_pins = 128, .label = "PX30-GPIO", .type = PX30, .grf_mux_offset = 0x0, @@ -3876,6 +3881,7 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = { static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .pin_banks = rv1108_pin_banks, .nr_banks = ARRAY_SIZE(rv1108_pin_banks), + .nr_pins = 128, .label = "RV1108-GPIO", .type = RV1108, .grf_mux_offset = 0x10, @@ -3897,6 +3903,7 @@ static struct rockchip_pin_bank rk2928_pin_banks[] = { static struct rockchip_pin_ctrl rk2928_pin_ctrl = { .pin_banks = rk2928_pin_banks, .nr_banks = ARRAY_SIZE(rk2928_pin_banks), + .nr_pins = 128, .label = "RK2928-GPIO", .type = RK2928, .grf_mux_offset = 0xa8, @@ -3912,6 +3919,7 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = { static struct rockchip_pin_ctrl rk3036_pin_ctrl = { .pin_banks = rk3036_pin_banks, .nr_banks = ARRAY_SIZE(rk3036_pin_banks), + .nr_pins = 96, .label = "RK3036-GPIO", .type = RK2928, .grf_mux_offset = 0xa8, @@ -3930,6 +3938,7 @@ static struct rockchip_pin_bank rk3066a_pin_banks[] = { static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { .pin_banks = rk3066a_pin_banks, .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), + .nr_pins = 176, .label = "RK3066a-GPIO", .type = RK2928, .grf_mux_offset = 0xa8, @@ -3946,6 +3955,7 @@ static struct rockchip_pin_bank rk3066b_pin_banks[] = { static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { .pin_banks = rk3066b_pin_banks, .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), + .nr_pins = 128, .label = "RK3066b-GPIO", .type = RK3066B, .grf_mux_offset = 0x60, @@ -3961,6 +3971,7 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = { static struct rockchip_pin_ctrl rk3128_pin_ctrl = { .pin_banks = rk3128_pin_banks, .nr_banks = ARRAY_SIZE(rk3128_pin_banks), + .nr_pins = 128, .label = "RK3128-GPIO", .type = RK3128, .grf_mux_offset = 0xa8, @@ -3981,6 +3992,7 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = { static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .pin_banks = rk3188_pin_banks, .nr_banks = ARRAY_SIZE(rk3188_pin_banks), + .nr_pins = 128, .label = "RK3188-GPIO", .type = RK3188, .grf_mux_offset = 0x60, @@ -3999,6 +4011,7 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = { static struct rockchip_pin_ctrl rk3228_pin_ctrl = { .pin_banks = rk3228_pin_banks, .nr_banks = ARRAY_SIZE(rk3228_pin_banks), + .nr_pins = 128, .label = "RK3228-GPIO", .type = RK3288, .grf_mux_offset = 0x0, @@ -4043,6 +4056,7 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = { static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .pin_banks = rk3288_pin_banks, .nr_banks = ARRAY_SIZE(rk3288_pin_banks), + .nr_pins = 264, .label = "RK3288-GPIO", .type = RK3288, .grf_mux_offset = 0x0, @@ -4079,6 +4093,7 @@ static struct rockchip_pin_bank rk3308_pin_banks[] = { static struct rockchip_pin_ctrl rk3308_pin_ctrl = { .pin_banks = rk3308_pin_banks, .nr_banks = ARRAY_SIZE(rk3308_pin_banks), + .nr_pins = 160, .label = "RK3308-GPIO", .type = RK3308, .grf_mux_offset = 0x0, @@ -4108,6 +4123,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .pin_banks = rk3328_pin_banks, .nr_banks = ARRAY_SIZE(rk3328_pin_banks), + .nr_pins = 128, .label = "RK3328-GPIO", .type = RK3288, .grf_mux_offset = 0x0, @@ -4134,6 +4150,7 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = { static struct rockchip_pin_ctrl rk3368_pin_ctrl = { .pin_banks = rk3368_pin_banks, .nr_banks = ARRAY_SIZE(rk3368_pin_banks), + .nr_pins = 128, .label = "RK3368-GPIO", .type = RK3368, .grf_mux_offset = 0x0, @@ -4198,6 +4215,7 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = { static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .pin_banks = rk3399_pin_banks, .nr_banks = ARRAY_SIZE(rk3399_pin_banks), + .nr_pins = 160, .label = "RK3399-GPIO", .type = RK3399, .grf_mux_offset = 0xe000, From patchwork Fri Jul 17 01:48:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668759 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 324CC1392 for ; Fri, 17 Jul 2020 01:49:39 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F03292070E for ; Fri, 17 Jul 2020 01:49:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="RgRG8lJg" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F03292070E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; 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Fri, 17 Jul 2020 01:49:26 +0000 Received: from localhost (unknown [192.168.167.13]) by lucky1.263xmail.com (Postfix) with ESMTP id 0E216EC17D; Fri, 17 Jul 2020 09:49:13 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P17843T139819799787264S1594950550837667_; Fri, 17 Jul 2020 09:49:13 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <062f2b5b04c8ad80b024e0c8c0ac27d2> X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 02/13] pinctrl: rockchip: modify rockchip_pin_ctrl to const struct Date: Fri, 17 Jul 2020 09:48:57 +0800 Message-Id: <20200717014908.13914-3-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_214925_662082_77A7BDF1 X-CRM114-Status: GOOD ( 12.74 ) X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.132 listed in list.dnswl.org] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.132 listed in wl.mailspike.net] X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org The rockchip_pin_ctrl structure actually is soc data structure for pinctrl on Rockchip SoCs. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 62 +++++++++++++++--------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index bc465da68f26..77c1e6744f6c 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -392,7 +392,7 @@ struct rockchip_pinctrl { struct regmap *regmap_pull; struct regmap *regmap_pmu; struct device *dev; - struct rockchip_pin_ctrl *ctrl; + const struct rockchip_pin_ctrl *ctrl; struct pinctrl_desc pctl; struct pinctrl_dev *pctl_dev; struct rockchip_pin_group *groups; @@ -779,7 +779,7 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, int *reg, u8 *bit, int *mask) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct rockchip_mux_recalced_data *data; int i; @@ -1396,7 +1396,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, int mux, u32 *loc, u32 *reg, u32 *value) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct rockchip_mux_route_data *data; int i; @@ -2112,7 +2112,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, int pin_num) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; int reg, ret; u32 data, temp, rmask_bits; @@ -2189,7 +2189,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, int pin_num, int strength) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; int reg, ret, i; u32 data, rmask, rmask_bits, temp; @@ -2297,7 +2297,7 @@ static int rockchip_pull_list[PULL_TYPE_MAX][4] = { static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; int reg, ret, pull_type; u8 bit; @@ -2341,7 +2341,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, int pin_num, int pull) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; int reg, ret, i, pull_type; u8 bit; @@ -2427,7 +2427,7 @@ static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; int reg, ret; u8 bit; @@ -2449,7 +2449,7 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, int pin_num, int enable) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; int reg, ret; u8 bit; @@ -2621,7 +2621,7 @@ static const struct pinmux_ops rockchip_pmx_ops = { * Pinconf_ops handling */ -static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, +static bool rockchip_pinconf_pull_valid(const struct rockchip_pin_ctrl *ctrl, enum pin_config_param pull) { switch (ctrl->type) { @@ -3366,7 +3366,7 @@ static void rockchip_irq_disable(struct irq_data *d) static int rockchip_interrupts_register(struct platform_device *pdev, struct rockchip_pinctrl *info) { - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct rockchip_pin_bank *bank = ctrl->pin_banks; unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; struct irq_chip_generic *gc; @@ -3447,7 +3447,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev, static int rockchip_gpiolib_register(struct platform_device *pdev, struct rockchip_pinctrl *info) { - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct rockchip_pin_bank *bank = ctrl->pin_banks; struct gpio_chip *gc; int ret; @@ -3493,7 +3493,7 @@ static int rockchip_gpiolib_register(struct platform_device *pdev, static int rockchip_gpiolib_unregister(struct platform_device *pdev, struct rockchip_pinctrl *info) { - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct rockchip_pin_bank *bank = ctrl->pin_banks; int i; @@ -3563,20 +3563,20 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, static const struct of_device_id rockchip_pinctrl_dt_match[]; /* retrieve the soc specific data */ -static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( +static const struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( struct rockchip_pinctrl *d, struct platform_device *pdev) { const struct of_device_id *match; struct device_node *node = pdev->dev.of_node; struct device_node *np; - struct rockchip_pin_ctrl *ctrl; + const const struct rockchip_pin_ctrl *ctrl; struct rockchip_pin_bank *bank; int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; u32 nr_pins; match = of_match_node(rockchip_pinctrl_dt_match, node); - ctrl = (struct rockchip_pin_ctrl *)match->data; + ctrl = (const struct rockchip_pin_ctrl *)match->data; for_each_child_of_node(node, np) { if (!of_find_property(np, "gpio-controller", NULL)) @@ -3748,7 +3748,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) { struct rockchip_pinctrl *info; struct device *dev = &pdev->dev; - struct rockchip_pin_ctrl *ctrl; + const const struct rockchip_pin_ctrl *ctrl; struct device_node *np = pdev->dev.of_node, *node; struct resource *res; void __iomem *base; @@ -3853,7 +3853,7 @@ static struct rockchip_pin_bank px30_pin_banks[] = { ), }; -static struct rockchip_pin_ctrl px30_pin_ctrl = { +static const struct rockchip_pin_ctrl px30_pin_ctrl = { .pin_banks = px30_pin_banks, .nr_banks = ARRAY_SIZE(px30_pin_banks), .nr_pins = 128, @@ -3878,7 +3878,7 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), }; -static struct rockchip_pin_ctrl rv1108_pin_ctrl = { +static const struct rockchip_pin_ctrl rv1108_pin_ctrl = { .pin_banks = rv1108_pin_banks, .nr_banks = ARRAY_SIZE(rv1108_pin_banks), .nr_pins = 128, @@ -3900,7 +3900,7 @@ static struct rockchip_pin_bank rk2928_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk2928_pin_ctrl = { +static const struct rockchip_pin_ctrl rk2928_pin_ctrl = { .pin_banks = rk2928_pin_banks, .nr_banks = ARRAY_SIZE(rk2928_pin_banks), .nr_pins = 128, @@ -3916,7 +3916,7 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = { PIN_BANK(2, 32, "gpio2"), }; -static struct rockchip_pin_ctrl rk3036_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3036_pin_ctrl = { .pin_banks = rk3036_pin_banks, .nr_banks = ARRAY_SIZE(rk3036_pin_banks), .nr_pins = 96, @@ -3935,7 +3935,7 @@ static struct rockchip_pin_bank rk3066a_pin_banks[] = { PIN_BANK(6, 16, "gpio6"), }; -static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3066a_pin_ctrl = { .pin_banks = rk3066a_pin_banks, .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), .nr_pins = 176, @@ -3952,7 +3952,7 @@ static struct rockchip_pin_bank rk3066b_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3066b_pin_ctrl = { .pin_banks = rk3066b_pin_banks, .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), .nr_pins = 128, @@ -3968,7 +3968,7 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3128_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3128_pin_ctrl = { .pin_banks = rk3128_pin_banks, .nr_banks = ARRAY_SIZE(rk3128_pin_banks), .nr_pins = 128, @@ -3989,7 +3989,7 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3188_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3188_pin_ctrl = { .pin_banks = rk3188_pin_banks, .nr_banks = ARRAY_SIZE(rk3188_pin_banks), .nr_pins = 128, @@ -4008,7 +4008,7 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3228_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3228_pin_ctrl = { .pin_banks = rk3228_pin_banks, .nr_banks = ARRAY_SIZE(rk3228_pin_banks), .nr_pins = 128, @@ -4053,7 +4053,7 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = { PIN_BANK(8, 16, "gpio8"), }; -static struct rockchip_pin_ctrl rk3288_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3288_pin_ctrl = { .pin_banks = rk3288_pin_banks, .nr_banks = ARRAY_SIZE(rk3288_pin_banks), .nr_pins = 264, @@ -4090,7 +4090,7 @@ static struct rockchip_pin_bank rk3308_pin_banks[] = { IOMUX_WIDTH_2BIT), }; -static struct rockchip_pin_ctrl rk3308_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3308_pin_ctrl = { .pin_banks = rk3308_pin_banks, .nr_banks = ARRAY_SIZE(rk3308_pin_banks), .nr_pins = 160, @@ -4120,7 +4120,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { 0), }; -static struct rockchip_pin_ctrl rk3328_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3328_pin_ctrl = { .pin_banks = rk3328_pin_banks, .nr_banks = ARRAY_SIZE(rk3328_pin_banks), .nr_pins = 128, @@ -4147,7 +4147,7 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3368_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3368_pin_ctrl = { .pin_banks = rk3368_pin_banks, .nr_banks = ARRAY_SIZE(rk3368_pin_banks), .nr_pins = 128, @@ -4212,7 +4212,7 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = { ), }; -static struct rockchip_pin_ctrl rk3399_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3399_pin_ctrl = { .pin_banks = rk3399_pin_banks, .nr_banks = ARRAY_SIZE(rk3399_pin_banks), .nr_pins = 160, From patchwork Fri Jul 17 01:48:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668751 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 33A526C1 for ; Fri, 17 Jul 2020 01:49:33 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CD4DD2070E for ; Fri, 17 Jul 2020 01:49:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Mh5/a3aK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CD4DD2070E Authentication-Results: mail.kernel.org; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFV9-0003fO-R2; Fri, 17 Jul 2020 01:49:28 +0000 Received: from lucky1.263xmail.com ([211.157.147.130]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFV5-0003YM-9G for linux-rockchip@lists.infradead.org; Fri, 17 Jul 2020 01:49:24 +0000 Received: from localhost (unknown [192.168.167.13]) by lucky1.263xmail.com (Postfix) with ESMTP id E198BCA8CA; Fri, 17 Jul 2020 09:49:13 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P17843T139819799787264S1594950550837667_; Fri, 17 Jul 2020 09:49:13 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <0b6cc61686a1891e65d89d2e784f7487> X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 03/13] pinctrl: rockchip: make driver be tristate module Date: Fri, 17 Jul 2020 09:48:58 +0800 Message-Id: <20200717014908.13914-4-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_214923_614662_EA048B08 X-CRM114-Status: GOOD ( 11.30 ) X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.130 listed in list.dnswl.org] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.130 listed in wl.mailspike.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Make pinctrl-rockchip driver to be tristate module, support to build as a module, this is useful for GKI. Signed-off-by: Jianqun Xu --- drivers/pinctrl/Kconfig | 2 +- drivers/pinctrl/pinctrl-rockchip.c | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 8828613c4e0e..dd4874e2ac67 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -207,7 +207,7 @@ config PINCTRL_OXNAS select MFD_SYSCON config PINCTRL_ROCKCHIP - bool + tristate "Rockchip gpio and pinctrl driver" select PINMUX select GENERIC_PINCONF select GENERIC_IRQ_CHIP diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 77c1e6744f6c..ec509ef8bd8d 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -16,10 +16,12 @@ */ #include +#include #include #include #include #include +#include #include #include #include @@ -4259,6 +4261,7 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = &rk3399_pin_ctrl }, {}, }; +MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); static struct platform_driver rockchip_pinctrl_driver = { .probe = rockchip_pinctrl_probe, @@ -4274,3 +4277,7 @@ static int __init rockchip_pinctrl_drv_register(void) return platform_driver_register(&rockchip_pinctrl_driver); } postcore_initcall(rockchip_pinctrl_drv_register); + +MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:pinctrl-rockchip"); From patchwork Fri Jul 17 01:48:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668755 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8AEDC1392 for ; Fri, 17 Jul 2020 01:49:35 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6224D207D0 for ; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFV8-0003eq-Uy; Fri, 17 Jul 2020 01:49:26 +0000 Received: from lucky1.263xmail.com ([211.157.147.131]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFV5-0003Yh-LR for linux-rockchip@lists.infradead.org; Fri, 17 Jul 2020 01:49:24 +0000 Received: from localhost (unknown [192.168.167.13]) by lucky1.263xmail.com (Postfix) with ESMTP id 4D2EEB020E; Fri, 17 Jul 2020 09:49:14 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P17843T139819799787264S1594950550837667_; Fri, 17 Jul 2020 09:49:14 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <5cab98d0e3e79e38ff217b6c8aa7abdd> X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 04/13] pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq Date: Fri, 17 Jul 2020 09:48:59 +0800 Message-Id: <20200717014908.13914-5-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_214923_988776_04B00B01 X-CRM114-Status: UNSURE ( 8.07 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.131 listed in list.dnswl.org] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.131 listed in wl.mailspike.net] X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org There need to enable pclk_gpio when do irq_create_mapping, since it will do access to gpio controller. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index ec509ef8bd8d..d34fada39227 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3155,7 +3155,9 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) if (!bank->domain) return -ENXIO; + clk_enable(bank->clk); virq = irq_create_mapping(bank->domain, offset); + clk_disable(bank->clk); return (virq) ? : -ENXIO; } From patchwork Fri Jul 17 01:52:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668765 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 463F2138C for ; Fri, 17 Jul 2020 01:52:34 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D13C2076D for ; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFY5-0004qA-2V; Fri, 17 Jul 2020 01:52:29 +0000 Received: from lucky1.263xmail.com ([211.157.147.133]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFY2-0004oR-47 for linux-rockchip@lists.infradead.org; Fri, 17 Jul 2020 01:52:27 +0000 Received: from localhost (unknown [192.168.167.70]) by lucky1.263xmail.com (Postfix) with ESMTP id 5B07CC5C96; Fri, 17 Jul 2020 09:52:22 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P22085T140330059949824S1594950740444703_; Fri, 17 Jul 2020 09:52:21 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 05/13] pinctrl: rockchip: create irq mapping in gpio_to_irq Date: Fri, 17 Jul 2020 09:52:19 +0800 Message-Id: <20200717015219.14047-1-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_215226_679897_FD08E646 X-CRM114-Status: GOOD ( 10.84 ) X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.133 listed in list.dnswl.org] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.133 listed in wl.mailspike.net] X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Remove totally irq mappings create in probe, the gpio irq mapping will be created when do gpio_to_irq -> rockchip_gpio_to_irq -> irq_create_mapping This patch can speed up system boot on, also abandon many unused irq mappings' create. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index d34fada39227..1be4627f3877 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3196,7 +3196,7 @@ static void rockchip_irq_demux(struct irq_desc *desc) irq = __ffs(pend); pend &= ~BIT(irq); - virq = irq_linear_revmap(bank->domain, irq); + virq = irq_find_mapping(bank->domain, irq); if (!virq) { dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); @@ -3375,7 +3375,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev, unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; struct irq_chip_generic *gc; int ret; - int i, j; + int i; for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { if (!bank->valid) { @@ -3402,7 +3402,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev, ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, "rockchip_gpio_irq", handle_level_irq, - clr, 0, IRQ_GC_INIT_MASK_CACHE); + clr, 0, 0); if (ret) { dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", bank->name); @@ -3411,14 +3411,6 @@ static int rockchip_interrupts_register(struct platform_device *pdev, continue; } - /* - * Linux assumes that all interrupts start out disabled/masked. - * Our driver only uses the concept of masked and always keeps - * things enabled, so for us that's all masked and all enabled. - */ - writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); - writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); - gc = irq_get_domain_generic_chip(bank->domain, 0); gc->reg_base = bank->reg_base; gc->private = bank; @@ -3435,13 +3427,17 @@ static int rockchip_interrupts_register(struct platform_device *pdev, gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; gc->wake_enabled = IRQ_MSK(bank->nr_pins); + /* + * Linux assumes that all interrupts start out disabled/masked. + * Our driver only uses the concept of masked and always keeps + * things enabled, so for us that's all masked and all enabled. + */ + writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); + writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); + gc->mask_cache = 0xffffffff; + irq_set_chained_handler_and_data(bank->irq, rockchip_irq_demux, bank); - - /* map the gpio irqs here, when the clock is still running */ - for (j = 0 ; j < 32 ; j++) - irq_create_mapping(bank->domain, j); - clk_disable(bank->clk); } From patchwork Fri Jul 17 01:52:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668767 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 73B8A138C for ; Fri, 17 Jul 2020 01:52:44 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 473032076D for ; Fri, 17 Jul 2020 01:52:44 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFYG-0004u9-GD; Fri, 17 Jul 2020 01:52:40 +0000 Received: from lucky1.263xmail.com ([211.157.147.132]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFYF-0004sK-6G for linux-rockchip@lists.infradead.org; Fri, 17 Jul 2020 01:52:40 +0000 Received: from localhost (unknown [192.168.167.209]) by lucky1.263xmail.com (Postfix) with ESMTP id 8D32DEC08D; Fri, 17 Jul 2020 09:52:35 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P17009T140099633260288S1594950754349190_; Fri, 17 Jul 2020 09:52:35 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <4339edc153396fc21e5612d10d58466a> X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 06/13] pinctrl: rockchip: do codingstyle Date: Fri, 17 Jul 2020 09:52:32 +0800 Message-Id: <20200717015232.14099-1-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_215239_517988_10F927C8 X-CRM114-Status: UNSURE ( 8.65 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.132 listed in list.dnswl.org] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.132 listed in wl.mailspike.net] X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Add RK3399 definitions to separate from other SoCs. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 1be4627f3877..71335ed003b3 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2050,6 +2050,9 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, #define RK3399_PULL_GRF_OFFSET 0xe040 #define RK3399_PULL_PMU_OFFSET 0x40 #define RK3399_DRV_3BITS_PER_PIN 3 +#define RK3399_PULL_BITS_PER_PIN 2 +#define RK3399_PULL_PINS_PER_REG 8 +#define RK3399_PULL_BANK_STRIDE 16 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, @@ -2062,22 +2065,22 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *regmap = info->regmap_pmu; *reg = RK3399_PULL_PMU_OFFSET; - *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; + *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE; - *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); - *bit = pin_num % RK3188_PULL_PINS_PER_REG; - *bit *= RK3188_PULL_BITS_PER_PIN; + *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3399_PULL_PINS_PER_REG; + *bit *= RK3399_PULL_BITS_PER_PIN; } else { *regmap = info->regmap_base; *reg = RK3399_PULL_GRF_OFFSET; /* correct the offset, as we're starting with the 3rd bank */ *reg -= 0x20; - *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; - *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4); - *bit = (pin_num % RK3188_PULL_PINS_PER_REG); - *bit *= RK3188_PULL_BITS_PER_PIN; + *bit = (pin_num % RK3399_PULL_PINS_PER_REG); + *bit *= RK3399_PULL_BITS_PER_PIN; } } From patchwork Fri Jul 17 01:53:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668771 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 490DF138C for ; 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Fri, 17 Jul 2020 09:53:08 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <918b3b7cdf0ed7d2ab8dc91c94b75d1a> X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 07/13] pinctrl: rockchip: do codingstyle Date: Fri, 17 Jul 2020 09:53:05 +0800 Message-Id: <20200717015305.14202-1-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_215314_492760_3FC78F6F X-CRM114-Status: UNSURE ( 7.90 ) X-CRM114-Notice: Please train this message. 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Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 34 ++++++++++++++++++------------ 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 71335ed003b3..8e3fa9011165 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1987,6 +1987,9 @@ static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, #define RK3368_PULL_GRF_OFFSET 0x100 #define RK3368_PULL_PMU_OFFSET 0x10 +#define RK3368_PULL_BITS_PER_PIN 2 +#define RK3368_PULL_PINS_PER_REG 8 +#define RK3368_PULL_BANK_STRIDE 16 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, @@ -1999,25 +2002,28 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *regmap = info->regmap_pmu; *reg = RK3368_PULL_PMU_OFFSET; - *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); - *bit = pin_num % RK3188_PULL_PINS_PER_REG; - *bit *= RK3188_PULL_BITS_PER_PIN; + *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3368_PULL_PINS_PER_REG; + *bit *= RK3368_PULL_BITS_PER_PIN; } else { *regmap = info->regmap_base; *reg = RK3368_PULL_GRF_OFFSET; /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; - *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; - *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + *reg += bank->bank_num * RK3368_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4); - *bit = (pin_num % RK3188_PULL_PINS_PER_REG); - *bit *= RK3188_PULL_BITS_PER_PIN; + *bit = (pin_num % RK3368_PULL_PINS_PER_REG); + *bit *= RK3368_PULL_BITS_PER_PIN; } } #define RK3368_DRV_PMU_OFFSET 0x20 #define RK3368_DRV_GRF_OFFSET 0x200 +#define RK3368_DRV_BITS_PER_PIN 2 +#define RK3368_DRV_PINS_PER_REG 8 +#define RK3368_DRV_BANK_STRIDE 16 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, @@ -2030,20 +2036,20 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *regmap = info->regmap_pmu; *reg = RK3368_DRV_PMU_OFFSET; - *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); - *bit = pin_num % RK3288_DRV_PINS_PER_REG; - *bit *= RK3288_DRV_BITS_PER_PIN; + *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RK3368_DRV_PINS_PER_REG; + *bit *= RK3368_DRV_BITS_PER_PIN; } else { *regmap = info->regmap_base; *reg = RK3368_DRV_GRF_OFFSET; /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; - *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; - *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + *reg += bank->bank_num * RK3368_DRV_BANK_STRIDE; + *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4); - *bit = (pin_num % RK3288_DRV_PINS_PER_REG); - *bit *= RK3288_DRV_BITS_PER_PIN; + *bit = (pin_num % RK3368_DRV_PINS_PER_REG); + *bit *= RK3368_DRV_BITS_PER_PIN; } } From patchwork Fri Jul 17 01:53:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668773 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9E1AE1392 for ; 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Fri, 17 Jul 2020 09:53:17 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 08/13] pinctrl: rockchip: do codingstyle Date: Fri, 17 Jul 2020 09:53:15 +0800 Message-Id: <20200717015315.14255-1-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_215321_366720_D7299DC3 X-CRM114-Status: UNSURE ( 7.57 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.131 listed in list.dnswl.org] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.131 listed in wl.mailspike.net] X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Add RK3308 definitions to separate from other SoCs. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 8e3fa9011165..44f051af97c6 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1952,6 +1952,9 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, } #define RK3308_PULL_OFFSET 0xa0 +#define RK3308_PULL_BITS_PER_PIN 2 +#define RK3308_PULL_PINS_PER_REG 8 +#define RK3308_PULL_BANK_STRIDE 16 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, @@ -1961,14 +1964,17 @@ static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *regmap = info->regmap_base; *reg = RK3308_PULL_OFFSET; - *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; - *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + *reg += bank->bank_num * RK3308_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3308_PULL_PINS_PER_REG) * 4); - *bit = (pin_num % RK3188_PULL_PINS_PER_REG); - *bit *= RK3188_PULL_BITS_PER_PIN; + *bit = (pin_num % RK3308_PULL_PINS_PER_REG); + *bit *= RK3308_PULL_BITS_PER_PIN; } #define RK3308_DRV_GRF_OFFSET 0x100 +#define RK3308_DRV_BITS_PER_PIN 2 +#define RK3308_DRV_PINS_PER_REG 8 +#define RK3308_DRV_BANK_STRIDE 16 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, @@ -1978,11 +1984,11 @@ static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *regmap = info->regmap_base; *reg = RK3308_DRV_GRF_OFFSET; - *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; - *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + *reg += bank->bank_num * RK3308_DRV_BANK_STRIDE; + *reg += ((pin_num / RK3308_DRV_PINS_PER_REG) * 4); - *bit = (pin_num % RK3288_DRV_PINS_PER_REG); - *bit *= RK3288_DRV_BITS_PER_PIN; + *bit = (pin_num % RK3308_DRV_PINS_PER_REG); + *bit *= RK3308_DRV_BITS_PER_PIN; } #define RK3368_PULL_GRF_OFFSET 0x100 From patchwork Fri Jul 17 01:53:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668775 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A2AF6138C for ; Fri, 17 Jul 2020 01:53:35 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 78FFF2076D for ; Fri, 17 Jul 2020 01:53:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="O28SsxeE" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 78FFF2076D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; 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Fri, 17 Jul 2020 01:53:30 +0000 Received: from localhost (unknown [192.168.167.235]) by lucky1.263xmail.com (Postfix) with ESMTP id 44809C5D6B; Fri, 17 Jul 2020 09:53:26 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P26706T140361238066944S1594950804654023_; Fri, 17 Jul 2020 09:53:25 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <6045a8117473b967c7cacb8c546d06de> X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 09/13] pinctrl: rockchip: do codingstyle Date: Fri, 17 Jul 2020 09:53:23 +0800 Message-Id: <20200717015323.14323-1-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_215329_810740_BC38099A X-CRM114-Status: UNSURE ( 7.57 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.133 listed in list.dnswl.org] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.133 listed in wl.mailspike.net] X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Add RK3228 definitions to separate from other SoCs. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 44f051af97c6..ec6a1a08f8b1 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1918,6 +1918,9 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, } #define RK3228_PULL_OFFSET 0x100 +#define RK3228_PULL_BITS_PER_PIN 2 +#define RK3228_PULL_PINS_PER_REG 8 +#define RK3228_PULL_BANK_STRIDE 16 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, @@ -1927,14 +1930,17 @@ static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *regmap = info->regmap_base; *reg = RK3228_PULL_OFFSET; - *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; - *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + *reg += bank->bank_num * RK3228_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3228_PULL_PINS_PER_REG) * 4); - *bit = (pin_num % RK3188_PULL_PINS_PER_REG); - *bit *= RK3188_PULL_BITS_PER_PIN; + *bit = (pin_num % RK3228_PULL_PINS_PER_REG); + *bit *= RK3228_PULL_BITS_PER_PIN; } #define RK3228_DRV_GRF_OFFSET 0x200 +#define RK3228_DRV_BITS_PER_PIN 2 +#define RK3228_DRV_PINS_PER_REG 8 +#define RK3228_DRV_BANK_STRIDE 16 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, @@ -1944,11 +1950,11 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *regmap = info->regmap_base; *reg = RK3228_DRV_GRF_OFFSET; - *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; - *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + *reg += bank->bank_num * RK3228_DRV_BANK_STRIDE; + *reg += ((pin_num / RK3228_DRV_PINS_PER_REG) * 4); - *bit = (pin_num % RK3288_DRV_PINS_PER_REG); - *bit *= RK3288_DRV_BITS_PER_PIN; + *bit = (pin_num % RK3228_DRV_PINS_PER_REG); + *bit *= RK3228_DRV_BITS_PER_PIN; } #define RK3308_PULL_OFFSET 0xa0 From patchwork Fri Jul 17 01:53:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668777 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9BB07138C for ; Fri, 17 Jul 2020 01:53:44 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 707D52076D for ; Fri, 17 Jul 2020 01:53:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="3PrAb4no" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 707D52076D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; 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Fri, 17 Jul 2020 01:53:40 +0000 Received: from localhost (unknown [192.168.167.13]) by lucky1.263xmail.com (Postfix) with ESMTP id C8F58CA817; Fri, 17 Jul 2020 09:53:34 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P17843T139820223420160S1594950813542175_; Fri, 17 Jul 2020 09:53:34 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <2cd34631c355ac32b25d606a1e33602c> X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 10/13] pinctrl: rockchip: do codingstyle Date: Fri, 17 Jul 2020 09:53:32 +0800 Message-Id: <20200717015332.14383-1-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_215339_498510_870A29EE X-CRM114-Status: UNSURE ( 8.69 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.130 listed in list.dnswl.org] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.130 listed in wl.mailspike.net] X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Add RK3288 definitons to separate from other SoCs. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index ec6a1a08f8b1..04e7027ec8e1 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1855,6 +1855,11 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, } #define RK3288_PULL_OFFSET 0x140 +#define RK3288_PULL_PMU_OFFSET 0x64 +#define RK3288_PULL_BITS_PER_PIN 2 +#define RK3288_PULL_PINS_PER_REG 8 +#define RK3288_PULL_BANK_STRIDE 16 + static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) @@ -1864,22 +1869,22 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, /* The first 24 pins of the first bank are located in PMU */ if (bank->bank_num == 0) { *regmap = info->regmap_pmu; - *reg = RK3188_PULL_PMU_OFFSET; + *reg = RK3288_PULL_PMU_OFFSET; - *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); - *bit = pin_num % RK3188_PULL_PINS_PER_REG; - *bit *= RK3188_PULL_BITS_PER_PIN; + *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4); + *bit = pin_num % RK3288_PULL_PINS_PER_REG; + *bit *= RK3288_PULL_BITS_PER_PIN; } else { *regmap = info->regmap_base; *reg = RK3288_PULL_OFFSET; /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; - *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; - *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + *reg += bank->bank_num * RK3288_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4); - *bit = (pin_num % RK3188_PULL_PINS_PER_REG); - *bit *= RK3188_PULL_BITS_PER_PIN; + *bit = (pin_num % RK3288_PULL_PINS_PER_REG); + *bit *= RK3288_PULL_BITS_PER_PIN; } } From patchwork Fri Jul 17 01:53:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668779 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CDF8F138C for ; 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Fri, 17 Jul 2020 09:53:41 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 11/13] pinctrl: rockchip: do codingstyle Date: Fri, 17 Jul 2020 09:53:39 +0800 Message-Id: <20200717015339.14440-1-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_215346_006239_62FD5952 X-CRM114-Status: UNSURE ( 7.76 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.131 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.131 listed in wl.mailspike.net] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Add RK3128 definitions to separate from other SoCs. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 04e7027ec8e1..3b74455dcdb2 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1799,6 +1799,8 @@ static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, }; #define RK3128_PULL_OFFSET 0x118 +#define RK3128_PULL_PINS_PER_REG 16 +#define RK3128_PULL_BANK_STRIDE 8 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, @@ -1808,10 +1810,10 @@ static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *regmap = info->regmap_base; *reg = RK3128_PULL_OFFSET; - *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; - *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); + *reg += bank->bank_num * RK3128_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3128_PULL_PINS_PER_REG) * 4); - *bit = pin_num % RK2928_PULL_PINS_PER_REG; + *bit = pin_num % RK3128_PULL_PINS_PER_REG; } #define RK3188_PULL_OFFSET 0x164 From patchwork Fri Jul 17 01:53:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668781 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7CF71138C for ; Fri, 17 Jul 2020 01:54:01 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 53F2C2076D for ; Fri, 17 Jul 2020 01:54:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="w/3umIGA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 53F2C2076D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=m2o85zATRauwCeBMSY3ev4UL2lFbWqbynZOeNsZef54=; b=w/3umIGATUru8nz4OHiz4xYPyP 3nxvDOwALUybURFTkLwZua71d8UXfbwnDoBpTELy3CmeOXUGf1exeHNh5M+02oCD07A7OsRhqzr/K eRfl09zQbZ/4QwSEC+fceZ9NZPLCEuoziEeRpym63tPbHe1A2JVuhp6koi4bFNIPXHqqpZI48dp1O BNGF7ykkX3+quJsDtJ7LJHLWdzVojRoCBrPsnGy76a0l59Uh/juyzfeX6wUAWjD9tsvygut40ibad DkSkVX6tabzV6VZkV4qPyo8WM4x5nk+fQ2A3DN6PzHGt1DBlgWonnJJ2nSMBr9qDs18OT0Dz3hwmR zmZp/lKw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFZV-0005YG-IC; Fri, 17 Jul 2020 01:53:57 +0000 Received: from lucky1.263xmail.com ([211.157.147.134]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFZT-0005V6-2C for linux-rockchip@lists.infradead.org; Fri, 17 Jul 2020 01:53:55 +0000 Received: from localhost (unknown [192.168.167.16]) by lucky1.263xmail.com (Postfix) with ESMTP id 0B7B8C0A63; Fri, 17 Jul 2020 09:53:50 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P18585T140686961395456S1594950827543475_; Fri, 17 Jul 2020 09:53:48 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 12/13] pinctrl: rockchip: define common codes without special chip name Date: Fri, 17 Jul 2020 09:53:46 +0800 Message-Id: <20200717015346.14502-1-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_215355_356221_8AC68E90 X-CRM114-Status: UNSURE ( 8.41 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.134 listed in list.dnswl.org] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.134 listed in wl.mailspike.net] X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Modify RK3399_DRV_3BITS_PER_PIN to ROCKCHIP_DRV_3BITS_PER_PIN, and modify RK3288_DRV_BITS_PER_PIN to ROCKCHIP_DRV_BITS_PER_PIN. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 3b74455dcdb2..71a367896297 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -75,6 +75,9 @@ enum rockchip_pinctrl_type { #define IOMUX_WIDTH_3BIT BIT(4) #define IOMUX_WIDTH_2BIT BIT(5) +#define ROCKCHIP_DRV_3BITS_PER_PIN (3) +#define ROCKCHIP_DRV_BITS_PER_PIN (2) + /** * @type: iomux variant using IOMUX_* constants * @offset: if initialized to -1 it will be autocalculated, by specifying @@ -2074,7 +2077,6 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, #define RK3399_PULL_GRF_OFFSET 0xe040 #define RK3399_PULL_PMU_OFFSET 0x40 -#define RK3399_DRV_3BITS_PER_PIN 3 #define RK3399_PULL_BITS_PER_PIN 2 #define RK3399_PULL_PINS_PER_REG 8 #define RK3399_PULL_BANK_STRIDE 16 @@ -2154,7 +2156,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, switch (drv_type) { case DRV_TYPE_IO_1V8_3V0_AUTO: case DRV_TYPE_IO_3V3_ONLY: - rmask_bits = RK3399_DRV_3BITS_PER_PIN; + rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN; switch (bit) { case 0 ... 12: /* regular case, nothing to do */ @@ -2197,7 +2199,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, case DRV_TYPE_IO_DEFAULT: case DRV_TYPE_IO_1V8_OR_3V0: case DRV_TYPE_IO_1V8_ONLY: - rmask_bits = RK3288_DRV_BITS_PER_PIN; + rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN; break; default: dev_err(info->dev, "unsupported pinctrl drive type: %d\n", @@ -2251,7 +2253,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, switch (drv_type) { case DRV_TYPE_IO_1V8_3V0_AUTO: case DRV_TYPE_IO_3V3_ONLY: - rmask_bits = RK3399_DRV_3BITS_PER_PIN; + rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN; switch (bit) { case 0 ... 12: /* regular case, nothing to do */ @@ -2291,7 +2293,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, case DRV_TYPE_IO_DEFAULT: case DRV_TYPE_IO_1V8_OR_3V0: case DRV_TYPE_IO_1V8_ONLY: - rmask_bits = RK3288_DRV_BITS_PER_PIN; + rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN; break; default: dev_err(info->dev, "unsupported pinctrl drive type: %d\n", From patchwork Fri Jul 17 01:53:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668783 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 120BD138C for ; Fri, 17 Jul 2020 01:54:08 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D165D2076D for ; Fri, 17 Jul 2020 01:54:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="zdCPp/tv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D165D2076D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=hKTgQl1wdpDQTt3eScS7iCqBdQIi6rONVcWXwhy6Avg=; b=zdCPp/tvoGaqljgoHKlL+sUxbo IL5+DxqshwK6ViTIpdvXJS3789mVR96DCkLnCMk3ImcttNbDE7iFqA3bHtP9H1ZfCa4zzwsq4V0wO EGclcfYR5ezZpFbqUpmboqr6HNVCHvYNnNmykyVM33twwm7QsoQi2E55rHHf6ZdCEZ7pH/eeyaXIM HW6lBPFkTDgMMydDWw0MiwsrQUs8EH5RzSB0LDuHS0Vufc8Piyq39X12L160b9dh6JQYSAMW3bQ0W Zl5sMmQsqx/P8goNPay6hDMv6bHJ6/mcLZ0ddKfl2p+Jho2hqbNVmIfqCFuDpFTgnJ5vnoiOwcnIW cGD3MsAw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFZc-0005c8-4M; Fri, 17 Jul 2020 01:54:04 +0000 Received: from lucky1.263xmail.com ([211.157.147.134]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwFZY-0005ZK-M3 for linux-rockchip@lists.infradead.org; Fri, 17 Jul 2020 01:54:02 +0000 Received: from localhost (unknown [192.168.167.69]) by lucky1.263xmail.com (Postfix) with ESMTP id 8AF5CC0B43; Fri, 17 Jul 2020 09:53:57 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P18496T139713576945408S1594950835552484_; Fri, 17 Jul 2020 09:53:57 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <732be8f3d3131584136fd4449fbbf3ed> X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 13/13] pinctrl: rockchip: do codingstyle by adding mux route definitions Date: Fri, 17 Jul 2020 09:53:54 +0800 Message-Id: <20200717015354.14555-1-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com> References: <20200717014908.13914-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_215401_440223_E60B442B X-CRM114-Status: GOOD ( 11.53 ) X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.134 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.134 listed in wl.mailspike.net] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Add MR_SAME/MR_GRF/MR_PMU definitions, and update data in mux route structures. This patch do nothing change, only do some codingstyle. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 674 +++++------------------------ 1 file changed, 104 insertions(+), 570 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 71a367896297..50558ffcc05c 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -78,6 +78,9 @@ enum rockchip_pinctrl_type { #define ROCKCHIP_DRV_3BITS_PER_PIN (3) #define ROCKCHIP_DRV_BITS_PER_PIN (2) +#define RK_GENMASK_VAL(h, l, v) \ + (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) + /** * @type: iomux variant using IOMUX_* constants * @offset: if initialized to -1 it will be autocalculated, by specifying @@ -290,6 +293,25 @@ struct rockchip_pin_bank { .pull_type[3] = pull3, \ } +#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ + { \ + .bank_num = ID, \ + .pin = PIN, \ + .func = FUNC, \ + .route_offset = REG, \ + .route_val = VAL, \ + .route_location = FLAG, \ + } + +#define MR_SAME(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME) + +#define MR_GRF(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF) + +#define MR_PMU(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) + /** * struct rockchip_mux_recalced_data: represent a pin iomux data. * @num: bank number. @@ -804,597 +826,109 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, } static struct rockchip_mux_route_data px30_mux_route_data[] = { - { - /* cif-d2m0 */ - .bank_num = 2, - .pin = 0, - .func = 1, - .route_offset = 0x184, - .route_val = BIT(16 + 7), - }, { - /* cif-d2m1 */ - .bank_num = 3, - .pin = 3, - .func = 3, - .route_offset = 0x184, - .route_val = BIT(16 + 7) | BIT(7), - }, { - /* pdm-m0 */ - .bank_num = 3, - .pin = 22, - .func = 2, - .route_offset = 0x184, - .route_val = BIT(16 + 8), - }, { - /* pdm-m1 */ - .bank_num = 2, - .pin = 22, - .func = 1, - .route_offset = 0x184, - .route_val = BIT(16 + 8) | BIT(8), - }, { - /* uart2-rxm0 */ - .bank_num = 1, - .pin = 27, - .func = 2, - .route_offset = 0x184, - .route_val = BIT(16 + 10), - }, { - /* uart2-rxm1 */ - .bank_num = 2, - .pin = 14, - .func = 2, - .route_offset = 0x184, - .route_val = BIT(16 + 10) | BIT(10), - }, { - /* uart3-rxm0 */ - .bank_num = 0, - .pin = 17, - .func = 2, - .route_offset = 0x184, - .route_val = BIT(16 + 9), - }, { - /* uart3-rxm1 */ - .bank_num = 1, - .pin = 15, - .func = 2, - .route_offset = 0x184, - .route_val = BIT(16 + 9) | BIT(9), - }, + MR_SAME(2, 0, 1, 0x184, RK_GENMASK_VAL(7, 7, 0)), /* cif-d2m0 */ + MR_SAME(3, 3, 3, 0x184, RK_GENMASK_VAL(7, 7, 1)), /* cif-d2m1 */ + MR_SAME(3, 22, 2, 0x184, RK_GENMASK_VAL(8, 8, 0)), /* pdm-m0 */ + MR_SAME(2, 22, 1, 0x184, RK_GENMASK_VAL(8, 8, 1)), /* pdm-m1 */ + MR_SAME(0, 17, 2, 0x184, RK_GENMASK_VAL(9, 9, 0)), /* uart3-rxm0 */ + MR_SAME(1, 15, 2, 0x184, RK_GENMASK_VAL(9, 9, 1)), /* uart3-rxm1 */ + MR_SAME(1, 27, 2, 0x184, RK_GENMASK_VAL(10, 10, 0)), /* uart2-rxm0 */ + MR_SAME(2, 14, 2, 0x184, RK_GENMASK_VAL(10, 10, 1)), /* uart2-rxm1 */ }; static struct rockchip_mux_route_data rk3128_mux_route_data[] = { - { - /* spi-0 */ - .bank_num = 1, - .pin = 10, - .func = 1, - .route_offset = 0x144, - .route_val = BIT(16 + 3) | BIT(16 + 4), - }, { - /* spi-1 */ - .bank_num = 1, - .pin = 27, - .func = 3, - .route_offset = 0x144, - .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), - }, { - /* spi-2 */ - .bank_num = 0, - .pin = 13, - .func = 2, - .route_offset = 0x144, - .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), - }, { - /* i2s-0 */ - .bank_num = 1, - .pin = 5, - .func = 1, - .route_offset = 0x144, - .route_val = BIT(16 + 5), - }, { - /* i2s-1 */ - .bank_num = 0, - .pin = 14, - .func = 1, - .route_offset = 0x144, - .route_val = BIT(16 + 5) | BIT(5), - }, { - /* emmc-0 */ - .bank_num = 1, - .pin = 22, - .func = 2, - .route_offset = 0x144, - .route_val = BIT(16 + 6), - }, { - /* emmc-1 */ - .bank_num = 2, - .pin = 4, - .func = 2, - .route_offset = 0x144, - .route_val = BIT(16 + 6) | BIT(6), - }, + MR_SAME(1, 10, 1, 0x144, RK_GENMASK_VAL(4, 3, 0)), /* spi-0 */ + MR_SAME(1, 27, 3, 0x144, RK_GENMASK_VAL(4, 3, 1)), /* spi-1 */ + MR_SAME(0, 13, 2, 0x144, RK_GENMASK_VAL(4, 3, 2)), /* spi-2 */ + MR_SAME(1, 5, 1, 0x144, RK_GENMASK_VAL(5, 5, 0)), /* i2s-0 */ + MR_SAME(1, 14, 1, 0x144, RK_GENMASK_VAL(5, 5, 1)), /* i2s-1 */ + MR_SAME(1, 22, 2, 0x144, RK_GENMASK_VAL(6, 6, 0)), /* emmc-0 */ + MR_SAME(2, 4, 2, 0x144, RK_GENMASK_VAL(6, 6, 1)), /* emmc-1 */ }; static struct rockchip_mux_route_data rk3188_mux_route_data[] = { - { - /* non-iomuxed emmc/flash pins on flash-dqs */ - .bank_num = 0, - .pin = 24, - .func = 1, - .route_location = ROCKCHIP_ROUTE_GRF, - .route_offset = 0xa0, - .route_val = BIT(16 + 11), - }, { - /* non-iomuxed emmc/flash pins on emmc-clk */ - .bank_num = 0, - .pin = 24, - .func = 2, - .route_location = ROCKCHIP_ROUTE_GRF, - .route_offset = 0xa0, - .route_val = BIT(16 + 11) | BIT(11), - }, + /* non-iomuxed emmc/flash pins on flash-dqs */ + MR_GRF(0, 24, 1, 0xa0, RK_GENMASK_VAL(11, 11, 0)), + /* non-iomuxed emmc/flash pins on emmc-clk */ + MR_GRF(0, 24, 2, 0xa0, RK_GENMASK_VAL(11, 11, 1)), }; static struct rockchip_mux_route_data rk3228_mux_route_data[] = { - { - /* pwm0-0 */ - .bank_num = 0, - .pin = 26, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16), - }, { - /* pwm0-1 */ - .bank_num = 3, - .pin = 21, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16) | BIT(0), - }, { - /* pwm1-0 */ - .bank_num = 0, - .pin = 27, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 1), - }, { - /* pwm1-1 */ - .bank_num = 0, - .pin = 30, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 1) | BIT(1), - }, { - /* pwm2-0 */ - .bank_num = 0, - .pin = 28, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 2), - }, { - /* pwm2-1 */ - .bank_num = 1, - .pin = 12, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 2) | BIT(2), - }, { - /* pwm3-0 */ - .bank_num = 3, - .pin = 26, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 3), - }, { - /* pwm3-1 */ - .bank_num = 1, - .pin = 11, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 3) | BIT(3), - }, { - /* sdio-0_d0 */ - .bank_num = 1, - .pin = 1, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 4), - }, { - /* sdio-1_d0 */ - .bank_num = 3, - .pin = 2, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 4) | BIT(4), - }, { - /* spi-0_rx */ - .bank_num = 0, - .pin = 13, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 5), - }, { - /* spi-1_rx */ - .bank_num = 2, - .pin = 0, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 5) | BIT(5), - }, { - /* emmc-0_cmd */ - .bank_num = 1, - .pin = 22, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 7), - }, { - /* emmc-1_cmd */ - .bank_num = 2, - .pin = 4, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 7) | BIT(7), - }, { - /* uart2-0_rx */ - .bank_num = 1, - .pin = 19, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 8), - }, { - /* uart2-1_rx */ - .bank_num = 1, - .pin = 10, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 8) | BIT(8), - }, { - /* uart1-0_rx */ - .bank_num = 1, - .pin = 10, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 11), - }, { - /* uart1-1_rx */ - .bank_num = 3, - .pin = 13, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 11) | BIT(11), - }, + MR_SAME(0, 26, 1, 0x50, RK_GENMASK_VAL(0, 0, 0)), /* pwm0-0 */ + MR_SAME(3, 21, 1, 0x50, RK_GENMASK_VAL(0, 0, 1)), /* pwm0-1 */ + MR_SAME(0, 27, 1, 0x50, RK_GENMASK_VAL(1, 1, 0)), /* pwm1-0 */ + MR_SAME(0, 30, 2, 0x50, RK_GENMASK_VAL(1, 1, 1)), /* pwm1-1 */ + MR_SAME(0, 28, 1, 0x50, RK_GENMASK_VAL(2, 2, 0)), /* pwm2-0 */ + MR_SAME(1, 12, 2, 0x50, RK_GENMASK_VAL(2, 2, 1)), /* pwm2-1 */ + MR_SAME(3, 26, 1, 0x50, RK_GENMASK_VAL(3, 3, 0)), /* pwm3-0 */ + MR_SAME(1, 11, 2, 0x50, RK_GENMASK_VAL(3, 3, 1)), /* pwm3-1 */ + MR_SAME(1, 1, 1, 0x50, RK_GENMASK_VAL(4, 4, 0)), /* sdio-0_d0 */ + MR_SAME(3, 2, 1, 0x50, RK_GENMASK_VAL(4, 4, 1)), /* sdio-1_d0 */ + MR_SAME(0, 13, 2, 0x50, RK_GENMASK_VAL(5, 5, 0)), /* spi-0_rx */ + MR_SAME(2, 0, 2, 0x50, RK_GENMASK_VAL(5, 5, 1)), /* spi-1_rx */ + MR_SAME(1, 22, 2, 0x50, RK_GENMASK_VAL(7, 7, 0)), /* emmc-0_cmd */ + MR_SAME(2, 4, 2, 0x50, RK_GENMASK_VAL(7, 7, 1)), /* emmc-1_cmd */ + MR_SAME(1, 19, 2, 0x50, RK_GENMASK_VAL(8, 8, 0)), /* uart2-0_rx */ + MR_SAME(1, 10, 2, 0x50, RK_GENMASK_VAL(8, 8, 1)), /* uart2-1_rx */ + MR_SAME(1, 10, 1, 0x50, RK_GENMASK_VAL(11, 11, 0)), /* uart1-0_rx */ + MR_SAME(3, 13, 1, 0x50, RK_GENMASK_VAL(11, 11, 1)), /* uart1-1_rx */ }; static struct rockchip_mux_route_data rk3288_mux_route_data[] = { - { - /* edphdmi_cecinoutt1 */ - .bank_num = 7, - .pin = 16, - .func = 2, - .route_offset = 0x264, - .route_val = BIT(16 + 12) | BIT(12), - }, { - /* edphdmi_cecinout */ - .bank_num = 7, - .pin = 23, - .func = 4, - .route_offset = 0x264, - .route_val = BIT(16 + 12), - }, + MR_SAME(7, 16, 2, 0x264, RK_GENMASK_VAL(12, 12, 1)), /* edphdmi_cecinoutt1 */ + MR_SAME(7, 23, 4, 0x264, RK_GENMASK_VAL(12, 12, 0)), /* edphdmi_cecinout */ }; static struct rockchip_mux_route_data rk3308_mux_route_data[] = { - { - /* rtc_clk */ - .bank_num = 0, - .pin = 19, - .func = 1, - .route_offset = 0x314, - .route_val = BIT(16 + 0) | BIT(0), - }, { - /* uart2_rxm0 */ - .bank_num = 1, - .pin = 22, - .func = 2, - .route_offset = 0x314, - .route_val = BIT(16 + 2) | BIT(16 + 3), - }, { - /* uart2_rxm1 */ - .bank_num = 4, - .pin = 26, - .func = 2, - .route_offset = 0x314, - .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), - }, { - /* i2c3_sdam0 */ - .bank_num = 0, - .pin = 15, - .func = 2, - .route_offset = 0x608, - .route_val = BIT(16 + 8) | BIT(16 + 9), - }, { - /* i2c3_sdam1 */ - .bank_num = 3, - .pin = 12, - .func = 2, - .route_offset = 0x608, - .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), - }, { - /* i2c3_sdam2 */ - .bank_num = 2, - .pin = 0, - .func = 3, - .route_offset = 0x608, - .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), - }, { - /* i2s-8ch-1-sclktxm0 */ - .bank_num = 1, - .pin = 3, - .func = 2, - .route_offset = 0x308, - .route_val = BIT(16 + 3), - }, { - /* i2s-8ch-1-sclkrxm0 */ - .bank_num = 1, - .pin = 4, - .func = 2, - .route_offset = 0x308, - .route_val = BIT(16 + 3), - }, { - /* i2s-8ch-1-sclktxm1 */ - .bank_num = 1, - .pin = 13, - .func = 2, - .route_offset = 0x308, - .route_val = BIT(16 + 3) | BIT(3), - }, { - /* i2s-8ch-1-sclkrxm1 */ - .bank_num = 1, - .pin = 14, - .func = 2, - .route_offset = 0x308, - .route_val = BIT(16 + 3) | BIT(3), - }, { - /* pdm-clkm0 */ - .bank_num = 1, - .pin = 4, - .func = 3, - .route_offset = 0x308, - .route_val = BIT(16 + 12) | BIT(16 + 13), - }, { - /* pdm-clkm1 */ - .bank_num = 1, - .pin = 14, - .func = 4, - .route_offset = 0x308, - .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), - }, { - /* pdm-clkm2 */ - .bank_num = 2, - .pin = 6, - .func = 2, - .route_offset = 0x308, - .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), - }, { - /* pdm-clkm-m2 */ - .bank_num = 2, - .pin = 4, - .func = 3, - .route_offset = 0x600, - .route_val = BIT(16 + 2) | BIT(2), - }, { - /* spi1_miso */ - .bank_num = 3, - .pin = 10, - .func = 3, - .route_offset = 0x314, - .route_val = BIT(16 + 9), - }, { - /* spi1_miso_m1 */ - .bank_num = 2, - .pin = 4, - .func = 2, - .route_offset = 0x314, - .route_val = BIT(16 + 9) | BIT(9), - }, { - /* owire_m0 */ - .bank_num = 0, - .pin = 11, - .func = 3, - .route_offset = 0x314, - .route_val = BIT(16 + 10) | BIT(16 + 11), - }, { - /* owire_m1 */ - .bank_num = 1, - .pin = 22, - .func = 7, - .route_offset = 0x314, - .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), - }, { - /* owire_m2 */ - .bank_num = 2, - .pin = 2, - .func = 5, - .route_offset = 0x314, - .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), - }, { - /* can_rxd_m0 */ - .bank_num = 0, - .pin = 11, - .func = 2, - .route_offset = 0x314, - .route_val = BIT(16 + 12) | BIT(16 + 13), - }, { - /* can_rxd_m1 */ - .bank_num = 1, - .pin = 22, - .func = 5, - .route_offset = 0x314, - .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), - }, { - /* can_rxd_m2 */ - .bank_num = 2, - .pin = 2, - .func = 4, - .route_offset = 0x314, - .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), - }, { - /* mac_rxd0_m0 */ - .bank_num = 1, - .pin = 20, - .func = 3, - .route_offset = 0x314, - .route_val = BIT(16 + 14), - }, { - /* mac_rxd0_m1 */ - .bank_num = 4, - .pin = 2, - .func = 2, - .route_offset = 0x314, - .route_val = BIT(16 + 14) | BIT(14), - }, { - /* uart3_rx */ - .bank_num = 3, - .pin = 12, - .func = 4, - .route_offset = 0x314, - .route_val = BIT(16 + 15), - }, { - /* uart3_rx_m1 */ - .bank_num = 0, - .pin = 17, - .func = 3, - .route_offset = 0x314, - .route_val = BIT(16 + 15) | BIT(15), - }, + MR_SAME(0, 19, 1, 0x314, RK_GENMASK_VAL(0, 0, 1)), /* rtc_clk */ + MR_SAME(1, 22, 2, 0x314, RK_GENMASK_VAL(3, 2, 0)), /* uart2_rxm0 */ + MR_SAME(4, 26, 2, 0x314, RK_GENMASK_VAL(3, 2, 1)), /* uart2_rxm1 */ + MR_SAME(0, 15, 2, 0x608, RK_GENMASK_VAL(9, 8, 0)), /* i2c3_sdam0 */ + MR_SAME(3, 12, 2, 0x608, RK_GENMASK_VAL(9, 8, 1)), /* i2c3_sdam1 */ + MR_SAME(2, 0, 3, 0x608, RK_GENMASK_VAL(9, 8, 2)), /* i2c3_sdam2 */ + MR_SAME(1, 3, 2, 0x308, RK_GENMASK_VAL(3, 3, 0)), /* i2s-8ch-1-sclktxm0 */ + MR_SAME(1, 4, 2, 0x308, RK_GENMASK_VAL(3, 3, 0)), /* i2s-8ch-1-sclkrxm0 */ + MR_SAME(1, 13, 2, 0x308, RK_GENMASK_VAL(3, 3, 1)), /* i2s-8ch-1-sclktxm1 */ + MR_SAME(1, 14, 2, 0x308, RK_GENMASK_VAL(3, 3, 1)), /* i2s-8ch-1-sclkrxm1 */ + MR_SAME(1, 4, 3, 0x308, RK_GENMASK_VAL(13, 12, 0)), /* pdm-clkm0 */ + MR_SAME(1, 14, 4, 0x308, RK_GENMASK_VAL(13, 12, 1)), /* pdm-clkm1 */ + MR_SAME(2, 6, 2, 0x308, RK_GENMASK_VAL(13, 12, 2)), /* pdm-clkm2 */ + MR_SAME(2, 4, 3, 0x600, RK_GENMASK_VAL(2, 2, 1)), /* pdm-clkm-m2 */ + MR_SAME(3, 10, 3, 0x314, RK_GENMASK_VAL(9, 9, 0)), /* spi1_miso */ + MR_SAME(2, 4, 2, 0x314, RK_GENMASK_VAL(9, 9, 1)), /* spi1_miso_m1 */ + MR_SAME(0, 11, 3, 0x314, RK_GENMASK_VAL(11, 10, 0)), /* owire_m0 */ + MR_SAME(1, 22, 7, 0x314, RK_GENMASK_VAL(11, 10, 1)), /* owire_m1 */ + MR_SAME(2, 2, 5, 0x314, RK_GENMASK_VAL(11, 10, 2)), /* owire_m2 */ + MR_SAME(0, 11, 2, 0x314, RK_GENMASK_VAL(13, 12, 0)), /* can_rxd_m0 */ + MR_SAME(1, 22, 5, 0x314, RK_GENMASK_VAL(13, 12, 1)), /* can_rxd_m1 */ + MR_SAME(2, 2, 4, 0x314, RK_GENMASK_VAL(13, 12, 2)), /* can_rxd_m2 */ + MR_SAME(1, 20, 3, 0x314, RK_GENMASK_VAL(14, 14, 0)), /* mac_rxd0_m0 */ + MR_SAME(4, 2, 2, 0x314, RK_GENMASK_VAL(14, 14, 1)), /* mac_rxd0_m1 */ + MR_SAME(3, 12, 4, 0x314, RK_GENMASK_VAL(15, 15, 0)), /* uart3_rx */ + MR_SAME(0, 17, 3, 0x314, RK_GENMASK_VAL(15, 15, 1)), /* uart3_rx_m1 */ }; static struct rockchip_mux_route_data rk3328_mux_route_data[] = { - { - /* uart2dbg_rxm0 */ - .bank_num = 1, - .pin = 1, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16) | BIT(16 + 1), - }, { - /* uart2dbg_rxm1 */ - .bank_num = 2, - .pin = 1, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16) | BIT(16 + 1) | BIT(0), - }, { - /* gmac-m1_rxd0 */ - .bank_num = 1, - .pin = 11, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 2) | BIT(2), - }, { - /* gmac-m1-optimized_rxd3 */ - .bank_num = 1, - .pin = 14, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 10) | BIT(10), - }, { - /* pdm_sdi0m0 */ - .bank_num = 2, - .pin = 19, - .func = 2, - .route_offset = 0x50, - .route_val = BIT(16 + 3), - }, { - /* pdm_sdi0m1 */ - .bank_num = 1, - .pin = 23, - .func = 3, - .route_offset = 0x50, - .route_val = BIT(16 + 3) | BIT(3), - }, { - /* spi_rxdm2 */ - .bank_num = 3, - .pin = 2, - .func = 4, - .route_offset = 0x50, - .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), - }, { - /* i2s2_sdim0 */ - .bank_num = 1, - .pin = 24, - .func = 1, - .route_offset = 0x50, - .route_val = BIT(16 + 6), - }, { - /* i2s2_sdim1 */ - .bank_num = 3, - .pin = 2, - .func = 6, - .route_offset = 0x50, - .route_val = BIT(16 + 6) | BIT(6), - }, { - /* card_iom1 */ - .bank_num = 2, - .pin = 22, - .func = 3, - .route_offset = 0x50, - .route_val = BIT(16 + 7) | BIT(7), - }, { - /* tsp_d5m1 */ - .bank_num = 2, - .pin = 16, - .func = 3, - .route_offset = 0x50, - .route_val = BIT(16 + 8) | BIT(8), - }, { - /* cif_data5m1 */ - .bank_num = 2, - .pin = 16, - .func = 4, - .route_offset = 0x50, - .route_val = BIT(16 + 9) | BIT(9), - }, + MR_SAME(1, 1, 2, 0x50, RK_GENMASK_VAL(1, 0, 0)), /* uart2dbg_rxm0 */ + MR_SAME(2, 1, 1, 0x50, RK_GENMASK_VAL(1, 0, 1)), /* uart2dbg_rxm1 */ + MR_SAME(1, 11, 2, 0x50, RK_GENMASK_VAL(2, 2, 1)), /* gmac-m1_rxd0 */ + MR_SAME(1, 14, 2, 0x50, RK_GENMASK_VAL(10, 10, 1)), /* gmac-m1-optimized_rxd3 */ + MR_SAME(2, 19, 2, 0x50, RK_GENMASK_VAL(3, 3, 0)), /* pdm_sdi0m0 */ + MR_SAME(1, 23, 3, 0x50, RK_GENMASK_VAL(3, 3, 1)), /* pdm_sdi0m1 */ + MR_SAME(3, 2, 4, 0x50, RK_GENMASK_VAL(5, 4, 2)), /* spi_rxdm2 */ + MR_SAME(1, 24, 1, 0x50, RK_GENMASK_VAL(6, 6, 0)), /* i2s2_sdim0 */ + MR_SAME(3, 2, 6, 0x50, RK_GENMASK_VAL(6, 6, 1)), /* i2s2_sdim1 */ + MR_SAME(2, 22, 3, 0x50, RK_GENMASK_VAL(7, 7, 1)), /* card_iom1 */ + MR_SAME(2, 16, 3, 0x50, RK_GENMASK_VAL(8, 8, 1)), /* tsp_d5m1 */ + MR_SAME(2, 16, 4, 0x50, RK_GENMASK_VAL(9, 9, 1)), /* cif_data5m1 */ }; static struct rockchip_mux_route_data rk3399_mux_route_data[] = { - { - /* uart2dbga_rx */ - .bank_num = 4, - .pin = 8, - .func = 2, - .route_offset = 0xe21c, - .route_val = BIT(16 + 10) | BIT(16 + 11), - }, { - /* uart2dbgb_rx */ - .bank_num = 4, - .pin = 16, - .func = 2, - .route_offset = 0xe21c, - .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), - }, { - /* uart2dbgc_rx */ - .bank_num = 4, - .pin = 19, - .func = 1, - .route_offset = 0xe21c, - .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), - }, { - /* pcie_clkreqn */ - .bank_num = 2, - .pin = 26, - .func = 2, - .route_offset = 0xe21c, - .route_val = BIT(16 + 14), - }, { - /* pcie_clkreqnb */ - .bank_num = 4, - .pin = 24, - .func = 1, - .route_offset = 0xe21c, - .route_val = BIT(16 + 14) | BIT(14), - }, + MR_SAME(4, 8, 2, 0xe21c, RK_GENMASK_VAL(11, 10, 0)), /* uart2dbga_rx */ + MR_SAME(4, 16, 2, 0xe21c, RK_GENMASK_VAL(11, 10, 1)), /* uart2dbgb_rx */ + MR_SAME(4, 19, 1, 0xe21c, RK_GENMASK_VAL(11, 10, 2)), /* uart2dbgc_rx */ + MR_SAME(2, 26, 2, 0xe21c, RK_GENMASK_VAL(14, 14, 0)), /* pcie_clkreqn */ + MR_SAME(4, 24, 1, 0xe21c, RK_GENMASK_VAL(14, 14, 1)), /* pcie_clkreqnb */ }; static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,