From patchwork Fri Jul 17 13:29:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 11670219 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 53A6E138C for ; Fri, 17 Jul 2020 13:29:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 38D7A20717 for ; Fri, 17 Jul 2020 13:29:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="nOJgcJ0X" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726386AbgGQN35 (ORCPT ); Fri, 17 Jul 2020 09:29:57 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:30134 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726090AbgGQN34 (ORCPT ); Fri, 17 Jul 2020 09:29:56 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1594992595; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=qvFYV5gSdJN7uGe/5cfb+tk9FUbHSiqsuZE2Uf3f6Vs=; b=nOJgcJ0XYqVrMbo9kQ9CUm4GIE1AOLVxHBtNDtAjK1FvpcphT+0Nm88JFMTCxEuTcQi8gMAT ggLGVkar6wNoie6IkgOF1tcoG69m137B05pFLW2kRjl1JTr67x9Ks+5vvMMTBbbao5vMO/sD hhPI1vUxmqA3VQy/e2FL5eg8U5E= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n16.prod.us-west-2.postgun.com with SMTP id 5f11a7d3ee86618575f31dc5 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 17 Jul 2020 13:29:55 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id E314EC433AF; Fri, 17 Jul 2020 13:29:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from akhilpo-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akhilpo) by smtp.codeaurora.org (Postfix) with ESMTPSA id 65EA4C433CA; Fri, 17 Jul 2020 13:29:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 65EA4C433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akhilpo@codeaurora.org From: Akhil P Oommen To: freedreno@lists.freedesktop.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, smasetty@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, saravanak@google.com, sibis@codeaurora.org, viresh.kumar@linaro.org, jonathan@marek.ca, robdclark@gmail.com, bjorn.andersson@linaro.org Subject: [PATCH v6 1/6] dt-bindings: drm/msm/gpu: Document gpu opp table Date: Fri, 17 Jul 2020 18:59:34 +0530 Message-Id: <1594992579-20662-2-git-send-email-akhilpo@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594992579-20662-1-git-send-email-akhilpo@codeaurora.org> References: <1594992579-20662-1-git-send-email-akhilpo@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sharat Masetty Update documentation to list the gpu opp table bindings including the newly added "opp-peak-kBps" needed for GPU-DDR bandwidth scaling. Signed-off-by: Sharat Masetty Acked-by: Rob Herring Signed-off-by: Akhil P Oommen --- .../devicetree/bindings/display/msm/gpu.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index fd779cd..1af0ff1 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -112,6 +112,34 @@ Example a6xx (with GMU): interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; interconnect-names = "gfx-mem"; + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = ; + opp-peak-kBps = <5412000>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = ; + opp-peak-kBps = <3072000>; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = ; + opp-peak-kBps = <3072000>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = ; + opp-peak-kBps = <1804000>; + }; + }; + qcom,gmu = <&gmu>; zap-shader { From patchwork Fri Jul 17 13:29:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 11670235 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 63E966C1 for ; Fri, 17 Jul 2020 13:30:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4175D20775 for ; Fri, 17 Jul 2020 13:30:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="elYuNJ6j" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726393AbgGQNac (ORCPT ); Fri, 17 Jul 2020 09:30:32 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:25836 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726221AbgGQNac (ORCPT ); Fri, 17 Jul 2020 09:30:32 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1594992631; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=EWYW/NS+fcpY2xbip8v2hloAa0bhAsxsf6dtJYGR1Bs=; b=elYuNJ6juyYdpf9u3UNBSVoJ/gP4hEw8TiE+u86P+vBHsX5iAherwMCNUBLBFXnzUtwalURT AVDnCSTyqtvW1lDP2q+bRRX0slsPDHfkIZlWx+YuRZ6EiRU6Ef+Ls4ZlN+SpEbTGd8YiYuqf H2F4X3yQUmamyeMHB5sk6icA+Ts= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n02.prod.us-west-2.postgun.com with SMTP id 5f11a7d98e36ecda301630a4 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 17 Jul 2020 13:30:01 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 17F8BC433B6; Fri, 17 Jul 2020 13:30:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from akhilpo-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akhilpo) by smtp.codeaurora.org (Postfix) with ESMTPSA id E3FDAC433AD; Fri, 17 Jul 2020 13:29:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E3FDAC433AD Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akhilpo@codeaurora.org From: Akhil P Oommen To: freedreno@lists.freedesktop.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, smasetty@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, saravanak@google.com, sibis@codeaurora.org, viresh.kumar@linaro.org, jonathan@marek.ca, robdclark@gmail.com, bjorn.andersson@linaro.org Subject: [PATCH v6 2/6] drm: msm: a6xx: send opp instead of a frequency Date: Fri, 17 Jul 2020 18:59:35 +0530 Message-Id: <1594992579-20662-3-git-send-email-akhilpo@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594992579-20662-1-git-send-email-akhilpo@codeaurora.org> References: <1594992579-20662-1-git-send-email-akhilpo@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sharat Masetty This patch changes the plumbing to send the devfreq recommended opp rather than the frequency. Also consolidate and rearrange the code in a6xx to set the GPU frequency and the icc vote in preparation for the upcoming changes for GPU->DDR scaling votes. Signed-off-by: Sharat Masetty Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 89 +++++++++++++++++++---------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/msm_gpu.c | 3 +- drivers/gpu/drm/msm/msm_gpu.h | 3 +- 4 files changed, 52 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 21e77d6..856db46 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -103,17 +103,45 @@ bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); } -static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) +void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) { - struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); - struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; - struct msm_gpu *gpu = &adreno_gpu->base; - int ret; + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; + u32 perf_index; + unsigned long gpu_freq; + int ret = 0; + + gpu_freq = dev_pm_opp_get_freq(opp); + + if (gpu_freq == gmu->freq) + return; + + for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) + if (gpu_freq == gmu->gpu_freqs[perf_index]) + break; + + gmu->current_perf_index = perf_index; + gmu->freq = gmu->gpu_freqs[perf_index]; + + /* + * This can get called from devfreq while the hardware is idle. Don't + * bring up the power if it isn't already active + */ + if (pm_runtime_get_if_in_use(gmu->dev) == 0) + return; + + if (!gmu->legacy) { + a6xx_hfi_set_freq(gmu, perf_index); + icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); + pm_runtime_put(gmu->dev); + return; + } gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, - ((3 & 0xf) << 28) | index); + ((3 & 0xf) << 28) | perf_index); /* * Send an invalid index as a vote for the bus bandwidth and let the @@ -134,37 +162,6 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) * for now leave it at max so that the performance is nominal. */ icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); -} - -void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq) -{ - struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - struct a6xx_gmu *gmu = &a6xx_gpu->gmu; - u32 perf_index = 0; - - if (freq == gmu->freq) - return; - - for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) - if (freq == gmu->gpu_freqs[perf_index]) - break; - - gmu->current_perf_index = perf_index; - gmu->freq = gmu->gpu_freqs[perf_index]; - - /* - * This can get called from devfreq while the hardware is idle. Don't - * bring up the power if it isn't already active - */ - if (pm_runtime_get_if_in_use(gmu->dev) == 0) - return; - - if (gmu->legacy) - __a6xx_gmu_set_freq(gmu, perf_index); - else - a6xx_hfi_set_freq(gmu, perf_index); - pm_runtime_put(gmu->dev); } @@ -839,6 +836,19 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) a6xx_gmu_rpmh_off(gmu); } +static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) +{ + struct dev_pm_opp *gpu_opp; + unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; + + gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); + if (IS_ERR_OR_NULL(gpu_opp)) + return; + + a6xx_gmu_set_freq(gpu, gpu_opp); + dev_pm_opp_put(gpu_opp); +} + int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; @@ -898,10 +908,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) enable_irq(gmu->hfi_irq); /* Set the GPU to the current freq */ - if (gmu->legacy) - __a6xx_gmu_set_freq(gmu, gmu->current_perf_index); - else - a6xx_hfi_set_freq(gmu, gmu->current_perf_index); + a6xx_gmu_set_initial_freq(gpu, gmu); /* * "enable" the GX power domain which won't actually do anything but it diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 7239b8b..03ba60d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -63,7 +63,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); -void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq); +void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp); unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index a22d306..82eb727 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -13,7 +13,6 @@ #include #include -#include #include #include #include @@ -34,7 +33,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq, return PTR_ERR(opp); if (gpu->funcs->gpu_set_freq) - gpu->funcs->gpu_set_freq(gpu, (u64)*freq); + gpu->funcs->gpu_set_freq(gpu, opp); else clk_set_rate(gpu->core_clk, *freq); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 429cb40..0db117a 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -9,6 +9,7 @@ #include #include +#include #include #include "msm_drv.h" @@ -61,7 +62,7 @@ struct msm_gpu_funcs { struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu); int (*gpu_state_put)(struct msm_gpu_state *state); unsigned long (*gpu_get_freq)(struct msm_gpu *gpu); - void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq); + void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp); struct msm_gem_address_space *(*create_address_space) (struct msm_gpu *gpu, struct platform_device *pdev); }; From patchwork Fri Jul 17 13:29:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 11670239 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 78A56138C for ; Fri, 17 Jul 2020 13:30:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5F0992067D for ; Fri, 17 Jul 2020 13:30:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="XRf0Hp00" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726761AbgGQNal (ORCPT ); Fri, 17 Jul 2020 09:30:41 -0400 Received: from mail29.static.mailgun.info ([104.130.122.29]:24604 "EHLO mail29.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726344AbgGQNal (ORCPT ); Fri, 17 Jul 2020 09:30:41 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1594992640; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=bPEgtL/MSbVgLWyY5yA0N+moWARpJvT0UPnIgruiK+4=; b=XRf0Hp00enw9niXku20ehU1HtmcMrPTBA+RSLgLQWLycwBulO0HcRFwzt6ooybqDhKd2Oloe SXc+zPK3ucqn1tcb+htZceThU2n+OQlqrItitFmTPrgyo66ucM7BUh69OYJujIS41OzeiZfL yHy4KXLHuaS35nW6QjIn+S+tyPA= X-Mailgun-Sending-Ip: 104.130.122.29 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n08.prod.us-west-2.postgun.com with SMTP id 5f11a7ddc9bd2efa2ef1fb2e (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 17 Jul 2020 13:30:05 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 3C315C433B1; Fri, 17 Jul 2020 13:30:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from akhilpo-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akhilpo) by smtp.codeaurora.org (Postfix) with ESMTPSA id 720CFC433A0; Fri, 17 Jul 2020 13:29:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 720CFC433A0 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akhilpo@codeaurora.org From: Akhil P Oommen To: freedreno@lists.freedesktop.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, smasetty@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, saravanak@google.com, sibis@codeaurora.org, viresh.kumar@linaro.org, jonathan@marek.ca, robdclark@gmail.com, bjorn.andersson@linaro.org Subject: [PATCH v6 3/6] drm: msm: a6xx: use dev_pm_opp_set_bw to scale DDR Date: Fri, 17 Jul 2020 18:59:36 +0530 Message-Id: <1594992579-20662-4-git-send-email-akhilpo@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594992579-20662-1-git-send-email-akhilpo@codeaurora.org> References: <1594992579-20662-1-git-send-email-akhilpo@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sharat Masetty This patches replaces the previously used static DDR vote and uses dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling GPU frequency. Also since the icc path voting is handled completely in the opp driver, remove the icc_path handle and its usage in the drm driver. Signed-off-by: Sharat Masetty Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 856db46..a6f43ff 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -133,7 +133,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) if (!gmu->legacy) { a6xx_hfi_set_freq(gmu, perf_index); - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); + dev_pm_opp_set_bw(&gpu->pdev->dev, opp); pm_runtime_put(gmu->dev); return; } @@ -157,11 +157,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) if (ret) dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); - /* - * Eventually we will want to scale the path vote with the frequency but - * for now leave it at max so that the performance is nominal. - */ - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); + dev_pm_opp_set_bw(&gpu->pdev->dev, opp); pm_runtime_put(gmu->dev); } @@ -849,6 +845,19 @@ static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) dev_pm_opp_put(gpu_opp); } +static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) +{ + struct dev_pm_opp *gpu_opp; + unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; + + gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); + if (IS_ERR_OR_NULL(gpu_opp)) + return; + + dev_pm_opp_set_bw(&gpu->pdev->dev, gpu_opp); + dev_pm_opp_put(gpu_opp); +} + int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; @@ -873,7 +882,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) } /* Set the bus quota to a reasonable value for boot */ - icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072)); + a6xx_gmu_set_initial_bw(gpu, gmu); /* Enable the GMU interrupt */ gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); @@ -1049,7 +1058,7 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) a6xx_gmu_shutdown(gmu); /* Remove the bus vote */ - icc_set_bw(gpu->icc_path, 0, 0); + dev_pm_opp_set_bw(&gpu->pdev->dev, NULL); /* * Make sure the GX domain is off before turning off the GMU (CX) From patchwork Fri Jul 17 13:29:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 11670225 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ADD996C1 for ; Fri, 17 Jul 2020 13:30:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 955FB20775 for ; Fri, 17 Jul 2020 13:30:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="XUArZY1l" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726556AbgGQNaL (ORCPT ); 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Fri, 17 Jul 2020 13:30:09 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 7BE6CC433AF; Fri, 17 Jul 2020 13:30:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from akhilpo-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akhilpo) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5A72CC433CB; Fri, 17 Jul 2020 13:30:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5A72CC433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akhilpo@codeaurora.org From: Akhil P Oommen To: freedreno@lists.freedesktop.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, smasetty@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, saravanak@google.com, sibis@codeaurora.org, viresh.kumar@linaro.org, jonathan@marek.ca, robdclark@gmail.com, bjorn.andersson@linaro.org Subject: [PATCH v6 4/6] arm64: dts: qcom: SDM845: Enable GPU DDR bw scaling Date: Fri, 17 Jul 2020 18:59:37 +0530 Message-Id: <1594992579-20662-5-git-send-email-akhilpo@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594992579-20662-1-git-send-email-akhilpo@codeaurora.org> References: <1594992579-20662-1-git-send-email-akhilpo@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sharat Masetty This patch adds the interconnects property for the gpu node and the opp-peak-kBps property to the opps of the gpu opp table. This should help enable DDR bandwidth scaling dynamically and proportionally to the GPU frequency. Signed-off-by: Sharat Masetty Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 8eb5a31..1cd2dae 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3515,42 +3515,52 @@ qcom,gmu = <&gmu>; + interconnects = <&mem_noc MASTER_GFX3D &mem_noc SLAVE_EBI1>; + interconnect-names = "gfx-mem"; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-710000000 { opp-hz = /bits/ 64 <710000000>; opp-level = ; + opp-peak-kBps = <7216000>; }; opp-675000000 { opp-hz = /bits/ 64 <675000000>; opp-level = ; + opp-peak-kBps = <7216000>; }; opp-596000000 { opp-hz = /bits/ 64 <596000000>; opp-level = ; + opp-peak-kBps = <6220000>; }; opp-520000000 { opp-hz = /bits/ 64 <520000000>; opp-level = ; + opp-peak-kBps = <6220000>; }; opp-414000000 { opp-hz = /bits/ 64 <414000000>; opp-level = ; + opp-peak-kBps = <4068000>; }; opp-342000000 { opp-hz = /bits/ 64 <342000000>; opp-level = ; + opp-peak-kBps = <2724000>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; opp-level = ; + opp-peak-kBps = <1648000>; }; }; }; From patchwork Fri Jul 17 13:29:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 11670251 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2C6396C1 for ; Fri, 17 Jul 2020 13:31:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0B70D207EA for ; Fri, 17 Jul 2020 13:31:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="QD20TezB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726524AbgGQNbK (ORCPT ); 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Fri, 17 Jul 2020 13:30:14 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 066FBC433C6; Fri, 17 Jul 2020 13:30:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from akhilpo-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akhilpo) by smtp.codeaurora.org (Postfix) with ESMTPSA id 1237DC433AD; Fri, 17 Jul 2020 13:30:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 1237DC433AD Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akhilpo@codeaurora.org From: Akhil P Oommen To: freedreno@lists.freedesktop.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, smasetty@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, saravanak@google.com, sibis@codeaurora.org, viresh.kumar@linaro.org, jonathan@marek.ca, robdclark@gmail.com, bjorn.andersson@linaro.org Subject: [PATCH v6 5/6] arm64: dts: qcom: sc7180: Add interconnects property for GPU Date: Fri, 17 Jul 2020 18:59:38 +0530 Message-Id: <1594992579-20662-6-git-send-email-akhilpo@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594992579-20662-1-git-send-email-akhilpo@codeaurora.org> References: <1594992579-20662-1-git-send-email-akhilpo@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sharat Masetty This patch adds the interconnects property to the GPU node. This enables the GPU->DDR path bandwidth voting. Signed-off-by: Sharat Masetty Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 31b9217..80fe54b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1470,6 +1470,9 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gfx-mem"; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; From patchwork Fri Jul 17 13:29:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 11670241 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A91346C1 for ; Fri, 17 Jul 2020 13:30:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 90B5820717 for ; Fri, 17 Jul 2020 13:30:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="mLmcVvEt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726851AbgGQNaq (ORCPT ); Fri, 17 Jul 2020 09:30:46 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:25836 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726383AbgGQNap (ORCPT ); Fri, 17 Jul 2020 09:30:45 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1594992645; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=YQ4zTOzVY7tD8+0LunMnnTS0zV8fWFiSWwGe3hpL4w0=; b=mLmcVvEt/ohadz14BDkPe8J4ObtTpQ6LVsV6Jcw+ef6wnTq0HVjWpPEtHrmj98HP0Ua4aE8H rw+vkhCPrpPaX+FmalpxNvGEPoANWoM0gq1pLqwNddYYKIrBK92hZk0L0c4NhO3KS6rgIV72 80x0jCEUcP1qflTLyWOReQHk63c= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n17.prod.us-west-2.postgun.com with SMTP id 5f11a7ea75eeb235f684d45a (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 17 Jul 2020 13:30:18 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 62904C43395; Fri, 17 Jul 2020 13:30:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from akhilpo-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: akhilpo) by smtp.codeaurora.org (Postfix) with ESMTPSA id A8527C433AF; Fri, 17 Jul 2020 13:30:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A8527C433AF Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=akhilpo@codeaurora.org From: Akhil P Oommen To: freedreno@lists.freedesktop.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jcrouse@codeaurora.org, smasetty@codeaurora.org, devicetree@vger.kernel.org, mka@chromium.org, saravanak@google.com, sibis@codeaurora.org, viresh.kumar@linaro.org, jonathan@marek.ca, robdclark@gmail.com, bjorn.andersson@linaro.org Subject: [PATCH v6 6/6] arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp Date: Fri, 17 Jul 2020 18:59:39 +0530 Message-Id: <1594992579-20662-7-git-send-email-akhilpo@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594992579-20662-1-git-send-email-akhilpo@codeaurora.org> References: <1594992579-20662-1-git-send-email-akhilpo@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sharat Masetty Add opp-peak-kBps bindings to the GPU opp table, listing the peak GPU -> DDR bandwidth requirement for each opp level. This will be used to scale the DDR bandwidth along with the GPU frequency dynamically. Signed-off-by: Sharat Masetty Reviewed-by: Matthias Kaehlcke Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 80fe54b..ff4ddf1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1479,36 +1479,43 @@ opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-level = ; + opp-peak-kBps = <8532000>; }; opp-650000000 { opp-hz = /bits/ 64 <650000000>; opp-level = ; + opp-peak-kBps = <7216000>; }; opp-565000000 { opp-hz = /bits/ 64 <565000000>; opp-level = ; + opp-peak-kBps = <5412000>; }; opp-430000000 { opp-hz = /bits/ 64 <430000000>; opp-level = ; + opp-peak-kBps = <5412000>; }; opp-355000000 { opp-hz = /bits/ 64 <355000000>; opp-level = ; + opp-peak-kBps = <3072000>; }; opp-267000000 { opp-hz = /bits/ 64 <267000000>; opp-level = ; + opp-peak-kBps = <3072000>; }; opp-180000000 { opp-hz = /bits/ 64 <180000000>; opp-level = ; + opp-peak-kBps = <1804000>; }; }; };