From patchwork Thu Oct 18 05:07:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianxin Pan X-Patchwork-Id: 10646709 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CCDEE13B0 for ; Thu, 18 Oct 2018 05:07:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BF2D62883D for ; Thu, 18 Oct 2018 05:07:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B34AD28866; Thu, 18 Oct 2018 05:07:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3E4A92883D for ; Thu, 18 Oct 2018 05:07:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727425AbeJRNGu (ORCPT ); Thu, 18 Oct 2018 09:06:50 -0400 Received: from mail-sh2.amlogic.com ([58.32.228.45]:28728 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727328AbeJRNGu (ORCPT ); Thu, 18 Oct 2018 09:06:50 -0400 Received: from localhost.localdomain (10.18.11.217) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Thu, 18 Oct 2018 13:07:27 +0800 From: Jianxin Pan To: Jerome Brunet , Neil Armstrong CC: Yixun Lan , Jianxin Pan , Kevin Hilman , Carlo Caione , Michael Turquette , Stephen Boyd , Rob Herring , Miquel Raynal , Boris Brezillon , Martin Blumenstingl , Liang Yang , Jian Hu , Qiufang Dai , Hanjie Lin , Victor Wan , , , , , Subject: [PATCH v5 1/3] clk: meson: add emmc sub clock phase delay driver Date: Thu, 18 Oct 2018 13:07:23 +0800 Message-ID: <1539839245-13793-2-git-send-email-jianxin.pan@amlogic.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1539839245-13793-1-git-send-email-jianxin.pan@amlogic.com> References: <1539839245-13793-1-git-send-email-jianxin.pan@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.217] Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yixun Lan Export the emmc sub clock phase delay ops which will be used by the emmc sub clock driver itself. Signed-off-by: Yixun Lan Signed-off-by: Jianxin Pan --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/clk-phase-delay.c | 79 +++++++++++++++++++++++++++++++++++++ drivers/clk/meson/clkc.h | 13 ++++++ 3 files changed, 93 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/meson/clk-phase-delay.c diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 72ec8c4..39ce566 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -2,7 +2,7 @@ # Makefile for Meson specific clk # -obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o clk-phase-delay.o obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o diff --git a/drivers/clk/meson/clk-phase-delay.c b/drivers/clk/meson/clk-phase-delay.c new file mode 100644 index 0000000..b9573a7 --- /dev/null +++ b/drivers/clk/meson/clk-phase-delay.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson MMC Sub Clock Controller Driver + * + * Copyright (c) 2017 Baylibre SAS. + * Author: Jerome Brunet + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yixun Lan + */ + +#include +#include "clkc.h" + +static int meson_clk_phase_delay_get_phase(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_delay_data *ph = + meson_clk_get_phase_delay_data(clk); + unsigned long period_ps, p, d; + int degrees; + u32 val; + + regmap_read(clk->map, ph->phase.reg_off, &val); + p = PARM_GET(ph->phase.width, ph->phase.shift, val); + degrees = p * 360 / (1 << (ph->phase.width)); + + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, + clk_hw_get_rate(hw)); + + d = PARM_GET(ph->delay.width, ph->delay.shift, val); + degrees += d * ph->delay_step_ps * 360 / period_ps; + degrees %= 360; + + return degrees; +} + +static void meson_clk_apply_phase_delay(struct clk_regmap *clk, + unsigned int phase, + unsigned int delay) +{ + struct meson_clk_phase_delay_data *ph = clk->data; + u32 val; + + regmap_read(clk->map, ph->delay.reg_off, &val); + val = PARM_SET(ph->phase.width, ph->phase.shift, val, phase); + val = PARM_SET(ph->delay.width, ph->delay.shift, val, delay); + regmap_write(clk->map, ph->delay.reg_off, val); +} + +static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_delay_data *ph = + meson_clk_get_phase_delay_data(clk); + unsigned long period_ps, d = 0, r; + u64 p; + + p = degrees % 360; + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, + clk_hw_get_rate(hw)); + + /* First compute the phase index (p), the remainder (r) is the + * part we'll try to acheive using the delays (d). + */ + r = do_div(p, 360 / (1 << (ph->phase.width))); + d = DIV_ROUND_CLOSEST(r * period_ps, + 360 * ph->delay_step_ps); + d = min(d, PMASK(ph->delay.width)); + + meson_clk_apply_phase_delay(clk, p, d); + return 0; +} + +const struct clk_ops meson_clk_phase_delay_ops = { + .get_phase = meson_clk_phase_delay_get_phase, + .set_phase = meson_clk_phase_delay_set_phase, +}; +EXPORT_SYMBOL_GPL(meson_clk_phase_delay_ops); diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 6b96d55..3309d78 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -105,6 +105,18 @@ struct clk_regmap _name = { \ }, \ }; +struct meson_clk_phase_delay_data { + struct parm phase; + struct parm delay; + unsigned int delay_step_ps; +}; + +static inline struct meson_clk_phase_delay_data * +meson_clk_get_phase_delay_data(struct clk_regmap *clk) +{ + return (struct meson_clk_phase_delay_data *)clk->data; +} + /* clk_ops */ extern const struct clk_ops meson_clk_pll_ro_ops; extern const struct clk_ops meson_clk_pll_ops; @@ -112,5 +124,6 @@ struct clk_regmap _name = { \ extern const struct clk_ops meson_clk_mpll_ro_ops; extern const struct clk_ops meson_clk_mpll_ops; extern const struct clk_ops meson_clk_phase_ops; +extern const struct clk_ops meson_clk_phase_delay_ops; #endif /* __CLKC_H */ From patchwork Thu Oct 18 05:07:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianxin Pan X-Patchwork-Id: 10646707 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9F5BA17D4 for ; Thu, 18 Oct 2018 05:07:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9143C2883D for ; Thu, 18 Oct 2018 05:07:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8549F28866; Thu, 18 Oct 2018 05:07:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 293F92883D for ; Thu, 18 Oct 2018 05:07:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727465AbeJRNGw (ORCPT ); Thu, 18 Oct 2018 09:06:52 -0400 Received: from mail-sh2.amlogic.com ([58.32.228.45]:28728 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727328AbeJRNGv (ORCPT ); Thu, 18 Oct 2018 09:06:51 -0400 Received: from localhost.localdomain (10.18.11.217) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Thu, 18 Oct 2018 13:07:27 +0800 From: Jianxin Pan To: Jerome Brunet , Neil Armstrong CC: Yixun Lan , Jianxin Pan , Kevin Hilman , Carlo Caione , Michael Turquette , Stephen Boyd , Rob Herring , Miquel Raynal , Boris Brezillon , Martin Blumenstingl , Liang Yang , Jian Hu , Qiufang Dai , Hanjie Lin , Victor Wan , , , , Subject: [PATCH v5 2/3] clk: meson: add DT documentation for emmc clock controller Date: Thu, 18 Oct 2018 13:07:24 +0800 Message-ID: <1539839245-13793-3-git-send-email-jianxin.pan@amlogic.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1539839245-13793-1-git-send-email-jianxin.pan@amlogic.com> References: <1539839245-13793-1-git-send-email-jianxin.pan@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.217] Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yixun Lan Document the MMC sub clock controller driver, the potential consumer of this driver is MMC or NAND. Also add four clock bindings IDs which provided by this driver. Reviewed-by: Rob Herring Signed-off-by: Yixun Lan Signed-off-by: Jianxin Pan --- .../devicetree/bindings/clock/amlogic,mmc-clkc.txt | 31 ++++++++++++++++++++++ include/dt-bindings/clock/amlogic,mmc-clkc.h | 17 ++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt create mode 100644 include/dt-bindings/clock/amlogic,mmc-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt new file mode 100644 index 0000000..9e6d343 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,mmc-clkc.txt @@ -0,0 +1,31 @@ +* Amlogic MMC Sub Clock Controller Driver + +The Amlogic MMC clock controller generates and supplies clock to support +MMC and NAND controller + +Required Properties: + +- compatible: should be: + "amlogic,gx-mmc-clkc" + "amlogic,axg-mmc-clkc" + +- #clock-cells: should be 1. +- clocks: phandles to clocks corresponding to the clock-names property +- clock-names: list of parent clock names + - "clkin0", "clkin1" + +Parent node should have the following properties : +- compatible: "amlogic,axg-mmc-clkc", "syscon". +- reg: base address and size of the MMC control register space. + +Example: Clock controller node: + +sd_mmc_c_clkc: clock-controller@7000 { + compatible = "amlogic,axg-mmc-clkc", "syscon"; + reg = <0x0 0x7000 0x0 0x4>; + #clock-cells = <1>; + + clock-names = "clkin0", "clkin1"; + clocks = <&clkc CLKID_SD_MMC_C_CLK0>, + <&clkc CLKID_FCLK_DIV2>; +}; diff --git a/include/dt-bindings/clock/amlogic,mmc-clkc.h b/include/dt-bindings/clock/amlogic,mmc-clkc.h new file mode 100644 index 0000000..162b949 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,mmc-clkc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Meson MMC sub clock tree IDs + * + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + * Author: Yixun Lan + */ + +#ifndef __MMC_CLKC_H +#define __MMC_CLKC_H + +#define CLKID_MMC_DIV 1 +#define CLKID_MMC_PHASE_CORE 2 +#define CLKID_MMC_PHASE_TX 3 +#define CLKID_MMC_PHASE_RX 4 + +#endif From patchwork Thu Oct 18 05:07:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianxin Pan X-Patchwork-Id: 10646705 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 044B717D4 for ; Thu, 18 Oct 2018 05:07:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E668C2883D for ; Thu, 18 Oct 2018 05:07:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D591828866; Thu, 18 Oct 2018 05:07:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 01D382883D for ; Thu, 18 Oct 2018 05:07:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727492AbeJRNG4 (ORCPT ); Thu, 18 Oct 2018 09:06:56 -0400 Received: from mail-sh2.amlogic.com ([58.32.228.45]:28728 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727464AbeJRNGy (ORCPT ); Thu, 18 Oct 2018 09:06:54 -0400 Received: from localhost.localdomain (10.18.11.217) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Thu, 18 Oct 2018 13:07:28 +0800 From: Jianxin Pan To: Jerome Brunet , Neil Armstrong CC: Yixun Lan , Jianxin Pan , Kevin Hilman , Carlo Caione , Michael Turquette , Stephen Boyd , Rob Herring , Miquel Raynal , Boris Brezillon , Martin Blumenstingl , Liang Yang , Jian Hu , Qiufang Dai , Hanjie Lin , Victor Wan , , , , Subject: [PATCH v5 3/3] clk: meson: add sub MMC clock controller driver Date: Thu, 18 Oct 2018 13:07:25 +0800 Message-ID: <1539839245-13793-4-git-send-email-jianxin.pan@amlogic.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1539839245-13793-1-git-send-email-jianxin.pan@amlogic.com> References: <1539839245-13793-1-git-send-email-jianxin.pan@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.217] Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yixun Lan The patch will add a MMC clock controller driver which used by MMC or NAND, It provide a mux and divider clock, and three phase clocks - core, tx, tx. Two clocks are provided as the parent of MMC clock controller from upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform. To specify which clock the MMC or NAND driver may consume, the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header can be used in the device tree sources. Signed-off-by: Yixun Lan Signed-off-by: Jianxin Pan --- drivers/clk/meson/Kconfig | 10 ++ drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-regmap.c | 27 +++- drivers/clk/meson/clk-regmap.h | 1 + drivers/clk/meson/mmc-clkc.c | 296 +++++++++++++++++++++++++++++++++++++++++ 5 files changed, 334 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/meson/mmc-clkc.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index efaa70f..8b8ccbc 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -15,6 +15,16 @@ config COMMON_CLK_MESON_AO select COMMON_CLK_REGMAP_MESON select RESET_CONTROLLER +config COMMON_CLK_MMC_MESON + tristate "Meson MMC Sub Clock Controller Driver" + depends on COMMON_CLK_AMLOGIC + select MFD_SYSCON + select REGMAP + help + Support for the MMC sub clock controller on Amlogic Meson Platform, + which include S905 (GXBB, GXL), A113D/X (AXG) devices. + Say Y if you want this clock enabled. + config COMMON_CLK_REGMAP_MESON bool select REGMAP diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 39ce566..31c16d5 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o +obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c index 305ee30..f96314d 100644 --- a/drivers/clk/meson/clk-regmap.c +++ b/drivers/clk/meson/clk-regmap.c @@ -113,8 +113,25 @@ static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate, clk_div_mask(div->width) << div->shift, val); }; -/* Would prefer clk_regmap_div_ro_ops but clashes with qcom */ +static void clk_regmap_div_init(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); + unsigned int val; + int ret; + + ret = regmap_read(clk->map, div->offset, &val); + if (ret) + return; + val &= (clk_div_mask(div->width) << div->shift); + if (!val) + regmap_update_bits(clk->map, div->offset, + clk_div_mask(div->width) << div->shift, + clk_div_mask(div->width)); +} + +/* Would prefer clk_regmap_div_ro_ops but clashes with qcom */ const struct clk_ops clk_regmap_divider_ops = { .recalc_rate = clk_regmap_div_recalc_rate, .round_rate = clk_regmap_div_round_rate, @@ -122,6 +139,14 @@ static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate, }; EXPORT_SYMBOL_GPL(clk_regmap_divider_ops); +const struct clk_ops clk_regmap_divider_with_init_ops = { + .recalc_rate = clk_regmap_div_recalc_rate, + .round_rate = clk_regmap_div_round_rate, + .set_rate = clk_regmap_div_set_rate, + .init = clk_regmap_div_init, +}; +EXPORT_SYMBOL_GPL(clk_regmap_divider_with_init_ops); + const struct clk_ops clk_regmap_divider_ro_ops = { .recalc_rate = clk_regmap_div_recalc_rate, .round_rate = clk_regmap_div_round_rate, diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h index ed2d434..0ab7d37 100644 --- a/drivers/clk/meson/clk-regmap.h +++ b/drivers/clk/meson/clk-regmap.h @@ -109,5 +109,6 @@ struct clk_regmap_mux_data { extern const struct clk_ops clk_regmap_mux_ops; extern const struct clk_ops clk_regmap_mux_ro_ops; +extern const struct clk_ops clk_regmap_divider_with_init_ops; #endif /* __CLK_REGMAP_H */ diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c new file mode 100644 index 0000000..5555e3f --- /dev/null +++ b/drivers/clk/meson/mmc-clkc.c @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson MMC Sub Clock Controller Driver + * + * Copyright (c) 2017 Baylibre SAS. + * Author: Jerome Brunet + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yixun Lan + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clkc.h" + +/* clock ID used by internal driver */ +#define CLKID_MMC_MUX 0 + +#define SD_EMMC_CLOCK 0 +#define CLK_DELAY_STEP_PS 200 +#define CLK_PHASE_STEP 30 +#define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP) + +#define MUX_CLK_NUM_PARENTS 2 +#define MMC_MAX_CLKS 5 + +struct mmc_clkc_data { + struct meson_clk_phase_delay_data tx; + struct meson_clk_phase_delay_data rx; +}; + +static struct clk_regmap_mux_data mmc_clkc_mux_data = { + .offset = SD_EMMC_CLOCK, + .mask = 0x3, + .shift = 6, + .flags = CLK_DIVIDER_ROUND_CLOSEST, +}; + +static struct clk_regmap_div_data mmc_clkc_div_data = { + .offset = SD_EMMC_CLOCK, + .shift = 0, + .width = 6, + .flags = CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED, +}; + +static struct meson_clk_phase_data mmc_clkc_core_phase = { + .ph = { + .reg_off = SD_EMMC_CLOCK, + .shift = 8, + .width = 2, + } +}; + +static const struct mmc_clkc_data mmc_clkc_gx_data = { + .tx = { + .phase = { + .reg_off = SD_EMMC_CLOCK, + .shift = 10, + .width = 2, + }, + .delay = { + .reg_off = SD_EMMC_CLOCK, + .shift = 16, + .width = 4, + }, + .delay_step_ps = CLK_DELAY_STEP_PS, + }, + .rx = { + .phase = { + .reg_off = SD_EMMC_CLOCK, + .shift = 12, + .width = 2, + }, + .delay = { + .reg_off = SD_EMMC_CLOCK, + .shift = 20, + .width = 4, + }, + .delay_step_ps = CLK_DELAY_STEP_PS, + }, +}; + +static const struct mmc_clkc_data mmc_clkc_axg_data = { + .tx = { + .phase = { + .reg_off = SD_EMMC_CLOCK, + .shift = 10, + .width = 2, + }, + .delay = { + .reg_off = SD_EMMC_CLOCK, + .shift = 16, + .width = 6, + }, + .delay_step_ps = CLK_DELAY_STEP_PS, + }, + .rx = { + .phase = { + .reg_off = SD_EMMC_CLOCK, + .shift = 12, + .width = 2, + }, + .delay = { + .reg_off = SD_EMMC_CLOCK, + .shift = 22, + .width = 6, + }, + .delay_step_ps = CLK_DELAY_STEP_PS, + }, +}; + +static const struct of_device_id mmc_clkc_match_table[] = { + { + .compatible = "amlogic,gx-mmc-clkc", + .data = &mmc_clkc_gx_data + }, + { + .compatible = "amlogic,axg-mmc-clkc", + .data = &mmc_clkc_axg_data + }, + {} +}; +MODULE_DEVICE_TABLE(of, mmc_clkc_match_table); + +static struct clk_regmap * +mmc_clkc_register_clk(struct device *dev, struct regmap *map, + struct clk_init_data *init, + const char *suffix, void *data) +{ + struct clk_regmap *clk; + char *name; + int ret; + + clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); + if (!clk) + return ERR_PTR(-ENOMEM); + + name = kasprintf(GFP_KERNEL, "%s#%s", dev_name(dev), suffix); + if (!name) + return ERR_PTR(-ENOMEM); + + init->name = name; + + clk->map = map; + clk->data = data; + clk->hw.init = init; + + ret = devm_clk_hw_register(dev, &clk->hw); + if (ret) + clk = ERR_PTR(ret); + + kfree(name); + return clk; +} + +static struct clk_regmap *mmc_clkc_register_mux(struct device *dev, + struct regmap *map) +{ + const char *parent_names[MUX_CLK_NUM_PARENTS]; + struct clk_init_data init; + struct clk_regmap *mux; + struct clk *clk; + int i; + + for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { + char name[8]; + + snprintf(name, sizeof(name), "clkin%d", i); + clk = devm_clk_get(dev, name); + if (IS_ERR(clk)) { + if (clk != ERR_PTR(-EPROBE_DEFER)) + dev_err(dev, "Missing clock %s\n", name); + return ERR_PTR((long)clk); + } + + parent_names[i] = __clk_get_name(clk); + } + + init.ops = &clk_regmap_mux_ops; + init.flags = CLK_SET_RATE_PARENT; + init.parent_names = parent_names; + init.num_parents = MUX_CLK_NUM_PARENTS; + + mux = mmc_clkc_register_clk(dev, map, &init, "mux", &mmc_clkc_mux_data); + if (IS_ERR(mux)) + dev_err(dev, "Mux clock registration failed\n"); + + return mux; +} + +static struct clk_regmap * +mmc_clkc_register_clk_with_parent(struct device *dev, struct regmap *map, + char *suffix, const char *parent, + unsigned long flags, + const struct clk_ops *ops, void *data) +{ + struct clk_init_data init; + struct clk_regmap *clk; + + init.ops = ops; + init.flags = flags; + init.parent_names = (const char* const []){ parent, }; + init.num_parents = 1; + + clk = mmc_clkc_register_clk(dev, map, &init, suffix, data); + if (IS_ERR(clk)) + dev_err(dev, "Core %s clock registration failed\n", suffix); + + return clk; +} + +static int mmc_clkc_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *onecell_data; + struct device *dev = &pdev->dev; + struct mmc_clkc_data *data; + struct regmap *map; + struct clk_regmap *mux, *div, *core, *rx, *tx; + + data = (struct mmc_clkc_data *)of_device_get_match_data(dev); + if (!data) + return -ENODEV; + + map = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(map)) { + dev_err(dev, "could not find mmc clock controller\n"); + return PTR_ERR(map); + } + + onecell_data = devm_kzalloc(dev, sizeof(*onecell_data) + + sizeof(*onecell_data->hws) * MMC_MAX_CLKS, + GFP_KERNEL); + if (!onecell_data) + return -ENOMEM; + + mux = mmc_clkc_register_mux(dev, map); + if (IS_ERR(mux)) + return PTR_ERR(mux); + + div = mmc_clkc_register_clk_with_parent(dev, map, "div", + clk_hw_get_name(&mux->hw), + CLK_SET_RATE_PARENT, + &clk_regmap_divider_with_init_ops, + &mmc_clkc_div_data); + if (IS_ERR(div)) + return PTR_ERR(div); + + core = mmc_clkc_register_clk_with_parent(dev, map, "core", + clk_hw_get_name(&div->hw), + CLK_SET_RATE_PARENT, + &meson_clk_phase_ops, + &mmc_clkc_core_phase); + if (IS_ERR(core)) + return PTR_ERR(core); + + rx = mmc_clkc_register_clk_with_parent(dev, map, "rx", + clk_hw_get_name(&core->hw), 0, + &meson_clk_phase_delay_ops, + &data->rx); + if (IS_ERR(rx)) + return PTR_ERR(rx); + + tx = mmc_clkc_register_clk_with_parent(dev, map, "tx", + clk_hw_get_name(&core->hw), 0, + &meson_clk_phase_delay_ops, + &data->tx); + if (IS_ERR(tx)) + return PTR_ERR(tx); + + onecell_data->hws[CLKID_MMC_MUX] = &mux->hw, + onecell_data->hws[CLKID_MMC_DIV] = &div->hw, + onecell_data->hws[CLKID_MMC_PHASE_CORE] = &core->hw, + onecell_data->hws[CLKID_MMC_PHASE_RX] = &rx->hw, + onecell_data->hws[CLKID_MMC_PHASE_TX] = &tx->hw, + onecell_data->num = MMC_MAX_CLKS; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + onecell_data); +} + +static struct platform_driver mmc_clkc_driver = { + .probe = mmc_clkc_probe, + .driver = { + .name = "meson-mmc-clkc", + .of_match_table = of_match_ptr(mmc_clkc_match_table), + }, +}; + +module_platform_driver(mmc_clkc_driver);