From patchwork Thu Jul 23 14:06:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Neeli X-Patchwork-Id: 11681033 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C1AE513B4 for ; Thu, 23 Jul 2020 14:08:25 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8D6CB2080D for ; Thu, 23 Jul 2020 14:08:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="LUx1qSY3"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="hxef7Bvq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8D6CB2080D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xilinx.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=aSKx4glTyVxahTLQ4t+MQT8XwBB0d6IwbhzF/DFGjcI=; b=LUx1qSY37zEFvA46nEIe3fsEv heacjdiltauR7FgbaDWWWJ06ar2Fq4Z/NxoldmdNo3yUrypU64uac3sTEMDijk3a5OQ5nS+eo0OvF 6eN5BUDYLOh34S/DQQVljGZgae4nvz4nrLO+qo+wmu7ujpgIzQ/276pFHECKAzYUCU13/FIpgHow3 2/fdFP2cThWxvOYyt1TXEvjTyFzkIll9wwYpdLryXm+fxmwShIkCkEVV6s+GUvkmmtNY8yPgQ/5Zl OcECNHb4u84nK/WjEAtsILPI6NKM0XPlKOcKY8spJtJhoBLxiOWP59xM5GIm//xB0L1TX5SsRdrUn iP6zICaRg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jybrp-0003we-4E; Thu, 23 Jul 2020 14:06:37 +0000 Received: from mail-bn7nam10on2082.outbound.protection.outlook.com ([40.107.92.82] helo=NAM10-BN7-obe.outbound.protection.outlook.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jybrd-0003tk-C1 for linux-arm-kernel@lists.infradead.org; Thu, 23 Jul 2020 14:06:26 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UbjCQYg5C4+24TJGLo0sg2cw8jVAUepf6aoq63HLVftUqq0r9gXnqVsM2CKVqkOl1Q/8Cm/e6e3vQNMxbAxIkhx6f5me8bdMRPNUKJ4u+rz4ta5KMVngON9/G+WmHOxrncO0fZZvppgvZkA8XpMjpy4QyLTNWEzsDaNNstyErbKGDfd8b6d488NPZYkMQl0HY+Aen/fZUeF4kqaQx63rxUA/BzTXQ7gEp+efX8MSHejYOJwhoZ7jAK/NsDx/+OgSj9EWki31Cta3QnGgws/QCkPcvLsZGT3slrO4uVickdbQgHb8tNGpoDBdIi5N/eh0loQvxazBe+u2FzaCQL5dKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FKx5wx31GLTD0nKRbG+gL64xdeOqQpb6ABdqTZyoYbo=; b=Zrww75innOFrB4CUsFexcxDtbcoAqcbNV+XmOtyOUCLw5KJky66Fxr6lh65sEEmnpHsaI135aRVO9y8aJgPAT5olpXVQOWwahozWGabda1vSchPblyI2mcn0Af5JUn4jMSCXG8S52hE22N456xbKC78Xu8bsGcoJaTr61/8FVLLKbk/2tm7xvQgANVD9h4CBvlZbQb96MieI1zamgcGPQltbMrl1YNk2shVyzi+L7e49bmLiov65vV45L09SVOmFzozgOgRAljKdlVOuubROl5kc+867fwmSErPENvXGst2Qy0PCVf9QUlo7KxanIKo1ld4TuORkkJljDoLYD7hZPw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FKx5wx31GLTD0nKRbG+gL64xdeOqQpb6ABdqTZyoYbo=; b=hxef7BvqyUcYND0pzFM5PyxA5oRntqYmfWAffDx3A5rCMVTcD6pcPlHZmzU6bZZdbcdbHveNvD33+uZ08qHXzP5itFNt7RKQLtNwP4xAXc3iRpkzi7mCNd+/bhidD7ccOAY1k7PnIihFn8xVUW28piZdy8wKMdL5sUykqoEQHb4= Received: from MN2PR04CA0002.namprd04.prod.outlook.com (2603:10b6:208:d4::15) by CY4PR0201MB3586.namprd02.prod.outlook.com (2603:10b6:910:8b::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3216.23; Thu, 23 Jul 2020 14:06:19 +0000 Received: from BL2NAM02FT021.eop-nam02.prod.protection.outlook.com (2603:10b6:208:d4:cafe::9c) by MN2PR04CA0002.outlook.office365.com (2603:10b6:208:d4::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3216.20 via Frontend Transport; Thu, 23 Jul 2020 14:06:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BL2NAM02FT021.mail.protection.outlook.com (10.152.77.158) with Microsoft SMTP Server id 15.20.3216.10 via Frontend Transport; Thu, 23 Jul 2020 14:06:18 +0000 Received: from [149.199.38.66] (port=56793 helo=smtp.xilinx.com) by xsj-pvapsmtpgw01 with esmtp (Exim 4.90) (envelope-from ) id 1jybpg-0004H0-Ld; Thu, 23 Jul 2020 07:04:24 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1jybrW-0005RQ-Lo; Thu, 23 Jul 2020 07:06:18 -0700 Received: from xsj-pvapsmtp01 (smtp2.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 06NE6E2P004452; Thu, 23 Jul 2020 07:06:14 -0700 Received: from [10.140.6.6] (helo=xhdappanad40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jybrR-0005Q2-UE; Thu, 23 Jul 2020 07:06:14 -0700 From: Srinivas Neeli To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, michal.simek@xilinx.com, shubhrajyoti.datta@xilinx.com, sgoud@xilinx.com Subject: [PATCH V2 1/3] gpio: xilinx: Add clock adaptation support Date: Thu, 23 Jul 2020 19:36:06 +0530 Message-Id: <1595513168-11965-2-git-send-email-srinivas.neeli@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595513168-11965-1-git-send-email-srinivas.neeli@xilinx.com> References: <1595513168-11965-1-git-send-email-srinivas.neeli@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: b2abba5e-6279-4067-9929-08d82f119263 X-MS-TrafficTypeDiagnostic: CY4PR0201MB3586: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cmvlo9RIh+GEXsubUpmM9uT/l271pLgTJym0BcsC3lp5aKvXuqFv+Mlsl1PyXAwBpoKwFHC734WUpZ2jyG1vLrOJE4YAYSZviBSY40X1Qqh8Db43XO7eVGg4qn0KfEErxwYowr3fKnOSaCtAs2GL1X/Q05tWo5cHBncVK28V9mod+5jYKrf5QlFz61e3Bfvvioi8mZbwPiGoMOLSM3jAfTFvveo/6LSYf3RIvtU4XjilC0SeVmnWFxxa/66GxoSalzXilNfykclCrUc0UsORDNRD6WH6xXFq43/W3Rmr1aSPW5y/Rh8szf2m4XcSIfQ7vvbI7aj/WvCinafufGTI5kaNGyTNJX2/nUGnixsrxffbeQOEJeVvatZIwZ4/zd0tMf3FsRhwZ47jC1/YY6snbQ== X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFTY:; SFS:(396003)(39860400002)(136003)(346002)(376002)(46966005)(186003)(70586007)(9786002)(70206006)(47076004)(356005)(478600001)(26005)(81166007)(44832011)(36756003)(82740400003)(82310400002)(2906002)(83380400001)(2616005)(8676002)(107886003)(336012)(426003)(4326008)(7696005)(6666004)(316002)(6636002)(8936002)(5660300002); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2020 14:06:18.9805 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2abba5e-6279-4067-9929-08d82f119263 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT021.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR0201MB3586 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200723_100625_453111_22BAFFE3 X-CRM114-Status: GOOD ( 23.47 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.92.82 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [40.107.92.82 listed in wl.mailspike.net] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, git@xilinx.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add support of clock adaptation for AXI GPIO driver. Signed-off-by: Srinivas Neeli --- Changes in V2: Add check for return value of platform_get_irq() API. --- drivers/gpio/gpio-xilinx.c | 111 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 109 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index 67f9f82e0db0..d103613e787a 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include /* Register Offset Definitions */ #define XGPIO_DATA_OFFSET (0x0) /* Data register */ @@ -38,6 +40,7 @@ * @gpio_state: GPIO state shadow register * @gpio_dir: GPIO direction shadow register * @gpio_lock: Lock used for synchronization + * @clk: clock resource for this driver */ struct xgpio_instance { struct gpio_chip gc; @@ -45,7 +48,8 @@ struct xgpio_instance { unsigned int gpio_width[2]; u32 gpio_state[2]; u32 gpio_dir[2]; - spinlock_t gpio_lock[2]; + spinlock_t gpio_lock[2]; /* For serializing operations */ + struct clk *clk; }; static inline int xgpio_index(struct xgpio_instance *chip, int gpio) @@ -256,6 +260,83 @@ static void xgpio_save_regs(struct xgpio_instance *chip) chip->gpio_dir[1]); } +static int xgpio_request(struct gpio_chip *chip, unsigned int offset) +{ + int ret = pm_runtime_get_sync(chip->parent); + + /* + * If the device is already active pm_runtime_get() will return 1 on + * success, but gpio_request still needs to return 0. + */ + return ret < 0 ? ret : 0; +} + +static void xgpio_free(struct gpio_chip *chip, unsigned int offset) +{ + pm_runtime_put(chip->parent); +} + +static int __maybe_unused xgpio_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct irq_data *data; + int irq = platform_get_irq(pdev, 0); + + if (irq < 0) { + dev_info(&pdev->dev, "platform_get_irq returned %d\n", irq); + return irq; + } + + data = irq_get_irq_data(irq); + if (!irqd_is_wakeup_set(data)) + return pm_runtime_force_suspend(dev); + + return 0; +} + +static int __maybe_unused xgpio_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct irq_data *data; + int irq = platform_get_irq(pdev, 0); + + if (irq < 0) { + dev_info(&pdev->dev, "platform_get_irq returned %d\n", irq); + return irq; + } + + data = irq_get_irq_data(irq); + + if (!irqd_is_wakeup_set(data)) + return pm_runtime_force_resume(dev); + + return 0; +} + +static int __maybe_unused xgpio_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct xgpio_instance *gpio = platform_get_drvdata(pdev); + + clk_disable(gpio->clk); + + return 0; +} + +static int __maybe_unused xgpio_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct xgpio_instance *gpio = platform_get_drvdata(pdev); + + return clk_enable(gpio->clk); +} + +static const struct dev_pm_ops xgpio_dev_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume) + SET_RUNTIME_PM_OPS(xgpio_runtime_suspend, + xgpio_runtime_resume, NULL) +}; + /** * xgpio_of_probe - Probe method for the GPIO device. * @pdev: pointer to the platform device @@ -324,6 +405,8 @@ static int xgpio_probe(struct platform_device *pdev) chip->gc.direction_output = xgpio_dir_out; chip->gc.get = xgpio_get; chip->gc.set = xgpio_set; + chip->gc.request = xgpio_request; + chip->gc.free = xgpio_free; chip->gc.set_multiple = xgpio_set_multiple; chip->gc.label = dev_name(&pdev->dev); @@ -334,15 +417,38 @@ static int xgpio_probe(struct platform_device *pdev) return PTR_ERR(chip->regs); } + chip->clk = devm_clk_get_optional(&pdev->dev, "s_axi_aclk"); + if (IS_ERR(chip->clk)) { + if (PTR_ERR(chip->clk) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Input clock not found\n"); + return PTR_ERR(chip->clk); + } + status = clk_prepare_enable(chip->clk); + if (status < 0) { + dev_err(&pdev->dev, "Failed to prepare clk\n"); + return status; + } + pm_runtime_enable(&pdev->dev); + status = pm_runtime_get_sync(&pdev->dev); + if (status < 0) + goto err_unprepare_clk; + xgpio_save_regs(chip); status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); if (status) { dev_err(&pdev->dev, "failed to add GPIO chip\n"); - return status; + goto err_pm_put; } + pm_runtime_put(&pdev->dev); return 0; +err_pm_put: + pm_runtime_put(&pdev->dev); +err_unprepare_clk: + pm_runtime_disable(&pdev->dev); + clk_unprepare(chip->clk); + return status; } static const struct of_device_id xgpio_of_match[] = { @@ -357,6 +463,7 @@ static struct platform_driver xgpio_plat_driver = { .driver = { .name = "gpio-xilinx", .of_match_table = xgpio_of_match, + .pm = &xgpio_dev_pm_ops, }, }; From patchwork Thu Jul 23 14:06:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Neeli X-Patchwork-Id: 11681035 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8D7616C1 for ; Thu, 23 Jul 2020 14:08:28 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 580ED20709 for ; Thu, 23 Jul 2020 14:08:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="OFglepC/"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="qIBll1AE" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 580ED20709 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xilinx.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=jfS3xY4zAMRXhH17pLAw9zH+NlNFFpcgByfHlgVOpTA=; b=OFglepC/jIdPWA3HBuWOSHcP0 LHqbosvHXIkv4MFIbIiHtQR+HLFJJkHmqI+g5ys1Nmrxit84qUJCQ6Ax17pN/2D9HvJ3BqUUJ9QZy vI5YoUWE2z0hRnVHMcJhZ0/IsRkjeVPsHXrYGli84KOrWrNZ1qqPbyv6O04UlV5auzk2RWrvM3k4P xv6sXHFBmFAY+JWWbEwc6Ck9UgFDJzx7lyZV0uDuzUteWPK8HyUuO7KLuykt7MTelqFFsPeGT5jOB Ae3gjN/knKUd2Q48A8x4faqzNiwrdBmad62UWV3SUGQ3u1uC6hqdTi4WcfH/EZN/7gvPNSUgGdBIp s/a7cN22w==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jybrg-0003uk-2j; Thu, 23 Jul 2020 14:06:28 +0000 Received: from mail-dm6nam10on2043.outbound.protection.outlook.com ([40.107.93.43] helo=NAM10-DM6-obe.outbound.protection.outlook.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jybra-0003t4-JU for linux-arm-kernel@lists.infradead.org; Thu, 23 Jul 2020 14:06:23 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=YVAuYZ8vFfHXWMxKULlBCqNZW6nFEE4suluA0fRuj6bQGnQg+jiXzGXq3oIRFFnozY8zRadF40ZV7c+ms+uP/Vv4rEUdqX6IdafO7hOfLqZu5UEGktjE195JlCmwm5kSS+wCJ7pPwUaE3TFaB5kGnHEoTLRcquHMg1RLaY16Z4qsC9OxI1ww0xDqf798ATYeiNs3tMQ9MIXFF6eIjbNky+X3TnxA+cPM17w0Tx7ehx2xAwr+jbIpuKXNusZeV+K3FquSFFI+jRkDTvYJ65mgMbv22GKw+qu9YORIpSS5ChhCi/st6FtlIEpMsUgL/sXLq+Vnb2D1HX1ARWk92vgxTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=26BrNPLQDVRxPyqG4SbXzSjiLN/MzxCXQ6FN/JNp2WU=; b=kFBuKhOmIEwh2EibEtvHYXVaQAFu35hrrLKTkoUH7XMPyRpNko80AZF7PTQo635JdnOOShpp1s26spxGrtXCLWR0UQO34Th1DctZ672210cYgt2ESFPVX+YHZ9MQI1qJwqhpuKfkm3ZuUpl+g/VNHl4fr40bqo3/WSMrIvdQ0U6GEWfVfjkjhknWrZWfirx1B5/DZdJhi7Adaq3NmyA54cVMvgllCJxKOkiO3ENLsT3aOA2spjAYd4qGZnhmGPy2W0roJQwdtTG43uHYVK3kFAh74rdx5CTtrm4FZJwmZtLK4GTzpYQq7AY58u5n32Ygnt1aKHpCLNMoNqYi7mC7Jg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=26BrNPLQDVRxPyqG4SbXzSjiLN/MzxCXQ6FN/JNp2WU=; b=qIBll1AE0FcYbWZPf4yA4faFhDT5KR1j9wZZsIYfYij6SYEEcJDmUUrua6jNaDIi3Spo6Js+REQ3u34GM5PPyeigQp8+T6WB41EfC6NYBfJUQ3TOinrUsop9Er1D5Nj/NnYLds8kUerWDiGEH5cw/RRXn+IhS7ojQY/Rv3t4rjE= Received: from CY4PR19CA0037.namprd19.prod.outlook.com (2603:10b6:903:103::23) by SN6PR02MB4382.namprd02.prod.outlook.com (2603:10b6:805:aa::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3216.20; Thu, 23 Jul 2020 14:06:19 +0000 Received: from CY1NAM02FT055.eop-nam02.prod.protection.outlook.com (2603:10b6:903:103:cafe::ec) by CY4PR19CA0037.outlook.office365.com (2603:10b6:903:103::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3216.23 via Frontend Transport; Thu, 23 Jul 2020 14:06:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by CY1NAM02FT055.mail.protection.outlook.com (10.152.74.80) with Microsoft SMTP Server id 15.20.3216.10 via Frontend Transport; Thu, 23 Jul 2020 14:06:19 +0000 Received: from [149.199.38.66] (port=56799 helo=smtp.xilinx.com) by xsj-pvapsmtpgw01 with esmtp (Exim 4.90) (envelope-from ) id 1jybpg-0004H3-Q4; Thu, 23 Jul 2020 07:04:24 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1jybrW-0005RQ-QC; Thu, 23 Jul 2020 07:06:18 -0700 Received: from xsj-pvapsmtp01 (xsj-smtp1.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 06NE6HS0004468; Thu, 23 Jul 2020 07:06:17 -0700 Received: from [10.140.6.6] (helo=xhdappanad40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jybrU-0005Q2-Na; Thu, 23 Jul 2020 07:06:17 -0700 From: Srinivas Neeli To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, michal.simek@xilinx.com, shubhrajyoti.datta@xilinx.com, sgoud@xilinx.com Subject: [PATCH V2 2/3] gpio: xilinx: Add interrupt support Date: Thu, 23 Jul 2020 19:36:07 +0530 Message-Id: <1595513168-11965-3-git-send-email-srinivas.neeli@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595513168-11965-1-git-send-email-srinivas.neeli@xilinx.com> References: <1595513168-11965-1-git-send-email-srinivas.neeli@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: a94913b7-25cb-4f84-357a-08d82f11926b X-MS-TrafficTypeDiagnostic: SN6PR02MB4382: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: a11w/U+gDISswNY7sSl6X4qUeVnJ3KseCJnAqFfunzS9RbTjmWl6JdWzUEoNmrvBh17l25g3Efo5U4VIcdMqYQzSwHiAwN+iMWyLBCoQgVYTkY0Otx1VUA/0CmM23R2F9bg3V7MiWbJ2HEyR5Phqzg7TSxLeG/RWDp1Un4xhyrvPl2atVimtO2wvt4IusNajvj0DZ/q9jcNdepTiBiCnManSahof0uCxFdmj/PwNfYXYL2RRecITTkfS3Fv/m5tMKXm0DjE59fHDIWB7IxS6VMrGlVH/5Gm5WB3z5q3TvtzxxeQ8fPdezDjY6Q9HsK0CdkCW7qVWU7wr6KmSLcf4fe+og8JjayKW8/NL1EVdTgAVDOKdBsw2Zq06ojOMZiwYc8QqPDOeGntHMUnzLglM/Q== X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFTY:; SFS:(136003)(346002)(39860400002)(396003)(376002)(46966005)(47076004)(316002)(44832011)(82740400003)(6666004)(2616005)(356005)(81166007)(478600001)(2906002)(30864003)(82310400002)(70206006)(5660300002)(426003)(70586007)(7696005)(6636002)(8936002)(8676002)(336012)(9786002)(107886003)(26005)(83380400001)(36756003)(186003)(4326008); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2020 14:06:19.0304 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a94913b7-25cb-4f84-357a-08d82f11926b X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT055.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB4382 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200723_100622_735246_32DA1103 X-CRM114-Status: GOOD ( 25.11 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.93.43 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [40.107.93.43 listed in wl.mailspike.net] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, git@xilinx.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Adds interrupt support to the Xilinx GPIO driver so that rising and falling edge line events can be supported. Since interrupt support is an optional feature in the Xilinx IP, the driver continues to support devices which have no interrupt provided. Signed-off-by: Robert Hancock Signed-off-by: Shubhrajyoti Datta Signed-off-by: Srinivas Neeli Reported-by: kernel test robot --- Changes in V2: Updated code to support rising edge and falling edge. Added xgpio_xlate() API to support gpio-keys. Updated code to check return value of of_property_read_u32. --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-xilinx.c | 295 ++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 277 insertions(+), 19 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 05e0801c6a78..239f8eb7a8eb 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -652,6 +652,7 @@ config GPIO_XGENE_SB config GPIO_XILINX tristate "Xilinx GPIO support" + select GPIOLIB_IRQCHIP help Say yes here to support the Xilinx FPGA GPIO device diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index d103613e787a..509606e92a1c 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -16,6 +16,9 @@ #include #include #include +#include +#include +#include /* Register Offset Definitions */ #define XGPIO_DATA_OFFSET (0x0) /* Data register */ @@ -23,6 +26,11 @@ #define XGPIO_CHANNEL_OFFSET 0x8 +#define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */ +#define XGPIO_GIER_IE BIT(31) +#define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */ +#define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */ + /* Read/Write access to the GPIO registers */ #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86) # define xgpio_readreg(offset) readl(offset) @@ -37,9 +45,14 @@ * @gc: GPIO chip * @regs: register block * @gpio_width: GPIO width for every channel - * @gpio_state: GPIO state shadow register + * @gpio_state: GPIO write state shadow register + * @gpio_last_irq_read: GPIO read state register from last interrupt * @gpio_dir: GPIO direction shadow register * @gpio_lock: Lock used for synchronization + * @irq: IRQ used by GPIO device + * @irq_enable: GPIO irq enable/disable bitfield + * @irq_rising_edge: GPIO irq rising edge enable/disable bitfield + * @irq_falling_edge: GPIO irq falling edge enable/disable bitfield * @clk: clock resource for this driver */ struct xgpio_instance { @@ -47,8 +60,13 @@ struct xgpio_instance { void __iomem *regs; unsigned int gpio_width[2]; u32 gpio_state[2]; + u32 gpio_last_irq_read[2]; u32 gpio_dir[2]; - spinlock_t gpio_lock[2]; /* For serializing operations */ + spinlock_t gpio_lock; /* For serializing operations */ + int irq; + u32 irq_enable[2]; + u32 irq_rising_edge[2]; + u32 irq_falling_edge[2]; struct clk *clk; }; @@ -114,7 +132,7 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) int index = xgpio_index(chip, gpio); int offset = xgpio_offset(chip, gpio); - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); /* Write to GPIO signal and set its direction to output */ if (val) @@ -125,7 +143,7 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + xgpio_regoffset(chip, gpio), chip->gpio_state[index]); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); } /** @@ -145,7 +163,7 @@ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, int index = xgpio_index(chip, 0); int offset, i; - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); /* Write to GPIO signals */ for (i = 0; i < gc->ngpio; i++) { @@ -156,9 +174,7 @@ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); index = xgpio_index(chip, i); - spin_lock_irqsave(&chip->gpio_lock[index], flags); } if (__test_and_clear_bit(i, mask)) { offset = xgpio_offset(chip, i); @@ -172,7 +188,7 @@ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); } /** @@ -191,14 +207,14 @@ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) int index = xgpio_index(chip, gpio); int offset = xgpio_offset(chip, gpio); - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); /* Set the GPIO bit in shadow register and set direction as input */ chip->gpio_dir[index] |= BIT(offset); xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); return 0; } @@ -222,7 +238,7 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) int index = xgpio_index(chip, gpio); int offset = xgpio_offset(chip, gpio); - spin_lock_irqsave(&chip->gpio_lock[index], flags); + spin_lock_irqsave(&chip->gpio_lock, flags); /* Write state of GPIO signal */ if (val) @@ -237,7 +253,7 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock, flags); return 0; } @@ -294,6 +310,45 @@ static int __maybe_unused xgpio_suspend(struct device *dev) return 0; } +/** + * xgpio_xlate - Translate gpio_spec to the GPIO number and flags + * @gc: Pointer to gpio_chip device structure. + * @gpiospec: gpio specifier as found in the device tree + * @flags: A flags pointer based on binding + * + * Return: + * irq number otherwise -EINVAL + */ +static int xgpio_xlate(struct gpio_chip *gc, + const struct of_phandle_args *gpiospec, u32 *flags) +{ + if (gc->of_gpio_n_cells < 2) { + WARN_ON(1); + return -EINVAL; + } + + if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) + return -EINVAL; + + if (gpiospec->args[0] >= gc->ngpio) + return -EINVAL; + + if (flags) + *flags = gpiospec->args[1]; + + return gpiospec->args[0]; +} + +/** + * xgpio_irq_ack - Acknowledge a child GPIO interrupt. + * This currently does nothing, but irq_ack is unconditionally called by + * handle_edge_irq and therefore must be defined. + * @irq_data: per irq and chip data passed down to chip functions + */ +static void xgpio_irq_ack(struct irq_data *irq_data) +{ +} + static int __maybe_unused xgpio_resume(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); @@ -338,6 +393,176 @@ static const struct dev_pm_ops xgpio_dev_pm_ops = { }; /** + * xgpio_irq_mask - Write the specified signal of the GPIO device. + * @irq_data: per irq and chip data passed down to chip functions + */ +static void xgpio_irq_mask(struct irq_data *irq_data) +{ + unsigned long flags; + struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); + int irq_offset = irqd_to_hwirq(irq_data); + int index = xgpio_index(chip, irq_offset); + int offset = xgpio_offset(chip, irq_offset); + + spin_lock_irqsave(&chip->gpio_lock, flags); + + chip->irq_enable[index] &= ~BIT(offset); + + dev_dbg(chip->gc.parent, "Disable %d irq, irq_enable_mask 0x%x\n", + irq_offset, chip->irq_enable[index]); + + if (!chip->irq_enable[index]) { + /* Disable per channel interrupt */ + u32 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); + + temp &= ~BIT(index); + xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp); + } + spin_unlock_irqrestore(&chip->gpio_lock, flags); +} + +/** + * xgpio_irq_unmask - Write the specified signal of the GPIO device. + * @irq_data: per irq and chip data passed down to chip functions + */ +static void xgpio_irq_unmask(struct irq_data *irq_data) +{ + unsigned long flags; + struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); + int irq_offset = irqd_to_hwirq(irq_data); + int index = xgpio_index(chip, irq_offset); + int offset = xgpio_offset(chip, irq_offset); + u32 old_enable = chip->irq_enable[index]; + + spin_lock_irqsave(&chip->gpio_lock, flags); + + chip->irq_enable[index] |= BIT(offset); + + dev_dbg(chip->gc.parent, "Enable %d irq, irq_enable_mask 0x%x\n", + irq_offset, chip->irq_enable[index]); + + if (!old_enable) { + /* Clear any existing per-channel interrupts */ + u32 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET) & + BIT(index); + + if (val) + xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); + + /* Update GPIO IRQ read data before enabling interrupt*/ + val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + + index * XGPIO_CHANNEL_OFFSET); + chip->gpio_last_irq_read[index] = val; + + /* Enable per channel interrupt */ + val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); + val |= BIT(index); + xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); + } + + spin_unlock_irqrestore(&chip->gpio_lock, flags); +} + +/** + * xgpio_set_irq_type - Write the specified signal of the GPIO device. + * @irq_data: Per irq and chip data passed down to chip functions + * @type: Interrupt type that is to be set for the gpio pin + * + * Return: + * 0 if interrupt type is supported otherwise otherwise -EINVAL + */ +static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) +{ + struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); + int irq_offset = irqd_to_hwirq(irq_data); + int index = xgpio_index(chip, irq_offset); + int offset = xgpio_offset(chip, irq_offset); + + /* The Xilinx GPIO hardware provides a single interrupt status + * indication for any state change in a given GPIO channel (bank). + * Therefore, only rising edge or falling edge triggers are + * supported. + */ + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_BOTH: + chip->irq_rising_edge[index] |= BIT(offset); + chip->irq_falling_edge[index] |= BIT(offset); + break; + case IRQ_TYPE_EDGE_RISING: + chip->irq_rising_edge[index] |= BIT(offset); + chip->irq_falling_edge[index] &= ~BIT(offset); + break; + case IRQ_TYPE_EDGE_FALLING: + chip->irq_rising_edge[index] &= ~BIT(offset); + chip->irq_falling_edge[index] |= BIT(offset); + break; + default: + return -EINVAL; + } + + irq_set_handler_locked(irq_data, handle_edge_irq); + return 0; +} + +static struct irq_chip xgpio_irqchip = { + .name = "gpio-xilinx", + .irq_ack = xgpio_irq_ack, + .irq_mask = xgpio_irq_mask, + .irq_unmask = xgpio_irq_unmask, + .irq_set_type = xgpio_set_irq_type, +}; + +/** + * xgpio_irqhandler - Gpio interrupt service routine + * @desc: Pointer to interrupt description + */ +static void xgpio_irqhandler(struct irq_desc *desc) +{ + struct xgpio_instance *chip = irq_desc_get_handler_data(desc); + struct irq_chip *irqchip = irq_desc_get_chip(desc); + u32 num_channels = chip->gpio_width[1] ? 2 : 1; + u32 offset = 0, index; + u32 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); + + xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); + + chained_irq_enter(irqchip, desc); + for (index = 0; index < num_channels; index++) { + if ((status & BIT(index))) { + unsigned long rising_events, falling_events, all_events; + unsigned long flags; + u32 data, bit; + + spin_lock_irqsave(&chip->gpio_lock, flags); + data = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + + index * XGPIO_CHANNEL_OFFSET); + rising_events = data & + ~chip->gpio_last_irq_read[index] & + chip->irq_enable[index] & + chip->irq_rising_edge[index]; + falling_events = ~data & + chip->gpio_last_irq_read[index] & + chip->irq_enable[index] & + chip->irq_falling_edge[index]; + dev_dbg(chip->gc.parent, + "IRQ chan %u rising 0x%lx falling 0x%lx\n", + index, rising_events, falling_events); + all_events = rising_events | falling_events; + chip->gpio_last_irq_read[index] = data; + spin_unlock_irqrestore(&chip->gpio_lock, flags); + + for_each_set_bit(bit, &all_events, 32) { + generic_handle_irq(irq_find_mapping + (chip->gc.irq.domain, offset + bit)); + } + } + offset += chip->gpio_width[index]; + } + + chained_irq_exit(irqchip, desc); +} + +/** * xgpio_of_probe - Probe method for the GPIO device. * @pdev: pointer to the platform device * @@ -350,7 +575,8 @@ static int xgpio_probe(struct platform_device *pdev) struct xgpio_instance *chip; int status = 0; struct device_node *np = pdev->dev.of_node; - u32 is_dual; + u32 is_dual = 0; + u32 cells = 2; chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); if (!chip) @@ -359,12 +585,18 @@ static int xgpio_probe(struct platform_device *pdev) platform_set_drvdata(pdev, chip); /* Update GPIO state shadow register with default value */ - of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]); + if (of_property_read_u32(np, "xlnx,dout-default", + &chip->gpio_state[0])) + dev_info(&pdev->dev, "Missing xlnx,dout-default property\n"); /* Update GPIO direction shadow register with default value */ if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0])) chip->gpio_dir[0] = 0xFFFFFFFF; + /* Update cells with gpio-cells value */ + if (of_property_read_u32(np, "#gpio-cells", &cells)) + dev_info(&pdev->dev, "Missing gpio-cells property\n"); + /* * Check device node and parent device node for device width * and assume default width of 32 @@ -372,15 +604,17 @@ static int xgpio_probe(struct platform_device *pdev) if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0])) chip->gpio_width[0] = 32; - spin_lock_init(&chip->gpio_lock[0]); + spin_lock_init(&chip->gpio_lock); if (of_property_read_u32(np, "xlnx,is-dual", &is_dual)) is_dual = 0; if (is_dual) { /* Update GPIO state shadow register with default value */ - of_property_read_u32(np, "xlnx,dout-default-2", - &chip->gpio_state[1]); + if (of_property_read_u32(np, "xlnx,dout-default-2", + &chip->gpio_state[1])) + dev_info(&pdev->dev, + "Missing xlnx,dout-default-2 property\n"); /* Update GPIO direction shadow register with default value */ if (of_property_read_u32(np, "xlnx,tri-default-2", @@ -394,8 +628,6 @@ static int xgpio_probe(struct platform_device *pdev) if (of_property_read_u32(np, "xlnx,gpio2-width", &chip->gpio_width[1])) chip->gpio_width[1] = 32; - - spin_lock_init(&chip->gpio_lock[1]); } chip->gc.base = -1; @@ -403,6 +635,8 @@ static int xgpio_probe(struct platform_device *pdev) chip->gc.parent = &pdev->dev; chip->gc.direction_input = xgpio_dir_in; chip->gc.direction_output = xgpio_dir_out; + chip->gc.of_gpio_n_cells = cells; + chip->gc.of_xlate = xgpio_xlate; chip->gc.get = xgpio_get; chip->gc.set = xgpio_set; chip->gc.request = xgpio_request; @@ -435,6 +669,29 @@ static int xgpio_probe(struct platform_device *pdev) xgpio_save_regs(chip); + chip->irq = platform_get_irq_optional(pdev, 0); + if (chip->irq <= 0) { + dev_info(&pdev->dev, "GPIO IRQ not set\n"); + } else { + u32 temp; + + /* Disable per-channel interrupts */ + xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0); + /* Clear any existing per-channel interrupts */ + temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); + xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp); + /* Enable global interrupts */ + xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE); + + chip->gc.irq.chip = &xgpio_irqchip; + chip->gc.irq.handler = handle_bad_irq; + chip->gc.irq.default_type = IRQ_TYPE_NONE; + chip->gc.irq.parent_handler = xgpio_irqhandler; + chip->gc.irq.parent_handler_data = chip; + chip->gc.irq.parents = (unsigned int *)&chip->irq; + chip->gc.irq.num_parents = 1; + } + status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); if (status) { dev_err(&pdev->dev, "failed to add GPIO chip\n"); From patchwork Thu Jul 23 14:06:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Neeli X-Patchwork-Id: 11681037 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 11914618 for ; Thu, 23 Jul 2020 14:08:33 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DD18720709 for ; Thu, 23 Jul 2020 14:08:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="IVGfY//L"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=xilinx.onmicrosoft.com header.i=@xilinx.onmicrosoft.com header.b="lDfeis9+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DD18720709 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xilinx.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3kqeg4AQrgb3ZDeq8i1NyrlSmKq6LCgO/QIw5cMAjAo=; b=IVGfY//LWR2AVhLDSQ5f7L5A7 btqVlnGfiGB4Tbx0yW9I9Kk1XO11fPU39xIlpKtg/y3p6Na7PZXFTy+3WI1Bzy7QvksQ1IS3JUIJP KogwEINIqEXTG4tkBaDuOrrr4Rupr7XJVwEh9HtGSzhaHWFA7qbbxEd3xlmgTr2LVdUCbzzV/Qek6 bSFo7+3MGaLtr8Xya5BlVMXns2CwXfSdvrOEKJC6Sp889grAQTvTezZn/R2cdM4jevosAydT4D/VG hYKzLNsu8gK8nLjoVSwB2CNx2HxDGE7k29bTfQyzhEGFO9ZElFoQknpna+Ua3zwlMr0aNNFkyRpxZ yR1M2bpfQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jybrr-0003x8-DU; Thu, 23 Jul 2020 14:06:39 +0000 Received: from mail-dm6nam12on2070.outbound.protection.outlook.com ([40.107.243.70] helo=NAM12-DM6-obe.outbound.protection.outlook.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jybrj-0003vD-Qi for linux-arm-kernel@lists.infradead.org; Thu, 23 Jul 2020 14:06:32 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iwh3BcFlFOKeJhKiXlg8X/vQuWr65i5oNLPQajYn0C0/OgAqQB1o7vc+F6bYAK65Vzpkj1oYxHNManIndFH9HbQJ0lpAWVbZ73vmzsQULNbBiFc6HdIkR+Nr4poGE0pMMY29YW6nU8SF3cqkJ5EXiTviL0LNb+EvqKs6FlvUCms1b0t+K+Bwa1Ho4gB9bm7qYLMlwnh5aMbM6qntD9lluXcRF3O6tdgfcq6UEGn0ojf6bHVaEvMVyAg6qSFll4viGmQPS9AzZom9TmE1oQohuhSf6kJBnk1N9Apv9usCNRIZu4pMAai0SAcuXFdV91qPynFYcauZRO2xSr4+2HG2qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ywkMrig5SSgN6/sqmk4HzYAND1AgcJ2iPorIfTQ34iw=; b=Zjn4EnWt/nG8LGM5YLnHSR/ccy2zjTh3FQvPYvPAT1SjHMnBctxb24fvonidkf8KVvS1e9lHs12OH4cmtIiYLNNws1Z5rkVKbmuMDzB0IEZltZ8K7QC6z97IV1P/TbvpMMTIoIHLw/jjM5SNogJ6giol00N/KG3n71pelnLqfuAUh+bg+fah9ovot3UBs0YsR6iPKSw8O75LHMs52WCDd6CFXXE/8rGWMB40EFByJCREGwfYHLuJ/hXPafvmkPiK+DE6CyrBsf5dh5/QnKDgamVJgVpSDHr80NTOy7Ok/ySOXpY/WC3tY7z+aFzBmtq1SFPon2p4crUd3v112AyCag== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ywkMrig5SSgN6/sqmk4HzYAND1AgcJ2iPorIfTQ34iw=; b=lDfeis9+UZVRtxXibhX32gczqEqCJf9RTN5BYcGbYoiibGRlei3W/kGcVIKJNjSgYvn/hX0DlASA7MJeS3+gmzpDlZU5+Ep6yId06jf6USw+gYWNpgSOsOSnYYKm4x6HuaOboJLdiNs+ORLssxJUiUV1ZtXw8+X6kMiAC5yXHSQ= Received: from MN2PR05CA0039.namprd05.prod.outlook.com (2603:10b6:208:236::8) by SN4PR0201MB3616.namprd02.prod.outlook.com (2603:10b6:803:4e::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3216.22; Thu, 23 Jul 2020 14:06:29 +0000 Received: from BL2NAM02FT055.eop-nam02.prod.protection.outlook.com (2603:10b6:208:236:cafe::4c) by MN2PR05CA0039.outlook.office365.com (2603:10b6:208:236::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3239.9 via Frontend Transport; Thu, 23 Jul 2020 14:06:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BL2NAM02FT055.mail.protection.outlook.com (10.152.77.126) with Microsoft SMTP Server id 15.20.3216.10 via Frontend Transport; Thu, 23 Jul 2020 14:06:29 +0000 Received: from [149.199.38.66] (port=56968 helo=smtp.xilinx.com) by xsj-pvapsmtpgw01 with esmtp (Exim 4.90) (envelope-from ) id 1jybpr-0004HR-0H; Thu, 23 Jul 2020 07:04:35 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1jybrh-0005To-0Q; Thu, 23 Jul 2020 07:06:29 -0700 Received: from xsj-pvapsmtp01 (smtp3.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 06NE6K0B004486; Thu, 23 Jul 2020 07:06:20 -0700 Received: from [10.140.6.6] (helo=xhdappanad40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1jybrX-0005Q2-PL; Thu, 23 Jul 2020 07:06:20 -0700 From: Srinivas Neeli To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, michal.simek@xilinx.com, shubhrajyoti.datta@xilinx.com, sgoud@xilinx.com Subject: [PATCH V2 3/3] MAINTAINERS: add fragment for xilinx GPIO drivers Date: Thu, 23 Jul 2020 19:36:08 +0530 Message-Id: <1595513168-11965-4-git-send-email-srinivas.neeli@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1595513168-11965-1-git-send-email-srinivas.neeli@xilinx.com> References: <1595513168-11965-1-git-send-email-srinivas.neeli@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: d5f9b105-95e8-40b3-d227-08d82f11988d X-MS-TrafficTypeDiagnostic: SN4PR0201MB3616: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:1227; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Jqv9787RC4TI3u7wi3TlNfXgoThYZ/W12FYCsFWDTA9vFYOWoaFlmVNm6QvGzmHKCIZCsLtd79MpXcXXQq8ibN+H80d4zFShF8YUGl0WCFoV7dzRfM95wKp/41Pqqx9zHze7l0U/iqPtCzMPilG/Ls+KW31CPlNBP8HrRre7JbZv5VnBvZx0WpuN2s5t7CPkM1rzcwVsd8oGtvc6fQmTjPMDWqyUBIZyKqkdf0o7eQXEXg8vUr7nnqOE4YS/zA3yNCBjtgocQ5fHC2buMFjkfaLyQT7UorJ9tztDAfPXBbBMyF7Te2ZiUZM/WDq01THgXHQuLb2dKZVrjsZ9KM2aVXX/nP2a/5OuO4Edb19RL35Lwjp2mqHC7ww3TegHBIRSf4rAmGE3rnDgax/44AiiIA== X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFTY:; SFS:(136003)(376002)(346002)(396003)(39860400002)(46966005)(107886003)(336012)(81166007)(2616005)(70206006)(82740400003)(47076004)(44832011)(70586007)(186003)(26005)(9786002)(4744005)(6666004)(8936002)(356005)(6636002)(7696005)(478600001)(2906002)(82310400002)(426003)(5660300002)(36756003)(8676002)(4326008)(316002); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2020 14:06:29.3235 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5f9b105-95e8-40b3-d227-08d82f11988d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT055.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN4PR0201MB3616 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200723_100631_919759_D43E1A9C X-CRM114-Status: UNSURE ( 9.10 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.243.70 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [40.107.243.70 listed in wl.mailspike.net] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, git@xilinx.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Added entry for xilinx GPIO drivers. Signed-off-by: Srinivas Neeli Acked-by: Michal Simek Acked-by: : Shubhrajyoti Datta --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ea296f213e45..71c40b0ddef6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18900,6 +18900,16 @@ S: Maintained F: Documentation/devicetree/bindings/net/can/xilinx_can.txt F: drivers/net/can/xilinx_can.c +XILINX GPIO DRIVER +M: Shubhrajyoti Datta +R: Srinivas Neeli +R: Michal Simek +S: Maintained +F: Documentation/devicetree/bindings/gpio/gpio-xilinx.txt +F: Documentation/devicetree/bindings/gpio/gpio-zynq.txt +F: drivers/gpio/gpio-xilinx.c +F: drivers/gpio/gpio-zynq.c + XILINX SD-FEC IP CORES M: Derek Kiernan M: Dragan Cvetic