From patchwork Tue Jul 28 10:06:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 11688831 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E22F722 for ; Tue, 28 Jul 2020 10:07:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B0E4020792 for ; Tue, 28 Jul 2020 10:07:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=xen0n.name header.i=@xen0n.name header.b="xqVLRY/a" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728496AbgG1KHE (ORCPT ); Tue, 28 Jul 2020 06:07:04 -0400 Received: from [115.28.160.31] ([115.28.160.31]:57932 "EHLO mailbox.box.xen0n.name" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728509AbgG1KHE (ORCPT ); Tue, 28 Jul 2020 06:07:04 -0400 Received: from ld50.lan (unknown [140.207.23.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 276FC60161; Tue, 28 Jul 2020 18:07:01 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1595930821; bh=Sy5D/qpMTXAVfR40gwMseHO9e3qqlPZ1+KWghnEkioY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xqVLRY/aKFxtXJPh5aYYF+5In2rwsjmtm9B0CWOIGpomFSjCHHnTtG7E9QS2sPt+h iFlc2RiFpx60bp8f8SE+xUxAi9/p5qCCYlKPvAcEVGo79smqn68FX+ub6v2Rqai3VI tcFKdj9/Vzc7/jpsQ1+VB+JAJySQbBjczZ0Jnh20= From: WANG Xuerui To: linux-mips@vger.kernel.org Cc: WANG Xuerui , Huacai Chen , Paul Burton Subject: [PATCH v4 1/3] MIPS: only register FTLBPar exception handler for supported models Date: Tue, 28 Jul 2020 18:06:53 +0800 Message-Id: <20200728100655.3005831-2-git@xen0n.name> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200728100655.3005831-1-git@xen0n.name> References: <20200728100655.3005831-1-git@xen0n.name> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Previously ExcCode 16 is unconditionally treated as the FTLB parity exception (FTLBPar), but in fact its semantic is implementation- dependent. Looking at various manuals it seems the FTLBPar exception is only present on some recent MIPS Technologies cores, so only register the handler on these. Fixes: 75b5b5e0a262790f ("MIPS: Add support for FTLBs") Reviewed-by: Huacai Chen Signed-off-by: WANG Xuerui Cc: Paul Burton --- arch/mips/include/asm/cpu-features.h | 4 ++++ arch/mips/include/asm/cpu.h | 1 + arch/mips/kernel/cpu-probe.c | 13 +++++++++++++ arch/mips/kernel/traps.c | 3 ++- 4 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 724dfddcab92..0b1bc7ed913b 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -568,6 +568,10 @@ # define cpu_has_mac2008_only __opt(MIPS_CPU_MAC_2008_ONLY) #endif +#ifndef cpu_has_ftlbparex +# define cpu_has_ftlbparex __opt(MIPS_CPU_FTLBPAREX) +#endif + #ifdef CONFIG_SMP /* * Some systems share FTLB RAMs between threads within a core (siblings in diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index f5b04e8f6061..9d08bd33b11f 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -427,6 +427,7 @@ enum cpu_type_enum { #define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */ #define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */ #define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */ +#define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */ /* * CPU ASE encodings diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index d9e8d39a7289..519d101fd009 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1827,6 +1827,19 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) default: break; } + + /* Recent MIPS cores use the implementation-dependent ExcCode 16 for + * cache/FTLB parity exceptions. + */ + switch (__get_cpu_type(c->cputype)) { + case CPU_PROAPTIV: + case CPU_P5600: + case CPU_P6600: + case CPU_I6400: + case CPU_I6500: + c->options |= MIPS_CPU_FTLBPAREX; + break; + } } static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 06aba49d37c9..9c37a6997259 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2454,7 +2454,8 @@ void __init trap_init(void) if (cpu_has_fpu && !cpu_has_nofpuex) set_except_vector(EXCCODE_FPE, handle_fpe); - set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb); + if (cpu_has_ftlbparex) + set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb); if (cpu_has_rixiex) { set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0); From patchwork Tue Jul 28 10:06:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 11688837 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 68AE214DD for ; Tue, 28 Jul 2020 10:07:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4664B207E8 for ; Tue, 28 Jul 2020 10:07:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=xen0n.name header.i=@xen0n.name header.b="eQ/xVJw2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728516AbgG1KHR (ORCPT ); Tue, 28 Jul 2020 06:07:17 -0400 Received: from [115.28.160.31] ([115.28.160.31]:57942 "EHLO mailbox.box.xen0n.name" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728439AbgG1KHQ (ORCPT ); Tue, 28 Jul 2020 06:07:16 -0400 Received: from ld50.lan (unknown [140.207.23.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 5542D60162; Tue, 28 Jul 2020 18:07:03 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1595930823; bh=JEEfYy78okpVAegUyJXkukgHSh8J+gMFXid6ZKz+zfY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eQ/xVJw2e4jOSjnTPzimiA3oB58EEh4aYmRSrj2/f7fQbjG32ATSjcnEn5YE8Zdr3 AJcPjhXb1zJJr1+I8sfLspneCqXCOszgHPm5xyoiOc4jRXmx6tJeEf3O3aZ6nyIc5q SZX3//eGp+QbqvBx3T9gGsQVysE9TTu5LcbBLmZU= From: WANG Xuerui To: linux-mips@vger.kernel.org Cc: WANG Xuerui , Huacai Chen , Jiaxun Yang , Tiezhu Yang Subject: [PATCH v4 2/3] MIPS: add definitions for Loongson-specific CP0.Diag1 register Date: Tue, 28 Jul 2020 18:06:54 +0800 Message-Id: <20200728100655.3005831-3-git@xen0n.name> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200728100655.3005831-1-git@xen0n.name> References: <20200728100655.3005831-1-git@xen0n.name> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org This register is named GSCause in Loongson manuals. It carries Loongson extended exception information. Reviewed-by: Huacai Chen Signed-off-by: WANG Xuerui Cc: Huacai Chen Cc: Jiaxun Yang Cc: Tiezhu Yang --- arch/mips/include/asm/mipsregs.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 11094d857b92..5ba268266d16 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -86,6 +86,7 @@ #define CP0_XCONTEXT $20 #define CP0_FRAMEMASK $21 #define CP0_DIAGNOSTIC $22 +#define CP0_DIAGNOSTIC1 $22, 1 #define CP0_DEBUG $23 #define CP0_DEPC $24 #define CP0_PERFORMANCE $25 @@ -1051,6 +1052,13 @@ /* Flush FTLB */ #define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13) +/* + * Diag1 (GSCause in Loongson-speak) fields + */ +/* Loongson-specific exception code (GSExcCode) */ +#define LOONGSON_DIAG1_EXCCODE_SHIFT 2 +#define LOONGSON_DIAG1_EXCCODE GENMASK(6, 2) + /* CvmCtl register field definitions */ #define CVMCTL_IPPCI_SHIFT 7 #define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT) From patchwork Tue Jul 28 10:06:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 11688835 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2937B14DD for ; Tue, 28 Jul 2020 10:07:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0CB6A207E8 for ; Tue, 28 Jul 2020 10:07:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=xen0n.name header.i=@xen0n.name header.b="kyAb3yH6" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728532AbgG1KHM (ORCPT ); Tue, 28 Jul 2020 06:07:12 -0400 Received: from [115.28.160.31] ([115.28.160.31]:57950 "EHLO mailbox.box.xen0n.name" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1728516AbgG1KHM (ORCPT ); Tue, 28 Jul 2020 06:07:12 -0400 Received: from ld50.lan (unknown [140.207.23.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id BE90260163; Tue, 28 Jul 2020 18:07:04 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1595930825; bh=m6wz7vQZvzTBdMAfe8GuGXNmpJR1uCDpXxJoXhtQIas=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kyAb3yH6rLZ4eQBH/v/1SUCm+7SQnP/XWrsbF7puJKLiigLgsDRqnW4O5kw0yrZci q7fVPTak77tKXKVYzqKDg6nWpY/99hzRRjdocwPOJ8TnME8RMd8E8MTg2ffVb8cSvm g+ETRM7HibpYNkhxzh9hLLDVqSr+mE826NJyzO0U= From: WANG Xuerui To: linux-mips@vger.kernel.org Cc: WANG Xuerui , Huacai Chen , Jiaxun Yang , Tiezhu Yang Subject: [PATCH v4 3/3] MIPS: handle Loongson-specific GSExc exception Date: Tue, 28 Jul 2020 18:06:55 +0800 Message-Id: <20200728100655.3005831-4-git@xen0n.name> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200728100655.3005831-1-git@xen0n.name> References: <20200728100655.3005831-1-git@xen0n.name> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Newer Loongson cores (Loongson-3A R2 and newer) use the implementation-dependent ExcCode 16 to signal Loongson-specific exceptions. The extended cause is put in the non-standard CP0.Diag1 register which is CP0 Register 22 Select 1, called GSCause in Loongson manuals. Inside is an exception code bitfield called GSExcCode, only codes 0 to 6 inclusive are documented (so far, in the Loongson 3A3000 User Manual, Volume 2). During experiments, it was found that some undocumented unprivileged instructions can trigger the also-undocumented GSExcCode 8 on Loongson 3A4000. Processor state is not corrupted, but we cannot continue without further knowledge, and Loongson is not providing that information as of this writing. So we send SIGILL on seeing this exception code to thwart easy local DoS attacks. Other exception codes are made fatal, partly because of insufficient knowledge, also partly because they are not as easily reproduced. None of them are encountered in the wild with upstream kernels and userspace so far. Some older cores (Loongson-3A1000 and Loongson-3B1500) have ExcCode 16 too, but the semantic is equivalent to GSExcCode 0. Because the respective manuals did not mention the CP0.Diag1 register or its read behavior, these cores are not covered in this patch, as MFC0 from non-existent CP0 registers is UNDEFINED according to the MIPS architecture spec. Reviewed-by: Huacai Chen Signed-off-by: WANG Xuerui Cc: Huacai Chen Cc: Jiaxun Yang Cc: Tiezhu Yang --- arch/mips/include/asm/cpu-features.h | 4 ++++ arch/mips/include/asm/cpu.h | 1 + arch/mips/include/asm/mipsregs.h | 3 +++ arch/mips/kernel/cpu-probe.c | 3 +++ arch/mips/kernel/genex.S | 7 ++++++ arch/mips/kernel/traps.c | 35 ++++++++++++++++++++++++++++ 6 files changed, 53 insertions(+) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 0b1bc7ed913b..78cf7e300f12 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -572,6 +572,10 @@ # define cpu_has_ftlbparex __opt(MIPS_CPU_FTLBPAREX) #endif +#ifndef cpu_has_gsexcex +# define cpu_has_gsexcex __opt(MIPS_CPU_GSEXCEX) +#endif + #ifdef CONFIG_SMP /* * Some systems share FTLB RAMs between threads within a core (siblings in diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 9d08bd33b11f..388a82f28a87 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -428,6 +428,7 @@ enum cpu_type_enum { #define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */ #define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */ #define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */ +#define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */ /* * CPU ASE encodings diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 5ba268266d16..4ddc12e4444a 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -474,6 +474,9 @@ /* Implementation specific trap codes used by MIPS cores */ #define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */ +/* Implementation specific trap codes used by Loongson cores */ +#define LOONGSON_EXCCODE_GSEXC 16 /* Loongson-specific exception */ + /* * Bits in the coprocessor 0 config register. */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 519d101fd009..e2955f1f6316 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -2043,6 +2043,9 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); + /* All Loongson processors covered here define ExcCode 16 as GSExc. */ + c->options |= MIPS_CPU_GSEXCEX; + switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */ switch (c->processor_id & PRID_REV_MASK) { diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index a1b966f3578e..5fa87d4b5dca 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -498,6 +498,12 @@ NESTED(nmi_handler, PT_SIZE, sp) KMODE .endm + .macro __build_clear_gsexc + mfc0 a1, CP0_DIAGNOSTIC1 + TRACE_IRQS_ON + STI + .endm + .macro __BUILD_silent exception .endm @@ -556,6 +562,7 @@ NESTED(nmi_handler, PT_SIZE, sp) BUILD_HANDLER fpe fpe fpe silent /* #15 */ #endif BUILD_HANDLER ftlb ftlb none silent /* #16 */ + BUILD_HANDLER gsexc gsexc gsexc silent /* #16 */ BUILD_HANDLER msa msa sti silent /* #21 */ BUILD_HANDLER mdmx mdmx sti silent /* #22 */ #ifdef CONFIG_HARDWARE_WATCHPOINTS diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 9c37a6997259..b95ef98fc847 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -90,6 +90,7 @@ extern asmlinkage void handle_tr(void); extern asmlinkage void handle_msa_fpe(void); extern asmlinkage void handle_fpe(void); extern asmlinkage void handle_ftlb(void); +extern asmlinkage void handle_gsexc(void); extern asmlinkage void handle_msa(void); extern asmlinkage void handle_mdmx(void); extern asmlinkage void handle_watch(void); @@ -1900,6 +1901,37 @@ asmlinkage void do_ftlb(void) cache_parity_error(); } +asmlinkage void do_gsexc(struct pt_regs *regs, u32 diag1) +{ + u32 exccode = (diag1 & LOONGSON_DIAG1_EXCCODE) >> + LOONGSON_DIAG1_EXCCODE_SHIFT; + enum ctx_state prev_state; + + prev_state = exception_enter(); + + switch (exccode) { + case 0x08: + /* Undocumented exception, will trigger on certain + * also-undocumented instructions accessible from userspace. + * Processor state is not otherwise corrupted, but currently + * we don't know how to proceed. Maybe there is some + * undocumented control flag to enable the instructions? + */ + force_sig(SIGILL); + break; + + default: + /* None of the other exceptions, documented or not, have + * further details given; none are encountered in the wild + * either. Panic in case some of them turn out to be fatal. + */ + show_regs(regs); + panic("Unhandled Loongson exception - GSCause = %08x", diag1); + } + + exception_exit(prev_state); +} + /* * SDBBP EJTAG debug exception handler. * We skip the instruction and return to the next instruction. @@ -2457,6 +2489,9 @@ void __init trap_init(void) if (cpu_has_ftlbparex) set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb); + if (cpu_has_gsexcex) + set_except_vector(LOONGSON_EXCCODE_GSEXC, handle_gsexc); + if (cpu_has_rixiex) { set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0); set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);