From patchwork Tue Jul 28 12:00:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11689047 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ACC2F138A for ; Tue, 28 Jul 2020 12:02:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 93FC1206D8 for ; Tue, 28 Jul 2020 12:02:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XhGRjwGT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729363AbgG1MBB (ORCPT ); Tue, 28 Jul 2020 08:01:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728433AbgG1MA5 (ORCPT ); Tue, 28 Jul 2020 08:00:57 -0400 Received: from mail-ej1-x644.google.com (mail-ej1-x644.google.com [IPv6:2a00:1450:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA2ECC061794; Tue, 28 Jul 2020 05:00:56 -0700 (PDT) Received: by mail-ej1-x644.google.com with SMTP id g11so8594744ejr.0; Tue, 28 Jul 2020 05:00:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ffWqQU26EKVHaH4j5TG8VdhwKZhWQGA8HNUdkfskr1g=; b=XhGRjwGTZha6i/yTV+XGzgtJ19Gpn6Af6MpVejeJZv1Ob0nHEtEPTmGQvdHj3wWeZA OJZRDvM6CrenC/peuCellSxg58Q4YTrRF1dHzSaa3fgYzUmbHlyyskhKISTaJ+sLl0Gy DfDy1rkA0aRQtYqOIixVSIWH7sBRc1B5idFtHZTITgoTOQ0hfWv1gcGbIdF+boZ1DoAu 3p7P28gHeupe8x3ElEg43Wi7QvNT9fift1ztA3iKy+3XzofKPQEIaDz1/0ghSRQpXe+U /P9e6pouDZGt/j4cNvXT3TlGcB3uuegPRs2iBiaiY084iDzgAyK8sNnGEHgcbTc3mnTK 28Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ffWqQU26EKVHaH4j5TG8VdhwKZhWQGA8HNUdkfskr1g=; b=IsfMU3g70eiRBBqp1KIV2gKI7M6I42SfKXbeE9KlYM3SFikGQNB5dZWkQhwU3AMZV8 G/K6Vf0Toj8cW547bvFd/iwykpdo86TvnhZKsvy7XQLQe2p7VvVSJ/tW5h6Mr7sftNif NsdWbQ55xuTN9YHe/Yqq9s3vNJ+zxezhdz9ssGxeUf1DiDmCirbe2voftcvclPoZrgWA ZsjUu1XrkCq7GJmlLdF3b1SMybMlMmX+N4kOdAFi259KhnqK9omv0VERXqiLe1p8L2x/ 6NIcwnzYZ5aSMNjWKAf7OAPJrxUTTPbLdvnJQ7XU8bPIrEE2QIbp0QsLT9dCeSpp3KIH 25ug== X-Gm-Message-State: AOAM53232v38bdlU4SUzNuIvdmp9V5Gn7DCqmV1utONccmGJjoSHRwMw Gii/E8eEWJuUcE2Uuy3hp2A= X-Google-Smtp-Source: ABdhPJySGywHKrMDtAGMCMCJezKcwlgt4bsxbE49z3gC/dJPNUvkaEKJIGl938aoMrw8a1SBIpiq/w== X-Received: by 2002:a17:906:3789:: with SMTP id n9mr26589606ejc.512.1595937655665; Tue, 28 Jul 2020 05:00:55 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id m20sm9066959ejk.90.2020.07.28.05.00.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2020 05:00:55 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 1/9] arm64: dts: qcom: msm8992: Add support for SDHCI2 Date: Tue, 28 Jul 2020 14:00:40 +0200 Message-Id: <20200728120049.90632-2-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200728120049.90632-1-konradybcio@gmail.com> References: <20200728120049.90632-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This will let us use SD cards on our devices. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 188fff2095f1..9b42ac42b171 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -269,6 +269,28 @@ sdhc_1: sdhci@f9824900 { status = "disabled"; }; + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + bus-width = <4>; + status = "disabled"; + }; + blsp1_uart2: serial@f991e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991e000 0x1000>; @@ -573,6 +595,42 @@ i2c13_sleep: i2c13-sleep { drive-strength = <2>; bias-disable; }; + + sdc2_clk_on: sdc2-clk-on { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + sdc2_clk_off: sdc2-clk-off { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_data_on: sdc2-data-on { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_data_off: sdc2-data-off { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; }; }; From patchwork Tue Jul 28 12:00:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11689023 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E3E8314DD for ; Tue, 28 Jul 2020 12:01:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CB4882070A for ; Tue, 28 Jul 2020 12:01:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OhIg1fTQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728532AbgG1MBO (ORCPT ); Tue, 28 Jul 2020 08:01:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729360AbgG1MA7 (ORCPT ); Tue, 28 Jul 2020 08:00:59 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31E6EC0619D2; Tue, 28 Jul 2020 05:00:59 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id g11so8594901ejr.0; Tue, 28 Jul 2020 05:00:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TF7XW+i8cbP3gIkhlhIAvvLS4ohbcx6+poBRM18scqo=; b=OhIg1fTQdLmmOgTdUB8tQOREg495rzSHC3h+iJ0gdW3qkQHC7lwxz0ya8UmppcA4bJ nEbeRRpAdpH9R8I3N7XCaCt0O8jDr+2UyguL3yh2Q+wqIZnJj0ocNQ81CMhll91eQ7jn QjX/C8CWu7Eznlhpj5Kg+DLzrfzyaAXyYIyL2a/9a2nUtXeSFPcjicQCU7BakvxVdgmp rgoelzIQ3OsDRjHoGQrYCBH3tpBP1o37B5XJ5V5G5oxJpuk9ohYtqdhQqynCVrPw61QV pWClnZsfhTlR7AKBr1wZ16nQ450ZDmw7A9CvI01aKTveRkq+jdrQvhKV2DmuN5CNKFEt /yMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TF7XW+i8cbP3gIkhlhIAvvLS4ohbcx6+poBRM18scqo=; b=i29uFnfLvpC4HkbIF9e5sDyTLzPNmyPucE3yqypUtjzgFeS8pRazq0rlHL+3X7lv4v C7QQIknIm4K/bxdb73naJaD5Lva/OMQxWVvVl3/ZaXJ6g33RaG5jHTOjUcVRmP4iSvk4 RxLg54qwO2Fxed1/pu5C6CRLkvb55uFYf1QNDtWjgNE0vAMcZNlIE8NFsGIQejN4+YCB YDrkEcV+ux8sNFOUEDUkSkSCl8KlPi4z3dQ5pfKVXjhjOlor1Fmf/z8jA5rYIMYzEvoc glo61kPOHDtEecAuOEZVY/LkU4Xq/F+VaZz4ad/DyiY5Gr9E6wOSyNdLTaNk5ioCP9XY Akmw== X-Gm-Message-State: AOAM532NsUtx/h0nLN1X82Tp3KFtb3rctCWJwYN32nRQ94pv7Qw9E+o0 vvSYf3YvTf47vwvzAm+F6BI= X-Google-Smtp-Source: ABdhPJzY8o0HSAQtgr/Of9SIxDF4WdBHD1mCWT4iXipAakxc2uo+Z9r7/vYhS8koW+loSkOs1vXSDQ== X-Received: by 2002:a17:906:cc51:: with SMTP id mm17mr5356124ejb.137.1595937657873; Tue, 28 Jul 2020 05:00:57 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id m20sm9066959ejk.90.2020.07.28.05.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2020 05:00:57 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/9] arm64: dts: qcom: msm8992: Add BLSP_I2C1 support Date: Tue, 28 Jul 2020 14:00:41 +0200 Message-Id: <20200728120049.90632-3-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200728120049.90632-1-konradybcio@gmail.com> References: <20200728120049.90632-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This will be required to support touchscreen on Lumia devices. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 35 +++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 9b42ac42b171..c7dc81311f6a 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -304,6 +304,27 @@ blsp1_uart2: serial@f991e000 { status = "disabled"; }; + /* + * This I2C seems to only be present on WP platforms + * and is likely disabled in firmware + * (hangs at least one device) on android platforms. + */ + blsp_i2c1: i2c@f9923000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0xf9923000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp_i2c2: i2c@f9924000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9924000 0x500>; @@ -524,6 +545,20 @@ sdc1_rclk_off: rclk-off { bias-pull-down; }; + i2c1_default: i2c1-default { + function = "blsp_i2c1"; + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + + i2c1_sleep: i2c1-sleep { + function = "gpio"; + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + i2c2_default: i2c2-default { function = "blsp_i2c2"; pins = "gpio6", "gpio7"; From patchwork Tue Jul 28 12:00:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11689015 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E4C9A138A for ; Tue, 28 Jul 2020 12:01:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CD3432070B for ; Tue, 28 Jul 2020 12:01:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="I2QS9qKS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729379AbgG1MBR (ORCPT ); Tue, 28 Jul 2020 08:01:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729367AbgG1MBG (ORCPT ); Tue, 28 Jul 2020 08:01:06 -0400 Received: from mail-ej1-x644.google.com (mail-ej1-x644.google.com [IPv6:2a00:1450:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AA72C061794; Tue, 28 Jul 2020 05:01:01 -0700 (PDT) Received: by mail-ej1-x644.google.com with SMTP id g19so6554517ejc.9; Tue, 28 Jul 2020 05:01:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IyAadO7Kj4svE/f2q3Z4e23jYOH8YNibv5HEpOFyPnU=; b=I2QS9qKSrAv3mifGQ4wDSuFxwmoGabSN9zc2D6U8ipjMW8pAvawisbMDf992Dp3fj4 PE92oW2HDLEjuw47a45YPMdMWbMtA3p7gVxhIZ1KTK4dEDA4YP35J1XVBe+HZK42hSI2 SOISi6OaPdc1ucnxypDto+Z1uipb1LTEfThL+6MptOLKYFo+yRW5sJfQ9/ib+gMaWlCj 9V/z20HrF/HjvVgGx0TBgbohIovFDG6CBHCJ3Y7QZnRLcD2SRX91tOAPi7iBwACfOR9k VZuTlk19NnN59ASY0cJGB2CaosmPI0SnIWhxDoiTn4lHe8U/moQC65zznGndXOVxtjgv w1Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IyAadO7Kj4svE/f2q3Z4e23jYOH8YNibv5HEpOFyPnU=; b=c2QzhUyPZhEs4FnYOf2XZG5mZxEPq5533G1o0LFeJ4xqywnJy242UPfNosR9cG96XQ C5Vh7jFhHsw4ZEQJrwxeo0ooiMo1R0gI4gMzQoYvVj1GtQLPuZh7XHiwIvN725Q/O6sV D8kCBaj6jV6QYSFjWmC2bv3Ejsn+4YhoNH/4ZK9wA2PE4v3k3iAHposOryS10Ly4D35J rf7IllWS0e44XxlAdp9xXDfS1sZpdaIrVPL4qPSbh9Q9hbURgMJTbqAAkXSzWRirsV1A fHZ+UD3YzSERocO8+I6YJAmTxIZc4EcWFGvrFwkOm9jG7hqX5jXvfnEhoVygh5xpONXC sKZA== X-Gm-Message-State: AOAM531FVU8VByXTtZBeVmN3450S36icqUBk6FA4xNgnY/o+3HZ2oLPn L/is6JyNCjQGF4IrrV0srgYUkqS2Pfw= X-Google-Smtp-Source: ABdhPJxDxLMtuTnk7fCzsV123GpwYSjEN50J+/erJ7uTMKcF56ukg6ZW2Gb2Jjw05WkykaiKDXOLBg== X-Received: by 2002:a17:906:69d3:: with SMTP id g19mr26323947ejs.402.1595937660155; Tue, 28 Jul 2020 05:01:00 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id m20sm9066959ejk.90.2020.07.28.05.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2020 05:00:59 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 3/9] arm64: dts: qcom: talkman: Add Synaptics RMI4 touchscreen Date: Tue, 28 Jul 2020 14:00:42 +0200 Message-Id: <20200728120049.90632-4-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200728120049.90632-1-konradybcio@gmail.com> References: <20200728120049.90632-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This adds touchscreen capabilities to the Lumia 950. Signed-off-by: Konrad Dybcio --- .../dts/qcom/msm8992-msft-lumia-talkman.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts index 3cc01f02219d..c337a86a5c77 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts @@ -32,6 +32,34 @@ chosen { }; }; +&blsp_i2c1 { + status = "okay"; + + rmi4-i2c-dev@4b { + compatible = "syna,rmi4-i2c"; + reg = <0x4b>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <77 IRQ_TYPE_EDGE_FALLING>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + syna,clip-x-low = <0>; + syna,clip-x-high = <1440>; + syna,clip-y-low = <0>; + syna,clip-y-high = <2560>; + }; + }; +}; + &sdhc_1 { status = "okay"; From patchwork Tue Jul 28 12:00:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11689019 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C13A6138A for ; Tue, 28 Jul 2020 12:01:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A8E14206D8 for ; Tue, 28 Jul 2020 12:01:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rUS1XigA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729276AbgG1MBV (ORCPT ); Tue, 28 Jul 2020 08:01:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729368AbgG1MBG (ORCPT ); Tue, 28 Jul 2020 08:01:06 -0400 Received: from mail-ej1-x641.google.com (mail-ej1-x641.google.com [IPv6:2a00:1450:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93ECFC0619D2; Tue, 28 Jul 2020 05:01:04 -0700 (PDT) Received: by mail-ej1-x641.google.com with SMTP id qc22so5569161ejb.4; Tue, 28 Jul 2020 05:01:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HfR71JevxYRyz0TRhP/dP0bQAGuhE76yoGQG/3ujNjQ=; b=rUS1XigATbQzlYoDZ4DMzRa2eedYzedsRIypiiqP7f/fnUKF99lpxJ8VTvukHmhG0h wYhf78pgkya+la2MOhznXTgk7doC4/z2pRUQG/LmQafuk5ciSE/dBSrJWunTbi/OtZ+r ko0Lv80L5A5M8D3SmuKzWAvdZMqMFSnKg3Cz76lBw0G1tibT16N0xQJqcs+JoGBNpkG7 fEThFrEWAuduDh5NTnc47DOXkLBYe4Zd7YLYCGpJV+vCrachsYBlvyjwQXIdomup/tE/ K70681gUN3nLqbit2WLHYrqTVONxjZaZ4CDSirpk+ZgTbH8b+BSwQ0uZQLtPhA4vSf8X Gixg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HfR71JevxYRyz0TRhP/dP0bQAGuhE76yoGQG/3ujNjQ=; b=PH2KTLlKQEbp4pOOOKeveCnPHhRX7d9xK5TAXXUqpw0YXvt3y7OVPLjV2yqrf05KlV c/8iP7UG+aWpxi3RmcD0qE/p6HXpO/1BwbDcsrPYIhNEmhgdbcRTaGzkTOsp+zV2TB8H VmROBZIPwECcsJVI6om4a8wgzc1x2BfiGYMxKpor9jyt96RDSVnE5MzFeoow07/2CKR/ Y5GYbqcwy4/9+6bnay4uuDnFrJzc4IlTojoiBTR+hhua1f7hJ+hJ1mSIfIl7wf/tCeby /0rPKnetmvJUMthPYnfQHMopUfEF6y1EC2drhJZMdg+dzV/6+jfG1IyKf4dxncU2E1F3 +sHg== X-Gm-Message-State: AOAM530pJOx56TYLkmbE5fT+9TD6ZN7lYnPRPn9TtG3DYxZ9fp8gYaID H6YDvqM4RsPKWoWgvR6c6fA= X-Google-Smtp-Source: ABdhPJzzgN/P5HqbMMWm6YUVLp/mYOXfnGat7YNAI+P/+MYBvKeNGmLwSpq2mv5x1FTwxhRoz9MCzg== X-Received: by 2002:a17:906:5f8a:: with SMTP id a10mr10029577eju.379.1595937663374; Tue, 28 Jul 2020 05:01:03 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id m20sm9066959ejk.90.2020.07.28.05.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2020 05:01:02 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 4/9] arm64: dts: qcom: msm8994: Add USB support Date: Tue, 28 Jul 2020 14:00:43 +0200 Message-Id: <20200728120049.90632-5-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200728120049.90632-1-konradybcio@gmail.com> References: <20200728120049.90632-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This is a very basic dwc3 configuration (no PHYs yet), but it works. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 6707f898607f..69c99a4cd817 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -282,6 +282,37 @@ frame@f9028000 { }; }; + usb3: usb@f92f8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0xf92f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + power-domains = <&gcc USB30_GDSC>; + qcom,select-utmi-as-pipe-clk; + + dwc3@f9200000 { + compatible = "snps,dwc3"; + reg = <0xf9200000 0xcc00>; + interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + sdhc1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; From patchwork Tue Jul 28 12:00:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11689039 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 226FE14DD for ; Tue, 28 Jul 2020 12:01:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 083FF206D7 for ; Tue, 28 Jul 2020 12:01:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DRnrQL2j" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729444AbgG1MBt (ORCPT ); Tue, 28 Jul 2020 08:01:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729369AbgG1MBH (ORCPT ); Tue, 28 Jul 2020 08:01:07 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4E6DC0619D4; Tue, 28 Jul 2020 05:01:06 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id d6so6532033ejr.5; Tue, 28 Jul 2020 05:01:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I2q93FVdT16iSOi/3vPrG4ZH4MZNlbJkhzRjHUU4qvI=; b=DRnrQL2jiANg1LCEiHbcsMAemscesJxlF/BScJWltuEPtWJgaKFG+PVuGW9l0rqJsy E8CxWg5HAmLffJCYMTwu3R53mcEt7eAThyslDukHxhqQJaQCg9l2e77xM++LCPfI/PRa a+9EifrOoaLfBUPW9n176A0RbCbC2Esmr0yQ28XLlN8lureqJostUIVXq2i8iq9r+o4A s8IqRl0nIncUTgC3Wr+P96B85iqWJxtWJIE0ErLTwwCE5zTd2LLrl8f1z8PMquFy5Ger 2QC4oF7hDe9kUiwO/I6AGWx9xt3ugCbPI+X3zakiZobmrle8YiJiINKCaxDAbU9CrlqB a6XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I2q93FVdT16iSOi/3vPrG4ZH4MZNlbJkhzRjHUU4qvI=; b=gAYlgul+qoGGwEP7VWwSaKFQz7Q/jfSWkJ0kmobcPHHbMefRCM8nYv/MttCo5TIvGp VpklOqnnmtih6GdkZioRlLD8hNNSB9YqO/7ABX7XTlo7s/Xh65RlAFpOUhG/NJYkB7Y5 Q2ovNh77Z5e9V31biYwSxCVhJo4trEa+fJ9GKH6TifwYaCZeaw9SM9fl+mN13eg2k1cP UhtYEdt07vATsNxIhRx+HmevUdjfl47mc/kmRD90bN9l7XujIfagGycfCG2WeXTM2VEZ j98ge58002i7+mnAWVuxy2T/euVoJuB58b2iv3g2cNgGm3dZ0vnmn+HtHyLNxgAFvSyU nesA== X-Gm-Message-State: AOAM533FuR8bJ8Hc3Wv6F3CwFT9UbqylFfDrxfxmoj2ufsqXMWvL8rik qaggfHiVcWABEjh1Wov1AJ8= X-Google-Smtp-Source: ABdhPJwzGWglviFaa19/EAZZVusEB9PVJX6tezEMVsH20V9O0umhp+H6N0A8L8X4h48ZE69Gi09zBQ== X-Received: by 2002:a17:906:b2d0:: with SMTP id cf16mr15708293ejb.514.1595937665567; Tue, 28 Jul 2020 05:01:05 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id m20sm9066959ejk.90.2020.07.28.05.01.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2020 05:01:05 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 5/9] arm64: dts: qcom: msm8992: Add USB support Date: Tue, 28 Jul 2020 14:00:44 +0200 Message-Id: <20200728120049.90632-6-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200728120049.90632-1-konradybcio@gmail.com> References: <20200728120049.90632-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This is a very basic dwc3 configuration (no PHYs yet), but it works. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index c7dc81311f6a..c9502fcf5d70 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -242,6 +242,37 @@ frame@f9028000 { }; }; + usb3: usb@f92f8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0xf92f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + power-domains = <&gcc USB30_GDSC>; + qcom,select-utmi-as-pipe-clk; + + dwc3@f9200000 { + compatible = "snps,dwc3"; + reg = <0xf9200000 0xcc00>; + interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + sdhc_1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; From patchwork Tue Jul 28 12:00:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11689037 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5959514DD for ; Tue, 28 Jul 2020 12:01:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3EB36206D8 for ; Tue, 28 Jul 2020 12:01:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NmhpGEGW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729439AbgG1MBt (ORCPT ); Tue, 28 Jul 2020 08:01:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729370AbgG1MBK (ORCPT ); Tue, 28 Jul 2020 08:01:10 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DBB2C0619D5; Tue, 28 Jul 2020 05:01:09 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id a21so20340452ejj.10; Tue, 28 Jul 2020 05:01:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AxIMuAf65xUDttFAgtX/y9hgYgI/2WC2s7dmySuaZaw=; b=NmhpGEGWSVBnwLu2+N3/c0iSY8Go+8rpPEhUj26swBotizptPO+rASAlQNAWxNOxbN AlKzP8/preRiYZAdVvTWvLN9vEELlYWnxZJrJEG85ni4DNhBWENETwcUmKTCzaVfsxwW oQZAf9E+AyJlSDq0jghUUOR0V21Md/lzbq9sBBac2HFjDIIwBWr3zqQv5VxwF4nwnfCk BJgkuzqUDMde8yMWs/psBvuarSCmMtU5lgNgPuI0OIyJwL1vYZf5NaRokCMJoASh8tIJ vAmGa9Oy6Q3P71gWsBpGZWEFhaToojGX3mxM7ScVcYVSQepKpibRg+oMQ3dhbgbUR31E d2kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AxIMuAf65xUDttFAgtX/y9hgYgI/2WC2s7dmySuaZaw=; b=hBNVA0PEoSsWwUdbCNRKy6ee2uk2RC6KgvQ9y1zFF9EyDK/h5Kc9UoHsaCfVQS5xm4 r4cjxIo3kDIgFpRJBf85Mle1EBaxfQbEXVmouToJT5idmJZfwc725G7YzAo8t/M+XUf9 e2qWWYGgYlLoUAxV4iBAHSQyo81YcNVn7tNKNHC5/Y5uhIMFsJ2KVCVJD/p6ZiFmOWxi jLY8/j7dTCXcjfHh9ZjifKx4eDzx2LqsqPnJeZ4XbvAA/qlRVd1JBIN1B5Zn/Se+epIZ vVst+7x0A3Bx3//0MizhDUZdIi+Ke4+L01dAgxgkVT0GFUsaE3+nnFkef2p6EVOlogwR ADdg== X-Gm-Message-State: AOAM532M9+0PWrkasmt8nLk2sp+WIY+CPXweHCfoaeh+ki8uptmiywwQ TXFTft7cEqFxWD/n+VtzEgg= X-Google-Smtp-Source: ABdhPJzQ5kX2vOw3FLXkdbvGCZTjeO3YALveizzDGimzXYeHn9NHXiyQLKsEIgkn62PatMmsz3ETNQ== X-Received: by 2002:a17:906:7709:: with SMTP id q9mr24689419ejm.123.1595937667943; Tue, 28 Jul 2020 05:01:07 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id m20sm9066959ejk.90.2020.07.28.05.01.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2020 05:01:07 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 6/9] clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs Date: Tue, 28 Jul 2020 14:00:45 +0200 Message-Id: <20200728120049.90632-7-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200728120049.90632-1-konradybcio@gmail.com> References: <20200728120049.90632-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This change adds GDSCs, resets and most of the missing clocks to the msm8994 GCC driver. The remaining ones are of local_vote_clk and gate_clk type, which are not yet supported upstream. Also reorder them to match the original downstream driver. Signed-off-by: Konrad Dybcio --- I plan on converting this to use parent_data later on, but I think we could merge it as-is for now..? drivers/clk/qcom/gcc-msm8994.c | 388 ++++++++++++++++++- include/dt-bindings/clock/qcom,gcc-msm8994.h | 36 ++ 2 files changed, 423 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index b7fc8c7ba195..144d2ba7a9be 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -20,6 +20,7 @@ #include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum { P_XO, @@ -1772,6 +1773,32 @@ static struct clk_branch gcc_gp3_clk = { }, }; +static struct clk_branch gcc_lpass_q6_axi_clk = { + .halt_reg = 0x0280, + .clkr = { + .enable_reg = 0x0280, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_lpass_q6_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_q6_bimc_axi_clk = { + .halt_reg = 0x0284, + .clkr = { + .enable_reg = 0x0284, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_mss_q6_bimc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pcie_0_aux_clk = { .halt_reg = 0x1ad4, .clkr = { @@ -1790,6 +1817,32 @@ static struct clk_branch gcc_pcie_0_aux_clk = { }, }; +static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { + .halt_reg = 0x1ad0, + .clkr = { + .enable_reg = 0x1ad0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_0_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_mstr_axi_clk = { + .halt_reg = 0x1acc, + .clkr = { + .enable_reg = 0x1acc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_0_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pcie_0_pipe_clk = { .halt_reg = 0x1ad8, .halt_check = BRANCH_HALT_DELAY, @@ -1809,6 +1862,20 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { }, }; +static struct clk_branch gcc_pcie_0_slv_axi_clk = { + .halt_reg = 0x1ac8, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1ac8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_0_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pcie_1_aux_clk = { .halt_reg = 0x1b54, .clkr = { @@ -1827,6 +1894,32 @@ static struct clk_branch gcc_pcie_1_aux_clk = { }, }; +static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { + .halt_reg = 0x1b54, + .clkr = { + .enable_reg = 0x1b54, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_1_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_mstr_axi_clk = { + .halt_reg = 0x1b50, + .clkr = { + .enable_reg = 0x1b50, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_1_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pcie_1_pipe_clk = { .halt_reg = 0x1b58, .halt_check = BRANCH_HALT_DELAY, @@ -1846,6 +1939,19 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { }, }; +static struct clk_branch gcc_pcie_1_slv_axi_clk = { + .halt_reg = 0x1b48, + .clkr = { + .enable_reg = 0x1b48, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pcie_1_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_pdm2_clk = { .halt_reg = 0x0ccc, .clkr = { @@ -1864,6 +1970,19 @@ static struct clk_branch gcc_pdm2_clk = { }, }; +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x0cc4, + .clkr = { + .enable_reg = 0x0cc4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_sdcc1_apps_clk = { .halt_reg = 0x04c4, .clkr = { @@ -1899,6 +2018,23 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { }, }; +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x0508, + .clkr = { + .enable_reg = 0x0508, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_sdcc2_ahb_clk", + .parent_names = (const char *[]){ + "periph_noc_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_sdcc2_apps_clk = { .halt_reg = 0x0504, .clkr = { @@ -1917,6 +2053,23 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; +static struct clk_branch gcc_sdcc3_ahb_clk = { + .halt_reg = 0x0548, + .clkr = { + .enable_reg = 0x0548, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_sdcc3_ahb_clk", + .parent_names = (const char *[]){ + "periph_noc_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_sdcc3_apps_clk = { .halt_reg = 0x0544, .clkr = { @@ -1935,6 +2088,23 @@ static struct clk_branch gcc_sdcc3_apps_clk = { }, }; +static struct clk_branch gcc_sdcc4_ahb_clk = { + .halt_reg = 0x0588, + .clkr = { + .enable_reg = 0x0588, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_sdcc4_ahb_clk", + .parent_names = (const char *[]){ + "periph_noc_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_sdcc4_apps_clk = { .halt_reg = 0x0584, .clkr = { @@ -1989,6 +2159,19 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = { }, }; +static struct clk_branch gcc_tsif_ahb_clk = { + .halt_reg = 0x0d84, + .clkr = { + .enable_reg = 0x0d84, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_tsif_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_tsif_ref_clk = { .halt_reg = 0x0d88, .clkr = { @@ -2007,6 +2190,19 @@ static struct clk_branch gcc_tsif_ref_clk = { }, }; +static struct clk_branch gcc_ufs_ahb_clk = { + .halt_reg = 0x1d4c, + .clkr = { + .enable_reg = 0x1d4c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_axi_clk = { .halt_reg = 0x1d48, .clkr = { @@ -2043,6 +2239,34 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = { }, }; +static struct clk_branch gcc_ufs_rx_symbol_0_clk = { + .halt_reg = 0x1d60, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1d60, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_rx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_rx_symbol_1_clk = { + .halt_reg = 0x1d64, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1d64, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_rx_symbol_1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_tx_cfg_clk = { .halt_reg = 0x1d50, .clkr = { @@ -2061,6 +2285,47 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = { }, }; +static struct clk_branch gcc_ufs_tx_symbol_0_clk = { + .halt_reg = 0x1d58, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1d58, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_tx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_tx_symbol_1_clk = { + .halt_reg = 0x1d5c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1d5c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_ufs_tx_symbol_1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb2_hs_phy_sleep_clk = { + .halt_reg = 0x04ac, + .clkr = { + .enable_reg = 0x04ac, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_usb2_hs_phy_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_usb30_master_clk = { .halt_reg = 0x03c8, .clkr = { @@ -2097,6 +2362,19 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = { }, }; +static struct clk_branch gcc_usb30_sleep_clk = { + .halt_reg = 0x03cc, + .clkr = { + .enable_reg = 0x03cc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_usb30_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_usb3_phy_aux_clk = { .halt_reg = 0x1408, .clkr = { @@ -2115,6 +2393,19 @@ static struct clk_branch gcc_usb3_phy_aux_clk = { }, }; +static struct clk_branch gcc_usb_hs_ahb_clk = { + .halt_reg = 0x0488, + .clkr = { + .enable_reg = 0x0488, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_usb_hs_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_usb_hs_system_clk = { .halt_reg = 0x0484, .clkr = { @@ -2133,6 +2424,59 @@ static struct clk_branch gcc_usb_hs_system_clk = { }, }; +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { + .halt_reg = 0x1a84, + .clkr = { + .enable_reg = 0x1a84, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data) + { + .name = "gcc_usb_phy_cfg_ahb2phy_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc pcie_gdsc = { + .gdscr = 0x1e18, + .pd = { + .name = "pcie", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc pcie_0_gdsc = { + .gdscr = 0x1ac4, + .pd = { + .name = "pcie_0", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc pcie_1_gdsc = { + .gdscr = 0x1b44, + .pd = { + .name = "pcie_1", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_gdsc = { + .gdscr = 0x3c4, + .pd = { + .name = "usb30", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc ufs_gdsc = { + .gdscr = 0x1d44, + .pd = { + .name = "ufs", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_msm8994_clocks[] = { [GPLL0_EARLY] = &gpll0_early.clkr, [GPLL0] = &gpll0.clkr, @@ -2233,26 +2577,64 @@ static struct clk_regmap *gcc_msm8994_clocks[] = { [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, + [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, + [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, + [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, + [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, + [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, + [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, + [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, - [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, + [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, + [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr, + [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, + [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr, + [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, + [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr, + [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr, [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, + [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, + [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, + [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, +}; + +static struct gdsc *gcc_msm8994_gdscs[] = { + [PCIE_GDSC] = &pcie_gdsc, + [PCIE_0_GDSC] = &pcie_0_gdsc, + [PCIE_1_GDSC] = &pcie_1_gdsc, + [USB30_GDSC] = &usb30_gdsc, + [UFS_GDSC] = &ufs_gdsc, +}; + +static const struct qcom_reset_map gcc_msm8994_resets[] = { + [USB3_PHY_RESET] = { 0x1400 }, + [USB3PHY_PHY_RESET] = { 0x1404 }, + [PCIE_PHY_0_RESET] = { 0x1b18 }, + [PCIE_PHY_1_RESET] = { 0x1b98 }, + [QUSB2_PHY_RESET] = { 0x04b8 }, }; static const struct regmap_config gcc_msm8994_regmap_config = { @@ -2267,6 +2649,10 @@ static const struct qcom_cc_desc gcc_msm8994_desc = { .config = &gcc_msm8994_regmap_config, .clks = gcc_msm8994_clocks, .num_clks = ARRAY_SIZE(gcc_msm8994_clocks), + .resets = gcc_msm8994_resets, + .num_resets = ARRAY_SIZE(gcc_msm8994_resets), + .gdscs = gcc_msm8994_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs), }; static const struct of_device_id gcc_msm8994_match_table[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h index 938969309e00..507b8d6effd2 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8994.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h @@ -126,5 +126,41 @@ #define GCC_USB3_PHY_AUX_CLK 116 #define GCC_USB_HS_SYSTEM_CLK 117 #define GCC_SDCC1_AHB_CLK 118 +#define GCC_LPASS_Q6_AXI_CLK 119 +#define GCC_MSS_Q6_BIMC_AXI_CLK 120 +#define GCC_PCIE_0_CFG_AHB_CLK 121 +#define GCC_PCIE_0_MSTR_AXI_CLK 122 +#define GCC_PCIE_0_SLV_AXI_CLK 123 +#define GCC_PCIE_1_CFG_AHB_CLK 124 +#define GCC_PCIE_1_MSTR_AXI_CLK 125 +#define GCC_PCIE_1_SLV_AXI_CLK 126 +#define GCC_PDM_AHB_CLK 127 +#define GCC_SDCC2_AHB_CLK 128 +#define GCC_SDCC3_AHB_CLK 129 +#define GCC_SDCC4_AHB_CLK 130 +#define GCC_TSIF_AHB_CLK 131 +#define GCC_UFS_AHB_CLK 132 +#define GCC_UFS_RX_SYMBOL_0_CLK 133 +#define GCC_UFS_RX_SYMBOL_1_CLK 134 +#define GCC_UFS_TX_SYMBOL_0_CLK 135 +#define GCC_UFS_TX_SYMBOL_1_CLK 136 +#define GCC_USB2_HS_PHY_SLEEP_CLK 137 +#define GCC_USB30_SLEEP_CLK 138 +#define GCC_USB_HS_AHB_CLK 139 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 140 + +/* GDSCs */ +#define PCIE_GDSC 0 +#define PCIE_0_GDSC 1 +#define PCIE_1_GDSC 2 +#define USB30_GDSC 3 +#define UFS_GDSC 4 + +/* Resets */ +#define USB3_PHY_RESET 0 +#define USB3PHY_PHY_RESET 1 +#define PCIE_PHY_0_RESET 2 +#define PCIE_PHY_1_RESET 3 +#define QUSB2_PHY_RESET 4 #endif From patchwork Tue Jul 28 12:00:46 2020 Content-Type: text/plain; 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[83.6.167.207]) by smtp.googlemail.com with ESMTPSA id m20sm9066959ejk.90.2020.07.28.05.01.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2020 05:01:09 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 7/9] arm64: dts: qcom: kitakami: Add Synaptics touchscreen Date: Tue, 28 Jul 2020 14:00:46 +0200 Message-Id: <20200728120049.90632-8-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200728120049.90632-1-konradybcio@gmail.com> References: <20200728120049.90632-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org All Kitakami devices seem to use the Synaptics RMI4 touchscreen attached to the same i2c bus. Configure and enable it. Signed-off-by: Konrad Dybcio --- .../qcom/msm8994-sony-xperia-kitakami.dtsi | 45 ++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 4032b7478f04..696cd39852f4 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -138,7 +138,34 @@ &blsp_i2c5 { &blsp_i2c6 { status = "okay"; - /* Synaptics touchscreen */ + rmi4-i2c-dev@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <42 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + + vdd-supply = <&pm8994_l22>; + vio-supply = <&pm8994_s4>; + + syna,reset-delay-ms = <220>; + syna,startup-delay-ms = <220>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + }; + }; }; &blsp1_uart2 { @@ -233,3 +260,19 @@ &sdhc1 { * vqmmc-supply = <&pm8994_s4>; */ }; + +&tlmm { + ts_int_active: ts-int-active { + pins = "gpio42"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + ts_reset_active: ts-reset-active { + pins = "gpio109"; + drive-strength = <2>; + bias-disable; + output-low; + }; +}; From patchwork Tue Jul 28 12:00:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11689027 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C4D7614DD for ; Tue, 28 Jul 2020 12:01:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AB5A8206D7 for ; Tue, 28 Jul 2020 12:01:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="seTbJ4DV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729413AbgG1MBh (ORCPT ); Tue, 28 Jul 2020 08:01:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728561AbgG1MBP (ORCPT ); Tue, 28 Jul 2020 08:01:15 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8211AC061794; Tue, 28 Jul 2020 05:01:15 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id z17so14575479edr.9; Tue, 28 Jul 2020 05:01:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/lXxR/NY5u0DlFOjxBacWTF69g+Zu3unhXyQAhYQnSE=; b=seTbJ4DV+V6KNulh2RG4Eue7x9j0lC0LmTz/F7K3QzpMEeGi0cF+huT6e/p3tC36rR 1cpGVbpGXytvL4Yj3oZE0l6EsWSQJfFC2j/YLBkVEBx3MjDLrf5NA9onyV0xsscDGj4r 8vA+uFR5lFfE3ab0AxarhOEg8KQcB94EW2W7kZ7EI5Qw4kXotNrnjYi1OKlm4NfwvU63 aeyyQjKFoZZEMJwedwf8c3RHTReSKSTkYyh+AsZewa2TFbDtILPRMdOF9MfcrvLaYuSG m4xLFcFo6TPDrTp6IY5Ur6tSJilNoIT+l1K4PzVWUaG34q/o9/h+83tdXtOC5V9jgOF+ R11A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/lXxR/NY5u0DlFOjxBacWTF69g+Zu3unhXyQAhYQnSE=; b=N2CniasuBL8XC4MFCVBvNdEtWis8o2+SRBFoBQAUHZ/hvSRTPzkWzw3qcsl61PCicg QGiYlsGG2AhW2RUiaUyJHJxq5Lfv6NaGr/L7rId2PLsWLcEM34lA1146l94BV1oHJJ2a SYiNKerehrZS+3ZU+sp++no84wQ+GWfS0lw5Il7MMx6ml3TXSWbcJ3s1vZz4uE1MBzYh ho1g2/qcrhaIo9M19JwxtGLT9gV62pGUnIdHwsocqu4ebMMvHJVacIlpq2XrGri7uyIw BwGwplkl5Hooq+X4sfV4qzRr8jTvUkH5vgb/4WYcNq5TFv3xyMpkUhp1uzscN/nkGTC5 dAdw== X-Gm-Message-State: AOAM5316+Qz3O2j+sCiZdtCpwXsMJqF77uaMDnpPa1h7JYvIZBckK86o wjlHAb01njUPY03HJMComcs= X-Google-Smtp-Source: ABdhPJwdLg1+fyHCsAbEt9grpZefQKn8cJqncGT0WM4xgb00xnJWNKOn1P6Ozu4L/VdD2y3scmeLbg== X-Received: by 2002:a05:6402:c86:: with SMTP id cm6mr8022220edb.205.1595937672297; Tue, 28 Jul 2020 05:01:12 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id m20sm9066959ejk.90.2020.07.28.05.01.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2020 05:01:11 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 8/9] arm64: dts: qcom: msm8994: Add SDHCI2 node Date: Tue, 28 Jul 2020 14:00:47 +0200 Message-Id: <20200728120049.90632-9-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200728120049.90632-1-konradybcio@gmail.com> References: <20200728120049.90632-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add SDHCI2 to enable use of uSD cards on msm8994. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 69c99a4cd817..58fc8b0321c3 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -336,6 +336,28 @@ sdhc1: sdhci@f9824900 { status = "disabled"; }; + sdhc2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + bus-width = <4>; + status = "disabled"; + }; + blsp1_dma: dma@f9904000 { compatible = "qcom,bam-v1.7.0"; reg = <0xf9904000 0x19000>; @@ -714,6 +736,42 @@ sdc1_rclk_off: rclk-off { pins = "sdc1_rclk"; bias-pull-down; }; + + sdc2_clk_on: sdc2-clk-on { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <10>; + }; + + sdc2_clk_off: sdc2-clk-off { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_data_on: sdc2-data-on { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_data_off: sdc2-data-off { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; }; }; From patchwork Tue Jul 28 12:00:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11689031 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2852914DD for ; Tue, 28 Jul 2020 12:01:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0FFBD206D8 for ; Tue, 28 Jul 2020 12:01:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lsigjsbc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729387AbgG1MBh (ORCPT ); Tue, 28 Jul 2020 08:01:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729375AbgG1MBQ (ORCPT ); Tue, 28 Jul 2020 08:01:16 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD82BC0619D2; Tue, 28 Jul 2020 05:01:15 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id dk23so8490045ejb.11; Tue, 28 Jul 2020 05:01:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3xVG670XkylcieeabI4BfFgFxbC/3cUWewC6wtfaP/Y=; b=lsigjsbcLg4U0fz2DXXJx6Dx+9kRltx8Q3OJh91jCAowBbFWJ66z7d6Ix651wJndte phN2g7QbZsy7xyqCeea088Lo5Q3ER78cU0gPdo/FWYfRKKcWSoG8eRjcl3jJZc63OkAv ByonmGBlh1OkelbbArUgZM9YYcCIjlRb0swiaDUG++flRzoUKqVdMSsFBY3Z4S7D+O9R oYde/E3lxnG9o6I2nCli3NP4vAgVbKpvEJKgZ8QnmibB9141v0Gw3UtWV4wI0X1QIPgb 3n0NVGj0jlXVLvtyrnWA6p0DlFwmxCOsYfcpy+6yXrlAgedKefXV072QIJjeAk6xu/nP cjoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3xVG670XkylcieeabI4BfFgFxbC/3cUWewC6wtfaP/Y=; b=T6Z/fPPfziYhlNp4MVIY9UWlzUqpwYCm+z03+H3xQKVMkCzXffHR6RZjpl1nEk/frf 4IhrVNAXzAo+u4p8fb7LxpmpY8H4A3qFdI2XC8gVtnoWBIx5UR5VP5FeUZkz9W5ST/XB 52cAvsDUg8ynvTlz6hibdjWt/6l4GbvvSrcN6GD2fMqaRTtLtHLPWM7pVmjZy5eo+Lqh /P8AM8dKQYh2Dt4HXW2ZQH1ZdkFkRyf7Y7y1Nkv8uQb7xQRW4xfae9dZrHZCCZrINjFM kMIZd3doK27uEaf7IUSYuVGGYuPzkjRC/L7JjqfnX+rRiYS//3tenJEH3MqXfVB7TkQo WjUg== X-Gm-Message-State: AOAM5302dZ9Ab+Lk0QcuA2WNyZzZKH0gJegzu4bZYZILIFvH1zg8AQPX FVoLr3d4IiBF+xOk3FLVYERS7ZxOROA= X-Google-Smtp-Source: ABdhPJzjg/8EY4mfnf/6DLLQKoIP4Iig8B48JFS1ys9qasBiMgYlTjXxbuVtY01YIiaWgRl/1jOSCA== X-Received: by 2002:a17:906:12cd:: with SMTP id l13mr18816915ejb.385.1595937674557; Tue, 28 Jul 2020 05:01:14 -0700 (PDT) Received: from localhost.localdomain (abad207.neoplus.adsl.tpnet.pl. [83.6.167.207]) by smtp.googlemail.com with ESMTPSA id m20sm9066959ejk.90.2020.07.28.05.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2020 05:01:14 -0700 (PDT) From: Konrad Dybcio To: konradybcio@gmail.com Cc: lauren.kelly@msn.com, Andy Gross , Bjorn Andersson , Rob Herring , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 9/9] arm64: dts: qcom: kitakami: Enable SDHCI2 Date: Tue, 28 Jul 2020 14:00:48 +0200 Message-Id: <20200728120049.90632-10-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200728120049.90632-1-konradybcio@gmail.com> References: <20200728120049.90632-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This enables the use of uSD cards. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 696cd39852f4..806e8ee00833 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -261,6 +261,10 @@ &sdhc1 { */ }; +&sdhc2 { + status = "okay"; +}; + &tlmm { ts_int_active: ts-int-active { pins = "gpio42";