From patchwork Wed Jul 29 06:30:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11690397 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F2B7C913 for ; Wed, 29 Jul 2020 06:31:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DAAD62076E for ; Wed, 29 Jul 2020 06:31:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="XiA3lQ2V" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726967AbgG2Gb1 (ORCPT ); Wed, 29 Jul 2020 02:31:27 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:52502 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726536AbgG2Gb1 (ORCPT ); Wed, 29 Jul 2020 02:31:27 -0400 X-UUID: 78c909727ed44807ad8c0b35ae1d9a81-20200729 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=W/S6wlW6rlHVWCPQFOfmo+0Q+i9GqsM92xqbMY9UD7Y=; b=XiA3lQ2VNHXC7L8u6I6yRaAIXNZvYhck9RwyFqLJEOQTqSaq/SeXbrVeCTJgfWCewoQCpOxN/btbPAuX5/CmpchotL3R/5qE3o9PQi20wDn4CMJY/2Tc22wErB2rwe6dw6qweOEUpZbhBlgbnyRMp7UxOeDvDkuylceE23Gbswg=; X-UUID: 78c909727ed44807ad8c0b35ae1d9a81-20200729 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 322846917; Wed, 29 Jul 2020 14:31:22 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 29 Jul 2020 14:31:20 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 29 Jul 2020 14:31:20 +0800 From: Crystal Guo To: , , CC: , , , , , , , Crystal Guo Subject: [v2,1/3] dt-bindings: watchdog: modify description for mt2712 and mt8183 Date: Wed, 29 Jul 2020 14:30:47 +0800 Message-ID: <1596004249-28655-2-git-send-email-crystal.guo@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596004249-28655-1-git-send-email-crystal.guo@mediatek.com> References: <1596004249-28655-1-git-send-email-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Besides watchdog, mt2712 and mt8183 also provide sub-system software reset features. But mt6589 not support this feature. Signed-off-by: Crystal Guo --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 4dd36bd..45eedc2 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -4,13 +4,13 @@ Required properties: - compatible should contain: "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 - "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712 + "mediatek,mt2712-wdt": for MT2712 "mediatek,mt6589-wdt": for MT6589 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623 "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 - "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183 + "mediatek,mt8183-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 - reg : Specifies base physical address and size of the registers. From patchwork Wed Jul 29 06:30:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11690393 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5A0DE14DD for ; Wed, 29 Jul 2020 06:31:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3F00B20825 for ; Wed, 29 Jul 2020 06:31:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Mld/gkse" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727007AbgG2Gba (ORCPT ); Wed, 29 Jul 2020 02:31:30 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:52502 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726816AbgG2Gb2 (ORCPT ); Wed, 29 Jul 2020 02:31:28 -0400 X-UUID: 5b1173f6ff6345429c19a9826aab50cc-20200729 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=8tvvtJkUNQwkHhqk8KQuaR8AggmTBYNhX5fZW/pno7U=; b=Mld/gkseXutwsk6fiVrO3dzsUzOhHWWKvByj+bkeBeKg5sIRuwoyzoHmPm+2lsylpi/ERzwLz/FBnwQmiBppaNj+mEL0TqtexereCe9dB/TbjOFDiSqmGHVEhTfqKpHa1YXxhYssFrjKzSFyu/Shb1WdTXn44Y+DthwVUynk4QE=; X-UUID: 5b1173f6ff6345429c19a9826aab50cc-20200729 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 258468352; Wed, 29 Jul 2020 14:31:22 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 29 Jul 2020 14:31:20 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 29 Jul 2020 14:31:21 +0800 From: Crystal Guo To: , , CC: , , , , , , , Crystal Guo Subject: [v2,2/3] dt-bindings: watchdog: add a new head file for toprgu reset-controllers Date: Wed, 29 Jul 2020 14:30:48 +0800 Message-ID: <1596004249-28655-3-git-send-email-crystal.guo@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596004249-28655-1-git-send-email-crystal.guo@mediatek.com> References: <1596004249-28655-1-git-send-email-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org merge all the reset numbers in one head file. Signed-off-by: Crystal Guo --- include/dt-bindings/reset-controller/mtk-resets.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mtk-resets.h diff --git a/include/dt-bindings/reset-controller/mtk-resets.h b/include/dt-bindings/reset-controller/mtk-resets.h new file mode 100644 index 0000000..d73a4ba --- /dev/null +++ b/include/dt-bindings/reset-controller/mtk-resets.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Mediatek Inc. + * + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MTK +#define _DT_BINDINGS_RESET_CONTROLLER_MTK + +#define MT2712_TOPRGU_SW_RST_NUM 11 +#define MT8183_TOPRGU_SW_RST_NUM 19 + +#endif From patchwork Wed Jul 29 06:30:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11690395 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A519E913 for ; Wed, 29 Jul 2020 06:31:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8C5CD206D7 for ; Wed, 29 Jul 2020 06:31:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ujOkxuaa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727047AbgG2Gbd (ORCPT ); Wed, 29 Jul 2020 02:31:33 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:43381 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726548AbgG2Gb2 (ORCPT ); Wed, 29 Jul 2020 02:31:28 -0400 X-UUID: 0ea0ecdcaa5c4cd89c68df2938baf999-20200729 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BdJ2r7/FoQTlh/kyQIChiopClhLjq/Zo9T1MCUvBGSY=; b=ujOkxuaaFzS5pxa5T+ahY3/pNAxY5y5qTy8w0N2AZfsgIo+Dmftp3b5zXPrb4dCzuYlrN/HejxVlEz3E4GQaY/XXwGDTrN6Rxqb1JkA/wlL/GbK+QY0TCZZP611nBDg1+DwiRmv/0h5W+96erCDHFZaqGEPndL+fN0utH1mhZko=; X-UUID: 0ea0ecdcaa5c4cd89c68df2938baf999-20200729 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 370366815; Wed, 29 Jul 2020 14:31:22 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 29 Jul 2020 14:31:21 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 29 Jul 2020 14:31:22 +0800 From: Crystal Guo To: , , CC: , , , , , , , Crystal Guo Subject: [v3,3/3] watchdog: mtk_wdt: merge all the reset numbers in one head file Date: Wed, 29 Jul 2020 14:30:49 +0800 Message-ID: <1596004249-28655-4-git-send-email-crystal.guo@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596004249-28655-1-git-send-email-crystal.guo@mediatek.com> References: <1596004249-28655-1-git-send-email-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org mt8xxx-resets.h actually just used to define TOPRGU_SW_RST_NUM. Instead of resubmit a new mt8xxx-reset.h for a new IC, merge all the reset numbers in one head file. Signed-off-by: Crystal Guo --- drivers/watchdog/mtk_wdt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index d6a6393..5000a49 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -9,8 +9,7 @@ * Based on sunxi_wdt.c */ -#include -#include +#include #include #include #include