From patchwork Wed Jul 29 06:47:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gautham R Shenoy X-Patchwork-Id: 11690417 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 57110913 for ; Wed, 29 Jul 2020 06:47:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4406122BF5 for ; Wed, 29 Jul 2020 06:47:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727080AbgG2Grx (ORCPT ); Wed, 29 Jul 2020 02:47:53 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:1980 "EHLO mx0b-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727069AbgG2Grw (ORCPT ); Wed, 29 Jul 2020 02:47:52 -0400 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06T6UqJx081895; Wed, 29 Jul 2020 02:47:47 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 32jqrsk7jb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Jul 2020 02:47:47 -0400 Received: from m0098421.ppops.net (m0098421.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 06T6VHE2083671; Wed, 29 Jul 2020 02:47:46 -0400 Received: from ppma02dal.us.ibm.com (a.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.10]) by mx0a-001b2d01.pphosted.com with ESMTP id 32jqrsk7hp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Jul 2020 02:47:46 -0400 Received: from pps.filterd (ppma02dal.us.ibm.com [127.0.0.1]) by ppma02dal.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 06T6UdlF004560; Wed, 29 Jul 2020 06:47:46 GMT Received: from b01cxnp22033.gho.pok.ibm.com (b01cxnp22033.gho.pok.ibm.com [9.57.198.23]) by ppma02dal.us.ibm.com with ESMTP id 32gcy4fhd7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Jul 2020 06:47:46 +0000 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 06T6ljld56492374 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 Jul 2020 06:47:45 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 53BC2B2065; Wed, 29 Jul 2020 06:47:45 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F2E07B205F; Wed, 29 Jul 2020 06:47:44 +0000 (GMT) Received: from sofia.ibm.com (unknown [9.85.85.173]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 29 Jul 2020 06:47:44 +0000 (GMT) Received: by sofia.ibm.com (Postfix, from userid 1000) id 9CEF82E2FB8; Wed, 29 Jul 2020 12:17:39 +0530 (IST) From: "Gautham R. Shenoy" To: Nicholas Piggin , Anton Blanchard , Nathan Lynch , Michael Ellerman , Michael Neuling , Vaidyanathan Srinivasan Cc: linuxppc-dev@ozlabs.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, "Gautham R. Shenoy" Subject: [PATCH v2 1/3] cpuidle-pseries: Set the latency-hint before entering CEDE Date: Wed, 29 Jul 2020 12:17:32 +0530 Message-Id: <1596005254-25753-2-git-send-email-ego@linux.vnet.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1596005254-25753-1-git-send-email-ego@linux.vnet.ibm.com> References: <1596005254-25753-1-git-send-email-ego@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-29_02:2020-07-28,2020-07-29 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=821 bulkscore=0 spamscore=0 adultscore=0 impostorscore=0 suspectscore=0 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007290041 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: "Gautham R. Shenoy" As per the PAPR, each H_CEDE call is associated with a latency-hint to be passed in the VPA field "cede_latency_hint". The CEDE states that we were implicitly entering so far is CEDE with latency-hint = 0. This patch explicitly sets the latency hint corresponding to the CEDE state that we are currently entering. While at it, we save the previous hint, to be restored once we wakeup from CEDE. This will be required in the future when we expose extended-cede states through the cpuidle framework, where each of them will have a different cede-latency hint. Reviewed-by: Vaidyanathan Srinivasan Signed-off-by: Gautham R. Shenoy --- drivers/cpuidle/cpuidle-pseries.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/cpuidle/cpuidle-pseries.c b/drivers/cpuidle/cpuidle-pseries.c index 3e058ad2..88e71c3 100644 --- a/drivers/cpuidle/cpuidle-pseries.c +++ b/drivers/cpuidle/cpuidle-pseries.c @@ -86,19 +86,27 @@ static void check_and_cede_processor(void) } } +#define NR_CEDE_STATES 1 /* CEDE with latency-hint 0 */ +#define NR_DEDICATED_STATES (NR_CEDE_STATES + 1) /* Includes snooze */ + +u8 cede_latency_hint[NR_DEDICATED_STATES]; static int dedicated_cede_loop(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { + u8 old_latency_hint; pseries_idle_prolog(); get_lppaca()->donate_dedicated_cpu = 1; + old_latency_hint = get_lppaca()->cede_latency_hint; + get_lppaca()->cede_latency_hint = cede_latency_hint[index]; HMT_medium(); check_and_cede_processor(); local_irq_disable(); get_lppaca()->donate_dedicated_cpu = 0; + get_lppaca()->cede_latency_hint = old_latency_hint; pseries_idle_epilog(); @@ -130,7 +138,7 @@ static int shared_cede_loop(struct cpuidle_device *dev, /* * States for dedicated partition case. */ -static struct cpuidle_state dedicated_states[] = { +static struct cpuidle_state dedicated_states[NR_DEDICATED_STATES] = { { /* Snooze */ .name = "snooze", .desc = "snooze", From patchwork Wed Jul 29 06:47:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gautham R Shenoy X-Patchwork-Id: 11690415 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 987FA913 for ; Wed, 29 Jul 2020 06:47:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 83AFD20838 for ; Wed, 29 Jul 2020 06:47:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727058AbgG2Grv (ORCPT ); Wed, 29 Jul 2020 02:47:51 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:64048 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726367AbgG2Grv (ORCPT ); Wed, 29 Jul 2020 02:47:51 -0400 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06T6WBgB109475; Wed, 29 Jul 2020 02:47:48 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 32jp1meruj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Jul 2020 02:47:48 -0400 Received: from m0098399.ppops.net (m0098399.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 06T6f9a3135796; Wed, 29 Jul 2020 02:47:47 -0400 Received: from ppma04dal.us.ibm.com (7a.29.35a9.ip4.static.sl-reverse.com [169.53.41.122]) by mx0a-001b2d01.pphosted.com with ESMTP id 32jp1meru6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Jul 2020 02:47:47 -0400 Received: from pps.filterd (ppma04dal.us.ibm.com [127.0.0.1]) by ppma04dal.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 06T6UML0029829; Wed, 29 Jul 2020 06:47:46 GMT Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by ppma04dal.us.ibm.com with ESMTP id 32gcq1fjea-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Jul 2020 06:47:46 +0000 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 06T6ljTL1245830 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 Jul 2020 06:47:45 GMT Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 743307805E; Wed, 29 Jul 2020 06:47:45 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BC01878060; Wed, 29 Jul 2020 06:47:44 +0000 (GMT) Received: from sofia.ibm.com (unknown [9.85.85.173]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 29 Jul 2020 06:47:44 +0000 (GMT) Received: by sofia.ibm.com (Postfix, from userid 1000) id A8AAC2E2FF4; Wed, 29 Jul 2020 12:17:39 +0530 (IST) From: "Gautham R. Shenoy" To: Nicholas Piggin , Anton Blanchard , Nathan Lynch , Michael Ellerman , Michael Neuling , Vaidyanathan Srinivasan Cc: linuxppc-dev@ozlabs.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, "Gautham R. Shenoy" Subject: [PATCH v2 2/3] cpuidle-pseries: Add function to parse extended CEDE records Date: Wed, 29 Jul 2020 12:17:33 +0530 Message-Id: <1596005254-25753-3-git-send-email-ego@linux.vnet.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1596005254-25753-1-git-send-email-ego@linux.vnet.ibm.com> References: <1596005254-25753-1-git-send-email-ego@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-29_02:2020-07-28,2020-07-29 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 phishscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007290041 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: "Gautham R. Shenoy" Currently we use CEDE with latency-hint 0 as the only other idle state on a dedicated LPAR apart from the polling "snooze" state. The platform might support additional extended CEDE idle states, which can be discovered through the "ibm,get-system-parameter" rtas-call made with CEDE_LATENCY_TOKEN. This patch adds a function to obtain information about the extended CEDE idle states from the platform and parse the contents to populate an array of extended CEDE states. These idle states thus discovered will be added to the cpuidle framework in the next patch. dmesg on a POWER9 LPAR, demonstrating the output of parsing the extended CEDE latency parameters. [ 5.913180] xcede : xcede_record_size = 10 [ 5.913183] xcede : Record 0 : hint = 1, latency =0x400 tb-ticks, Wake-on-irq = 1 [ 5.913188] xcede : Record 1 : hint = 2, latency =0x3e8000 tb-ticks, Wake-on-irq = 0 [ 5.913193] cpuidle : Skipping the 2 Extended CEDE idle states Reviewed-by: Vaidyanathan Srinivasan Signed-off-by: Gautham R. Shenoy --- drivers/cpuidle/cpuidle-pseries.c | 129 +++++++++++++++++++++++++++++++++++++- 1 file changed, 127 insertions(+), 2 deletions(-) diff --git a/drivers/cpuidle/cpuidle-pseries.c b/drivers/cpuidle/cpuidle-pseries.c index 88e71c3..b1dc24d 100644 --- a/drivers/cpuidle/cpuidle-pseries.c +++ b/drivers/cpuidle/cpuidle-pseries.c @@ -21,6 +21,7 @@ #include #include #include +#include static struct cpuidle_driver pseries_idle_driver = { .name = "pseries_idle", @@ -86,9 +87,120 @@ static void check_and_cede_processor(void) } } -#define NR_CEDE_STATES 1 /* CEDE with latency-hint 0 */ +struct xcede_latency_records { + u8 latency_hint; + u64 wakeup_latency_tb_ticks; + u8 responsive_to_irqs; +}; + +/* + * XCEDE : Extended CEDE states discovered through the + * "ibm,get-systems-parameter" rtas-call with the token + * CEDE_LATENCY_TOKEN + */ +#define MAX_XCEDE_STATES 4 +#define XCEDE_LATENCY_RECORD_SIZE 10 +#define XCEDE_LATENCY_PARAM_MAX_LENGTH (2 + 2 + \ + (MAX_XCEDE_STATES * XCEDE_LATENCY_RECORD_SIZE)) + +#define CEDE_LATENCY_TOKEN 45 + +#define NR_CEDE_STATES (MAX_XCEDE_STATES + 1) /* CEDE with latency-hint 0 */ #define NR_DEDICATED_STATES (NR_CEDE_STATES + 1) /* Includes snooze */ +struct xcede_latency_records xcede_records[MAX_XCEDE_STATES]; +unsigned int nr_xcede_records; +char xcede_parameters[XCEDE_LATENCY_PARAM_MAX_LENGTH]; + +static int parse_cede_parameters(void) +{ + int ret = -1, i; + u16 payload_length; + u8 xcede_record_size; + u32 total_xcede_records_size; + char *payload; + + memset(xcede_parameters, 0, XCEDE_LATENCY_PARAM_MAX_LENGTH); + + ret = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1, + NULL, CEDE_LATENCY_TOKEN, __pa(xcede_parameters), + XCEDE_LATENCY_PARAM_MAX_LENGTH); + + if (ret) { + pr_err("xcede: Error parsing CEDE_LATENCY_TOKEN\n"); + return ret; + } + + payload_length = be16_to_cpu(*(__be16 *)(&xcede_parameters[0])); + payload = &xcede_parameters[2]; + + /* + * If the platform supports the cede latency settings + * information system parameter it must provide the following + * information in the NULL terminated parameter string: + * + * a. The first byte is the length “N” of each cede + * latency setting record minus one (zero indicates a length + * of 1 byte). + * + * b. For each supported cede latency setting a cede latency + * setting record consisting of the first “N” bytes as per + * the following table. + * + * ----------------------------- + * | Field | Field | + * | Name | Length | + * ----------------------------- + * | Cede Latency | 1 Byte | + * | Specifier Value | | + * ----------------------------- + * | Maximum wakeup | | + * | latency in | 8 Bytes| + * | tb-ticks | | + * ----------------------------- + * | Responsive to | | + * | external | 1 Byte | + * | interrupts | | + * ----------------------------- + * + * This version has cede latency record size = 10. + */ + xcede_record_size = (u8)payload[0] + 1; + + if (xcede_record_size != XCEDE_LATENCY_RECORD_SIZE) { + pr_err("xcede : Expected record-size %d. Observed size %d.\n", + XCEDE_LATENCY_RECORD_SIZE, xcede_record_size); + return -EINVAL; + } + + pr_info("xcede : xcede_record_size = %d\n", xcede_record_size); + + /* + * Since the payload_length includes the last NULL byte and + * the xcede_record_size, the remaining bytes correspond to + * array of all cede_latency settings. + */ + total_xcede_records_size = payload_length - 2; + nr_xcede_records = total_xcede_records_size / xcede_record_size; + + payload++; + for (i = 0; i < nr_xcede_records; i++) { + struct xcede_latency_records *record = &xcede_records[i]; + + record->latency_hint = (u8)payload[0]; + record->wakeup_latency_tb_ticks = + be64_to_cpu(*(__be64 *)(&payload[1])); + record->responsive_to_irqs = (u8)payload[9]; + payload += xcede_record_size; + pr_info("xcede : Record %d : hint = %u, latency =0x%llx tb-ticks, Wake-on-irq = %u\n", + i, record->latency_hint, + record->wakeup_latency_tb_ticks, + record->responsive_to_irqs); + } + + return 0; +} + u8 cede_latency_hint[NR_DEDICATED_STATES]; static int dedicated_cede_loop(struct cpuidle_device *dev, struct cpuidle_driver *drv, @@ -219,6 +331,19 @@ static int pseries_cpuidle_driver_init(void) return 0; } +static int add_pseries_idle_states(void) +{ + int nr_states = 2; /* By default we have snooze, CEDE */ + + if (parse_cede_parameters()) + return nr_states; + + pr_info("cpuidle : Skipping the %d Extended CEDE idle states\n", + nr_xcede_records); + + return nr_states; +} + /* * pseries_idle_probe() * Choose state table for shared versus dedicated partition @@ -241,7 +366,7 @@ static int pseries_idle_probe(void) max_idle_state = ARRAY_SIZE(shared_states); } else { cpuidle_state_table = dedicated_states; - max_idle_state = ARRAY_SIZE(dedicated_states); + max_idle_state = add_pseries_idle_states(); } } else return -ENODEV; From patchwork Wed Jul 29 06:47:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gautham R Shenoy X-Patchwork-Id: 11690421 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 879C313B6 for ; Wed, 29 Jul 2020 06:48:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 78C882084D for ; Wed, 29 Jul 2020 06:48:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727069AbgG2Gr5 (ORCPT ); Wed, 29 Jul 2020 02:47:57 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:5756 "EHLO mx0b-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726367AbgG2Gry (ORCPT ); Wed, 29 Jul 2020 02:47:54 -0400 Received: from pps.filterd (m0127361.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06T6WjnN140771; Wed, 29 Jul 2020 02:47:49 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 32jpwdc5uw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Jul 2020 02:47:49 -0400 Received: from m0127361.ppops.net (m0127361.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 06T6Y0Dv144223; Wed, 29 Jul 2020 02:47:48 -0400 Received: from ppma02dal.us.ibm.com (a.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.10]) by mx0a-001b2d01.pphosted.com with ESMTP id 32jpwdc5tu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Jul 2020 02:47:47 -0400 Received: from pps.filterd (ppma02dal.us.ibm.com [127.0.0.1]) by ppma02dal.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 06T6Ugl3004588; Wed, 29 Jul 2020 06:47:46 GMT Received: from b01cxnp23032.gho.pok.ibm.com (b01cxnp23032.gho.pok.ibm.com [9.57.198.27]) by ppma02dal.us.ibm.com with ESMTP id 32gcy4fhd9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Jul 2020 06:47:46 +0000 Received: from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com [9.57.199.110]) by b01cxnp23032.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 06T6ljLM44564816 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 Jul 2020 06:47:46 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DFAC7AE05F; Wed, 29 Jul 2020 06:47:45 +0000 (GMT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 40635AE060; Wed, 29 Jul 2020 06:47:45 +0000 (GMT) Received: from sofia.ibm.com (unknown [9.85.85.173]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 29 Jul 2020 06:47:45 +0000 (GMT) Received: by sofia.ibm.com (Postfix, from userid 1000) id B7D562E2FF5; Wed, 29 Jul 2020 12:17:39 +0530 (IST) From: "Gautham R. Shenoy" To: Nicholas Piggin , Anton Blanchard , Nathan Lynch , Michael Ellerman , Michael Neuling , Vaidyanathan Srinivasan Cc: linuxppc-dev@ozlabs.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, "Gautham R. Shenoy" Subject: [PATCH v2 3/3] cpuidle-pseries : Fixup exit latency for CEDE(0) Date: Wed, 29 Jul 2020 12:17:34 +0530 Message-Id: <1596005254-25753-4-git-send-email-ego@linux.vnet.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1596005254-25753-1-git-send-email-ego@linux.vnet.ibm.com> References: <1596005254-25753-1-git-send-email-ego@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-29_03:2020-07-28,2020-07-29 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 mlxscore=0 bulkscore=0 impostorscore=0 spamscore=0 adultscore=0 suspectscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007290043 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: "Gautham R. Shenoy" We are currently assuming that CEDE(0) has exit latency 10us, since there is no way for us to query from the platform. However, if the wakeup latency of an Extended CEDE state is smaller than 10us, then we can be sure that the exit latency of CEDE(0) cannot be more than that. that. In this patch, we fix the exit latency of CEDE(0) if we discover an Extended CEDE state with wakeup latency smaller than 10us. Benchmark results: ebizzy: 2 ebizzy threads bound to the same big-core. 25% improvement in the avg records/s with patch. x without_patch + with_patch N Min Max Median Avg Stddev x 10 2491089 5834307 5398375 4244335 1596244.9 + 10 2893813 5834474 5832448 5327281.3 1055941.4 context_switch2 : There is no major regression observed with this patch as seen from the context_switch2 benchmark. context_switch2 across CPU0 CPU1 (Both belong to same big-core, but different small cores). We observe a minor 0.14% regression in the number of context-switches (higher is better). x without_patch + with_patch N Min Max Median Avg Stddev x 500 348872 362236 354712 354745.69 2711.827 + 500 349422 361452 353942 354215.4 2576.9258 Difference at 99.0% confidence -530.288 +/- 430.963 -0.149484% +/- 0.121485% (Student's t, pooled s = 2645.24) context_switch2 across CPU0 CPU8 (Different big-cores). We observe a 0.37% improvement in the number of context-switches (higher is better). x without_patch + with_patch N Min Max Median Avg Stddev x 500 287956 294940 288896 288977.23 646.59295 + 500 288300 294646 289582 290064.76 1161.9992 Difference at 99.0% confidence 1087.53 +/- 153.194 0.376337% +/- 0.0530125% (Student's t, pooled s = 940.299) schbench: No major difference could be seen until the 99.9th percentile. Without-patch Latency percentiles (usec) 50.0th: 29 75.0th: 39 90.0th: 49 95.0th: 59 *99.0th: 13104 99.5th: 14672 99.9th: 15824 min=0, max=17993 With-patch: Latency percentiles (usec) 50.0th: 29 75.0th: 40 90.0th: 50 95.0th: 61 *99.0th: 13648 99.5th: 14768 99.9th: 15664 min=0, max=29812 Reviewed-by: Vaidyanathan Srinivasan Signed-off-by: Gautham R. Shenoy --- drivers/cpuidle/cpuidle-pseries.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/cpuidle/cpuidle-pseries.c b/drivers/cpuidle/cpuidle-pseries.c index b1dc24d..0b2f115 100644 --- a/drivers/cpuidle/cpuidle-pseries.c +++ b/drivers/cpuidle/cpuidle-pseries.c @@ -334,12 +334,42 @@ static int pseries_cpuidle_driver_init(void) static int add_pseries_idle_states(void) { int nr_states = 2; /* By default we have snooze, CEDE */ + int i; + u64 min_latency_us = dedicated_states[1].exit_latency; /* CEDE latency */ if (parse_cede_parameters()) return nr_states; - pr_info("cpuidle : Skipping the %d Extended CEDE idle states\n", - nr_xcede_records); + for (i = 0; i < nr_xcede_records; i++) { + u64 latency_tb = xcede_records[i].wakeup_latency_tb_ticks; + u64 latency_us = tb_to_ns(latency_tb) / NSEC_PER_USEC; + + if (latency_us < min_latency_us) + min_latency_us = latency_us; + } + + /* + * We are currently assuming that CEDE(0) has exit latency + * 10us, since there is no way for us to query from the + * platform. + * + * However, if the wakeup latency of an Extended CEDE state is + * smaller than 10us, then we can be sure that CEDE(0) + * requires no more than that. + * + * Perform the fix-up. + */ + if (min_latency_us < dedicated_states[1].exit_latency) { + u64 cede0_latency = min_latency_us - 1; + + if (cede0_latency <= 0) + cede0_latency = min_latency_us; + + dedicated_states[1].exit_latency = cede0_latency; + dedicated_states[1].target_residency = 10 * (cede0_latency); + pr_info("cpuidle : Fixed up CEDE exit latency to %llu us\n", + cede0_latency); + } return nr_states; }