From patchwork Wed Jul 29 12:07:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690915 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3408A13B1 for ; Wed, 29 Jul 2020 12:09:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 20AA322BEB for ; Wed, 29 Jul 2020 12:09:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726644AbgG2MIW (ORCPT ); Wed, 29 Jul 2020 08:08:22 -0400 Received: from inva021.nxp.com ([92.121.34.21]:37740 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726476AbgG2MIV (ORCPT ); Wed, 29 Jul 2020 08:08:21 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 42D62200FDB; Wed, 29 Jul 2020 14:08:19 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 303D1200FAB; Wed, 29 Jul 2020 14:08:19 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 89C732032B; Wed, 29 Jul 2020 14:08:18 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 01/17] dt-bindings: clocks: imx8mp: Rename audiomix ids clocks to audio_blk_ctrl Date: Wed, 29 Jul 2020 15:07:47 +0300 Message-Id: <1596024483-21482-2-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org In the reference manual the actual name is Audio BLK_CTRL. Lets make it more obvious here by renaming from audiomix to audio_blk_ctrl. Signed-off-by: Abel Vesa --- include/dt-bindings/clock/imx8mp-clock.h | 120 +++++++++++++++---------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 7a23f28..6008f32 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -324,66 +324,66 @@ #define IMX8MP_CLK_END 313 -#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 -#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 -#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 -#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 -#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 -#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 -#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 -#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 -#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 -#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 -#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 -#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 -#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 -#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 -#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 -#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 -#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 -#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 -#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 -#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 -#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 -#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 -#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_IPG 0 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1 1 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK2 2 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK3 3 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_IPG 4 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1 5 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK2 6 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK3 7 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG 8 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1 9 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK2 10 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK3 11 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG 12 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1 13 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK2 14 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK3 15 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_IPG 16 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1 17 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK2 18 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK3 19 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_IPG 20 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1 21 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK2 22 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK3 23 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_ASRC_IPG 24 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG 25 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA2_ROOT 26 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT 27 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SPBA2_ROOT 28 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT 29 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT 30 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_IPG 31 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG 32 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_AUD2HTX_IPG 33 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_EDMA_ROOT 34 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_AUDPLL_ROOT 35 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_MU2_ROOT 36 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_MU3_ROOT 37 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_PHY 38 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT 39 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1_SEL 40 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK2_SEL 41 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1_SEL 42 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK2_SEL 43 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1_SEL 44 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK2_SEL 45 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI4_MCLK1_SEL 46 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI4_MCLK2_SEL 47 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1_SEL 48 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK2_SEL 49 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1_SEL 50 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK2_SEL 51 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1_SEL 52 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK2_SEL 53 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_SEL 54 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_REF_SEL 55 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL 56 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_BYPASS 57 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_OUT 58 -#define IMX8MP_CLK_AUDIOMIX_END 59 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_END 59 #endif From patchwork Wed Jul 29 12:07:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690885 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2B6E014E3 for ; Wed, 29 Jul 2020 12:08:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 198872083E for ; Wed, 29 Jul 2020 12:08:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726718AbgG2MIX (ORCPT ); Wed, 29 Jul 2020 08:08:23 -0400 Received: from inva020.nxp.com ([92.121.34.13]:47910 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726353AbgG2MIV (ORCPT ); Wed, 29 Jul 2020 08:08:21 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id F14101A1120; Wed, 29 Jul 2020 14:08:19 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E454F1A1111; Wed, 29 Jul 2020 14:08:19 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 3FD262032B; Wed, 29 Jul 2020 14:08:19 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 02/17] dt-bindings: reset: imx8mp: Add audio blk_ctrl reset IDs Date: Wed, 29 Jul 2020 15:07:48 +0300 Message-Id: <1596024483-21482-3-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org These will be used by the imx8mp for blk-ctrl driver. Signed-off-by: Abel Vesa --- include/dt-bindings/reset/imx8mp-reset.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index 2e8c910..fca0c9bff 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -47,4 +47,9 @@ #define IMX8MP_RESET_NUM 38 +#define IMX8MP_AUDIO_BLK_CTRL_EARC_RESET 0 +#define IMX8MP_AUDIO_BLK_CTRL_EARC_PHY_RESET 1 + +#define IMX8MP_AUDIO_BLK_CTRL_RESET_NUM 2 + #endif From patchwork Wed Jul 29 12:07:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690917 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22AFD14E3 for ; Wed, 29 Jul 2020 12:09:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 14E6D22CAE for ; Wed, 29 Jul 2020 12:09:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726709AbgG2MJU (ORCPT ); Wed, 29 Jul 2020 08:09:20 -0400 Received: from inva020.nxp.com ([92.121.34.13]:47934 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726628AbgG2MIW (ORCPT ); Wed, 29 Jul 2020 08:08:22 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id B4CE61A1111; Wed, 29 Jul 2020 14:08:20 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A47941A01D1; Wed, 29 Jul 2020 14:08:20 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id F3CF82032B; Wed, 29 Jul 2020 14:08:19 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 03/17] dt-bindings: clock: imx8mp: Add ids for the audio shared gate Date: Wed, 29 Jul 2020 15:07:49 +0300 Message-Id: <1596024483-21482-4-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org All these IDs are for one single HW gate (CCGR101) that is shared between these root clocks. Signed-off-by: Abel Vesa Acked-by: Rob Herring --- include/dt-bindings/clock/imx8mp-clock.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 6008f32..78ebe8e 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -322,7 +322,17 @@ #define IMX8MP_CLK_HSIO_AXI 311 #define IMX8MP_CLK_MEDIA_ISP 312 -#define IMX8MP_CLK_END 313 +#define IMX8MP_CLK_AUDIO_AHB_ROOT 313 +#define IMX8MP_CLK_AUDIO_AXI_ROOT 314 +#define IMX8MP_CLK_SAI1_ROOT 315 +#define IMX8MP_CLK_SAI2_ROOT 316 +#define IMX8MP_CLK_SAI3_ROOT 317 +#define IMX8MP_CLK_SAI5_ROOT 318 +#define IMX8MP_CLK_SAI6_ROOT 319 +#define IMX8MP_CLK_SAI7_ROOT 320 +#define IMX8MP_CLK_PDM_ROOT 321 + +#define IMX8MP_CLK_END 322 #define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_IPG 0 #define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1 1 From patchwork Wed Jul 29 12:07:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690911 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 785511575 for ; Wed, 29 Jul 2020 12:09:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 60F6022CAF for ; Wed, 29 Jul 2020 12:09:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726799AbgG2MIY (ORCPT ); Wed, 29 Jul 2020 08:08:24 -0400 Received: from inva021.nxp.com ([92.121.34.21]:37790 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726341AbgG2MIX (ORCPT ); Wed, 29 Jul 2020 08:08:23 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 66F55200FF6; Wed, 29 Jul 2020 14:08:21 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 5A3CA200FBB; Wed, 29 Jul 2020 14:08:21 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id B3CF22032B; Wed, 29 Jul 2020 14:08:20 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 04/17] dt-bindings: clock: imx8mp: Add media blk_ctrl clock IDs Date: Wed, 29 Jul 2020 15:07:50 +0300 Message-Id: <1596024483-21482-5-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org These will be used by the imx8mp for blk-ctrl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring --- include/dt-bindings/clock/imx8mp-clock.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 78ebe8e..bb465a7 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -396,4 +396,32 @@ #define IMX8MP_CLK_AUDIO_BLK_CTRL_END 59 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_PCLK 0 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_CLKREF 1 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_PCLK 2 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_ACLK 3 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_PIXEL 4 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_APB 5 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_PROC 6 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_APB 7 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_BUS_BLK 8 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_PCLK 9 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_ACLK 10 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_PIXEL 11 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_APB 12 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_COR 13 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AXI 14 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AHB 15 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_COR 16 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AXI 17 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AHB 18 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_COR 19 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AXI 20 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AHB 21 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI2 22 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_AXI 23 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_AXI 24 + +#define IMX8MP_CLK_MEDIA_BLK_CTRL_END 25 + #endif From patchwork Wed Jul 29 12:07:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690909 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E1EB013B1 for ; Wed, 29 Jul 2020 12:09:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CBAEE20809 for ; Wed, 29 Jul 2020 12:09:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726825AbgG2MIY (ORCPT ); Wed, 29 Jul 2020 08:08:24 -0400 Received: from inva020.nxp.com ([92.121.34.13]:47952 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726707AbgG2MIY (ORCPT ); Wed, 29 Jul 2020 08:08:24 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 1E7101A111A; Wed, 29 Jul 2020 14:08:22 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 113581A01D1; Wed, 29 Jul 2020 14:08:22 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 69A252032B; Wed, 29 Jul 2020 14:08:21 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 05/17] dt-bindings: reset: imx8mp: Add media blk_ctrl reset IDs Date: Wed, 29 Jul 2020 15:07:51 +0300 Message-Id: <1596024483-21482-6-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org These will be used by the imx8mp for blk-ctrl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring --- include/dt-bindings/reset/imx8mp-reset.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index fca0c9bff..13e56dd 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -52,4 +52,32 @@ #define IMX8MP_AUDIO_BLK_CTRL_RESET_NUM 2 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI_PCLK 0 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI_CLKREF 1 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_PCLK 2 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_ACLK 3 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_PIXEL 4 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_APB 5 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_PROC 6 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_APB 7 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_BUS_BLK 8 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_PCLK 9 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_ACLK 10 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_PIXEL 11 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_APB 12 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_COR 13 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_AXI 14 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_AHB 15 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_COR 16 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_AXI 17 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_AHB 18 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_COR 19 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_AXI 20 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_AHB 21 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI2 22 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_AXI 23 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_AXI 24 + +#define IMX8MP_MEDIA_BLK_CTRL_RESET_NUM 25 + #endif From patchwork Wed Jul 29 12:07:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690913 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6CA9714E3 for ; Wed, 29 Jul 2020 12:09:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E5DF2083B for ; Wed, 29 Jul 2020 12:09:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726957AbgG2MJO (ORCPT ); Wed, 29 Jul 2020 08:09:14 -0400 Received: from inva020.nxp.com ([92.121.34.13]:47978 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726709AbgG2MIY (ORCPT ); Wed, 29 Jul 2020 08:08:24 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id CBC7D1A01D1; Wed, 29 Jul 2020 14:08:22 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id BB7D31A1122; Wed, 29 Jul 2020 14:08:22 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 205622032B; Wed, 29 Jul 2020 14:08:22 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 06/17] dt-bindings: clock: imx8mp: Add hdmi blk_ctrl clock IDs Date: Wed, 29 Jul 2020 15:07:52 +0300 Message-Id: <1596024483-21482-7-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org These will be used by the imx8mp for blk-ctrl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring --- include/dt-bindings/clock/imx8mp-clock.h | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index bb465a7..6b90831 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -396,6 +396,46 @@ #define IMX8MP_CLK_AUDIO_BLK_CTRL_END 59 +#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_APB_CLK 0 +#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_B_CLK 1 +#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_REF266M_CLK 2 +#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL24M_CLK 3 +#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL32K_CLK 4 +#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_TX_PIX_CLK 5 +#define IMX8MP_CLK_HDMI_BLK_CTRL_IRQS_STEER_CLK 6 +#define IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDMI_CLK 7 +#define IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDCP_CLK 8 +#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_APB_CLK 9 +#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_B_CLK 10 +#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PDI_CLK 11 +#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PIX_CLK 12 +#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_SPU_CLK 13 +#define IMX8MP_CLK_HDMI_BLK_CTRL_FDCC_REF_CLK 14 +#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_APB_CLK 15 +#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_B_CLK 16 +#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_CEA_CLK 17 +#define IMX8MP_CLK_HDMI_BLK_CTRL_VSFD_CEA_CLK 18 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_HPI_CLK 19 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_APB_CLK 20 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_CEC_CLK 21 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_ESM_CLK 22 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_GPA_CLK 23 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIXEL_CLK 24 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SFR_CLK 25 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SKP_CLK 26 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PREP_CLK 27 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_APB_CLK 28 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_INT_CLK 29 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SEC_MEM_CLK 30 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_SKP_CLK 31 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_VID_LINK_PIX_CLK 32 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_APB_CLK 33 +#define IMX8MP_CLK_HDMI_BLK_CTRL_HTXPHY_CLK_SEL 34 +#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_CLK_SEL 35 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIPE_CLK_SEL 36 + +#define IMX8MP_CLK_HDMI_BLK_CTRL_END 37 + #define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_PCLK 0 #define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_CLKREF 1 #define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_PCLK 2 From patchwork Wed Jul 29 12:07:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690907 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1C0941575 for ; Wed, 29 Jul 2020 12:09:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0F77122CB3 for ; Wed, 29 Jul 2020 12:09:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726878AbgG2MIZ (ORCPT ); Wed, 29 Jul 2020 08:08:25 -0400 Received: from inva021.nxp.com ([92.121.34.21]:37816 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726774AbgG2MIZ (ORCPT ); Wed, 29 Jul 2020 08:08:25 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 875EA200FBB; Wed, 29 Jul 2020 14:08:23 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 7A860200FAB; Wed, 29 Jul 2020 14:08:23 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id CAA222032B; Wed, 29 Jul 2020 14:08:22 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 07/17] dt-bindings: reset: imx8mp: Add hdmi blk_ctrl reset IDs Date: Wed, 29 Jul 2020 15:07:53 +0300 Message-Id: <1596024483-21482-8-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org These will be used imx8mp for blk-ctrl driver. Signed-off-by: Abel Vesa Acked-by: Rob Herring --- include/dt-bindings/reset/imx8mp-reset.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h index 13e56dd..c1ca79c 100644 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -80,4 +80,16 @@ #define IMX8MP_MEDIA_BLK_CTRL_RESET_NUM 25 +#define IMX8MP_HDMI_BLK_CTRL_HDMI_TX_RESET 0 +#define IMX8MP_HDMI_BLK_CTRL_HDMI_PHY_RESET 1 +#define IMX8MP_HDMI_BLK_CTRL_HDMI_PAI_RESET 2 +#define IMX8MP_HDMI_BLK_CTRL_HDMI_PVI_RESET 3 +#define IMX8MP_HDMI_BLK_CTRL_HDMI_TRNG_RESET 4 +#define IMX8MP_HDMI_BLK_CTRL_IRQ_STEER_RESET 5 +#define IMX8MP_HDMI_BLK_CTRL_HDMI_HDCP_RESET 6 +#define IMX8MP_HDMI_BLK_CTRL_LCDIF_RESET 7 + +#define IMX8MP_HDMI_BLK_CTRL_RESET_NUM 8 + + #endif From patchwork Wed Jul 29 12:07:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690905 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 816F514E3 for ; Wed, 29 Jul 2020 12:09:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 733C320809 for ; Wed, 29 Jul 2020 12:09:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726918AbgG2MI1 (ORCPT ); Wed, 29 Jul 2020 08:08:27 -0400 Received: from inva021.nxp.com ([92.121.34.21]:37790 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726817AbgG2MI0 (ORCPT ); Wed, 29 Jul 2020 08:08:26 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 3F02D200FDB; Wed, 29 Jul 2020 14:08:24 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 31B81200FAB; Wed, 29 Jul 2020 14:08:24 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 8ACC72032B; Wed, 29 Jul 2020 14:08:23 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 08/17] clk: imx8mp: Add audio shared gate Date: Wed, 29 Jul 2020 15:07:54 +0300 Message-Id: <1596024483-21482-9-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org According to the RM, the CCGR101 is shared for the following root clocks: - AUDIO_AHB_CLK_ROOT - AUDIO_AXI_CLK_ROOT - SAI2_CLK_ROOT - SAI3_CLK_ROOT - SAI5_CLK_ROOT - SAI6_CLK_ROOT - SAI7_CLK_ROOT - PDM_CLK_ROOT Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8mp.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index ca74771..462c558 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -17,6 +17,7 @@ static u32 share_count_nand; static u32 share_count_media; +static u32 share_count_audio; static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; @@ -731,7 +732,16 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0); hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0); hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0); - hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "ipg_root", ccm_base + 0x4650, 0); + + hws[IMX8MP_CLK_AUDIO_AHB_ROOT] = imx_clk_hw_gate2_shared2("audio_ahb_root", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_AUDIO_AXI_ROOT] = imx_clk_hw_gate2_shared2("audio_axi_root", "audio_axi", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root", "sai1", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root", "sai2", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root", "sai3", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root", "sai5", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root", "sai6", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root", "sai7", ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root", "pdm", ccm_base + 0x4650, 0, &share_count_audio); hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core", hws[IMX8MP_CLK_A53_CORE]->clk, From patchwork Wed Jul 29 12:07:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690887 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B8C1114E3 for ; Wed, 29 Jul 2020 12:08:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9A652083E for ; Wed, 29 Jul 2020 12:08:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726909AbgG2MI0 (ORCPT ); Wed, 29 Jul 2020 08:08:26 -0400 Received: from inva020.nxp.com ([92.121.34.13]:47952 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726846AbgG2MI0 (ORCPT ); Wed, 29 Jul 2020 08:08:26 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id F3DCF1A1111; Wed, 29 Jul 2020 14:08:24 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E713B1A1128; Wed, 29 Jul 2020 14:08:24 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 413182032B; Wed, 29 Jul 2020 14:08:24 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 09/17] arm64: dts: Remove imx-hdmimix-reset header file Date: Wed, 29 Jul 2020 15:07:55 +0300 Message-Id: <1596024483-21482-10-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The hdmi BLK_CTRL ids have been moved to imx8mp-reset.h Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9de2aa1..daa1769 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include From patchwork Wed Jul 29 12:07:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690903 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 18FE613B1 for ; Wed, 29 Jul 2020 12:09:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 01E522083B for ; Wed, 29 Jul 2020 12:09:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726962AbgG2MI2 (ORCPT ); Wed, 29 Jul 2020 08:08:28 -0400 Received: from inva021.nxp.com ([92.121.34.21]:37884 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726819AbgG2MI2 (ORCPT ); Wed, 29 Jul 2020 08:08:28 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id AA3DD200FAB; Wed, 29 Jul 2020 14:08:25 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 9D8FF2012EC; Wed, 29 Jul 2020 14:08:25 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 022772032B; Wed, 29 Jul 2020 14:08:24 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 10/17] Documentation: bindings: clk: Add bindings for i.MX BLK_CTRL Date: Wed, 29 Jul 2020 15:07:56 +0300 Message-Id: <1596024483-21482-11-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Document the i.MX BLK_CTRL with its devicetree properties. Signed-off-by: Abel Vesa --- .../bindings/clock/fsl,imx-blk-ctrl.yaml | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/fsl,imx-blk-ctrl.yaml diff --git a/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctrl.yaml b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctrl.yaml new file mode 100644 index 00000000..036d3d3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,imx-blk-ctrl.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/fsl,imx-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX BLK_CTRL + +description: | + i.MX BLK_CTRL is a conglomerate of different GPRs that are + dedicated to a specific subsystem. Because it usually contains + clocks amongst other things, it needs access to the i.MX clocks + API. All the other functionalities it provides can work just fine + from the clock subsystem tree. + +maintainers: + - Abel Vesa + +properties: + reg: + maxItems: 1 + + compatible: + items: + - const: fsl,imx8mp-blk-ctrl + - const: syscon + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - power-domains + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + audio-blk-ctrl: blk-ctrl@30e20000 { + compatible = "fsl,imx8mp-blk-ctrl", "syscon"; + reg = <0x30e20000 0x10000>; + power-domains = <&audiomix_pd>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Wed Jul 29 12:07:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690901 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30A5914E3 for ; Wed, 29 Jul 2020 12:09:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A5B322CA0 for ; Wed, 29 Jul 2020 12:09:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726981AbgG2MIa (ORCPT ); Wed, 29 Jul 2020 08:08:30 -0400 Received: from inva021.nxp.com ([92.121.34.21]:37816 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726353AbgG2MI3 (ORCPT ); Wed, 29 Jul 2020 08:08:29 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 63C112012EC; Wed, 29 Jul 2020 14:08:26 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 55383201044; Wed, 29 Jul 2020 14:08:26 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id ACB232032B; Wed, 29 Jul 2020 14:08:25 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 11/17] clk: imx: Add blk_ctrl combo driver Date: Wed, 29 Jul 2020 15:07:57 +0300 Message-Id: <1596024483-21482-12-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On i.MX8MP, there is a new type of IP which is called BLK_CTRL in RM and usually is comprised of some GPRs that are considered too generic to be part of any dedicated IP from that specific subsystem. In general, some of the GPRs have some clock bits, some have reset bits, so in order to be able to use the imx clock API, this needs to be in a clock driver. From there it can use the reset controller API and leave the rest to the syscon. This driver is intended to work with the following BLK_CTRL IPs found in i.MX8MP (but it might be reused by the future i.MX platforms that have this kind of IP in their design): - Audio - Media - HDMI Signed-off-by: Abel Vesa --- drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-blk-ctrl.c | 318 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-blk-ctrl.h | 81 +++++++++++ 3 files changed, 400 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-blk-ctrl.c create mode 100644 drivers/clk/imx/clk-blk-ctrl.h diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 928f874c..7afe1df 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -27,7 +27,7 @@ obj-$(CONFIG_MXC_CLK_SCU) += \ obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o -obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o +obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-blk-ctrl.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o diff --git a/drivers/clk/imx/clk-blk-ctrl.c b/drivers/clk/imx/clk-blk-ctrl.c new file mode 100644 index 00000000..a46e674 --- /dev/null +++ b/drivers/clk/imx/clk-blk-ctrl.c @@ -0,0 +1,318 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 NXP. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" +#include "clk-blk-ctrl.h" + +struct reset_hw { + u32 offset; + u32 shift; + u32 mask; +}; + +struct pm_safekeep_info { + uint32_t *regs_values; + uint32_t *regs_offsets; + uint32_t regs_num; +}; + +struct imx_blk_ctrl_drvdata { + void __iomem *base; + struct reset_controller_dev rcdev; + struct reset_hw *rst_hws; + struct pm_safekeep_info pm_info; + + spinlock_t lock; +}; + +static int imx_blk_ctrl_reset_set(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct imx_blk_ctrl_drvdata *drvdata = container_of(rcdev, + struct imx_blk_ctrl_drvdata, rcdev); + unsigned int offset = drvdata->rst_hws[id].offset; + unsigned int shift = drvdata->rst_hws[id].shift; + unsigned int mask = drvdata->rst_hws[id].mask; + void __iomem *reg_addr = drvdata->base + offset; + unsigned long flags; + u32 reg; + + if (assert) { + pm_runtime_get_sync(rcdev->dev); + spin_lock_irqsave(&drvdata->lock, flags); + reg = readl(reg_addr); + writel(reg & ~(mask << shift), reg_addr); + spin_unlock_irqrestore(&drvdata->lock, flags); + } else { + spin_lock_irqsave(&drvdata->lock, flags); + reg = readl(reg_addr); + writel(reg | (mask << shift), reg_addr); + spin_unlock_irqrestore(&drvdata->lock, flags); + pm_runtime_put(rcdev->dev); + } + + return 0; +} + +static int imx_blk_ctrl_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + imx_blk_ctrl_reset_set(rcdev, id, true); + return imx_blk_ctrl_reset_set(rcdev, id, false); +} + +static int imx_blk_ctrl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return imx_blk_ctrl_reset_set(rcdev, id, true); +} + +static int imx_blk_ctrl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return imx_blk_ctrl_reset_set(rcdev, id, false); +} + +static const struct reset_control_ops imx_blk_ctrl_reset_ops = { + .reset = imx_blk_ctrl_reset_reset, + .assert = imx_blk_ctrl_reset_assert, + .deassert = imx_blk_ctrl_reset_deassert, +}; + +static int imx_blk_ctrl_register_reset_controller(struct device *dev) +{ + struct imx_blk_ctrl_drvdata *drvdata = dev_get_drvdata(dev); + const struct imx_blk_ctrl_dev_data *dev_data = of_device_get_match_data(dev); + struct reset_hw *hws; + int max = dev_data->resets_max; + int i; + + spin_lock_init(&drvdata->lock); + + drvdata->rcdev.owner = THIS_MODULE; + drvdata->rcdev.nr_resets = max; + drvdata->rcdev.ops = &imx_blk_ctrl_reset_ops; + drvdata->rcdev.of_node = dev->of_node; + drvdata->rcdev.dev = dev; + + drvdata->rst_hws = devm_kzalloc(dev, sizeof(struct reset_hw) * max, + GFP_KERNEL); + hws = drvdata->rst_hws; + + for (i = 0; i < dev_data->hws_num; i++) { + struct imx_blk_ctrl_hw *hw = &dev_data->hws[i]; + + if (hw->type != BLK_CTRL_RESET) + continue; + + hws[hw->id].offset = hw->offset; + hws[hw->id].shift = hw->shift; + hws[hw->id].mask = hw->mask; + } + + return devm_reset_controller_register(dev, &drvdata->rcdev); +} +static struct clk_hw *imx_blk_ctrl_register_one_clock(struct device *dev, + struct imx_blk_ctrl_hw *hw) +{ + struct imx_blk_ctrl_drvdata *drvdata = dev_get_drvdata(dev); + void __iomem *base = drvdata->base; + struct clk_hw *clk_hw; + + switch (hw->type) { + case BLK_CTRL_CLK_MUX: + clk_hw = imx_dev_clk_hw_mux_flags(dev, hw->name, + base + hw->offset, + hw->shift, hw->width, + hw->parents, + hw->parents_count, + hw->flags); + break; + case BLK_CTRL_CLK_GATE: + clk_hw = imx_dev_clk_hw_gate(dev, hw->name, hw->parents, + base + hw->offset, hw->shift); + break; + case BLK_CTRL_CLK_SHARED_GATE: + clk_hw = imx_dev_clk_hw_gate_shared(dev, hw->name, + hw->parents, + base + hw->offset, + hw->shift, + hw->shared_count); + break; + case BLK_CTRL_CLK_PLL14XX: + clk_hw = imx_dev_clk_hw_pll14xx(dev, hw->name, hw->parents, + base + hw->offset, hw->pll_tbl); + break; + default: + clk_hw = NULL; + }; + + return clk_hw; +} + +static int imx_blk_ctrl_register_clock_controller(struct device *dev) +{ + const struct imx_blk_ctrl_dev_data *dev_data = of_device_get_match_data(dev); + struct clk_hw_onecell_data *clk_hw_data; + struct clk_hw **hws; + int i; + + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, + dev_data->hws_num), GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num = dev_data->clocks_max; + hws = clk_hw_data->hws; + + for (i = 0; i < dev_data->hws_num; i++) { + struct imx_blk_ctrl_hw *hw = &dev_data->hws[i]; + struct clk_hw *tmp = imx_blk_ctrl_register_one_clock(dev, hw); + + if (!tmp) + continue; + hws[hw->id] = tmp; + } + + imx_check_clk_hws(hws, dev_data->clocks_max); + + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + clk_hw_data); +} + +static int imx_blk_ctrl_init_runtime_pm_safekeeping(struct device *dev) +{ + const struct imx_blk_ctrl_dev_data *dev_data = of_device_get_match_data(dev); + struct imx_blk_ctrl_drvdata *drvdata = dev_get_drvdata(dev); + struct pm_safekeep_info *pm_info = &drvdata->pm_info; + u32 regs_num = dev_data->pm_runtime_saved_regs_num; + const u32 *regs_offsets = dev_data->pm_runtime_saved_regs; + + if (!dev_data->pm_runtime_saved_regs_num) + return 0; + + pm_info->regs_values = devm_kzalloc(dev, + sizeof(u32) * regs_num, + GFP_KERNEL); + if (WARN_ON(IS_ERR(pm_info->regs_values))) + return PTR_ERR(pm_info->regs_values); + + pm_info->regs_offsets = kmemdup(regs_offsets, + regs_num * sizeof(u32), GFP_KERNEL); + if (WARN_ON(IS_ERR(pm_info->regs_offsets))) + return PTR_ERR(pm_info->regs_offsets); + + pm_info->regs_num = regs_num; + + return 0; +} + +static int imx_blk_ctrl_probe(struct platform_device *pdev) +{ + struct imx_blk_ctrl_drvdata *drvdata; + struct device *dev = &pdev->dev; + int ret; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (WARN_ON(!drvdata)) + return -ENOMEM; + + drvdata->base = devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(drvdata->base))) + return PTR_ERR(drvdata->base); + + dev_set_drvdata(dev, drvdata); + + ret = imx_blk_ctrl_init_runtime_pm_safekeeping(dev); + if (ret) + return ret; + + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + ret = imx_blk_ctrl_register_clock_controller(dev); + if (ret) { + pm_runtime_put(dev); + return ret; + } + + ret = imx_blk_ctrl_register_reset_controller(dev); + + pm_runtime_put(dev); + + return ret; +} + +static void imx_blk_ctrl_read_write(struct device *dev, bool write) +{ + struct imx_blk_ctrl_drvdata *drvdata = dev_get_drvdata(dev); + struct pm_safekeep_info *pm_info = &drvdata->pm_info; + void __iomem *base = drvdata->base; + int i; + + if (!pm_info->regs_num) + return; + + for (i = 0; i < pm_info->regs_num; i++) { + u32 offset = pm_info->regs_offsets[i]; + + if (write) + writel(pm_info->regs_values[i], base + offset); + else + pm_info->regs_values[i] = readl(base + offset); + } + +} + +static int imx_blk_ctrl_runtime_suspend(struct device *dev) +{ + imx_blk_ctrl_read_write(dev, false); + + return 0; +} + +static int imx_blk_ctrl_runtime_resume(struct device *dev) +{ + imx_blk_ctrl_read_write(dev, true); + + return 0; +} + +static const struct dev_pm_ops imx_blk_ctrl_pm_ops = { + SET_RUNTIME_PM_OPS(imx_blk_ctrl_runtime_suspend, + imx_blk_ctrl_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static const struct of_device_id imx_blk_ctrl_of_match[] = { + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_blk_ctrl_of_match); + +static struct platform_driver imx_blk_ctrl_driver = { + .probe = imx_blk_ctrl_probe, + .driver = { + .name = "imx-blk-ctrl", + .of_match_table = of_match_ptr(imx_blk_ctrl_of_match), + .pm = &imx_blk_ctrl_pm_ops, + }, +}; +module_platform_driver(imx_blk_ctrl_driver); diff --git a/drivers/clk/imx/clk-blk-ctrl.h b/drivers/clk/imx/clk-blk-ctrl.h new file mode 100644 index 00000000..b3b7fc37 --- /dev/null +++ b/drivers/clk/imx/clk-blk-ctrl.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __MACH_IMX_CLK_BLK_CTRL_H +#define __MACH_IMX_CLK_BLK_CTRL_H + +enum imx_blk_ctrl_hw_type { + BLK_CTRL_CLK_MUX, + BLK_CTRL_CLK_GATE, + BLK_CTRL_CLK_SHARED_GATE, + BLK_CTRL_CLK_PLL14XX, + BLK_CTRL_RESET, +}; + +struct imx_blk_ctrl_hw { + int type; + char *name; + u32 offset; + u32 shift; + u32 mask; + u32 width; + u32 flags; + u32 id; + void *parents; + u32 parents_count; + int *shared_count; + struct imx_pll14xx_clk *pll_tbl; +}; + +struct imx_blk_ctrl_dev_data { + struct imx_blk_ctrl_hw *hws; + u32 hws_num; + + u32 clocks_max; + u32 resets_max; + + u32 pm_runtime_saved_regs_num; + u32 pm_runtime_saved_regs[]; +}; + +#define IMX_BLK_CTRL(_type, _name, _id, _offset, _shift, _width, _mask, _parents, _parents_count, _flags, sh_count, _pll_tbl) \ + { \ + .type = _type, \ + .name = _name, \ + .id = _id, \ + .offset = _offset, \ + .shift = _shift, \ + .width = _width, \ + .mask = _mask, \ + .parents = _parents, \ + .parents_count = _parents_count, \ + .flags = _flags, \ + .shared_count = sh_count, \ + .pll_tbl = _pll_tbl, \ + } + +#define IMX_BLK_CTRL_CLK_MUX(_name, _id, _offset, _shift, _width, _parents) \ + IMX_BLK_CTRL(BLK_CTRL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), 0, NULL, NULL) + +#define IMX_BLK_CTRL_CLK_MUX_FLAGS(_name, _id, _offset, _shift, _width, _parents, _flags) \ + IMX_BLK_CTRL(BLK_CTRL_CLK_MUX, _name, _id, _offset, _shift, _width, 0, _parents, ARRAY_SIZE(_parents), _flags, NULL, NULL) + +#define IMX_BLK_CTRL_CLK_GATE(_name, _id, _offset, _shift, _parents) \ + IMX_BLK_CTRL(BLK_CTRL_CLK_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, NULL, NULL) + +#define IMX_BLK_CTRL_CLK_SHARED_GATE(_name, _id, _offset, _shift, _parents, sh_count) \ + IMX_BLK_CTRL(BLK_CTRL_CLK_SHARED_GATE, _name, _id, _offset, _shift, 1, 0, _parents, 1, 0, sh_count, NULL) + +#define IMX_BLK_CTRL_CLK_PLL14XX(_name, _id, _offset, _parents, _pll_tbl) \ + IMX_BLK_CTRL(BLK_CTRL_CLK_PLL14XX, _name, _id, _offset, 0, 0, 0, _parents, 1, 0, NULL, _pll_tbl) + +#define IMX_BLK_CTRL_RESET(_id, _offset, _shift) \ + IMX_BLK_CTRL(BLK_CTRL_RESET, NULL, _id, _offset, _shift, 0, 1, NULL, 0, 0, NULL, NULL) + +#define IMX_BLK_CTRL_RESET_MASK(_id, _offset, _shift, mask) \ + IMX_BLK_CTRL(BLK_CTRL_RESET, NULL, _id, _offset, _shift, 0, mask, NULL, 0, 0, NULL, NULL) + +extern const struct imx_blk_ctrl_dev_data imx8mp_audio_blk_ctrl_dev_data __initconst; +extern const struct imx_blk_ctrl_dev_data imx8mp_media_blk_ctrl_dev_data __initconst; +extern const struct imx_blk_ctrl_dev_data imx8mp_hdmi_blk_ctrl_dev_data __initconst; + +#endif + From patchwork Wed Jul 29 12:07:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690891 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ACE941575 for ; Wed, 29 Jul 2020 12:08:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 91AF22083B for ; Wed, 29 Jul 2020 12:08:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727006AbgG2MIc (ORCPT ); Wed, 29 Jul 2020 08:08:32 -0400 Received: from inva021.nxp.com ([92.121.34.21]:37790 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726933AbgG2MIb (ORCPT ); Wed, 29 Jul 2020 08:08:31 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 21958201044; Wed, 29 Jul 2020 14:08:27 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 0B346200FDB; Wed, 29 Jul 2020 14:08:27 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 648432032B; Wed, 29 Jul 2020 14:08:26 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 12/17] clk: imx8mp: Add audio blk_ctrl clocks and resets Date: Wed, 29 Jul 2020 15:07:58 +0300 Message-Id: <1596024483-21482-13-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add audio blk_ctrl clocks and resets in the i.MX8MP clock driver to be picked up by the clk-blk-ctrl driver. Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-blk-ctrl.c | 4 ++ drivers/clk/imx/clk-imx8mp.c | 138 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 142 insertions(+) diff --git a/drivers/clk/imx/clk-blk-ctrl.c b/drivers/clk/imx/clk-blk-ctrl.c index a46e674..67cf223 100644 --- a/drivers/clk/imx/clk-blk-ctrl.c +++ b/drivers/clk/imx/clk-blk-ctrl.c @@ -303,6 +303,10 @@ static const struct dev_pm_ops imx_blk_ctrl_pm_ops = { }; static const struct of_device_id imx_blk_ctrl_of_match[] = { + { + .compatible = "fsl,imx8mp-audio-blk-ctrl", + .data = &imx8mp_audio_blk_ctrl_dev_data + }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, imx_blk_ctrl_of_match); diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 462c558..00e7f5e 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -14,11 +15,148 @@ #include #include "clk.h" +#include "clk-blk-ctrl.h" + +#define IMX_AUDIO_BLK_CTRL_CLKEN0 0x0 +#define IMX_AUDIO_BLK_CTRL_CLKEN1 0x4 +#define IMX_AUDIO_BLK_CTRL_EARC 0x200 +#define IMX_AUDIO_BLK_CTRL_SAI1_MCLK_SEL 0x300 +#define IMX_AUDIO_BLK_CTRL_SAI2_MCLK_SEL 0x304 +#define IMX_AUDIO_BLK_CTRL_SAI3_MCLK_SEL 0x308 +#define IMX_AUDIO_BLK_CTRL_SAI5_MCLK_SEL 0x30C +#define IMX_AUDIO_BLK_CTRL_SAI6_MCLK_SEL 0x310 +#define IMX_AUDIO_BLK_CTRL_SAI7_MCLK_SEL 0x314 +#define IMX_AUDIO_BLK_CTRL_PDM_CLK 0x318 +#define IMX_AUDIO_BLK_CTRL_SAI_PLL_GNRL_CTL 0x400 +#define IMX_AUDIO_BLK_CTRL_SAI_PLL_FDIVL_CTL0 0x404 +#define IMX_AUDIO_BLK_CTRL_SAI_PLL_FDIVL_CTL1 0x408 +#define IMX_AUDIO_BLK_CTRL_SAI_PLL_SSCG_CTL 0x40C +#define IMX_AUDIO_BLK_CTRL_SAI_PLL_MNIT_CTL 0x410 +#define IMX_AUDIO_BLK_CTRL_IPG_LP_CTRL 0x504 + +#define IMX_MEDIA_BLK_CTRL_SFT_RSTN 0x0 +#define IMX_MEDIA_BLK_CTRL_CLK_EN 0x4 static u32 share_count_nand; static u32 share_count_media; static u32 share_count_audio; +static int shared_count_pdm; + +static const struct imx_pll14xx_rate_table imx_blk_ctrl_sai_pll_tbl[] = { + PLL_1443X_RATE(650000000U, 325, 3, 2, 0), +}; + +static const struct imx_pll14xx_clk imx_blk_ctrl_sai_pll = { + .type = PLL_1443X, + .rate_table = imx_blk_ctrl_sai_pll_tbl, +}; + +static const char * const imx_sai_mclk2_sels[] = {"sai1_root", "sai2_root", "sai3_root", "dummy", + "sai5_root", "sai6_root", "sai7_root", "sai1_mclk", + "sai2_mclk", "sai3_mclk", "dummy", + "sai5_mclk", "sai6_mclk", "sai7_mclk", "spdif1_ext_clk"}; +static const char * const imx_sai1_mclk1_sels[] = {"sai1_root", "sai1_mclk", }; +static const char * const imx_sai2_mclk1_sels[] = {"sai2_root", "sai2_mclk", }; +static const char * const imx_sai3_mclk1_sels[] = {"sai3_root", "sai3_mclk", }; +static const char * const imx_sai5_mclk1_sels[] = {"sai5_root", "sai5_mclk", }; +static const char * const imx_sai6_mclk1_sels[] = {"sai6_root", "sai6_mclk", }; +static const char * const imx_sai7_mclk1_sels[] = {"sai7_root", "sai7_mclk", }; +static const char * const imx_pdm_sels[] = {"pdm_root", "sai_pll_div2", "dummy", "dummy" }; +static const char * const imx_sai_pll_ref_sels[] = {"osc_24m", "dummy", "dummy", "dummy", }; +static const char * const imx_sai_pll_bypass_sels[] = {"sai_pll", "sai_pll_ref_sel", }; + +static struct imx_blk_ctrl_hw imx8mp_audio_blk_ctrl_hws[] = { + /* clocks */ + IMX_BLK_CTRL_CLK_MUX("sai_pll_ref_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_REF_SEL, 0x400, 0, 2, imx_sai_pll_ref_sels), + IMX_BLK_CTRL_CLK_PLL14XX("sai_pll", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL, 0x400, "sai_pll_ref_sel", &imx_blk_ctrl_sai_pll), + IMX_BLK_CTRL_CLK_MUX_FLAGS("sai_pll_bypass", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_BYPASS, 0x400, 4, 1, imx_sai_pll_bypass_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTRL_CLK_GATE("sai_pll_out", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_OUT, 0x400, 13, "sai_pll_bypass"), + IMX_BLK_CTRL_CLK_MUX_FLAGS("sai1_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1_SEL, 0x300, 0, 1, imx_sai1_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTRL_CLK_MUX("sai1_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK2_SEL, 0x300, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTRL_CLK_MUX_FLAGS("sai2_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1_SEL, 0x304, 0, 1, imx_sai2_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTRL_CLK_MUX("sai2_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK2_SEL, 0x304, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTRL_CLK_MUX_FLAGS("sai3_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1_SEL, 0x308, 0, 1, imx_sai3_mclk1_sels, CLK_SET_RATE_PARENT), + IMX_BLK_CTRL_CLK_MUX("sai3_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK2_SEL, 0x308, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTRL_CLK_MUX("sai5_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1_SEL, 0x30C, 0, 1, imx_sai5_mclk1_sels), + IMX_BLK_CTRL_CLK_MUX("sai5_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK2_SEL, 0x30C, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTRL_CLK_MUX("sai6_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1_SEL, 0x310, 0, 1, imx_sai6_mclk1_sels), + IMX_BLK_CTRL_CLK_MUX("sai6_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK2_SEL, 0x310, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTRL_CLK_MUX("sai7_mclk1_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1_SEL, 0x314, 0, 1, imx_sai7_mclk1_sels), + IMX_BLK_CTRL_CLK_MUX("sai7_mclk2_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK2_SEL, 0x314, 1, 4, imx_sai_mclk2_sels), + IMX_BLK_CTRL_CLK_GATE("sai1_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_IPG, 0, 0, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("sai1_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1, 0, 1, "sai1_mclk1_sel"), + IMX_BLK_CTRL_CLK_GATE("sai1_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK2, 0, 2, "sai1_mclk2_sel"), + IMX_BLK_CTRL_CLK_GATE("sai1_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK3, 0, 3, "sai_pll_out"), + IMX_BLK_CTRL_CLK_GATE("sai2_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_IPG, 0, 4, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("sai2_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1, 0, 5, "sai2_mclk1_sel"), + IMX_BLK_CTRL_CLK_GATE("sai2_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK2, 0, 6, "sai2_mclk2_sel"), + IMX_BLK_CTRL_CLK_GATE("sai2_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK3, 0, 7, "sai_pll_out"), + IMX_BLK_CTRL_CLK_GATE("sai3_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG, 0, 8, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("sai3_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1, 0, 9, "sai3_mclk1_sel"), + IMX_BLK_CTRL_CLK_GATE("sai3_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK2, 0, 10, "sai3_mclk2_sel"), + IMX_BLK_CTRL_CLK_GATE("sai3_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK3, 0, 11, "sai_pll_out"), + IMX_BLK_CTRL_CLK_GATE("sai5_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG, 0, 12, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("sai5_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1, 0, 13, "sai5_mclk1_sel"), + IMX_BLK_CTRL_CLK_GATE("sai5_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK2, 0, 14, "sai5_mclk2_sel"), + IMX_BLK_CTRL_CLK_GATE("sai5_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK3, 0, 15, "sai_pll_out"), + IMX_BLK_CTRL_CLK_GATE("sai6_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_IPG, 0, 16, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("sai6_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1, 0, 17, "sai6_mclk1_sel"), + IMX_BLK_CTRL_CLK_GATE("sai6_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK2, 0, 18, "sai6_mclk2_sel"), + IMX_BLK_CTRL_CLK_GATE("sai6_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK3, 0, 19, "sai_pll_out"), + IMX_BLK_CTRL_CLK_GATE("sai7_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_IPG, 0, 20, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("sai7_mclk1_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1, 0, 21, "sai7_mclk1_sel"), + IMX_BLK_CTRL_CLK_GATE("sai7_mclk2_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK2, 0, 22, "sai7_mclk2_sel"), + IMX_BLK_CTRL_CLK_GATE("sai7_mclk3_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK3, 0, 23, "sai_pll_out"), + IMX_BLK_CTRL_CLK_GATE("asrc_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_ASRC_IPG, 0, 24, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_SHARED_GATE("pdm_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG, 0, 25, "audio_ahb_root", &shared_count_pdm), + IMX_BLK_CTRL_CLK_SHARED_GATE("pdm_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT, 0, 25, "pdm_root", &shared_count_pdm), + IMX_BLK_CTRL_CLK_GATE("sdma2_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA2_ROOT, 0, 26, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("sdma3_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT, 0, 27, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("spba2_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_SPBA2_ROOT, 0, 28, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("dsp_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT, 0, 29, "audio_axi_root"), + IMX_BLK_CTRL_CLK_GATE("dsp_dbg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT, 0, 30, "audio_axi_root"), + IMX_BLK_CTRL_CLK_GATE("earc_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_IPG, 0, 31, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("ocram_a_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG, 4, 0, "audio_axi_root"), + IMX_BLK_CTRL_CLK_GATE("aud2htx_ipg_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_AUD2HTX_IPG, 4, 1, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("edma_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_EDMA_ROOT, 4, 2, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("aud_pll_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_AUDPLL_ROOT, 4, 3, "osc_24m"), + IMX_BLK_CTRL_CLK_GATE("mu2_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_MU2_ROOT, 4, 4, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("mu3_root_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_MU3_ROOT, 4, 5, "audio_ahb_root"), + IMX_BLK_CTRL_CLK_GATE("earc_phy_clk", IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_PHY, 4, 6, "sai_pll_out"), + IMX_BLK_CTRL_CLK_MUX("pdm_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_SEL, 0x318, 1, 4, imx_pdm_sels), + + /* resets */ + IMX_BLK_CTRL_RESET(IMX8MP_AUDIO_BLK_CTRL_EARC_RESET, 0x200, 0), + IMX_BLK_CTRL_RESET(IMX8MP_AUDIO_BLK_CTRL_EARC_PHY_RESET, 0x200, 1), +}; + +const struct imx_blk_ctrl_dev_data imx8mp_audio_blk_ctrl_dev_data __initconst = { + .hws = imx8mp_audio_blk_ctrl_hws, + .hws_num = ARRAY_SIZE(imx8mp_audio_blk_ctrl_hws), + .clocks_max = IMX8MP_CLK_AUDIO_BLK_CTRL_END, + .resets_max = IMX8MP_AUDIO_BLK_CTRL_RESET_NUM, + .pm_runtime_saved_regs_num = 16, + .pm_runtime_saved_regs = { + IMX_AUDIO_BLK_CTRL_CLKEN0, + IMX_AUDIO_BLK_CTRL_CLKEN1, + IMX_AUDIO_BLK_CTRL_EARC, + IMX_AUDIO_BLK_CTRL_SAI1_MCLK_SEL, + IMX_AUDIO_BLK_CTRL_SAI2_MCLK_SEL, + IMX_AUDIO_BLK_CTRL_SAI3_MCLK_SEL, + IMX_AUDIO_BLK_CTRL_SAI5_MCLK_SEL, + IMX_AUDIO_BLK_CTRL_SAI6_MCLK_SEL, + IMX_AUDIO_BLK_CTRL_SAI7_MCLK_SEL, + IMX_AUDIO_BLK_CTRL_PDM_CLK, + IMX_AUDIO_BLK_CTRL_SAI_PLL_GNRL_CTL, + IMX_AUDIO_BLK_CTRL_SAI_PLL_FDIVL_CTL0, + IMX_AUDIO_BLK_CTRL_SAI_PLL_FDIVL_CTL1, + IMX_AUDIO_BLK_CTRL_SAI_PLL_SSCG_CTL, + IMX_AUDIO_BLK_CTRL_SAI_PLL_MNIT_CTL, + IMX_AUDIO_BLK_CTRL_IPG_LP_CTRL + }, +}; + static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; From patchwork Wed Jul 29 12:07:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690899 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A24CE14E3 for ; Wed, 29 Jul 2020 12:09:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8EE9620809 for ; Wed, 29 Jul 2020 12:09:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727791AbgG2MJE (ORCPT ); Wed, 29 Jul 2020 08:09:04 -0400 Received: from inva020.nxp.com ([92.121.34.13]:48080 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726957AbgG2MIa (ORCPT ); Wed, 29 Jul 2020 08:08:30 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id C2E281A1120; Wed, 29 Jul 2020 14:08:27 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id B5E621A111A; Wed, 29 Jul 2020 14:08:27 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 1AB8C2032B; Wed, 29 Jul 2020 14:08:27 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 13/17] clk: imx8mp: Add hdmi blk_ctrl clocks and resets Date: Wed, 29 Jul 2020 15:07:59 +0300 Message-Id: <1596024483-21482-14-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add hdmi blk_ctrl clocks and resets in the i.MX8MP clock driver to be picked up by the clk-blk-ctrl driver. Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-blk-ctrl.c | 4 +++ drivers/clk/imx/clk-imx8mp.c | 63 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/drivers/clk/imx/clk-blk-ctrl.c b/drivers/clk/imx/clk-blk-ctrl.c index 67cf223..cee7298 100644 --- a/drivers/clk/imx/clk-blk-ctrl.c +++ b/drivers/clk/imx/clk-blk-ctrl.c @@ -307,6 +307,10 @@ static const struct of_device_id imx_blk_ctrl_of_match[] = { .compatible = "fsl,imx8mp-audio-blk-ctrl", .data = &imx8mp_audio_blk_ctrl_dev_data }, + { + .compatible = "fsl,imx8mp-hdmi-blk-ctrl", + .data = &imx8mp_hdmi_blk_ctrl_dev_data + }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, imx_blk_ctrl_of_match); diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 00e7f5e..6b0f4ef 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -66,6 +66,61 @@ static const char * const imx_pdm_sels[] = {"pdm_root", "sai_pll_div2", "dummy", static const char * const imx_sai_pll_ref_sels[] = {"osc_24m", "dummy", "dummy", "dummy", }; static const char * const imx_sai_pll_bypass_sels[] = {"sai_pll", "sai_pll_ref_sel", }; +static const char * const imx_hdmi_phy_clks_sels[] = {"hdmi_glb_24m", "dummy", }; +static const char * const imx_lcdif_clks_sels[] = {"dummy", "hdmi_glb_pix", }; +static const char * const imx_hdmi_pipe_clks_sels[] = {"dummy", "hdmi_glb_pix", }; + +static struct imx_blk_ctrl_hw imx8mp_hdmi_blk_ctrl_hws[] = { + /* clocks */ + IMX_BLK_CTRL_CLK_GATE("hdmi_glb_apb", IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_APB_CLK, 0x40, 0, "hdmi_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_glb_b", IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_B_CLK, 0x40, 1, "hdmi_axi"), + IMX_BLK_CTRL_CLK_GATE("hdmi_glb_ref_266m", IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_REF266M_CLK, 0x40, 2, "hdmi_ref_266m"), + IMX_BLK_CTRL_CLK_GATE("hdmi_glb_24m", IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL24M_CLK, 0x40, 4, "hdmi_24m"), + IMX_BLK_CTRL_CLK_GATE("hdmi_glb_32k", IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL32K_CLK, 0x40, 5, "osc_32k"), + IMX_BLK_CTRL_CLK_GATE("hdmi_glb_pix", IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_TX_PIX_CLK, 0x40, 7, "hdmi_phy"), + IMX_BLK_CTRL_CLK_GATE("hdmi_irq_steer", IMX8MP_CLK_HDMI_BLK_CTRL_IRQS_STEER_CLK, 0x40, 9, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_noc", IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDMI_CLK, 0x40, 10, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdcp_noc", IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDCP_CLK, 0x40, 11, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("lcdif3_apb", IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_APB_CLK, 0x40, 16, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("lcdif3_b", IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_B_CLK, 0x40, 17, "hdmi_glb_b"), + IMX_BLK_CTRL_CLK_GATE("lcdif3_pdi", IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PDI_CLK, 0x40, 18, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("lcdif3_pxl", IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PIX_CLK, 0x40, 19, "hdmi_glb_pix"), + IMX_BLK_CTRL_CLK_GATE("lcdif3_spu", IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_SPU_CLK, 0x40, 20, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_fdcc_ref", IMX8MP_CLK_HDMI_BLK_CTRL_FDCC_REF_CLK, 0x50, 2, "hdmi_fdcc_tst"), + IMX_BLK_CTRL_CLK_GATE("hrv_mwr_apb", IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_APB_CLK, 0x50, 3, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hrv_mwr_b", IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_B_CLK, 0x50, 4, "hdmi_glb_axi"), + IMX_BLK_CTRL_CLK_GATE("hrv_mwr_cea", IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_CEA_CLK, 0x50, 5, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("vsfd_cea", IMX8MP_CLK_HDMI_BLK_CTRL_VSFD_CEA_CLK, 0x50, 6, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_hpi", IMX8MP_CLK_HDMI_BLK_CTRL_TX_HPI_CLK, 0x50, 13, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_apb", IMX8MP_CLK_HDMI_BLK_CTRL_TX_APB_CLK, 0x50, 14, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_cec", IMX8MP_CLK_HDMI_BLK_CTRL_TX_CEC_CLK, 0x50, 15, "hdmi_glb_32k"), + IMX_BLK_CTRL_CLK_GATE("hdmi_esm", IMX8MP_CLK_HDMI_BLK_CTRL_TX_ESM_CLK, 0x50, 16, "hdmi_glb_ref_266m"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_gpa", IMX8MP_CLK_HDMI_BLK_CTRL_TX_GPA_CLK, 0x50, 17, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_pix", IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIXEL_CLK, 0x50, 18, "hdmi_glb_pix"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_sfr", IMX8MP_CLK_HDMI_BLK_CTRL_TX_SFR_CLK, 0x50, 19, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_skp", IMX8MP_CLK_HDMI_BLK_CTRL_TX_SKP_CLK, 0x50, 20, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_tx_prep", IMX8MP_CLK_HDMI_BLK_CTRL_TX_PREP_CLK, 0x50, 21, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_phy_apb", IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_APB_CLK, 0x50, 22, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_phy_int", IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_INT_CLK, 0x50, 24, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_sec_mem", IMX8MP_CLK_HDMI_BLK_CTRL_TX_SEC_MEM_CLK, 0x50, 25, "hdmi_glb_ref_266m"), + IMX_BLK_CTRL_CLK_GATE("hdmi_trng_skp", IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_SKP_CLK, 0x50, 27, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_GATE("hdmi_vid_pix", IMX8MP_CLK_HDMI_BLK_CTRL_TX_VID_LINK_PIX_CLK, 0x50, 28, "hdmi_glb_pix"), + IMX_BLK_CTRL_CLK_GATE("hdmi_trng_apb", IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_APB_CLK, 0x50, 30, "hdmi_glb_apb"), + IMX_BLK_CTRL_CLK_MUX("hdmi_phy_sel", IMX8MP_CLK_HDMI_BLK_CTRL_HTXPHY_CLK_SEL, 0x50, 10, 1, imx_hdmi_phy_clks_sels), + IMX_BLK_CTRL_CLK_MUX("lcdif_clk_sel", IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_CLK_SEL, 0x50, 11, 1, imx_lcdif_clks_sels), + IMX_BLK_CTRL_CLK_MUX("hdmi_pipe_sel", IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIPE_CLK_SEL, 0x50, 12, 1, imx_hdmi_pipe_clks_sels), + + /* resets */ + IMX_BLK_CTRL_RESET_MASK(IMX8MP_HDMI_BLK_CTRL_HDMI_TX_RESET, 0x20, 6, 0x33), + IMX_BLK_CTRL_RESET(IMX8MP_HDMI_BLK_CTRL_HDMI_PHY_RESET, 0x20, 12), + IMX_BLK_CTRL_RESET(IMX8MP_HDMI_BLK_CTRL_HDMI_PAI_RESET, 0x20, 18), + IMX_BLK_CTRL_RESET(IMX8MP_HDMI_BLK_CTRL_HDMI_PAI_RESET, 0x20, 22), + IMX_BLK_CTRL_RESET(IMX8MP_HDMI_BLK_CTRL_HDMI_TRNG_RESET, 0x20, 20), + IMX_BLK_CTRL_RESET(IMX8MP_HDMI_BLK_CTRL_IRQ_STEER_RESET, 0x20, 16), + IMX_BLK_CTRL_RESET(IMX8MP_HDMI_BLK_CTRL_HDMI_HDCP_RESET, 0x20, 13), + IMX_BLK_CTRL_RESET_MASK(IMX8MP_HDMI_BLK_CTRL_LCDIF_RESET, 0x20, 4, 0x3), +}; + static struct imx_blk_ctrl_hw imx8mp_audio_blk_ctrl_hws[] = { /* clocks */ IMX_BLK_CTRL_CLK_MUX("sai_pll_ref_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_REF_SEL, 0x400, 0, 2, imx_sai_pll_ref_sels), @@ -131,6 +186,14 @@ static struct imx_blk_ctrl_hw imx8mp_audio_blk_ctrl_hws[] = { IMX_BLK_CTRL_RESET(IMX8MP_AUDIO_BLK_CTRL_EARC_PHY_RESET, 0x200, 1), }; +const struct imx_blk_ctrl_dev_data imx8mp_hdmi_blk_ctrl_dev_data __initconst = { + .hws = imx8mp_hdmi_blk_ctrl_hws, + .hws_num = ARRAY_SIZE(imx8mp_hdmi_blk_ctrl_hws), + .clocks_max = IMX8MP_CLK_HDMI_BLK_CTRL_END, + .resets_max = IMX8MP_HDMI_BLK_CTRL_RESET_NUM, + .pm_runtime_saved_regs_num = 0 +}; + const struct imx_blk_ctrl_dev_data imx8mp_audio_blk_ctrl_dev_data __initconst = { .hws = imx8mp_audio_blk_ctrl_hws, .hws_num = ARRAY_SIZE(imx8mp_audio_blk_ctrl_hws), From patchwork Wed Jul 29 12:08:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690893 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D3E9213B1 for ; Wed, 29 Jul 2020 12:08:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C2E8B21744 for ; Wed, 29 Jul 2020 12:08:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727001AbgG2MIc (ORCPT ); Wed, 29 Jul 2020 08:08:32 -0400 Received: from inva020.nxp.com ([92.121.34.13]:48114 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726971AbgG2MIa (ORCPT ); Wed, 29 Jul 2020 08:08:30 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 7CBFB1A01D1; Wed, 29 Jul 2020 14:08:28 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6C7521A1111; Wed, 29 Jul 2020 14:08:28 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id C52F72032B; Wed, 29 Jul 2020 14:08:27 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 14/17] clk: imx8mp: Add media blk_ctrl clocks and resets Date: Wed, 29 Jul 2020 15:08:00 +0300 Message-Id: <1596024483-21482-15-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add media blk_ctrl clocks and resets in the i.MX8MP clock driver to be picked up by the clk-blk-ctrl driver. Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-blk-ctrl.c | 4 +++ drivers/clk/imx/clk-imx8mp.c | 68 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/drivers/clk/imx/clk-blk-ctrl.c b/drivers/clk/imx/clk-blk-ctrl.c index cee7298..81fc91c 100644 --- a/drivers/clk/imx/clk-blk-ctrl.c +++ b/drivers/clk/imx/clk-blk-ctrl.c @@ -308,6 +308,10 @@ static const struct of_device_id imx_blk_ctrl_of_match[] = { .data = &imx8mp_audio_blk_ctrl_dev_data }, { + .compatible = "fsl,imx8mp-media-blk-ctrl", + .data = &imx8mp_media_blk_ctrl_dev_data + }, + { .compatible = "fsl,imx8mp-hdmi-blk-ctrl", .data = &imx8mp_hdmi_blk_ctrl_dev_data }, diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 6b0f4ef..8553032 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -121,6 +121,62 @@ static struct imx_blk_ctrl_hw imx8mp_hdmi_blk_ctrl_hws[] = { IMX_BLK_CTRL_RESET_MASK(IMX8MP_HDMI_BLK_CTRL_LCDIF_RESET, 0x20, 4, 0x3), }; +static struct imx_blk_ctrl_hw imx8mp_media_blk_ctrl_hws[] = { + /* clocks */ + IMX_BLK_CTRL_CLK_GATE("mipi_dsi_pclk", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_PCLK, 0x4, 0, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("mipi_dsi_clkref", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_CLKREF, 0x4, 1, "media_mipi_phy1_ref"), + IMX_BLK_CTRL_CLK_GATE("mipi_csi_pclk", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_PCLK, 0x4, 2, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("mipi_csi_aclk", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_ACLK, 0x4, 3, "media_cam1_pix_root_clk"), + IMX_BLK_CTRL_CLK_GATE("lcdif_pixel_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_PIXEL, 0x4, 4, "media_disp1_pix_root_clk"), + IMX_BLK_CTRL_CLK_GATE("lcdif_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_APB, 0x4, 5, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("isi_proc_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_PROC, 0x4, 6, "media_axi_root_clk"), + IMX_BLK_CTRL_CLK_GATE("isi_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_APB, 0x4, 7, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("bus_blk_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_BUS_BLK, 0x4, 8, "media_axi_root_clk"), + IMX_BLK_CTRL_CLK_GATE("mipi_csi2_pclk", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_PCLK, 0x4, 9, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("mipi_csi2_aclk", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_ACLK, 0x4, 10, "media_cam2_pix_root_clk"), + IMX_BLK_CTRL_CLK_GATE("lcdif2_pixel_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_PIXEL, 0x4, 11, "media_disp2_pix_root_clk"), + IMX_BLK_CTRL_CLK_GATE("lcdif2_apb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_APB, 0x4, 12, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("isp1_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_COR, 0x4, 13, "media_isp_root_clk"), + IMX_BLK_CTRL_CLK_GATE("isp1_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AXI, 0x4, 14, "media_axi_root_clk"), + IMX_BLK_CTRL_CLK_GATE("isp1_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AHB, 0x4, 15, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("isp0_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_COR, 0x4, 16, "media_isp_root_clk"), + IMX_BLK_CTRL_CLK_GATE("isp0_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AXI, 0x4, 17, "media_axi_root_clk"), + IMX_BLK_CTRL_CLK_GATE("isp0_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AHB, 0x4, 18, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("dwe_cor_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_COR, 0x4, 19, "media_axi_root_clk"), + IMX_BLK_CTRL_CLK_GATE("dwe_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AXI, 0x4, 20, "media_axi_root_clk"), + IMX_BLK_CTRL_CLK_GATE("dwe_ahb_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AHB, 0x4, 21, "media_apb_root_clk"), + IMX_BLK_CTRL_CLK_GATE("mipi_dsi2_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI2, 0x4, 22, "media_mipi_phy1_ref"), + IMX_BLK_CTRL_CLK_GATE("lcdif_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_AXI, 0x4, 23, "media_axi_root_clk"), + IMX_BLK_CTRL_CLK_GATE("lcdif2_axi_clk", IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_AXI, 0x4, 24, "media_axi_root_clk"), + + /* resets */ + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI_PCLK, 0, 0), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI_CLKREF, 0, 1), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_PCLK, 0, 2), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_ACLK, 0, 3), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_PIXEL, 0, 4), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_APB, 0, 5), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_PROC, 0, 6), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_APB, 0, 7), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_BUS_BLK, 0, 8), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_PCLK, 0, 9), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_ACLK, 0, 10), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_PIXEL, 0, 11), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_APB, 0, 12), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_COR, 0, 13), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_AXI, 0, 14), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_AHB, 0, 15), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_COR, 0, 16), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_AXI, 0, 17), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_AHB, 0, 18), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_COR, 0, 19), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_AXI, 0, 20), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_AHB, 0, 21), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI2, 0, 22), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_AXI, 0, 23), + IMX_BLK_CTRL_RESET(IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_AXI, 0, 24) +}; + static struct imx_blk_ctrl_hw imx8mp_audio_blk_ctrl_hws[] = { /* clocks */ IMX_BLK_CTRL_CLK_MUX("sai_pll_ref_sel", IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_REF_SEL, 0x400, 0, 2, imx_sai_pll_ref_sels), @@ -194,6 +250,18 @@ const struct imx_blk_ctrl_dev_data imx8mp_hdmi_blk_ctrl_dev_data __initconst = { .pm_runtime_saved_regs_num = 0 }; +const struct imx_blk_ctrl_dev_data imx8mp_media_blk_ctrl_dev_data __initconst = { + .hws = imx8mp_media_blk_ctrl_hws, + .hws_num = ARRAY_SIZE(imx8mp_media_blk_ctrl_hws), + .clocks_max = IMX8MP_CLK_MEDIA_BLK_CTRL_END, + .resets_max = IMX8MP_MEDIA_BLK_CTRL_RESET_NUM, + .pm_runtime_saved_regs_num = 2, + .pm_runtime_saved_regs = { + IMX_MEDIA_BLK_CTRL_SFT_RSTN, + IMX_MEDIA_BLK_CTRL_CLK_EN, + }, +}; + const struct imx_blk_ctrl_dev_data imx8mp_audio_blk_ctrl_dev_data __initconst = { .hws = imx8mp_audio_blk_ctrl_hws, .hws_num = ARRAY_SIZE(imx8mp_audio_blk_ctrl_hws), From patchwork Wed Jul 29 12:08:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690897 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 767B714E3 for ; Wed, 29 Jul 2020 12:09:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5F6422083B for ; Wed, 29 Jul 2020 12:09:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726993AbgG2MIb (ORCPT ); Wed, 29 Jul 2020 08:08:31 -0400 Received: from inva020.nxp.com ([92.121.34.13]:48130 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726976AbgG2MIb (ORCPT ); Wed, 29 Jul 2020 08:08:31 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 39B081A111A; Wed, 29 Jul 2020 14:08:29 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2CAAF1A1111; Wed, 29 Jul 2020 14:08:29 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 7CEFA2032B; Wed, 29 Jul 2020 14:08:28 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 15/17] arm64: dts: imx8mp: Add audio_blk_ctrl node Date: Wed, 29 Jul 2020 15:08:01 +0300 Message-Id: <1596024483-21482-16-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Some of the features of the audio_ctrl will be used by some different drivers in a way those drivers will know best, so adding the syscon compatible we allow those to do just that. Only the resets and the clocks are registered bit the clk-blk-ctrl driver. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index daa1769..b985875 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -736,6 +736,23 @@ }; }; + aips5: bus@30c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + audio_blk_ctrl: audio-blk-ctrl@30e20000 { + compatible = "fsl,imx8mp-audio-blk-ctrl", "syscon"; + reg = <0x30e20000 0x50C>; + power-domains = <&audiomix_pd>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, From patchwork Wed Jul 29 12:08:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690895 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 426F613B1 for ; Wed, 29 Jul 2020 12:09:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 355AF22BF5 for ; Wed, 29 Jul 2020 12:09:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726353AbgG2MI7 (ORCPT ); Wed, 29 Jul 2020 08:08:59 -0400 Received: from inva021.nxp.com ([92.121.34.21]:37972 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726984AbgG2MIb (ORCPT ); Wed, 29 Jul 2020 08:08:31 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id ECEA7200FBB; Wed, 29 Jul 2020 14:08:29 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id E0904200FAB; Wed, 29 Jul 2020 14:08:29 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 3C1BF2032B; Wed, 29 Jul 2020 14:08:29 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 16/17] arm64: dts: imx8mp: Add media_blk_ctrl node Date: Wed, 29 Jul 2020 15:08:02 +0300 Message-Id: <1596024483-21482-17-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Some of the features of the media_ctrl will be used by some different drivers in a way those drivers will know best, so adding the syscon compatible we allow those to do just that. Only the resets and the clocks are registered bit the clk-blk-ctrl driver. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index b985875..172c548 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -736,6 +736,23 @@ }; }; + aips4: bus@32c00000 { + compatible = "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + media_blk_ctrl: media-blk-ctrl@32ec0000 { + compatible = "fsl,imx8mp-media-blk-ctrl", "syscon"; + reg = <0x32ec0000 0x10000>; + power-domains = <&mediamix_pd>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; + aips5: bus@30c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30c00000 0x400000>; From patchwork Wed Jul 29 12:08:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 11690889 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 109DA14E3 for ; Wed, 29 Jul 2020 12:08:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EC26D22CB2 for ; Wed, 29 Jul 2020 12:08:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727008AbgG2MIc (ORCPT ); Wed, 29 Jul 2020 08:08:32 -0400 Received: from inva021.nxp.com ([92.121.34.21]:37816 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726707AbgG2MIb (ORCPT ); Wed, 29 Jul 2020 08:08:31 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id AE520200FDB; Wed, 29 Jul 2020 14:08:30 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 9EF25200FAB; Wed, 29 Jul 2020 14:08:30 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id EF1E52032B; Wed, 29 Jul 2020 14:08:29 +0200 (CEST) From: Abel Vesa To: Mike Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Philipp Zabel , Anson Huang , Dong Aisheng , Peng Fan , Fugang Duan Cc: NXP Linux Team , linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: [PATCH 17/17] arm64: dts: imx8mp: Add hdmi_blk_ctrl node Date: Wed, 29 Jul 2020 15:08:03 +0300 Message-Id: <1596024483-21482-18-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> References: <1596024483-21482-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Some of the features of the hdmi_ctrl will be used by some different drivers in a way those drivers will know best, so adding the syscon compatible we allow those to do just that. Only the resets and the clocks are registered bit the clk-blk-ctrl driver. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 172c548..5a76c4d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -751,6 +751,15 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + hdmi_blk_ctrl: hdmi-blk-ctrl@32fc0000 { + compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; + reg = <0x32fc0000 0x1000>; + power-domains = <&hdmimix_pd>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; }; aips5: bus@30c00000 {