From patchwork Thu Jul 30 00:48:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 11692105 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B904D1392 for ; Thu, 30 Jul 2020 00:48:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A1FDE2072A for ; Thu, 30 Jul 2020 00:48:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A1FDE2072A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E1476E820; Thu, 30 Jul 2020 00:48:29 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6DBB66E820 for ; Thu, 30 Jul 2020 00:48:28 +0000 (UTC) IronPort-SDR: 5tBipHK5fk9pNQDPOwTfSytnISCXuvX7vihzRYx9K6YlP6ouDewypkB0zo8WAzmWJYJk//JQsM PPDvAWnY1IUw== X-IronPort-AV: E=McAfee;i="6000,8403,9697"; a="152751066" X-IronPort-AV: E=Sophos;i="5.75,412,1589266800"; d="scan'208";a="152751066" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2020 17:48:27 -0700 IronPort-SDR: DcvTXvpTbYtxrlvMhX/Aw/G0NNU460HK256G75mysLR/CIfKM0iRw6HygGDCDhXomBbt414EDb Y27tmQh2ooiA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,412,1589266800"; d="scan'208";a="274032919" Received: from orsosgc001.ra.intel.com ([10.23.184.150]) by fmsmga008.fm.intel.com with ESMTP; 29 Jul 2020 17:48:27 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org Date: Wed, 29 Jul 2020 17:48:21 -0700 Message-Id: <20200730004826.8415-2-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200730004826.8415-1-umesh.nerlige.ramappa@intel.com> References: <20200730004826.8415-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/6] drm/i915: Allow removal of whitelist register and refactor X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" - Add a helper to remove whitelisted register from the list. - Refactor _wa_add to use _wa_index to find an existing whitelisted register. - Free the old list when growing the whitelist. Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 82 +++++++++++++++------ 1 file changed, 58 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index cef1c122696f..98927f5d63ab 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -81,10 +81,49 @@ static void wa_init_finish(struct i915_wa_list *wal) wal->wa_count, wal->name, wal->engine_name); } +static int _wa_index(struct i915_wa_list *wal, i915_reg_t reg) +{ + unsigned int addr = i915_mmio_reg_offset(reg); + int start = 0, end = wal->count; + + while (start < end) { + int mid = start + (end - start) / 2; + unsigned int wal_reg = i915_mmio_reg_offset(wal->list[mid].reg); + + wal_reg &= RING_FORCE_TO_NONPRIV_ADDRESS_MASK; + + if (wal_reg < addr) + start = mid + 1; + else if (wal_reg > addr) + end = mid; + else + return mid; + } + + return -1; +} + +static void _wa_remove(struct i915_wa_list *wal, i915_reg_t reg) +{ + int index = _wa_index(wal, reg); + struct i915_wa *wa = wal->list; + + if (index < 0) + return; + + memset(wa + index, 0, sizeof(*wa)); + + while (index < wal->count - 1) { + swap(wa[index], wa[index + 1]); + index++; + } + + wal->count--; +} + static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) { - unsigned int addr = i915_mmio_reg_offset(wa->reg); - unsigned int start = 0, end = wal->count; + int index; const unsigned int grow = WA_LIST_CHUNK; struct i915_wa *wa_; @@ -100,36 +139,31 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) return; } - if (wal->list) + if (wal->list) { memcpy(list, wal->list, sizeof(*wa) * wal->count); + kfree(wal->list); + } wal->list = list; } - while (start < end) { - unsigned int mid = start + (end - start) / 2; + index = _wa_index(wal, wa->reg); + if (index >= 0) { + wa_ = &wal->list[index]; - if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { - start = mid + 1; - } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { - end = mid; - } else { - wa_ = &wal->list[mid]; - - if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { - DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", - i915_mmio_reg_offset(wa_->reg), - wa_->clr, wa_->set); - - wa_->set &= ~wa->clr; - } + if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { + DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", + i915_mmio_reg_offset(wa_->reg), + wa_->clr, wa_->set); - wal->wa_count++; - wa_->set |= wa->set; - wa_->clr |= wa->clr; - wa_->read |= wa->read; - return; + wa_->set &= ~wa->clr; } + + wal->wa_count++; + wa_->set |= wa->set; + wa_->clr |= wa->clr; + wa_->read |= wa->read; + return; } wal->wa_count++; From patchwork Thu Jul 30 00:48:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 11692109 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 228106C1 for ; Thu, 30 Jul 2020 00:48:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0B5242072A for ; Thu, 30 Jul 2020 00:48:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0B5242072A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 22E496E824; Thu, 30 Jul 2020 00:48:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 979DD6E821 for ; Thu, 30 Jul 2020 00:48:28 +0000 (UTC) IronPort-SDR: B0F9i1GcdZw3EW8ZjykjvBNp9aL5gEM9VcUfAs9j9h7NM9AOITCFQg73aOupsSI/EZrMg0TDd3 Qdg5IZioJ/3g== X-IronPort-AV: E=McAfee;i="6000,8403,9697"; a="152751068" X-IronPort-AV: E=Sophos;i="5.75,412,1589266800"; d="scan'208";a="152751068" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2020 17:48:27 -0700 IronPort-SDR: Y69vzDztj3/WlrAxJxjTDXHEtE0CXnLWlA2tvfwHjREXjnBFEbAWJbjBOJKv7ltv8RIjE2/rYD bo85UvPGmSDA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,412,1589266800"; d="scan'208";a="274032922" Received: from orsosgc001.ra.intel.com ([10.23.184.150]) by fmsmga008.fm.intel.com with ESMTP; 29 Jul 2020 17:48:27 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org Date: Wed, 29 Jul 2020 17:48:22 -0700 Message-Id: <20200730004826.8415-3-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200730004826.8415-1-umesh.nerlige.ramappa@intel.com> References: <20200730004826.8415-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/selftests: Clear flags when using wa->reg for comparison X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The flags field of the wa->reg has whitelist settings as opposed to the value returned from i915_mmio_reg_offset(reg). Clear the flags before compare. Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/gt/selftest_workarounds.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index febc9e6692ba..3753f65f62b1 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -918,6 +918,9 @@ static bool find_reg(struct drm_i915_private *i915, { u32 offset = i915_mmio_reg_offset(reg); + /* Clear non priv flags */ + offset &= RING_FORCE_TO_NONPRIV_ADDRESS_MASK; + while (count--) { if (INTEL_INFO(i915)->gen_mask & tbl->gen_mask && i915_mmio_reg_offset(tbl->reg) == offset) From patchwork Thu Jul 30 00:48:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 11692113 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 40D351392 for ; Thu, 30 Jul 2020 00:48:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 29C332072A for ; Thu, 30 Jul 2020 00:48:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 29C332072A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E12CB6E827; Thu, 30 Jul 2020 00:48:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id C100C6E820 for ; Thu, 30 Jul 2020 00:48:28 +0000 (UTC) IronPort-SDR: isUKq+HrGUdfZv0Q+1BYo2c8vMXo9Wd1hInTz5zFZAN7hDZv1WbDnir7o7vAT1jlNkjwbq/wXA rjKBdhZVWuFA== X-IronPort-AV: E=McAfee;i="6000,8403,9697"; a="152751069" X-IronPort-AV: E=Sophos;i="5.75,412,1589266800"; d="scan'208";a="152751069" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2020 17:48:28 -0700 IronPort-SDR: iVmrhtayURLv56xjemP4vOGliAhwCdG1Khte5H1tmxljN83X7kClGffcmjklgVZR2NyTzxM4tl uXPMrwNGAGfA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,412,1589266800"; d="scan'208";a="274032926" Received: from orsosgc001.ra.intel.com ([10.23.184.150]) by fmsmga008.fm.intel.com with ESMTP; 29 Jul 2020 17:48:27 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org Date: Wed, 29 Jul 2020 17:48:23 -0700 Message-Id: <20200730004826.8415-4-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200730004826.8415-1-umesh.nerlige.ramappa@intel.com> References: <20200730004826.8415-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/perf: Ensure observation logic is not clock gated X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Piotr Maciejewski A clock gating switch can control if the performance monitoring and observation logic is enaled or not. Ensure that we enable the clocks. v2: Separate code from other patches (Lionel) v3: Reset PMON enable when disabling perf to save power (Lionel) Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL") Signed-off-by: Piotr Maciejewski Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_perf.c | 13 +++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index c6f6370283cf..fe408c327d3c 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -2493,6 +2493,14 @@ gen12_enable_metric_set(struct i915_perf_stream *stream, (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT)) : 0); + /* + * Initialize Super Queue Internal Cnt Register + * Set PMON Enable in order to collect valid metrics. + */ + intel_uncore_write(uncore, GEN12_SQCNT1, + intel_uncore_read(uncore, GEN12_SQCNT1) | + GEN12_SQCNT1_PMON_ENABLE); + /* * Update all contexts prior writing the mux configurations as we need * to make sure all slices/subslices are ON before writing to NOA @@ -2552,6 +2560,11 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream) /* Make sure we disable noa to save power. */ intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0); + + /* Reset PMON Enable to save power. */ + intel_uncore_write(uncore, GEN12_SQCNT1, + intel_uncore_read(uncore, GEN12_SQCNT1) & + ~GEN12_SQCNT1_PMON_ENABLE); } static void gen7_oa_enable(struct i915_perf_stream *stream) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a0d31f3bf634..9cc3e312b6b7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -696,6 +696,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define OABUFFER_SIZE_16M (7 << 3) #define GEN12_OA_TLB_INV_CR _MMIO(0xceec) +#define GEN12_SQCNT1 _MMIO(0x8718) +#define GEN12_SQCNT1_PMON_ENABLE (1 << 30) /* Gen12 OAR unit */ #define GEN12_OAR_OACONTROL _MMIO(0x2960) From patchwork Thu Jul 30 00:48:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 11692111 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 392DF6C1 for ; Thu, 30 Jul 2020 00:48:37 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2200D2072A for ; Thu, 30 Jul 2020 00:48:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2200D2072A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8FE826E826; Thu, 30 Jul 2020 00:48:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id F04916E822 for ; Thu, 30 Jul 2020 00:48:28 +0000 (UTC) IronPort-SDR: AzJy2HZBaCryg2AtYwC2v4/krmZ4SR/cQ3928yiHF4jeLat2B85Q8e6amsQ20wDSDTRVWJyJdh A+l5LOG1/CHA== X-IronPort-AV: E=McAfee;i="6000,8403,9697"; a="152751070" X-IronPort-AV: E=Sophos;i="5.75,412,1589266800"; d="scan'208";a="152751070" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2020 17:48:28 -0700 IronPort-SDR: FM3+xBv5BOCrRYjew9ijY/w0RNh7NKX0QD5cxAmwyqIyJesOx0Hqb00neP8BdlNflMpkYCydzy 0zXhnjY4Z1uQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,412,1589266800"; d="scan'208";a="274032929" Received: from orsosgc001.ra.intel.com ([10.23.184.150]) by fmsmga008.fm.intel.com with ESMTP; 29 Jul 2020 17:48:27 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org Date: Wed, 29 Jul 2020 17:48:24 -0700 Message-Id: <20200730004826.8415-5-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200730004826.8415-1-umesh.nerlige.ramappa@intel.com> References: <20200730004826.8415-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/6] drm/i915/perf: Whitelist OA report trigger registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Piotr Maciejewski OA reports can be triggered into the OA buffer by writing into the OAREPORTTRIG registers. Whitelist the registers to allow non-privileged user to trigger reports. Whitelist registers only if perf_stream_paranoid is set to 0. In i915_perf_open_ioctl, this setting is checked and the whitelist is enabled accordingly. On closing the perf fd, the whitelist is removed. This ensures that the access to the whitelist is gated by perf_stream_paranoid. v2: - Move related change to this patch (Lionel) - Bump up perf revision (Lionel) v3: Pardon whitelisted registers for selftest (Umesh) v4: Document supported gens for the feature (Lionel) v5: Whitelist registers only if perf_stream_paranoid is set to 0 (Jon) Signed-off-by: Piotr Maciejewski Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Lionel Landwerlin --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 67 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_workarounds.h | 3 + drivers/gpu/drm/i915/i915_perf.c | 33 +++++++++- drivers/gpu/drm/i915/i915_perf_types.h | 5 ++ 4 files changed, 105 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 98927f5d63ab..e096282ad547 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1671,6 +1671,73 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine) i915_mmio_reg_offset(RING_NOPID(base))); } +struct i915_oa_wl { + i915_reg_t reg; + u32 flags; +} gen9_oa_regs[] = { + { OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW }, + { OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW }, +}, gen12_oa_regs[] = { + { GEN12_OAG_OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW }, + { GEN12_OAG_OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW }, +}; + +static void whitelist_delete_perf_counters(struct i915_wa_list *wal, + struct i915_oa_wl *regs, + int count) +{ + while (count--) { + _wa_remove(wal, regs->reg); + regs++; + } + + wa_init_finish(wal); +} + +static void whitelist_build_perf_counters(struct i915_wa_list *wal, + struct i915_oa_wl *regs, + int count) +{ + while (count--) { + whitelist_reg_ext(wal, regs->reg, regs->flags); + regs++; + } +} + +void intel_engine_apply_oa_whitelist(struct intel_engine_cs *engine) +{ + struct i915_wa_list *w = &engine->whitelist; + struct drm_i915_private *i915 = engine->i915; + + if (IS_GEN(i915, 12)) + whitelist_build_perf_counters(w, gen12_oa_regs, + ARRAY_SIZE(gen12_oa_regs)); + else if (INTEL_GEN(i915) > 8) + whitelist_build_perf_counters(w, gen9_oa_regs, + ARRAY_SIZE(gen9_oa_regs)); + else + return; + + intel_engine_apply_whitelist(engine); +} + +void intel_engine_remove_oa_whitelist(struct intel_engine_cs *engine) +{ + struct i915_wa_list *w = &engine->whitelist; + struct drm_i915_private *i915 = engine->i915; + + if (IS_GEN(i915, 12)) + whitelist_delete_perf_counters(w, gen12_oa_regs, + ARRAY_SIZE(gen12_oa_regs)); + else if (INTEL_GEN(i915) > 8) + whitelist_delete_perf_counters(w, gen9_oa_regs, + ARRAY_SIZE(gen9_oa_regs)); + else + return; + + intel_engine_apply_whitelist(engine); +} + static void rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.h b/drivers/gpu/drm/i915/gt/intel_workarounds.h index 8c9c769c2204..5ad3f44f615d 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.h +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.h @@ -32,6 +32,9 @@ bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from); void intel_engine_init_whitelist(struct intel_engine_cs *engine); void intel_engine_apply_whitelist(struct intel_engine_cs *engine); +void intel_engine_apply_oa_whitelist(struct intel_engine_cs *engine); +void intel_engine_remove_oa_whitelist(struct intel_engine_cs *engine); + void intel_engine_init_workarounds(struct intel_engine_cs *engine); void intel_engine_apply_workarounds(struct intel_engine_cs *engine); int intel_engine_verify_workarounds(struct intel_engine_cs *engine, diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index fe408c327d3c..0e2313d50c91 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -201,6 +201,7 @@ #include "gt/intel_gt.h" #include "gt/intel_lrc_reg.h" #include "gt/intel_ring.h" +#include "gt/intel_workarounds.h" #include "i915_drv.h" #include "i915_perf.h" @@ -1353,6 +1354,9 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) BUG_ON(stream != perf->exclusive_stream); + if (stream->oa_whitelisted) + intel_engine_remove_oa_whitelist(stream->engine); + /* * Unset exclusive_stream first, it will be checked while disabling * the metric set on gen8+. @@ -1448,7 +1452,8 @@ static void gen8_init_oa_buffer(struct i915_perf_stream *stream) * bit." */ intel_uncore_write(uncore, GEN8_OABUFFER, gtt_offset | - OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT); + OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT | + GEN7_OABUFFER_EDGE_TRIGGER); intel_uncore_write(uncore, GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK); /* Mark that we need updated tail pointers to read from... */ @@ -1501,7 +1506,8 @@ static void gen12_init_oa_buffer(struct i915_perf_stream *stream) * bit." */ intel_uncore_write(uncore, GEN12_OAG_OABUFFER, gtt_offset | - OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT); + OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT | + GEN7_OABUFFER_EDGE_TRIGGER); intel_uncore_write(uncore, GEN12_OAG_OATAILPTR, gtt_offset & GEN12_OAG_OATAILPTR_MASK); @@ -3474,6 +3480,22 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf, if (!(param->flags & I915_PERF_FLAG_DISABLED)) i915_perf_enable_locked(stream); + /* + * OA whitelist allows non-privileged access to some OA counters for + * triggering reports into the OA buffer. This is only allowed if + * perf_stream_paranoid is set to 0 by the sysadmin. + * + * We want to make sure this is almost the last thing we do before + * returning the stream fd. If we do end up checking for errors in code + * that follows this, we MUST call intel_engine_remove_oa_whitelist in + * the error handling path to remove the whitelisted registers. + */ + if (!i915_perf_stream_paranoid && + props->sample_flags & SAMPLE_OA_REPORT) { + intel_engine_apply_oa_whitelist(stream->engine); + stream->oa_whitelisted = true; + } + /* Take a reference on the driver that will be kept with stream_fd * until its release. */ @@ -4445,8 +4467,13 @@ int i915_perf_ioctl_version(void) * * 5: Add DRM_I915_PERF_PROP_POLL_OA_PERIOD parameter that controls the * interval for the hrtimer used to check for OA data. + * + * 6: Whitelist OATRIGGER registers to allow user to trigger reports + * into the OA buffer. This applies only to gen8+. The feature can + * only be accessed if perf_stream_paranoid is set to 0 by privileged + * user. */ - return 5; + return 6; } #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h index a36a455ae336..35f8240fd6ce 100644 --- a/drivers/gpu/drm/i915/i915_perf_types.h +++ b/drivers/gpu/drm/i915/i915_perf_types.h @@ -311,6 +311,11 @@ struct i915_perf_stream { * buffer should be checked for available data. */ u64 poll_oa_period; + + /** + * @oa_whitelisted: Indicates that the oa registers are whitelisted. + */ + bool oa_whitelisted; }; /** From patchwork Thu Jul 30 00:48:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 11692115 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A54E6C1 for ; Thu, 30 Jul 2020 00:48:39 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2337A2072A for ; Thu, 30 Jul 2020 00:48:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2337A2072A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 020006E823; Thu, 30 Jul 2020 00:48:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 25D876E820 for ; Thu, 30 Jul 2020 00:48:29 +0000 (UTC) IronPort-SDR: l9OLngAASbsaqSzmvli9krLRbVW8l35F8lqP0hGzbhZb0LGbD5yZeG9uzrTJ8hV2DU3kf7Bn29 B24HAautWgwA== X-IronPort-AV: E=McAfee;i="6000,8403,9697"; a="152751071" X-IronPort-AV: E=Sophos;i="5.75,412,1589266800"; d="scan'208";a="152751071" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2020 17:48:28 -0700 IronPort-SDR: iZXkxph88fMcGCZsWvH+sCUBQfL1HE31s++SsZud3cjF2GCzsaH2KCPSSGJYMQidmeUBznbLUC 5UzjH8bTZeOQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,412,1589266800"; d="scan'208";a="274032932" Received: from orsosgc001.ra.intel.com ([10.23.184.150]) by fmsmga008.fm.intel.com with ESMTP; 29 Jul 2020 17:48:28 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org Date: Wed, 29 Jul 2020 17:48:25 -0700 Message-Id: <20200730004826.8415-6-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200730004826.8415-1-umesh.nerlige.ramappa@intel.com> References: <20200730004826.8415-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/6] drm/i915/perf: Whitelist OA counter and buffer registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Piotr Maciejewski It is useful to have markers in the OA reports to identify triggered reports. Whitelist some OA counters that can be used as markers. A triggered report can be found faster if we can sample the HW tail and head registers when the report was triggered. Whitelist OA buffer specific registers. v2: - Bump up the perf revision (Lionel) - Use indexing for counters (Lionel) - Fix selftest for oa ticking register (Umesh) v3: Pardon whitelisted registers for selftest (Umesh) v4: - Document whitelisted registers (Lionel) - Fix live isolated whitelist for OA regs (Umesh) v5: - Free up whitelist slots. Remove GPU_TICKS and A20 counter (Piotr) - Whitelist registers only if perf_stream_paranoid is set to 0 (Jon) Signed-off-by: Piotr Maciejewski Signed-off-by: Umesh Nerlige Ramappa Reviewed-by: Lionel Landwerlin --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++ drivers/gpu/drm/i915/i915_perf.c | 10 +++++++++- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index e096282ad547..f4bd15d6b75f 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1677,9 +1677,17 @@ struct i915_oa_wl { } gen9_oa_regs[] = { { OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW }, { OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW }, + { OA_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW | + RING_FORCE_TO_NONPRIV_RANGE_4 }, + { GEN8_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD | + RING_FORCE_TO_NONPRIV_RANGE_4 }, }, gen12_oa_regs[] = { { GEN12_OAG_OAREPORTTRIG2, RING_FORCE_TO_NONPRIV_ACCESS_RW }, { GEN12_OAG_OAREPORTTRIG6, RING_FORCE_TO_NONPRIV_ACCESS_RW }, + { GEN12_OAG_PERF_COUNTER_A(18), RING_FORCE_TO_NONPRIV_ACCESS_RW | + RING_FORCE_TO_NONPRIV_RANGE_4 }, + { GEN12_OAG_OASTATUS, RING_FORCE_TO_NONPRIV_ACCESS_RD | + RING_FORCE_TO_NONPRIV_RANGE_4 }, }; static void whitelist_delete_perf_counters(struct i915_wa_list *wal, diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 0e2313d50c91..9b55521cb09b 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -4472,8 +4472,16 @@ int i915_perf_ioctl_version(void) * into the OA buffer. This applies only to gen8+. The feature can * only be accessed if perf_stream_paranoid is set to 0 by privileged * user. + * + * 7: Whitelist below OA registers for user to identify the location of + * triggered reports in the OA buffer. This applies only to gen8+. + * The feature can only be accessed if perf_stream_paranoid is set to + * 0 by privileged user. + * + * - OA buffer head/tail/status/buffer registers for read only + * - OA counters A18, A19, A20 for read/write */ - return 6; + return 7; } #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9cc3e312b6b7..6b30f076d8eb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -974,6 +974,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 #define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 +/* Performance counters registers */ +#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx)) +#define OA_PERF_COUNTER_A_UPPER(idx) _MMIO(0x2800 + 8 * (idx) + 4) + +/* Gen12 Performance counters registers */ +#define GEN12_OAG_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx)) +#define GEN12_OAG_PERF_COUNTER_A_UPPER(idx) _MMIO(0xD980 + 8 * (idx) + 4) + /* Same layout as OASTARTTRIGX */ #define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900) #define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904) From patchwork Thu Jul 30 00:48:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umesh Nerlige Ramappa X-Patchwork-Id: 11692107 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 674CE6C1 for ; Thu, 30 Jul 2020 00:48:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 500E72072A for ; Thu, 30 Jul 2020 00:48:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 500E72072A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6B4546E822; Thu, 30 Jul 2020 00:48:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id E21CB6E821 for ; Thu, 30 Jul 2020 00:48:28 +0000 (UTC) IronPort-SDR: hbzZSTbjV5Je7OT31FUxxjhwq2vVYUNuOQSACdUxL3B1igZqHTx/5UhQ++tSx1/tUXu4w52dC/ 8PA6qSNKd8bA== X-IronPort-AV: E=McAfee;i="6000,8403,9697"; a="148983719" X-IronPort-AV: E=Sophos;i="5.75,412,1589266800"; d="scan'208";a="148983719" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2020 17:48:27 -0700 IronPort-SDR: LDCY2FuxpeW0d8fR5mhTicS9T6s+ESmPDunWrmwTrj+7M8CO7KO1ytrAp2k0rMNizKyVdnq2vs TmSpV8N29Ksw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,412,1589266800"; d="scan'208";a="274032935" Received: from orsosgc001.ra.intel.com ([10.23.184.150]) by fmsmga008.fm.intel.com with ESMTP; 29 Jul 2020 17:48:28 -0700 From: Umesh Nerlige Ramappa To: intel-gfx@lists.freedesktop.org Date: Wed, 29 Jul 2020 17:48:26 -0700 Message-Id: <20200730004826.8415-7-umesh.nerlige.ramappa@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200730004826.8415-1-umesh.nerlige.ramappa@intel.com> References: <20200730004826.8415-1-umesh.nerlige.ramappa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/perf: Map OA buffer to user space for gen12 performance query X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Piotr Maciejewski i915 used to support time based sampling mode which is good for overall system monitoring, but is not enough for query mode used to measure a single draw call or dispatch. Gen9-Gen11 are using current i915 perf implementation for query, but Gen12+ requires a new approach for query based on triggered reports within oa buffer. Triggering reports into the OA buffer is achieved by writing into a a trigger register. Optionally an unused counter/register is set with a marker value such that a triggered report can be identified in the OA buffer. Reports are usually triggered at the start and end of work that is measured. Since OA buffer is large and queries can be frequent, an efficient way to look for triggered reports is required. By knowing the current head and tail offsets into the OA buffer, it is easier to determine the locality of the reports of interest. Current perf OA interface does not expose head/tail information to the user and it filters out invalid reports before sending data to user. Also considering limited size of user buffer used during a query, creating a 1:1 copy of the OA buffer at the user space added undesired complexity. The solution was to map the OA buffer to user space provided (1) that it is accessed from a privileged user. (2) OA report filtering is not used. These 2 conditions would satisfy the safety criteria that the current perf interface addresses. To enable the query: - Add an ioctl to expose head and tail to the user - Add an ioctl to return size and offset of the OA buffer - Map the OA buffer to the user space v2: - Improve commit message (Chris) - Do not mmap based on gem object filp. Instead, use perf_fd and support mmap syscall (Chris) - Pass non-zero offset in mmap to enforce the right object is mapped (Chris) - Do not expose gpu_address (Chris) - Verify start and length of vma for page alignment (Lionel) - Move SQNTL config out (Lionel) v3: (Chris) - Omit redundant checks - Return VM_FAULT_SIGBUS is old stream is closed - Maintain reference counts to stream in vm_open and vm_close - Use switch to identify object to be mapped v4: Call kref_put on closing perf fd (Chris) v5: - Strip access to OA buffer from unprivileged child of a privileged parent. Use VM_DONTCOPY - Enforce MAP_PRIVATE by checking for VM_MAYSHARE v6: (Chris) - Use len of -1 in unmap_mapping_range - Don't use stream->oa_buffer.vma->obj in vm_fault_oa - Use kernel block comment style - do_mmap gets a reference to the file and puts it in do_munmap, so no need to maintain a reference to i915_perf_stream. Hence, remove vm_open/vm_close and stream->closed hooks/checks. (Umesh) - Do not allow mmap if SAMPLE_OA_REPORT is not set during i915_perf_open_ioctl. - Drop ioctl returning head/tail since this information is already whitelisted. Remove hooks to read head register. Signed-off-by: Piotr Maciejewski Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_mman.h | 2 + drivers/gpu/drm/i915/i915_perf.c | 117 ++++++++++++++++++++++- include/uapi/drm/i915_drm.h | 16 ++++ 4 files changed, 135 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index b23368529a40..7c4b9b0c334b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -204,7 +204,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj, return view; } -static vm_fault_t i915_error_to_vmf_fault(int err) +vm_fault_t i915_error_to_vmf_fault(int err) { switch (err) { default: diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.h b/drivers/gpu/drm/i915/gem/i915_gem_mman.h index efee9e0d2508..1190a3a228ea 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.h @@ -29,4 +29,6 @@ void i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj); void i915_gem_object_release_mmap_offset(struct drm_i915_gem_object *obj); +vm_fault_t i915_error_to_vmf_fault(int err); + #endif diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 9b55521cb09b..a995ebad0b17 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -192,10 +192,12 @@ */ #include +#include #include #include #include "gem/i915_gem_context.h" +#include "gem/i915_gem_mman.h" #include "gt/intel_engine_pm.h" #include "gt/intel_engine_user.h" #include "gt/intel_gt.h" @@ -3218,6 +3220,38 @@ static long i915_perf_config_locked(struct i915_perf_stream *stream, return ret; } +#define I915_PERF_OA_BUFFER_MMAP_OFFSET 1 + +/** + * i915_perf_oa_buffer_info_locked - size and offset of the OA buffer + * @stream: i915 perf stream + * @arg: pointer to oa buffer info filled by this function. + */ +static int i915_perf_oa_buffer_info_locked(struct i915_perf_stream *stream, + unsigned long arg) +{ + struct drm_i915_perf_oa_buffer_info info; + void __user *output = (void __user *)arg; + + if (i915_perf_stream_paranoid && !perfmon_capable()) { + DRM_DEBUG("Insufficient privileges to access OA buffer info\n"); + return -EACCES; + } + + if (!output) + return -EINVAL; + + memset(&info, 0, sizeof(info)); + + info.size = stream->oa_buffer.vma->size; + info.offset = I915_PERF_OA_BUFFER_MMAP_OFFSET * PAGE_SIZE; + + if (copy_to_user(output, &info, sizeof(info))) + return -EFAULT; + + return 0; +} + /** * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs * @stream: An i915 perf stream @@ -3243,6 +3277,8 @@ static long i915_perf_ioctl_locked(struct i915_perf_stream *stream, return 0; case I915_PERF_IOCTL_CONFIG: return i915_perf_config_locked(stream, arg); + case I915_PERF_IOCTL_GET_OA_BUFFER_INFO: + return i915_perf_oa_buffer_info_locked(stream, arg); } return -EINVAL; @@ -3318,12 +3354,87 @@ static int i915_perf_release(struct inode *inode, struct file *file) i915_perf_destroy_locked(stream); mutex_unlock(&perf->lock); + /* + * User could have multiple vmas from multiple mmaps. We want to zap + * them all here. + */ + unmap_mapping_range(file->f_mapping, 0, -1, 1); + /* Release the reference the perf stream kept on the driver. */ drm_dev_put(&perf->i915->drm); return 0; } +static vm_fault_t vm_fault_oa(struct vm_fault *vmf) +{ + struct vm_area_struct *vma = vmf->vma; + struct i915_perf_stream *stream = vma->vm_private_data; + int err; + + err = remap_io_sg(vma, + vma->vm_start, vma->vm_end - vma->vm_start, + stream->oa_buffer.vma->pages->sgl, -1); + + return i915_error_to_vmf_fault(err); +} + +static const struct vm_operations_struct vm_ops_oa = { + .fault = vm_fault_oa, +}; + +int i915_perf_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct i915_perf_stream *stream = file->private_data; + + /* mmap-ing OA buffer to user space MUST absolutely be privileged */ + if (i915_perf_stream_paranoid && !perfmon_capable()) { + DRM_DEBUG("Insufficient privileges to map OA buffer\n"); + return -EACCES; + } + + switch (vma->vm_pgoff) { + /* + * A non-zero offset ensures that we are mapping the right object. Also + * leaves room for future objects added to this implementation. + */ + case I915_PERF_OA_BUFFER_MMAP_OFFSET: + if (!(stream->sample_flags & SAMPLE_OA_REPORT)) + return -EINVAL; + + if (vma->vm_end - vma->vm_start > OA_BUFFER_SIZE) + return -EINVAL; + + /* + * Only support VM_READ. Enforce MAP_PRIVATE by checking for + * VM_MAYSHARE. + */ + if (vma->vm_flags & (VM_WRITE | VM_EXEC | + VM_SHARED | VM_MAYSHARE)) + return -EINVAL; + + vma->vm_flags &= ~(VM_MAYWRITE | VM_MAYEXEC); + + /* + * If the privileged parent forks and child drops root + * privilege, we do not want the child to retain access to the + * mapped OA buffer. Explicitly set VM_DONTCOPY to avoid such + * cases. + */ + vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND | + VM_DONTDUMP | VM_DONTCOPY; + break; + + default: + return -EINVAL; + } + + vma->vm_page_prot = vm_get_page_prot(vma->vm_flags); + vma->vm_private_data = stream; + vma->vm_ops = &vm_ops_oa; + + return 0; +} static const struct file_operations fops = { .owner = THIS_MODULE, @@ -3336,6 +3447,7 @@ static const struct file_operations fops = { * to handle 32bits compatibility. */ .compat_ioctl = i915_perf_ioctl, + .mmap = i915_perf_mmap, }; @@ -4480,8 +4592,11 @@ int i915_perf_ioctl_version(void) * * - OA buffer head/tail/status/buffer registers for read only * - OA counters A18, A19, A20 for read/write + * + * 8: Added an option to map oa buffer at umd driver level and trigger + * oa reports within oa buffer from command buffer. */ - return 7; + return 8; } #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 00546062e023..36f6b9799ecd 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -2048,6 +2048,22 @@ struct drm_i915_perf_open_param { */ #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2) +/** + * Returns OA buffer properties to be used with mmap. + * + * This ioctl is available in perf revision 8. + */ +#define I915_PERF_IOCTL_GET_OA_BUFFER_INFO _IO('i', 0x3) + +/** + * OA buffer size and offset. + */ +struct drm_i915_perf_oa_buffer_info { + __u32 size; + __u32 offset; + __u64 reserved[4]; +}; + /** * Common to all i915 perf records */