From patchwork Thu Jul 30 08:51:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huacai Chen X-Patchwork-Id: 11692505 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 88B0A138A for ; Thu, 30 Jul 2020 08:49:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6C6A22075F for ; Thu, 30 Jul 2020 08:49:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ax4JzCzO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728993AbgG3ItY (ORCPT ); Thu, 30 Jul 2020 04:49:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725892AbgG3ItX (ORCPT ); Thu, 30 Jul 2020 04:49:23 -0400 Received: from mail-pj1-x1042.google.com (mail-pj1-x1042.google.com [IPv6:2607:f8b0:4864:20::1042]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58558C061794 for ; Thu, 30 Jul 2020 01:49:23 -0700 (PDT) Received: by mail-pj1-x1042.google.com with SMTP id t6so18573pjr.0 for ; Thu, 30 Jul 2020 01:49:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=++P31NeE21DapI5PKuZBnfatNTZfMQFN1Qtq98D7WGE=; b=ax4JzCzOn2+Oq/cIMpVqHe3FJEeS/Jj9XNp35lFV8CYdoLLRrMg+l2w/Mr5B82jucS wO2+w2RP9pu1SKMPmZy832qTQHO2HIxf2/I36vUU0Vv48YQmczRRE13vt2/8mj1wvxT5 YzVwFUp5pGDnkxDlslZw1zowWdazDeDlzltaD0TidmaG7qsnZL0RIY3PxF5Kl0WB9kDO Udpjxyk0oxI7xQSDpokm1IL3tyI6CPPfJgAcMKdvNJhiDNc4pq78oUPM2owXRpVEzH7/ 8Q/e05U1jPXklT3TyvGsZOGaeqRdXGl6EEmU5ecPXaGPVmY50jzqfxDdFow7HTviB07b 3PYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=++P31NeE21DapI5PKuZBnfatNTZfMQFN1Qtq98D7WGE=; b=jhl2Ok4Fw2ReVK+HPRsAG2YN50ZaXPM3PsAbR3oprdW2RmR3NOcfY9uMYCgM6DjGT6 xA7P63jbpmq9qbHKwPSjh7vux4SI7DPiBG7LskhGkkfiPrH0AMlQP6DLwvpqTDz3GcVk y+DMAqeXHlNLg8h+zPUeHo/1SbZmeptwJoUBdcnmyA93zttQPM75Y1VgkqeEO/FIa/sO YNh90GVCqO3ggq7xE0dplwnsSjLWVdu8u5Ft/Vvqk+JZLon5FOWHOPMupGx1uBAEn+/q XkktYPDgX+bnOMio5ZDY0Ebz267n26RcsIZQrXUlJv+lypjOnBeKizezRaaXb/bO4Tkm LeRg== X-Gm-Message-State: AOAM530cB24+gG/paCzFkjPCm901BOO3u8P/G4Zi+rDowkRhqzX3e9lc DOn9WTPhSz1jD+cn5JysWG8= X-Google-Smtp-Source: ABdhPJzVFPoGOkdoc/bdWgYVnynCkpQTlmOWmD1u+mHRCgosogfM1oVtA6oNKVxrle3zHvEdEpmhug== X-Received: by 2002:a17:90a:1b42:: with SMTP id q60mr2187989pjq.78.1596098962961; Thu, 30 Jul 2020 01:49:22 -0700 (PDT) Received: from software.domain.org ([45.77.13.216]) by smtp.gmail.com with ESMTPSA id m26sm5235345pff.84.2020.07.30.01.49.19 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Jul 2020 01:49:22 -0700 (PDT) From: Huacai Chen To: Thomas Bogendoerfer , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring Cc: linux-mips@vger.kernel.org, Fuxin Zhang , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH V2 1/5] dt-bindings: interrupt-controller: Update Loongson HTVEC description Date: Thu, 30 Jul 2020 16:51:26 +0800 Message-Id: <1596099090-23516-2-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1596099090-23516-1-git-send-email-chenhc@lemote.com> References: <1596099090-23516-1-git-send-email-chenhc@lemote.com> Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Loongson HTVEC support 8 parents interrupts in maximum, so update the maxItems description. Reviewed-by: Jiaxun Yang Signed-off-by: Huacai Chen --- .../devicetree/bindings/interrupt-controller/loongson,htvec.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml index e865cd8..87a7455 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml @@ -22,8 +22,8 @@ properties: interrupts: minItems: 1 - maxItems: 4 - description: Four parent interrupts that receive chained interrupts. + maxItems: 8 + description: Eight parent interrupts that receive chained interrupts. interrupt-controller: true From patchwork Thu Jul 30 08:51:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huacai Chen X-Patchwork-Id: 11692511 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9B46514E3 for ; Thu, 30 Jul 2020 08:49:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 80B2E207F5 for ; Thu, 30 Jul 2020 08:49:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cMxM2kQN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729008AbgG3It4 (ORCPT ); Thu, 30 Jul 2020 04:49:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729182AbgG3Itw (ORCPT ); Thu, 30 Jul 2020 04:49:52 -0400 Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1CE5C061794 for ; Thu, 30 Jul 2020 01:49:51 -0700 (PDT) Received: by mail-pl1-x641.google.com with SMTP id q17so13417200pls.9 for ; Thu, 30 Jul 2020 01:49:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=EZ3vo3o4fkwi2u3isWcrvkspCsvOHO2HUcyzQaTNXYo=; b=cMxM2kQNFprtJ4h21PG46HIM7yxmcNQdJP2nW0IYAPZWKSCG+F8PNu96JZ5KHbHjiy olHWlyVRuBJqm7oHIGqrHECe0jZG9A3+VLjq0y7hHf6N3u2CtHHnM+NJgHny3JIOETM9 b4xIxfkT0f4cVnp+wi9UbbZa9e9R2AGeWbRJ57kGn6t6RpEeIOCbWU1gH3yVMWnSAPbN 3t2sCOvi+VfyWRbxTrWPqeE79Igy53hOuxqfgLQSMFJxTiHZ6Lr0xOUdIFITLSao9Ybn PMUT222ufETlg2f/mA2VEa56JymuA8cSHdggEPfZD0eqYwHtxGEl8/i67EgNn3w00+Fn jEjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=EZ3vo3o4fkwi2u3isWcrvkspCsvOHO2HUcyzQaTNXYo=; b=OkD4TdY0Yd7yh6oaqbD6454zHO/4YdfMQzHExdc8wyF3sXFrHXi6ubpX/vuBJHCtGR eoeFbvlwSP5R6Na3ua9HhoSV+Ve0GQfhNsXRgR26m2FCs+7ej2EnistHu7OkiKjpckmV 5idsn0umAHB+lEJGKxTZC8Qp+a4Fn88HVgtIOPsEG+YvGWTJm79R4DW7snjZgjiDJ955 zSRV9cN/Fylzi3Qbf0ncOKj1DL0D4AjR1OXRfzQbvnh8A6q6XZLFH2dSZccb+tYeUGY3 GxvWdeLFBavD+BhcCFnesMophjZr+JDohtsGGkMQMtwYMx3Js85FPNnWTLvVauuYx0AE +L8A== X-Gm-Message-State: AOAM531Sgsnlb0B/1LWYER49GjKAAoqlgMa+aVmNerajBSPxogRZTJEd Mker5HGaLKTSqqb1iKfZUqc= X-Google-Smtp-Source: ABdhPJz44ds3TWDy8oNgDPVMjk8mTkt+EwNzmVU3qDApE9CE42+yjGYRPay+oSD83xvAlu+ERN+kbA== X-Received: by 2002:a17:90a:eac9:: with SMTP id ev9mr2147016pjb.106.1596098991234; Thu, 30 Jul 2020 01:49:51 -0700 (PDT) Received: from software.domain.org ([45.77.13.216]) by smtp.gmail.com with ESMTPSA id m26sm5235345pff.84.2020.07.30.01.49.47 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Jul 2020 01:49:50 -0700 (PDT) From: Huacai Chen To: Thomas Bogendoerfer , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring Cc: linux-mips@vger.kernel.org, Fuxin Zhang , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH V2 2/5] MIPS: DTS: Fix number of msi vectors for Loongson64G Date: Thu, 30 Jul 2020 16:51:27 +0800 Message-Id: <1596099090-23516-3-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1596099090-23516-1-git-send-email-chenhc@lemote.com> References: <1596099090-23516-1-git-send-email-chenhc@lemote.com> Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org HT irqs vectors are 8 groups, each group has 32 irqs, Loongson64C CPUs can use only 4 groups and Loongson64G CPUs can use all 8 groups. So the number of msi vectors of Loongson64G is 192 (32*8 - 64 = 192). Fixes: 24af105962c8004edb9f5bf84 ("MIPS: Loongson64: DeviceTree for LS7A PCH") Signed-off-by: Huacai Chen --- arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts b/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts index bdc911e..c945f85 100644 --- a/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts +++ b/arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts @@ -20,7 +20,11 @@ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, <25 IRQ_TYPE_LEVEL_HIGH>, <26 IRQ_TYPE_LEVEL_HIGH>, - <27 IRQ_TYPE_LEVEL_HIGH>; + <27 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <29 IRQ_TYPE_LEVEL_HIGH>, + <30 IRQ_TYPE_LEVEL_HIGH>, + <31 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -31,7 +35,7 @@ interrupt-controller; msi-controller; loongson,msi-base-vec = <64>; - loongson,msi-num-vecs = <128>; + loongson,msi-num-vecs = <192>; interrupt-parent = <&htvec>; }; }; From patchwork Thu Jul 30 08:51:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huacai Chen X-Patchwork-Id: 11692517 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7BD136C1 for ; Thu, 30 Jul 2020 08:50:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E80D2083E for ; Thu, 30 Jul 2020 08:50:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ksw7S/NP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728817AbgG3IuE (ORCPT ); Thu, 30 Jul 2020 04:50:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726899AbgG3IuD (ORCPT ); Thu, 30 Jul 2020 04:50:03 -0400 Received: from mail-pj1-x1041.google.com (mail-pj1-x1041.google.com [IPv6:2607:f8b0:4864:20::1041]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA735C061794; Thu, 30 Jul 2020 01:50:02 -0700 (PDT) Received: by mail-pj1-x1041.google.com with SMTP id e4so334495pjd.0; Thu, 30 Jul 2020 01:50:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=DA36TOmA1PD/0mCPsEB57TyuMgX2vtehFyCbtd+xX9k=; b=ksw7S/NPAiAINSHeIBvQ6xx3kDKrPMigAe4mWDNe93bFVHv4MNhgColtvNzsLrdW7y I1OPzUHZnguuNCRKWNhTr7oAMos5ffA/bshtdmOUOUDZeQ06itySQtY5ro6aF+KYraaI qbi7IN+7QIS0M4M398DkETASF+QwFn/J7U6NKjFs3EOP1xwKbZONX9jz90R/A3jd6PKP hcFBQGsYDWT6iFJnS7fhPnfOm3fSW4vPePkYappXmH9ISD95KUV/LoM9Xh6Tksv7X3zY X908v3+vEzZtjz0xMUOvEp6oUkGABZvUULI1R/oAViUkvrPiFMCV/PUUdO0Y8G4XCz8+ Xyyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=DA36TOmA1PD/0mCPsEB57TyuMgX2vtehFyCbtd+xX9k=; b=s1qt7b+WUWJuPSGJNMjwfpGeWCVLy7wsTneEtiUv1UGeEQDhYy9z8/CLfAe2lnjIc5 3ST+RaX/eH7v3I3acCpfjmoyQnUoK++RgcqsjFqCDnPV0+yDMrn+V31Sgx0CDjN4sc2c QqxaqnUOyo5CCUqiXlEl1l0KY+fyXiH7ZUbdLbKfRoddbEZEJehqDgUBtSC4CGdCaWfK Z+XKrKHFmKzTYblecsFfXgDw1QgOvzsYe++CZyBmA0GYTQ36yys824YMObD5Ko2xDMls nNjQrbXyFmffKuTq1tLaiuPg84wr/IS2MzpnjrdNBkS6gySFK8c+DuVNulwmFvKdWGGT u7Sg== X-Gm-Message-State: AOAM533DCFDZLHSP4orSImY2a2fVJca0suOB6x/etTWdMy9HVTXoe+zA 2+vXpgQDxGr0zk+3l8x2vq28Fgi/0G5VXA== X-Google-Smtp-Source: ABdhPJz9v6NeQjzox+rx7h5LXULsrVjC3LdguJ0WsqR6YXy411sJ0g9t4JGD1EueJ22W5JcFFLbRTA== X-Received: by 2002:a63:8ec7:: with SMTP id k190mr32558429pge.261.1596099002457; Thu, 30 Jul 2020 01:50:02 -0700 (PDT) Received: from software.domain.org ([45.77.13.216]) by smtp.gmail.com with ESMTPSA id m26sm5235345pff.84.2020.07.30.01.49.58 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Jul 2020 01:50:01 -0700 (PDT) From: Huacai Chen To: Thomas Bogendoerfer , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring Cc: linux-mips@vger.kernel.org, Fuxin Zhang , Huacai Chen , Jiaxun Yang , Huacai Chen , stable@vger.kernel.org Subject: [PATCH V2 3/5] irqchip: loongson-liointc: Fix misuse of gc->mask_cache Date: Thu, 30 Jul 2020 16:51:28 +0800 Message-Id: <1596099090-23516-4-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1596099090-23516-1-git-send-email-chenhc@lemote.com> References: <1596099090-23516-1-git-send-email-chenhc@lemote.com> Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org In gc->mask_cache bits, 1 means enabled and 0 means disabled, but in the loongson-liointc driver mask_cache is misused by reverting its meaning. This patch fix the bug and update the comments as well. Fixes: dbb152267908c4b2c3639492a ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") Cc: stable@vger.kernel.org Reviewed-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-liointc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c index 63b6147..08165c5 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -60,7 +60,7 @@ static void liointc_chained_handle_irq(struct irq_desc *desc) if (!pending) { /* Always blame LPC IRQ if we have that bug */ if (handler->priv->has_lpc_irq_errata && - (handler->parent_int_map & ~gc->mask_cache & + (handler->parent_int_map & gc->mask_cache & BIT(LIOINTC_ERRATA_IRQ))) pending = BIT(LIOINTC_ERRATA_IRQ); else @@ -131,11 +131,11 @@ static void liointc_resume(struct irq_chip_generic *gc) irq_gc_lock_irqsave(gc, flags); /* Disable all at first */ writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE); - /* Revert map cache */ + /* Restore map cache */ for (i = 0; i < LIOINTC_CHIP_IRQ; i++) writeb(priv->map_cache[i], gc->reg_base + i); - /* Revert mask cache */ - writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE); + /* Restore mask cache */ + writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE); irq_gc_unlock_irqrestore(gc, flags); } @@ -243,7 +243,7 @@ int __init liointc_of_init(struct device_node *node, ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; ct->chip.irq_set_type = liointc_set_type; - gc->mask_cache = 0xffffffff; + gc->mask_cache = 0; priv->gc = gc; for (i = 0; i < LIOINTC_NUM_PARENT; i++) { From patchwork Thu Jul 30 08:51:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huacai Chen X-Patchwork-Id: 11692519 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B82CC138A for ; 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Thu, 30 Jul 2020 01:51:07 -0700 (PDT) Received: from software.domain.org ([45.77.13.216]) by smtp.gmail.com with ESMTPSA id m26sm5235345pff.84.2020.07.30.01.51.03 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Jul 2020 01:51:06 -0700 (PDT) From: Huacai Chen To: Thomas Bogendoerfer , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring Cc: linux-mips@vger.kernel.org, Fuxin Zhang , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH V2 4/5] irqchip: loongson-htvec: Support 8 groups of HT vectors Date: Thu, 30 Jul 2020 16:51:29 +0800 Message-Id: <1596099090-23516-5-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1596099090-23516-1-git-send-email-chenhc@lemote.com> References: <1596099090-23516-1-git-send-email-chenhc@lemote.com> Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The original version can only used by old Loongson-3 which only use 4 groups of HT vectors. Now Loongson-3A R4 can use 8 groups, so improve the driver to support all 8 groups. Fixes: 818e915fbac518e8c78e1877a ("irqchip: Add Loongson HyperTransport Vector support") Reviewed-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-htvec.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c index 1ece933..e7722fa 100644 --- a/drivers/irqchip/irq-loongson-htvec.c +++ b/drivers/irqchip/irq-loongson-htvec.c @@ -19,15 +19,14 @@ /* Registers */ #define HTVEC_EN_OFF 0x20 -#define HTVEC_MAX_PARENT_IRQ 4 +#define HTVEC_MAX_PARENT_IRQ 8 #define VEC_COUNT_PER_REG 32 -#define VEC_REG_COUNT 4 -#define VEC_COUNT (VEC_COUNT_PER_REG * VEC_REG_COUNT) #define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG) #define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG) struct htvec { + int num_parents; void __iomem *base; struct irq_domain *htvec_domain; raw_spinlock_t htvec_lock; @@ -43,7 +42,7 @@ static void htvec_irq_dispatch(struct irq_desc *desc) chained_irq_enter(chip, desc); - for (i = 0; i < VEC_REG_COUNT; i++) { + for (i = 0; i < priv->num_parents; i++) { pending = readl(priv->base + 4 * i); while (pending) { int bit = __ffs(pending); @@ -147,7 +146,7 @@ static void htvec_reset(struct htvec *priv) u32 idx; /* Clear IRQ cause registers, mask all interrupts */ - for (idx = 0; idx < VEC_REG_COUNT; idx++) { + for (idx = 0; idx < priv->num_parents; idx++) { writel_relaxed(0x0, priv->base + HTVEC_EN_OFF + 4 * idx); writel_relaxed(0xFFFFFFFF, priv->base); } @@ -157,7 +156,7 @@ static int htvec_of_init(struct device_node *node, struct device_node *parent) { struct htvec *priv; - int err, parent_irq[4], num_parents = 0, i; + int err, parent_irq[8], i; priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) @@ -176,19 +175,18 @@ static int htvec_of_init(struct device_node *node, if (parent_irq[i] <= 0) break; - num_parents++; + priv->num_parents++; } - if (!num_parents) { + if (!priv->num_parents) { pr_err("Failed to get parent irqs\n"); err = -ENODEV; goto iounmap_base; } priv->htvec_domain = irq_domain_create_linear(of_node_to_fwnode(node), - VEC_COUNT, - &htvec_domain_ops, - priv); + (VEC_COUNT_PER_REG * priv->num_parents), + &htvec_domain_ops, priv); if (!priv->htvec_domain) { pr_err("Failed to create IRQ domain\n"); err = -ENOMEM; @@ -197,7 +195,7 @@ static int htvec_of_init(struct device_node *node, htvec_reset(priv); - for (i = 0; i < num_parents; i++) + for (i = 0; i < priv->num_parents; i++) irq_set_chained_handler_and_data(parent_irq[i], htvec_irq_dispatch, priv); From patchwork Thu Jul 30 08:51:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huacai Chen X-Patchwork-Id: 11692521 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BA0C6138A for ; Thu, 30 Jul 2020 08:55:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A274B20838 for ; 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Thu, 30 Jul 2020 01:55:23 -0700 (PDT) Received: from software.domain.org ([45.77.13.216]) by smtp.gmail.com with ESMTPSA id m26sm5235345pff.84.2020.07.30.01.55.18 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Jul 2020 01:55:22 -0700 (PDT) From: Huacai Chen To: Thomas Bogendoerfer , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring Cc: linux-mips@vger.kernel.org, Fuxin Zhang , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH V2 5/5] irqchip: loongson-pch-pic: Fix the misused irq flow handler Date: Thu, 30 Jul 2020 16:51:30 +0800 Message-Id: <1596099090-23516-6-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1596099090-23516-1-git-send-email-chenhc@lemote.com> References: <1596099090-23516-1-git-send-email-chenhc@lemote.com> Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Loongson PCH PIC is a standard level triggered PIC, and it need to clear interrupt during unmask. Fixes: ef8c01eb64ca6719da449dab0 ("irqchip: Add Loongson PCH PIC controller") Tested-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-pch-pic.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c index 2a05b93..61d06df 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -64,15 +64,6 @@ static void pch_pic_bitclr(struct pch_pic *priv, int offset, int bit) raw_spin_unlock(&priv->pic_lock); } -static void pch_pic_eoi_irq(struct irq_data *d) -{ - u32 idx = PIC_REG_IDX(d->hwirq); - struct pch_pic *priv = irq_data_get_irq_chip_data(d); - - writel(BIT(PIC_REG_BIT(d->hwirq)), - priv->base + PCH_PIC_CLR + idx * 4); -} - static void pch_pic_mask_irq(struct irq_data *d) { struct pch_pic *priv = irq_data_get_irq_chip_data(d); @@ -85,6 +76,9 @@ static void pch_pic_unmask_irq(struct irq_data *d) { struct pch_pic *priv = irq_data_get_irq_chip_data(d); + writel(BIT(PIC_REG_BIT(d->hwirq)), + priv->base + PCH_PIC_CLR + PIC_REG_IDX(d->hwirq) * 4); + irq_chip_unmask_parent(d); pch_pic_bitclr(priv, PCH_PIC_MASK, d->hwirq); } @@ -124,7 +118,6 @@ static struct irq_chip pch_pic_irq_chip = { .irq_mask = pch_pic_mask_irq, .irq_unmask = pch_pic_unmask_irq, .irq_ack = irq_chip_ack_parent, - .irq_eoi = pch_pic_eoi_irq, .irq_set_affinity = irq_chip_set_affinity_parent, .irq_set_type = pch_pic_set_type, }; @@ -150,7 +143,7 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq, irq_domain_set_info(domain, virq, hwirq, &pch_pic_irq_chip, priv, - handle_fasteoi_ack_irq, NULL, NULL); + handle_level_irq, NULL, NULL); irq_set_probe(virq); return 0;