From patchwork Thu Jul 30 10:21:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11692723 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 99EA213B6 for ; Thu, 30 Jul 2020 10:22:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 812DB2075F for ; Thu, 30 Jul 2020 10:22:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="FXrzGDF8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729077AbgG3KWZ (ORCPT ); Thu, 30 Jul 2020 06:22:25 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:47266 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728897AbgG3KWY (ORCPT ); Thu, 30 Jul 2020 06:22:24 -0400 X-UUID: 30ef0792b6324cfe84793aa17270bdd4-20200730 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=43JS2ywwVdDeLI1qVoCoqy50NzYC0F+9yWEVszhkYxw=; b=FXrzGDF8/QNQOMseFgIUMCTP2M4EO3AIiTA3/0fKZ9MRb3l9JDY3v0ndBt2vVMdSBS73/VD6cYlE12cZFRHt7DWKqT1cHMixXhWKyHZVBBD64WFdIJRQEoaQeJ86up2mhhbcjWcnPU6MuV0BTX3KOU7r3RNNk8HmLIiWwDFyN2w=; X-UUID: 30ef0792b6324cfe84793aa17270bdd4-20200730 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1926846719; Thu, 30 Jul 2020 18:22:21 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jul 2020 18:22:17 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jul 2020 18:22:17 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v3,1/5] dt-binding: mediatek: watchdog: fix the description of compatible Date: Thu, 30 Jul 2020 18:21:46 +0800 Message-ID: <1596104510-11113-2-git-send-email-crystal.guo@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596104510-11113-1-git-send-email-crystal.guo@mediatek.com> References: <1596104510-11113-1-git-send-email-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Besides watchdog, mt2712 and nt8183 also provide sub-system software reset features. But mt6589 not support this feature Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 4dd36bd..45eedc2 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -4,13 +4,13 @@ Required properties: - compatible should contain: "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 - "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712 + "mediatek,mt2712-wdt": for MT2712 "mediatek,mt6589-wdt": for MT6589 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623 "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 - "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183 + "mediatek,mt8183-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 - reg : Specifies base physical address and size of the registers. From patchwork Thu Jul 30 10:21:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11692727 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2957C1746 for ; Thu, 30 Jul 2020 10:22:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0719D2082E for ; Thu, 30 Jul 2020 10:22:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="po32Poj8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729156AbgG3KWc (ORCPT ); Thu, 30 Jul 2020 06:22:32 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:65091 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729140AbgG3KW1 (ORCPT ); Thu, 30 Jul 2020 06:22:27 -0400 X-UUID: b64e2d8b526146dbb1017a7bd3ffb8e3-20200730 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3k0kVNO88tHkCKWTChsoc7KVWWIDowKBe7aJrkR/NCI=; b=po32Poj8kCkAvsGQ0W4jFI7u2NaHA57V2BH91jKPruYEqnJtxTFofbLWbMqg5WRwByRz6UWJIXzN5iBG2/if6a+/yFz8wV6O9EsujrcGVeD3Ql+LfD9mJljrH7/QAiHu1XlyT9XnwIsKm63JeDe7jcP13yJGmvG3VukS7xibrPs=; X-UUID: b64e2d8b526146dbb1017a7bd3ffb8e3-20200730 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1215805369; Thu, 30 Jul 2020 18:22:22 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jul 2020 18:22:18 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jul 2020 18:22:17 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v3,2/5] arm64: dts: mt8183: update watchdog device node Date: Thu, 30 Jul 2020 18:21:47 +0800 Message-ID: <1596104510-11113-3-git-send-email-crystal.guo@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596104510-11113-1-git-send-email-crystal.guo@mediatek.com> References: <1596104510-11113-1-git-send-email-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org update watchdog device node for MT8183 Signed-off-by: Crystal Guo --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 1e03c84..f8d8357 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -310,8 +310,7 @@ }; watchdog: watchdog@10007000 { - compatible = "mediatek,mt8183-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt8183-wdt"; reg = <0 0x10007000 0 0x100>; #reset-cells = <1>; }; From patchwork Thu Jul 30 10:21:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11692725 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DBF6814E3 for ; Thu, 30 Jul 2020 10:22:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C2C412083B for ; Thu, 30 Jul 2020 10:22:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ry4XVukt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726814AbgG3KWb (ORCPT ); Thu, 30 Jul 2020 06:22:31 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:65477 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728897AbgG3KW1 (ORCPT ); Thu, 30 Jul 2020 06:22:27 -0400 X-UUID: 50062b7bbd184cfe929dc849e34609b4-20200730 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=QDlQ0gnoVvfRjOVlPrmnQKeNq40xRyUCNuWe8BeV8Zo=; b=ry4XVuktaP/TGM/JbxU58QN150UIVkmG4RrcRpc9sdrqmGWT4UKJ955kXJCIfbZ24LW5bjXpDylDPYHLeEd6/Aucb6PdJEvENOgV1qWpAowegEMcayBVx2tkaYXNiyCDa0T6gTGHghNOEd+2IksRMXGaVPhjfBTkeIKu/M71sng=; X-UUID: 50062b7bbd184cfe929dc849e34609b4-20200730 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1593641337; Thu, 30 Jul 2020 18:22:23 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jul 2020 18:22:19 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jul 2020 18:22:18 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v3,3/5] dt-binding: mediatek: mt8192: update mtk-wdt document Date: Thu, 30 Jul 2020 18:21:48 +0800 Message-ID: <1596104510-11113-4-git-send-email-crystal.guo@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596104510-11113-1-git-send-email-crystal.guo@mediatek.com> References: <1596104510-11113-1-git-send-email-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org update mtk-wdt document for MT8192 platform Signed-off-by: Crystal Guo --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 45eedc2..e36ba60 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -12,6 +12,7 @@ Required properties: "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 "mediatek,mt8183-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 + "mediatek,mt8192-wdt": for MT8192 - reg : Specifies base physical address and size of the registers. From patchwork Thu Jul 30 10:21:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11692737 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8BD4F13B6 for ; Thu, 30 Jul 2020 10:22:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 75E922083B for ; Thu, 30 Jul 2020 10:22:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="AnCLwfNR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729140AbgG3KWj (ORCPT ); Thu, 30 Jul 2020 06:22:39 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:34215 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728972AbgG3KW2 (ORCPT ); Thu, 30 Jul 2020 06:22:28 -0400 X-UUID: 9506b8dc5a2442229bffa56ed4d0c835-20200730 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=650NVCPZG1KcydX0hTrnKCdiU0nIw3CgigzQoQXdQQk=; b=AnCLwfNRoY0Za/crMZD+KmDbN9m1OhpBK3T4QnCwpTA+Fz6xaizLnA8+Bsri4uF3GYNldQEECciG96dspMNWxteHicn2/O+UikznD446kZTC1aOWaHhyo3cENUvchTpwDeFmYBPKVuUM/nCwDrGjO5z9AFNxZ07AcWHbZkKJLmY=; X-UUID: 9506b8dc5a2442229bffa56ed4d0c835-20200730 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1624301822; Thu, 30 Jul 2020 18:22:23 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jul 2020 18:22:19 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jul 2020 18:22:19 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v3,4/5] dt-binding: mt8192: add toprgu reset-controller head file Date: Thu, 30 Jul 2020 18:21:49 +0800 Message-ID: <1596104510-11113-5-git-send-email-crystal.guo@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596104510-11113-1-git-send-email-crystal.guo@mediatek.com> References: <1596104510-11113-1-git-send-email-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org add toprgu reset-controller head file for MT8192 platform Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger --- .../dt-bindings/reset-controller/mt8192-resets.h | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h new file mode 100644 index 0000000..84fee34 --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8192-resets.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Yong Liang + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 + +#define MT8183_TOPRGU_MM_SW_RST 1 +#define MT8183_TOPRGU_MFG_SW_RST 2 +#define MT8183_TOPRGU_VENC_SW_RST 3 +#define MT8183_TOPRGU_VDEC_SW_RST 4 +#define MT8183_TOPRGU_IMG_SW_RST 5 +#define MT8183_TOPRGU_MD_SW_RST 7 +#define MT8183_TOPRGU_CONN_SW_RST 9 +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8183_TOPRGU_IPU0_SW_RST 14 +#define MT8183_TOPRGU_IPU1_SW_RST 15 +#define MT8183_TOPRGU_AUDIO_SW_RST 17 +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 +#define MT8192_TOPRGU_MJC_SW_RST 19 +#define MT8192_TOPRGU_C2K_S2_SW_RST 20 +#define MT8192_TOPRGU_C2K_SW_RST 21 +#define MT8192_TOPRGU_PERI_SW_RST 22 +#define MT8192_TOPRGU_PERI_AO_SW_RST 23 + +#define MT8192_TOPRGU_SW_RST_NUM 23 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ From patchwork Thu Jul 30 10:21:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11692735 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 67F3814E3 for ; Thu, 30 Jul 2020 10:22:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4CAAF22CBE for ; Thu, 30 Jul 2020 10:22:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="gVq6JnDk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729230AbgG3KWj (ORCPT ); Thu, 30 Jul 2020 06:22:39 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:13093 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729143AbgG3KW2 (ORCPT ); Thu, 30 Jul 2020 06:22:28 -0400 X-UUID: ed3745d291e7428c98bf4b7c5c9ee8a1-20200730 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BJIvEQojTWHUoFsviCh26y09bDiTiAOtQb+FKP21A8g=; b=gVq6JnDkmSgSZxAfQGIX3deUFGl7oiAdzmefVcE0P9ZNeTUsVotCQjmaevAF14/+bb+mIAi0IHWvTzIhGo5A+sGMYXQKc2gc8Hbp0DDP4C9c5VVidoTCsmkHKgWvJmWyC70nJJNCG4Nq8TlDRZjBB6N5RuDw1jwqAMZxADm9Xuw=; X-UUID: ed3745d291e7428c98bf4b7c5c9ee8a1-20200730 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1062283760; Thu, 30 Jul 2020 18:22:24 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jul 2020 18:22:20 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jul 2020 18:22:20 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v3,5/5] watchdog: mt8192: add wdt support Date: Thu, 30 Jul 2020 18:21:50 +0800 Message-ID: <1596104510-11113-6-git-send-email-crystal.guo@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1596104510-11113-1-git-send-email-crystal.guo@mediatek.com> References: <1596104510-11113-1-git-send-email-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Add support for watchdog device found in MT8192 SoC Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger Reviewed-by: Guenter Roeck --- drivers/watchdog/mtk_wdt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index d6a6393..aef0c2d 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -76,6 +77,10 @@ struct mtk_wdt_data { .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, }; +static const struct mtk_wdt_data mt8192_data = { + .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM, +}; + static int toprgu_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -322,6 +327,7 @@ static int mtk_wdt_resume(struct device *dev) { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, { .compatible = "mediatek,mt6589-wdt" }, { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);