From patchwork Fri Jul 31 04:57:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wesley Cheng X-Patchwork-Id: 11694081 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EEB8713B1 for ; Fri, 31 Jul 2020 04:57:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D57892074B for ; Fri, 31 Jul 2020 04:57:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="ZZLMT1dd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730161AbgGaE5T (ORCPT ); Fri, 31 Jul 2020 00:57:19 -0400 Received: from mail29.static.mailgun.info ([104.130.122.29]:28148 "EHLO mail29.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729523AbgGaE5T (ORCPT ); Fri, 31 Jul 2020 00:57:19 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1596171439; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=KqX0wJwFwjRWMCgKqLdvIZWRqiJV7nWZl0ANfpcdGlM=; b=ZZLMT1ddf0EhDJRMm1HcjI8v5UHJnOXt5yRjSgqDNip2j5axpM/vGxqlXv0saGfzH9l5jj9r n4X7PcDTOGHmZRBiPNf6OTIv5kqIDAzgpXaMXQzC/YXq+hunmXNyqW0pOCwm62aOlf/XbBcq fZ8Sok5WFF/8OC5YtobfWQQ+CqM= X-Mailgun-Sending-Ip: 104.130.122.29 X-Mailgun-Sid: WyIxZTE2YSIsICJsaW51eC11c2JAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n12.prod.us-east-1.postgun.com with SMTP id 5f23a4ae798b1029682db712 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 31 Jul 2020 04:57:18 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 799CCC433B1; Fri, 31 Jul 2020 04:57:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from wcheng-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: wcheng) by smtp.codeaurora.org (Postfix) with ESMTPSA id 696AFC433CA; Fri, 31 Jul 2020 04:57:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 696AFC433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=wcheng@codeaurora.org From: Wesley Cheng To: bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, agross@kernel.org, balbi@kernel.org, gregkh@linuxfoundation.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, jackp@codeaurora.org, Wesley Cheng Subject: [PATCH 1/3] arm64: boot: dts: qcom: sm8150: Add nodes for PMIC based typec detection Date: Thu, 30 Jul 2020 21:57:10 -0700 Message-Id: <20200731045712.28495-2-wcheng@codeaurora.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200731045712.28495-1-wcheng@codeaurora.org> References: <20200731045712.28495-1-wcheng@codeaurora.org> MIME-Version: 1.0 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Introduce required child nodes to enable the PMIC based USB type C driver. This consits of connector and endpoint nodes to drivers, which manage the type C mux and the USB role switch. Signed-off-by: Wesley Cheng --- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 37 ++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index ba3b5b802954..c7d5aab69b56 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -413,6 +413,28 @@ &pm8150b_vbus { status = "okay"; }; +&pm8150b_typec { + status = "okay"; + connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + usb3_data_ss: endpoint@0 { + remote-endpoint = <&qmp_ss_mux>; + }; + usb3_role: endpoint@1 { + remote-endpoint = <&dwc3_drd_switch>; + }; + }; + }; + }; +}; + &usb_1_hsphy { status = "okay"; vdda-pll-supply = <&vdd_usb_hs_core>; @@ -424,12 +446,25 @@ &usb_1_qmpphy { status = "okay"; vdda-phy-supply = <&vreg_l3c_1p2>; vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; + orientation-switch; + port { + qmp_ss_mux: endpoint@0 { + remote-endpoint = <&usb3_data_ss>; + }; + }; }; &usb_1 { status = "okay"; + usb-role-switch; + port { + dwc3_drd_switch: endpoint@0 { + remote-endpoint = <&usb3_role>; + }; + }; }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; }; From patchwork Fri Jul 31 04:57:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wesley Cheng X-Patchwork-Id: 11694095 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0B1A3913 for ; Fri, 31 Jul 2020 04:57:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E363A21D95 for ; Fri, 31 Jul 2020 04:57:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="AURaN9KI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731131AbgGaE5z (ORCPT ); Fri, 31 Jul 2020 00:57:55 -0400 Received: from mail29.static.mailgun.info ([104.130.122.29]:38943 "EHLO mail29.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731024AbgGaE5y (ORCPT ); Fri, 31 Jul 2020 00:57:54 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1596171473; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=g13fmLH5MWoCaZ2CBH1tKm0KPDV4tSk0QYM43fNfZuY=; b=AURaN9KIDmlIbJ2XcSWInqTLeGSbGEkU/Q/euVlEZDvpdrK2h0X/rl9PbCMHpRxqnHtA3kD0 pcm8LzPYn3Yy5mEV7s7yLYxda5Cd4inQzMk3qbsqx7XoQ2DibdRXLIaeD4PLfVuqOKsRN0l4 5Lbevwu+y/UWXIHrefvKMKYQDMc= X-Mailgun-Sending-Ip: 104.130.122.29 X-Mailgun-Sid: WyIxZTE2YSIsICJsaW51eC11c2JAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n15.prod.us-east-1.postgun.com with SMTP id 5f23a4af90893260ddaac3aa (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 31 Jul 2020 04:57:19 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 44EEFC433C9; Fri, 31 Jul 2020 04:57:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=ham autolearn_force=no version=3.4.0 Received: from wcheng-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: wcheng) by smtp.codeaurora.org (Postfix) with ESMTPSA id 26E51C433CB; Fri, 31 Jul 2020 04:57:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 26E51C433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=wcheng@codeaurora.org From: Wesley Cheng To: bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, agross@kernel.org, balbi@kernel.org, gregkh@linuxfoundation.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, jackp@codeaurora.org, Wesley Cheng Subject: [PATCH 2/3] phy: qcom-qmp: Register as a typec switch for orientation detection Date: Thu, 30 Jul 2020 21:57:11 -0700 Message-Id: <20200731045712.28495-3-wcheng@codeaurora.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200731045712.28495-1-wcheng@codeaurora.org> References: <20200731045712.28495-1-wcheng@codeaurora.org> MIME-Version: 1.0 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The lane select switch for USB typec orientation is within the USB QMP PHY. the current device. It could be connected through an endpoint, to an independent device handling the typec detection, ie the QCOM SPMI typec driver. Signed-off-by: Wesley Cheng --- drivers/phy/qualcomm/Kconfig | 11 +++++ drivers/phy/qualcomm/phy-qcom-qmp.c | 70 +++++++++++++++++++++++++++-- 2 files changed, 78 insertions(+), 3 deletions(-) diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 928db510b86c..43f46a1b3db1 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -48,6 +48,17 @@ config PHY_QCOM_QMP Enable this to support the QMP PHY transceiver that is used with controllers such as PCIe, UFS, and USB on Qualcomm chips. +if PHY_QCOM_QMP +config PHY_QCOM_QMP_TYPEC + bool "Enable QCOM QMP PHY Type C Switch Support" + depends on PHY_QCOM_QMP=y && TYPEC=y || PHY_QCOM_QMP=m && TYPEC + help + Register a type C switch from the QMP PHY driver for type C + orientation support. This has dependencies with if the type C kernel + configuration is enabled or not. This support will not be present if + USB type C is disabled. +endif + config PHY_QCOM_QUSB2 tristate "Qualcomm QUSB2 PHY Driver" depends on OF && (ARCH_QCOM || COMPILE_TEST) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 562053ce9455..29d8a3570328 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -19,6 +19,7 @@ #include #include #include +#include #include @@ -66,6 +67,9 @@ /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ +#define SW_PORTSELECT_VAL BIT(0) +#define SW_PORTSELECT_MUX BIT(1) + #define PHY_INIT_COMPLETE_TIMEOUT 10000 #define POWER_DOWN_DELAY_US_MIN 10 #define POWER_DOWN_DELAY_US_MAX 11 @@ -1845,6 +1849,8 @@ struct qmp_phy { * @phy_initialized: indicate if PHY has been initialized * @mode: current PHY mode * @ufs_reset: optional UFS PHY reset handle + * @sw: typec switch for receiving orientation changes + * @orientation: carries current CC orientation */ struct qcom_qmp { struct device *dev; @@ -1864,6 +1870,8 @@ struct qcom_qmp { enum phy_mode mode; struct reset_control *ufs_reset; + struct typec_switch *sw; + enum typec_orientation orientation; }; static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -2485,6 +2493,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) void __iomem *pcs = qphy->pcs; void __iomem *dp_com = qmp->dp_com; int ret, i; + unsigned int val; mutex_lock(&qmp->phy_mutex); if (qmp->init_count++) { @@ -2534,6 +2543,13 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, USB3_MODE | DP_MODE); + if (cfg->is_dual_lane_phy) { + val = SW_PORTSELECT_MUX; + if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) + val |= SW_PORTSELECT_VAL; + qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, val); + } + /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | @@ -2559,7 +2575,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy) if (cfg->has_phy_com_ctrl) { void __iomem *status; - unsigned int mask, val; + unsigned int mask; qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], @@ -3242,6 +3258,47 @@ static const struct dev_pm_ops qcom_qmp_phy_pm_ops = { qcom_qmp_phy_runtime_resume, NULL) }; +#if IS_ENABLED(CONFIG_PHY_QCOM_QMP_TYPEC) +static int qcom_qmp_phy_typec_switch_set(struct typec_switch *sw, + enum typec_orientation orientation) +{ + struct qcom_qmp *qmp = typec_switch_get_drvdata(sw); + struct qmp_phy *qphy = qmp->phys[0]; + + qmp->orientation = orientation; + if (qmp->phy_initialized) { + qcom_qmp_phy_disable(qphy->phy); + qcom_qmp_phy_enable(qphy->phy); + } + + return 0; +} + +static int qcom_qmp_phy_typec_switch_register(struct qcom_qmp *qmp) +{ + struct typec_switch_desc sw_desc; + struct device *dev = qmp->dev; + + if (qmp->cfg->is_dual_lane_phy) { + sw_desc.drvdata = qmp; + sw_desc.fwnode = dev->fwnode; + sw_desc.set = qcom_qmp_phy_typec_switch_set; + qmp->sw = typec_switch_register(dev, &sw_desc); + if (IS_ERR(qmp->sw)) { + dev_err(dev, "Error registering typec switch: %ld\n", + PTR_ERR(qmp->sw)); + } + } + + return 0; +} +#else +static int qcom_qmp_phy_typec_switch_register(struct qcom_qmp *qmp) +{ + return 0; +} +#endif + static int qcom_qmp_phy_probe(struct platform_device *pdev) { struct qcom_qmp *qmp; @@ -3250,7 +3307,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) struct device_node *child; struct phy_provider *phy_provider; void __iomem *base; - int num, id; + int num = 0, id; int ret; qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); @@ -3302,7 +3359,11 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) return ret; } - num = of_get_available_child_count(dev->of_node); + qcom_qmp_phy_typec_switch_register(qmp); + for_each_available_child_of_node(dev->of_node, child) { + if (!strncmp("lanes", child->name, 5)) + num++; + } /* do we have a rogue child node ? */ if (num > qmp->cfg->nlanes) return -EINVAL; @@ -3322,6 +3383,9 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) for_each_available_child_of_node(dev->of_node, child) { /* Create per-lane phy */ + if (strncmp("lanes", child->name, 5)) + continue; + ret = qcom_qmp_phy_create(dev, child, id); if (ret) { dev_err(dev, "failed to create lane%d phy, %d\n", From patchwork Fri Jul 31 04:57:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wesley Cheng X-Patchwork-Id: 11694091 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 20E0E913 for ; Fri, 31 Jul 2020 04:57:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0519321744 for ; Fri, 31 Jul 2020 04:57:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="L0vynrM4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730899AbgGaE5n (ORCPT ); Fri, 31 Jul 2020 00:57:43 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:58620 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730905AbgGaE5m (ORCPT ); Fri, 31 Jul 2020 00:57:42 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1596171461; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=GAjtKd4k/JuD5DE6qHj3UJXwuF//h2iJZpWppiv8aWo=; b=L0vynrM4sjqEJY12C6Wh1dVfzELQbmcPq9FzKZeB1WgW6yPU3JdHl2HnILeOwyW2Hy7cTkeX ukWjIq246xXW3E4J8lQb5qe+9+l1jdgmkKEN8tomyXgpSb7HSggkoZwWM7UfUv5gDhea9ELL 1UjlJuMmosHY/+EW9xur/AybyFc= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyIxZTE2YSIsICJsaW51eC11c2JAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n13.prod.us-east-1.postgun.com with SMTP id 5f23a4b0f89b692ba2945cbe (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 31 Jul 2020 04:57:20 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 0B2D3C433C9; Fri, 31 Jul 2020 04:57:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from wcheng-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: wcheng) by smtp.codeaurora.org (Postfix) with ESMTPSA id D6C82C433C6; Fri, 31 Jul 2020 04:57:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D6C82C433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=wcheng@codeaurora.org From: Wesley Cheng To: bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, agross@kernel.org, balbi@kernel.org, gregkh@linuxfoundation.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, jackp@codeaurora.org, Wesley Cheng Subject: [PATCH 3/3] usb: dwc3: dwc3-qcom: Find USB connector and register role switch Date: Thu, 30 Jul 2020 21:57:12 -0700 Message-Id: <20200731045712.28495-4-wcheng@codeaurora.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200731045712.28495-1-wcheng@codeaurora.org> References: <20200731045712.28495-1-wcheng@codeaurora.org> MIME-Version: 1.0 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org If registering a USB typeC connector, the connector node may not be a child of the DWC3 QCOM device. Utilize devcon graph search to lookup if any remote endpoints contain the connector. If a connector is present, the DWC3 QCOM will register a USB role switch to receive role change events, as well as attain a reference to the DWC3 core role switch to pass the event down. Signed-off-by: Wesley Cheng --- drivers/usb/dwc3/dwc3-qcom.c | 103 ++++++++++++++++++++++++++++++++++- 1 file changed, 101 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index e1e78e9824b1..fe1e8a4ab7d6 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include "core.h" @@ -71,6 +73,9 @@ struct dwc3_qcom { struct notifier_block vbus_nb; struct notifier_block host_nb; + struct usb_role_switch *role_sw; + struct usb_role_switch *dwc3_drd_sw; + const struct dwc3_acpi_pdata *acpi_pdata; enum usb_dr_mode mode; @@ -190,6 +195,73 @@ static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom) return 0; } +static int dwc3_qcom_usb_role_switch_set(struct usb_role_switch *sw, + enum usb_role role) +{ + struct dwc3_qcom *qcom = usb_role_switch_get_drvdata(sw); + struct fwnode_handle *child; + bool enable = false; + + if (!qcom->dwc3_drd_sw) { + child = device_get_next_child_node(qcom->dev, NULL); + if (child) { + qcom->dwc3_drd_sw = usb_role_switch_find_by_fwnode(child); + fwnode_handle_put(child); + if (IS_ERR(qcom->dwc3_drd_sw)) { + qcom->dwc3_drd_sw = NULL; + return 0; + } + } + } + + usb_role_switch_set_role(qcom->dwc3_drd_sw, role); + + if (role == USB_ROLE_DEVICE) + enable = true; + else + enable = false; + + qcom->mode = (role == USB_ROLE_HOST) ? USB_DR_MODE_HOST : + USB_DR_MODE_PERIPHERAL; + dwc3_qcom_vbus_overrride_enable(qcom, enable); + return 0; +} + +static enum usb_role dwc3_qcom_usb_role_switch_get(struct usb_role_switch *sw) +{ + struct dwc3_qcom *qcom = usb_role_switch_get_drvdata(sw); + enum usb_role role; + + switch (qcom->mode) { + case USB_DR_MODE_HOST: + role = USB_ROLE_HOST; + break; + case USB_DR_MODE_PERIPHERAL: + role = USB_ROLE_DEVICE; + break; + default: + role = USB_ROLE_DEVICE; + break; + } + + return role; +} + +static int dwc3_qcom_setup_role_switch(struct dwc3_qcom *qcom) +{ + struct usb_role_switch_desc dwc3_role_switch = {NULL}; + + dwc3_role_switch.fwnode = dev_fwnode(qcom->dev); + dwc3_role_switch.set = dwc3_qcom_usb_role_switch_set; + dwc3_role_switch.get = dwc3_qcom_usb_role_switch_get; + dwc3_role_switch.driver_data = qcom; + qcom->role_sw = usb_role_switch_register(qcom->dev, &dwc3_role_switch); + if (IS_ERR(qcom->role_sw)) + return PTR_ERR(qcom->role_sw); + + return 0; +} + static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) { if (qcom->hs_phy_irq) { @@ -540,6 +612,25 @@ static int dwc3_qcom_of_register_core(struct platform_device *pdev) return 0; } +static void *dwc3_qcom_find_usb_connector_match(struct device_connection *con, + int ep, void *data) +{ + if (!fwnode_property_match_string(con->fwnode, "compatible", + "gpio-usb-b-connector") || + !fwnode_property_match_string(con->fwnode, "compatible", + "usb-c-connector")) + return con->fwnode; + return 0; +} + +static bool dwc3_qcom_find_usb_connector(struct platform_device *pdev) +{ + struct fwnode_handle *fwnode = pdev->dev.fwnode; + + return fwnode_connection_find_match(fwnode, "connector", NULL, + dwc3_qcom_find_usb_connector_match); +} + static int dwc3_qcom_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -644,8 +735,13 @@ static int dwc3_qcom_probe(struct platform_device *pdev) if (qcom->mode == USB_DR_MODE_PERIPHERAL) dwc3_qcom_vbus_overrride_enable(qcom, true); - /* register extcon to override sw_vbus on Vbus change later */ - ret = dwc3_qcom_register_extcon(qcom); + if (dwc3_qcom_find_usb_connector(pdev)) { + ret = dwc3_qcom_setup_role_switch(qcom); + } else { + /* register extcon to override sw_vbus on Vbus change later */ + ret = dwc3_qcom_register_extcon(qcom); + } + if (ret) goto depopulate; @@ -679,6 +775,9 @@ static int dwc3_qcom_remove(struct platform_device *pdev) struct device *dev = &pdev->dev; int i; + usb_role_switch_unregister(qcom->role_sw); + usb_role_switch_put(qcom->dwc3_drd_sw); + of_platform_depopulate(dev); for (i = qcom->num_clocks - 1; i >= 0; i--) {