From patchwork Fri Jul 31 11:43:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11694885 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 65495912 for ; Fri, 31 Jul 2020 12:43:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4A1B42245C for ; Fri, 31 Jul 2020 12:43:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="t0dpG410" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733153AbgGaMnL (ORCPT ); Fri, 31 Jul 2020 08:43:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733101AbgGaMnL (ORCPT ); Fri, 31 Jul 2020 08:43:11 -0400 Received: from mail-ed1-x544.google.com (mail-ed1-x544.google.com [IPv6:2a00:1450:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFAE3C061574; Fri, 31 Jul 2020 05:43:10 -0700 (PDT) Received: by mail-ed1-x544.google.com with SMTP id i26so18944731edv.4; Fri, 31 Jul 2020 05:43:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=kTEKWlV4nOSheNgHEWqv/22qBE+Vx8ikH8s2qmj4c7s=; b=t0dpG410UoQ/AaCrJfLmpl35pb7gf3W1ueoUC8Kx/JGEDzX7QhXn5oMP733MHTQBAs 4LHic3AIM6xJiSRqq86G0JWPXwCyYpMFkw1J37Hgzea7FX23P8viHUNdV3GNCMT2+KyH 30SP4kpBZIQ7kkMIRQBBtv/0a0tqGNdn7OGEPahzFad8ybt4zUqY/+DIhgIkc4MH7WBE Ipg+7wJV93OZWFJfr80g3CHPMHWQlOpprwu9VAiS83J2a5O9VqKZzPcK9J7TRQ4wD5Eh ClijEVwOSSt5Ab03vnsaD5eKXzsZszfeQxc31WMyDT2QiXIB5oa54S3zN/3m8F1OluCA +QkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=kTEKWlV4nOSheNgHEWqv/22qBE+Vx8ikH8s2qmj4c7s=; b=nwYo8B/lD+q4CkN1IQMnYPdG0Mx6EH6sKJnoyC95KIMzeN0l/0aulw7FtVi6nJOwS9 q+Eq3Koew9N5/yvDH2/Kh/kLVJCAMkUSO8CIIyEn3V7HVrDeqSnWZaECYfJ8VLl06VX2 EddxUqXX9f4qFTOVidds5h0g9/pRuH7Lpmqfe3Ml28P00vjqat+6FL5+3ZhMX6v92v5v CMRTGTXB8qH6lXeUj+F5mu1itapJbtbrTso7ZaSE77n/V/aN0kcQP1J1XYfopdbGXSxC aqjeTVfXue7/n8n4Z6HvP8HDRTzjPmA31uYRwD2VGPBXamHNPbuMaTHZxEwG/TOzcNNJ dtwA== X-Gm-Message-State: AOAM5314rgExP9jC4NxyxKdpJOYUfyyrhSM5VxiGrlRVA+AkuXs+E6Un rW8eFpETwgxvrlhnV5/UeDs= X-Google-Smtp-Source: ABdhPJx87fnYc/ryc1eaPTpKu9cM5/FUxmCOhynUIBbPcaF0NGu/M6CJK7gWLKoZuQT408yhWdXUOA== X-Received: by 2002:aa7:c45a:: with SMTP id n26mr3749694edr.45.1596199389154; Fri, 31 Jul 2020 05:43:09 -0700 (PDT) Received: from net.saheed (95C84E0A.dsl.pool.telekom.hu. [149.200.78.10]) by smtp.gmail.com with ESMTPSA id g23sm8668514ejb.24.2020.07.31.05.43.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2020 05:43:08 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 08/12] PCI: Check if pcie_capability_read_*() reads ~0 Date: Fri, 31 Jul 2020 13:43:25 +0200 Message-Id: <20200731114329.100848-1-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On failure pcie_capability_read_*() sets it's last parameter, val to 0. However, with Patch 12/12, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). Since ~0 is an invalid value in here, Add extra check for ~0 in the if condition to ensure success or failure. Suggested-by: Bjorn Helgaas Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/probe.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 2f66988cea25..af95f67c19a7 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1124,7 +1124,7 @@ static void pci_enable_crs(struct pci_dev *pdev) /* Enable CRS Software Visibility if supported */ pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); - if (root_cap & PCI_EXP_RTCAP_CRSVIS) + if ((root_cap != (u16)~0) && (root_cap & PCI_EXP_RTCAP_CRSVIS)) pcie_capability_set_word(pdev, PCI_EXP_RTCTL, PCI_EXP_RTCTL_CRSSVE); } @@ -1521,7 +1521,7 @@ void set_pcie_hotplug_bridge(struct pci_dev *pdev) u32 reg32; pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); - if (reg32 & PCI_EXP_SLTCAP_HPC) + if ((reg32 != (u32)~0) && (reg32 & PCI_EXP_SLTCAP_HPC)) pdev->is_hotplug_bridge = 1; } @@ -2060,7 +2060,7 @@ bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); - return !!(v & PCI_EXP_DEVCTL_RELAX_EN); + return ((v != (u16)~0) && (v & PCI_EXP_DEVCTL_RELAX_EN)); } EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); @@ -2101,11 +2101,11 @@ static void pci_configure_ltr(struct pci_dev *dev) return; pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_LTR)) + if ((cap == (u32)~0) || !(cap & PCI_EXP_DEVCAP2_LTR)) return; pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); - if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { + if ((ctl != (u32)~0) && (ctl & PCI_EXP_DEVCTL2_LTR_EN)) { if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { dev->ltr_path = 1; return; @@ -2147,7 +2147,7 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev) return; pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) + if ((cap == (u32)~0) || !(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) return; pcie_type = pci_pcie_type(dev); From patchwork Fri Jul 31 11:43:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11694899 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8EA46722 for ; Fri, 31 Jul 2020 12:43:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7614622B3F for ; Fri, 31 Jul 2020 12:43:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GMfvm+H2" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733254AbgGaMnM (ORCPT ); Fri, 31 Jul 2020 08:43:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733101AbgGaMnL (ORCPT ); Fri, 31 Jul 2020 08:43:11 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92B9AC061574; Fri, 31 Jul 2020 05:43:11 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id w9so31265152ejc.8; Fri, 31 Jul 2020 05:43:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mu3KVS+jjnoE6TtDYHUGs04kgKz7VUXIOhtqaMe4L8k=; b=GMfvm+H2DwlxEhK0B+zbV8ssTcAL/5E/KjNfTanwFqrgfEUOmkR2UszOuUm7NVCrQN H2yKipSG9Y/TmMbjseu0nl0keYDGluJ3fDRpgdZMJeRxgqTstTW1wzvsWGDuVuoDlVaG bFRd5gafMnXo9eD/Euk/xm9KE8aw4gVr92jhqjEGso5l+IGn0sc4KAhJwkE5lN3sZ9Ww tLF3HFcNAuCgtTL7/81bU/WDHJahrvkMneLlHmiZpZgEuiTaOEBcpzcnrcI68OL9WVn+ 6m93gwcBBdMRa2MIn6d7Il9Aus1rFT1xzX9fJLS00rEOMyzvX5yoky8uGiW+iKYQci1j PHKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mu3KVS+jjnoE6TtDYHUGs04kgKz7VUXIOhtqaMe4L8k=; b=Tn2hy4p6XxwT+i5z9e3bhH+rFz75HgArbwgTvkHXE7FaB/EI6Wsl8Xm7yCq2ymD/Vp MMsl79pqFkvJAIj8bpdK7vgB7s7IN07qHNL+OlKfbjhR8qtWjbHdek+pVlWKX1veN4Ki 96ImNksy9a4xCyhCRQJQj7n+VxalhUmZR8FWiRxTQY1TQJd94h8P7o6kJ3RMydZ6oWLX 1acBlMROOAv4Ma89/svbzSqkZwyUnqHy7RHbQFtitsFx/JMN5sDh9uL7JQrm4Ihe7umg M7uxAUSk7vE8fLxZ/12I8EnBlHq6z1yDskAq5jEGs82vgWFQ05NEo/B1MthAgjB9dDHp njbQ== X-Gm-Message-State: AOAM533fmf1c/DT7QI70oFwKZwnc1yEfDg9opXvPTSesLBWG5INO93oa F4jmAFNjnQzI2EPMyNnIedU= X-Google-Smtp-Source: ABdhPJzFvrIqdL0TTLhGyuFNtlAocl0tVTusk/30IvWSRwDYeEoMZH80mm/NNJqy7fAqpVg+0+r2Gg== X-Received: by 2002:a17:906:26d6:: with SMTP id u22mr4066761ejc.271.1596199390289; Fri, 31 Jul 2020 05:43:10 -0700 (PDT) Received: from net.saheed (95C84E0A.dsl.pool.telekom.hu. [149.200.78.10]) by smtp.gmail.com with ESMTPSA id g23sm8668514ejb.24.2020.07.31.05.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2020 05:43:09 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 09/12] PCI/PM: Check if pcie_capability_read_*() reads ~0 Date: Fri, 31 Jul 2020 13:43:26 +0200 Message-Id: <20200731114329.100848-2-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200731114329.100848-1-refactormyself@gmail.com> References: <20200731114329.100848-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On failure pcie_capability_read_*() sets it's last parameter, val to 0. However, with Patch 12/12, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). Since ~0 is an invalid value in here, Add extra check for ~0 to ensure success or failure. pci_enable_atomic_ops_to_root(): Continue looping through the device heirarchy on failure. pcie_wait_for_link_delay(): Add extra check for ~0 to the condition for breaking out of the loop. Delay only on success otherwise report error and return false. pcie_bandwidth_available(): On read failure move up the device heirarchy and continue. pcie_get_speed_cap(): On read failure, report error and return PCI_SPEED_UNKNOWN Suggested-by: Bjorn Helgaas Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pci.c | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index c9338f914a0e..1dd3659f1388 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3216,7 +3216,7 @@ void pci_configure_ari(struct pci_dev *dev) return; pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_ARI)) + if ((cap == (u32)~0) || !(cap & PCI_EXP_DEVCAP2_ARI)) return; if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { @@ -3635,13 +3635,13 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) /* Ensure switch ports support AtomicOp routing */ case PCI_EXP_TYPE_UPSTREAM: case PCI_EXP_TYPE_DOWNSTREAM: - if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) + if ((cap == (u32)~0) || !(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) return -EINVAL; break; /* Ensure root port supports all the sizes we care about */ case PCI_EXP_TYPE_ROOT_PORT: - if ((cap & cap_mask) != cap_mask) + if ((cap == (u32)~0) || ((cap & cap_mask) != cap_mask) return -EINVAL; break; } @@ -3650,7 +3650,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) { pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl2); - if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) + if ((ctl2 != (u32)~0) && (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)) return -EINVAL; } @@ -4512,7 +4512,7 @@ bool pcie_has_flr(struct pci_dev *dev) return false; pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); - return cap & PCI_EXP_DEVCAP_FLR; + return ((cap != (u32)~0) && (cap & PCI_EXP_DEVCAP_FLR)); } EXPORT_SYMBOL_GPL(pcie_has_flr); @@ -4672,19 +4672,19 @@ static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, for (;;) { pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); - if (ret == active) + if ((lnk_status != (u16)~0) && (ret == active)) break; if (timeout <= 0) break; msleep(10); timeout -= 10; } - if (active && ret) + if ((lnk_status != (u16)~0) && active && ret) msleep(delay); - else if (ret != active) + else if ((lnk_status == (u16)~0) || (ret != active)) pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n", active ? "set" : "cleared"); - return ret == active; + return ((lnk_status != (u16)~0) && (ret == active)); } /** @@ -5773,6 +5773,11 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, while (dev) { pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); + if (lnksta == (u16)~0) { + dev = pci_upstream_bridge(dev); + continue; + } + next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; @@ -5819,12 +5824,21 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) * where only 2.5 GT/s and 5.0 GT/s speeds were defined. */ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); + if (lnkcap2 == (u32)~0) { + dev_err(dev, "Read link speed capability has failed.\n"); + return PCI_SPEED_UNKNOWN; + } /* PCIe r3.0-compliant */ if (lnkcap2) return PCIE_LNKCAP2_SLS2SPEED(lnkcap2); pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (lnkcap == (u32)~0) { + dev_err(dev, "Read link speed capability has failed.\n"); + return PCI_SPEED_UNKNOWN; + } + if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB) return PCIE_SPEED_5_0GT; else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB) @@ -5846,7 +5860,7 @@ enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) u32 lnkcap; pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); - if (lnkcap) + if (lnkcap && (lnkcap != (u32)~0)) return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; return PCIE_LNK_WIDTH_UNKNOWN; From patchwork Fri Jul 31 11:43:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11694897 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 44AC81575 for ; Fri, 31 Jul 2020 12:43:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2F0CA22B3F for ; Fri, 31 Jul 2020 12:43:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="la4y7H95" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733275AbgGaMnO (ORCPT ); Fri, 31 Jul 2020 08:43:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733264AbgGaMnN (ORCPT ); Fri, 31 Jul 2020 08:43:13 -0400 Received: from mail-ej1-x641.google.com (mail-ej1-x641.google.com [IPv6:2a00:1450:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4BD5C061574; Fri, 31 Jul 2020 05:43:12 -0700 (PDT) Received: by mail-ej1-x641.google.com with SMTP id qc22so16496244ejb.4; Fri, 31 Jul 2020 05:43:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/Ag7HqTEQtYdyspkqndjVsChgoDS9cn0cuUanYprdzE=; b=la4y7H95zYX+4CoEy2KWgnwHd0vnmrS28bchsmakne3qS/Vr/Sky6Ev/YjdhUqhr2M XV6t+xXPeSq67btafNbmmSQyX6H9Yjj6rqvQ4qQ10ZNZfft55b6Mu1XvNLySCyeIhlo+ FYjF95d8mEvYs/i4achpXV9/bc03XFcBlPd3IgZ1pmjARJ4NohyI4Ci0XDdgUmxZR6fL FiKXofe+k246mlqbVeBqo6MOCPJ9krPxzZ63zpFAoCbdXgJzl4i9pTg+xBnSFRcz8Css jdo5DKuyFa+YL0IdzZjS76IB3PCVBEPaTgDrC7DSGknO1gOfOpC1534vpFnEVCQUWdy4 6Hjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/Ag7HqTEQtYdyspkqndjVsChgoDS9cn0cuUanYprdzE=; b=Ci/q+m69qxcdsGJvjMfpAb5TfYUS3KfToYuVDeTwJS09x/acxSp+S/PLPWHInpb6S7 9NzxR9ql6D4rOIDnfckQ3DUBafMEzOf0HvELmZjBkKMGk9wi5tdnnEAPG0cS1eQPxVRV NP0r8OXsSnmpaFBe2fSd/VhL6TYUvwqxLLQy7nA8epIV/LaTyz+Y35nmSXRmUNtX3qZs zYXBm4jaFFi0yFn4aMl7zlYRVZCc2bMZ/6+wqku1WJDUSc/F0+/YDQn9P1/gksBcDEgn 62RoMqmkAx/ceznwVLpeB/RM1br/j1aukh5Vcx3/sn7z4SjTMzKbsXHCKCGB+JBHa9eW JBUA== X-Gm-Message-State: AOAM5331jgCvN1EkiyMjWxB8e7HnjLxuULt3XXSna9aHwLq2oUntU3tw 975H0osahlvoeGvvbyumNaA= X-Google-Smtp-Source: ABdhPJxazhT1zvPbkIt354Q4EdFJPin4xMuEu5PAgWug8jOv4Gl1YG1P2lHcWL7ADSCeylA9M/RQ7Q== X-Received: by 2002:a17:906:7855:: with SMTP id p21mr3869401ejm.492.1596199391572; Fri, 31 Jul 2020 05:43:11 -0700 (PDT) Received: from net.saheed (95C84E0A.dsl.pool.telekom.hu. [149.200.78.10]) by smtp.gmail.com with ESMTPSA id g23sm8668514ejb.24.2020.07.31.05.43.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2020 05:43:11 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org, Russell Currey , Sam Bobroff , "Oliver O'Halloran" Cc: "Saheed O. Bolarinwa" , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 10/12] PCI/AER: Check if pcie_capability_read_*() reads ~0 Date: Fri, 31 Jul 2020 13:43:27 +0200 Message-Id: <20200731114329.100848-3-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200731114329.100848-1-refactormyself@gmail.com> References: <20200731114329.100848-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On failure pcie_capability_read_*() sets it's last parameter, val to 0. However, with Patch 12/12, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). Since ~0 is an invalid value in here, Add extra check for ~0 to the if condition to confirm failure. Suggested-by: Bjorn Helgaas Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 3acf56683915..dbeabc370efc 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -829,7 +829,7 @@ static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info) /* Check if AER is enabled */ pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16); - if (!(reg16 & PCI_EXP_AER_FLAGS)) + if ((reg16 == (u16)~0) || !(reg16 & PCI_EXP_AER_FLAGS)) return false; if (!aer) From patchwork Fri Jul 31 11:43:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11694895 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 26D44912 for ; Fri, 31 Jul 2020 12:43:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0F85622B3F for ; Fri, 31 Jul 2020 12:43:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ld0t00pE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733289AbgGaMnQ (ORCPT ); Fri, 31 Jul 2020 08:43:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733281AbgGaMnO (ORCPT ); Fri, 31 Jul 2020 08:43:14 -0400 Received: from mail-ej1-x641.google.com (mail-ej1-x641.google.com [IPv6:2a00:1450:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BD4EC061574; Fri, 31 Jul 2020 05:43:14 -0700 (PDT) Received: by mail-ej1-x641.google.com with SMTP id kq25so18332432ejb.3; Fri, 31 Jul 2020 05:43:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W3jrzpfEeWtPMNu6ebBkWvuMrQ1sgOT+1rw4Pu7mEnM=; b=ld0t00pEM0MZcb/2HS5Hxc5/1Alb6cpV0465TUImsXBfXqlUiXv3qgnP5THp7GdyWt 8PN897B99gz/5u30giINZNvDMT6/mWuvIXe+TcNMuLxTvnH9PCytRwpSraftTJMgQpWe spoy/g9Lh0dsyUDMi87W9NTpVJ2/JlZ3B2T3++DAouHdqUuMr4fStgrbobkymQoX5/nx LG/NUMGNDA29W4D704MLbhgeamT2vFggAA15Dd8orS57Vd6d1CNKgfLP7fpy87FzJkLH UPK/9ubqDzWSkKxoO8jdts69q2aW31ePssin6RT9S8aPsvQphdqn8XgF5w3oA6zSoxmE Dw9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W3jrzpfEeWtPMNu6ebBkWvuMrQ1sgOT+1rw4Pu7mEnM=; b=UjJdcjDUKeH2U/VGuQ92H9MlzmpTciwNYvS81MamMaxEVXXF+zcZ+FAPBqdQ1lZXRW DYVRIgvGJIT25G4GnvCI3Z6HobcRakFqTIId36WHbfKOwpdOllaDGsIvUMDBaEGTTTqU J+bbk4ZycEtJ6SV5tYhLGc+GS2MXbcciRr0xdlvCqWqpt0jgQXRcapeXqjjLUZkfLXI3 EaV8CtygCkBzB1E1zTbvdkylnmw85gkWqefza0VIJ39o3LKQY1QUAe72T3CJB9zLZZK7 i9kVHP/UVU3cbW0bFFYhWbKDC0IaLZ22eKfa/X6MZgQjqRugmqL1pX3205LKmLZaBa/m W+cA== X-Gm-Message-State: AOAM531R7adiB8z2rn2pXQ2jm/sJr+H54x3es+HLwp3jQRdQ4a3GYu/2 9WBtKCWu3fbqnQHr0L4MFI1CvACss45Ytw== X-Google-Smtp-Source: ABdhPJyJ0iZIhz348o3l6wmkHxHvqln6F0gnPCiag58gIVbti5JjZMxnOWyTHRJJZGkCk1hWy3BckA== X-Received: by 2002:a17:906:1f53:: with SMTP id d19mr3799144ejk.327.1596199392870; Fri, 31 Jul 2020 05:43:12 -0700 (PDT) Received: from net.saheed (95C84E0A.dsl.pool.telekom.hu. [149.200.78.10]) by smtp.gmail.com with ESMTPSA id g23sm8668514ejb.24.2020.07.31.05.43.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2020 05:43:12 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 11/12] PCI/ASPM: Check if pcie_capability_read_*() reads ~0 Date: Fri, 31 Jul 2020 13:43:28 +0200 Message-Id: <20200731114329.100848-4-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200731114329.100848-1-refactormyself@gmail.com> References: <20200731114329.100848-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On failure pcie_capability_read_*() sets it's last parameter, val to 0. However, with Patch 12/12, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x). Since ~0 is an invalid value in here, Add extra check for ~0 to the if condition to confirm failure. Suggested-by: Bjorn Helgaas Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index b17e5ffd31b1..5e84a5ee94b0 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -223,7 +223,7 @@ static bool pcie_retrain_link(struct pcie_link_state *link) end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; do { pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_LT)) + if ((reg16 == (u16)~0) || !(reg16 & PCI_EXP_LNKSTA_LT)) break; msleep(1); } while (time_before(jiffies, end_jiffies)); @@ -250,23 +250,23 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) /* Check downstream component if bit Slot Clock Configuration is 1 */ pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_SLC)) + if ((reg16 == (u16)~0) || !(reg16 & PCI_EXP_LNKSTA_SLC)) same_clock = 0; /* Check upstream component if bit Slot Clock Configuration is 1 */ pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_SLC)) + if ((reg16 == (u16)~0) || !(reg16 & PCI_EXP_LNKSTA_SLC)) same_clock = 0; /* Port might be already in common clock mode */ pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); - if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) { + if ((reg16 != (u16)~0) && same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) { bool consistent = true; list_for_each_entry(child, &linkbus->devices, bus_list) { pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); - if (!(reg16 & PCI_EXP_LNKCTL_CCC)) { + if ((reg16 == (u16)~0) || !(reg16 & PCI_EXP_LNKCTL_CCC)) { consistent = false; break; } From patchwork Fri Jul 31 11:43:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Saheed O. Bolarinwa" X-Patchwork-Id: 11694893 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 73C9D1575 for ; Fri, 31 Jul 2020 12:43:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5C1132245C for ; Fri, 31 Jul 2020 12:43:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Boub8lNC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733303AbgGaMnR (ORCPT ); Fri, 31 Jul 2020 08:43:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733294AbgGaMnQ (ORCPT ); Fri, 31 Jul 2020 08:43:16 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39046C061574; Fri, 31 Jul 2020 05:43:16 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id a26so5480429ejc.2; Fri, 31 Jul 2020 05:43:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z7WaVDyC31Xqp9aG4vaiaHbvwp6b775oA7lj7CzrKBo=; b=Boub8lNC8OOZzaDP7HakRmCigQ9s+TmAZKT/FvTXISovow+eY1+3iv9s7tVr5dADQb tIF5zqqI08ULoL0yyrXmhoapYfXxmRW0lyX2RCJXcewDU1EB9xdyPBrZABXn08aJJ28c Ix6TlonWfWSChmEA3cZnWfApy3SwFu1s8TocFkM7yBDwtH78cBXTAF1xTDgYs+VIg8UE kcTAWODekL0CEEpa/XJHHc7Z1xM6Zm5QjgRxMYhQQz3mO4eSz2plfe9QNw1SAJHLLj1J ZA6BNEbFTnFQK6vaB1h+hfyveE/uv2QDJ4RmDfBaoT3ERtSvXRg9SGL9BruBwod71w3x jyzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z7WaVDyC31Xqp9aG4vaiaHbvwp6b775oA7lj7CzrKBo=; b=odC0C2Z8qjc/R3Sxg0m4I69+a65FMfT2PdfWwCtNsIWoRrbgPdA+xt0zGud2eEx0/5 ngabfGy3s7C4W9vCCQ0o1gmzVhzDwrJHa+wrLnWQIZayyjumBn8lNQRm3lYMXBMtA584 LBXgkCEGQh2jyKGcN9NghACKAH4M7awzVYg1VpZs3kayTb10Qn+5lo/f00IJ9C41ipul jiZdEfgvwsirvdJvFev6GW5oGPl5s3uN+oJbhsoXzVbvVl5nWXJL4eBGM0NZvzTv44zI FPZvuIULjyCzNbGLSbnhZq93NPV4mixtQKviRH9hWBdcgs9bLaB4sAdkYnqQYEs/cU9h 8+Vg== X-Gm-Message-State: AOAM532XKTpbopjI5UTUXS/eMRcU41K8ehA6w8GKqZdSMzL3D1mGOAqk tM+vhD+Xftju+LX5tijJ6sc= X-Google-Smtp-Source: ABdhPJz2I4wMlXEMP6P1KRM4mmo8+jpv64fXNEUIP720yCcVBp2o7uTyVYR6ab20bRx5VLVhSw6mFA== X-Received: by 2002:a17:906:3281:: with SMTP id 1mr3932259ejw.132.1596199394967; Fri, 31 Jul 2020 05:43:14 -0700 (PDT) Received: from net.saheed (95C84E0A.dsl.pool.telekom.hu. [149.200.78.10]) by smtp.gmail.com with ESMTPSA id g23sm8668514ejb.24.2020.07.31.05.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2020 05:43:14 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Cc: "Saheed O. Bolarinwa" , bjorn@helgaas.com, skhan@linuxfoundation.org, linux-kernel-mentees@lists.linuxfoundation.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org, QCA ath9k Development , linux-wireless@vger.kernel.org, netdev@vger.kernel.org, linux-acpi@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Mike Marciniszyn , Dennis Dalessandro , Doug Ledford , Jason Gunthorpe , Arnd Bergmann , Greg Kroah-Hartman , "David S. Miller" , Kalle Valo , Jakub Kicinski , "Rafael J. Wysocki" , Len Brown , Russell Currey , Sam Bobroff , "Oliver O'Halloran" Subject: [PATCH v4 12/12] PCI: Remove '*val = 0' from pcie_capability_read_*() Date: Fri, 31 Jul 2020 13:43:29 +0200 Message-Id: <20200731114329.100848-5-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200731114329.100848-1-refactormyself@gmail.com> References: <20200731114329.100848-1-refactormyself@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org There are several reasons why a PCI capability read may fail whether the device is present or not. If this happens, pcie_capability_read_*() will return -EINVAL/PCIBIOS_BAD_REGISTER_NUMBER or PCIBIOS_DEVICE_NOT_FOUND and *val is set to 0. This behaviour if further ensured by this code inside pcie_capability_read_*() ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); /* * Reset *val to 0 if pci_read_config_dword() fails, it may * have been written as 0xFFFFFFFF if hardware error happens * during pci_read_config_dword(). */ if (ret) *val = 0; return ret; a) Since all pci_generic_config_read() does is read a register value, it may return success after reading a ~0 which *may* have been fabricated by the PCI host bridge due to a read timeout. Hence pci_read_config_*() will return success with a fabricated ~0 in *val, indicating a problem. In this case, the assumed behaviour of pcie_capability_read_*() will be wrong. To avoid error slipping through, more checks are necessary. b) pci_read_config_*() will return PCIBIOS_DEVICE_NOT_FOUND only if dev->error_state = pci_channel_io_perm_failure (i.e. pci_dev_is_disconnected()) or if pci_generic_config_read() can't find the device. In both cases *val is initially set to ~0 but as shown in the code above pcie_capability_read_*() resets it back to 0. Even with this effort, drivers still have to perform validation checks more so if 0 is a valid value. Most drivers only consider the case (b) and in some cases, there is the expectation that on timeout *val has a fabricated value of ~0, which *may* not always be true as explained in (a). In any case, checks need to be done to validate the value read and maybe confirm which error has occurred. It is better left to the drivers to do. Remove the reset of *val to 0 when pci_read_config_*() fails. Suggested-by: Bjorn Helgaas Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/access.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/drivers/pci/access.c b/drivers/pci/access.c index 79c4a2ef269a..ec95edbb1ac8 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -413,13 +413,6 @@ int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val) if (pcie_capability_reg_implemented(dev, pos)) { ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val); - /* - * Reset *val to 0 if pci_read_config_word() fails, it may - * have been written as 0xFFFF if hardware error happens - * during pci_read_config_word(). - */ - if (ret) - *val = 0; return ret; } @@ -448,13 +441,6 @@ int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val) if (pcie_capability_reg_implemented(dev, pos)) { ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val); - /* - * Reset *val to 0 if pci_read_config_dword() fails, it may - * have been written as 0xFFFFFFFF if hardware error happens - * during pci_read_config_dword(). - */ - if (ret) - *val = 0; return ret; }