From patchwork Mon Aug 3 07:14:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11697471 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2ADA5138A for ; Mon, 3 Aug 2020 07:15:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 10668206E9 for ; Mon, 3 Aug 2020 07:15:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="GfoefXQ3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725861AbgHCHPv (ORCPT ); Mon, 3 Aug 2020 03:15:51 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:38599 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725831AbgHCHPv (ORCPT ); Mon, 3 Aug 2020 03:15:51 -0400 X-UUID: f4ffb50abf1b4c5c8a1058b85745fd28-20200803 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=UzIoA2ysnfBcZNVziS897PQDQ/2KuLvwQgA3q2i0GJY=; b=GfoefXQ3SdLHjV0aruE7AATe9oECvc+NTpJ+GgQhUTR4l9mGA987PoWZm/anPc+6czag73n/DckCs5FVaDtfZUIM8W7ng/JKUv5GIpVhXFd+DmesLgBpNyWElzx2UHthOLAjMVTMm2lTPNCDhcg8rFw6iPzbDAHhm3JA5A/NXPg=; X-UUID: f4ffb50abf1b4c5c8a1058b85745fd28-20200803 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 756827328; Mon, 03 Aug 2020 15:15:48 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 Aug 2020 15:15:45 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 Aug 2020 15:15:44 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v4,1/5] dt-binding: mediatek: watchdog: fix the description of compatible Date: Mon, 3 Aug 2020 15:14:57 +0800 Message-ID: <20200803071501.30634-2-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200803071501.30634-1-crystal.guo@mediatek.com> References: <20200803071501.30634-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org The watchdog driver for MT2712 and MT8183 relies on DT data, so the fallback compatible MT6589 won't work. Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger Reviewed-by: Guenter Roeck --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 4dd36bd3f1ad..45eedc2c3141 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -4,13 +4,13 @@ Required properties: - compatible should contain: "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 - "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712 + "mediatek,mt2712-wdt": for MT2712 "mediatek,mt6589-wdt": for MT6589 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623 "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 - "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183 + "mediatek,mt8183-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 - reg : Specifies base physical address and size of the registers. From patchwork Mon Aug 3 07:14:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11697481 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1BDC5722 for ; Mon, 3 Aug 2020 07:16:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 025FE206D7 for ; Mon, 3 Aug 2020 07:16:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="JDChQfHQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726034AbgHCHPx (ORCPT ); Mon, 3 Aug 2020 03:15:53 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:55485 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725831AbgHCHPw (ORCPT ); Mon, 3 Aug 2020 03:15:52 -0400 X-UUID: c2537ea433c54336b342b289ab9c929e-20200803 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=lpuSKaOUayTd7d3eBZZ9hu+OIt66WFsS5MXoXt1AMMA=; b=JDChQfHQ9So2Gfdu9O5IMh1k+Q5DnwCaHDJCTXPAhl9FTlClyNY5//GJsE67qSJz5bp1owv1aZJyTOXjQVCzi0xREKuqAYx0DP8fP7A1JA7moUXXl64O1sblQbw797HXJO5OQZE6eO1q1D6XpRW/7NIcSWMaUbHtM17UCPuuNaY=; X-UUID: c2537ea433c54336b342b289ab9c929e-20200803 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1811670260; Mon, 03 Aug 2020 15:15:48 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 Aug 2020 15:15:45 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 Aug 2020 15:15:45 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v4,2/5] arm64: dts: mt8183: update watchdog device node Date: Mon, 3 Aug 2020 15:14:58 +0800 Message-ID: <20200803071501.30634-3-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200803071501.30634-1-crystal.guo@mediatek.com> References: <20200803071501.30634-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org The watchdog driver for MT8183 relies on DT data, so the fallback compatible MT6589 won't work, need to update watchdog device node to sync with watchdog dt-binding document. Signed-off-by: Crystal Guo Acked-by: Guenter Roeck --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 1e03c849dc5d..f8d835746ab8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -310,8 +310,7 @@ }; watchdog: watchdog@10007000 { - compatible = "mediatek,mt8183-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt8183-wdt"; reg = <0 0x10007000 0 0x100>; #reset-cells = <1>; }; From patchwork Mon Aug 3 07:14:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11697473 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B0BDF138A for ; Mon, 3 Aug 2020 07:15:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 98FAE2075A for ; Mon, 3 Aug 2020 07:15:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="JKqzL3gW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726118AbgHCHPy (ORCPT ); Mon, 3 Aug 2020 03:15:54 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:55066 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725855AbgHCHPx (ORCPT ); Mon, 3 Aug 2020 03:15:53 -0400 X-UUID: 83db4d96e74947709a2fa7bc6fea14ae-20200803 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=V0XHyqq4D13l/tJUvNmzHj4e1uk9k7au8T5F6+FRuGc=; b=JKqzL3gWm3iwjR1uZRSksSFpivJJIglj7ZN9gk8INWxZjxFes7PSiyX/FlPlpiZpf2xkTbrVuLAJd0YELfiGubcXwlRbOlqB2DO8ZjvwzA3eoHphgaM6Dm8lWaA3L7UD6eO2niCEutg54hRzoAj7Ug8selPNG+5UbWZMuwMZ8yg=; X-UUID: 83db4d96e74947709a2fa7bc6fea14ae-20200803 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1357255327; Mon, 03 Aug 2020 15:15:49 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 Aug 2020 15:15:46 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 Aug 2020 15:15:46 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v4,3/5] dt-binding: mediatek: mt8192: update mtk-wdt document Date: Mon, 3 Aug 2020 15:14:59 +0800 Message-ID: <20200803071501.30634-4-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200803071501.30634-1-crystal.guo@mediatek.com> References: <20200803071501.30634-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org update mtk-wdt document for MT8192 platform Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger Reviewed-by: Guenter Roeck --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 45eedc2c3141..e36ba60de829 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -12,6 +12,7 @@ Required properties: "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 "mediatek,mt8183-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 + "mediatek,mt8192-wdt": for MT8192 - reg : Specifies base physical address and size of the registers. From patchwork Mon Aug 3 07:15:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11697479 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 57F4F138A for ; Mon, 3 Aug 2020 07:16:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4000B206E9 for ; Mon, 3 Aug 2020 07:16:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="M0gif7lQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726243AbgHCHQA (ORCPT ); Mon, 3 Aug 2020 03:16:00 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:39511 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726125AbgHCHPz (ORCPT ); Mon, 3 Aug 2020 03:15:55 -0400 X-UUID: da9ff929f236497985a6641e3534a480-20200803 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=CNroCAZ0RL2N4ZfavyHWU/kNJ5us1mqnMHLPTgRxTSI=; b=M0gif7lQTTZI2Kps5e9YXK+h5ChG3QBhzNG+n2X8uOG/5ggKCkI40KJ3gcXGaae+25iZyevPHqkTXF+nVNsD2m7ktid1gZ1vqbzkzH6uJ8woUO9hIi0RoY05WWU3TeXQw8a4Qd6ZIpYUaFmiiPCXA1JRuMypvZR2cIBIx7W3d6c=; X-UUID: da9ff929f236497985a6641e3534a480-20200803 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1374218471; Mon, 03 Aug 2020 15:15:51 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 Aug 2020 15:15:47 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 Aug 2020 15:15:47 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v4,4/5] dt-binding: mt8192: add toprgu reset-controller head file Date: Mon, 3 Aug 2020 15:15:00 +0800 Message-ID: <20200803071501.30634-5-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200803071501.30634-1-crystal.guo@mediatek.com> References: <20200803071501.30634-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: CC8ACE99E7C3A2203BB499DE3F720B05598A06C197EC599126E29BFB8327004D2000:8 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org add toprgu reset-controller head file for MT8192 platform Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger Acked-by: Guenter Roeck --- .../reset-controller/mt8192-resets.h | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h new file mode 100644 index 000000000000..84fee34f1c32 --- /dev/null +++ b/include/dt-bindings/reset-controller/mt8192-resets.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Yong Liang + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 + +#define MT8183_TOPRGU_MM_SW_RST 1 +#define MT8183_TOPRGU_MFG_SW_RST 2 +#define MT8183_TOPRGU_VENC_SW_RST 3 +#define MT8183_TOPRGU_VDEC_SW_RST 4 +#define MT8183_TOPRGU_IMG_SW_RST 5 +#define MT8183_TOPRGU_MD_SW_RST 7 +#define MT8183_TOPRGU_CONN_SW_RST 9 +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8183_TOPRGU_IPU0_SW_RST 14 +#define MT8183_TOPRGU_IPU1_SW_RST 15 +#define MT8183_TOPRGU_AUDIO_SW_RST 17 +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 +#define MT8192_TOPRGU_MJC_SW_RST 19 +#define MT8192_TOPRGU_C2K_S2_SW_RST 20 +#define MT8192_TOPRGU_C2K_SW_RST 21 +#define MT8192_TOPRGU_PERI_SW_RST 22 +#define MT8192_TOPRGU_PERI_AO_SW_RST 23 + +#define MT8192_TOPRGU_SW_RST_NUM 23 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ From patchwork Mon Aug 3 07:15:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Guo X-Patchwork-Id: 11697475 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D93FD722 for ; Mon, 3 Aug 2020 07:15:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BE1E6206D7 for ; Mon, 3 Aug 2020 07:15:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="KV7eRf6U" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726149AbgHCHPz (ORCPT ); Mon, 3 Aug 2020 03:15:55 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:55879 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726077AbgHCHPy (ORCPT ); Mon, 3 Aug 2020 03:15:54 -0400 X-UUID: 0a3e5537fda44713a809bef3a2fb8372-20200803 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=CHjYwY83mGtQyAozDroVVTm5cwJQTRU4xw97Fx3g4E4=; b=KV7eRf6US1Dn1adMUwV+ROkMxKfDagXQcv1G4gsLN9fql8pB67wjdG7lAHMtqgWtTgW7uIsydGkWEapIdIWrLgnFYtNSZ+Zgma9W1G2wSdtSQv3hhGj16ES+NE1Raoys4VS89FnFnaDAfEbnaJtvqC/ON23LNAvjd8+8Q4cUylQ=; X-UUID: 0a3e5537fda44713a809bef3a2fb8372-20200803 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1312730950; Mon, 03 Aug 2020 15:15:51 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 Aug 2020 15:15:48 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 Aug 2020 15:15:48 +0800 From: Crystal Guo To: , , CC: , , , , , , Crystal Guo Subject: [v4,5/5] watchdog: mt8192: add wdt support Date: Mon, 3 Aug 2020 15:15:01 +0800 Message-ID: <20200803071501.30634-6-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200803071501.30634-1-crystal.guo@mediatek.com> References: <20200803071501.30634-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Add support for watchdog device found in MT8192 SoC Signed-off-by: Crystal Guo Reviewed-by: Matthias Brugger Reviewed-by: Guenter Roeck --- drivers/watchdog/mtk_wdt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index d6a6393f609d..aef0c2db6a11 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -76,6 +77,10 @@ static const struct mtk_wdt_data mt8183_data = { .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM, }; +static const struct mtk_wdt_data mt8192_data = { + .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM, +}; + static int toprgu_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -322,6 +327,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = { { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, { .compatible = "mediatek,mt6589-wdt" }, { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, + { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);