From patchwork Fri Oct 19 12:29:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 10649311 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1E05E13A4 for ; Fri, 19 Oct 2018 12:49:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 071AF28AC4 for ; Fri, 19 Oct 2018 12:49:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EF2D228ADA; Fri, 19 Oct 2018 12:49:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8BABE28AC4 for ; Fri, 19 Oct 2018 12:49:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Date:Message-Id: In-Reply-To:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: References:List-Owner; bh=AP/eeGmXk6nABBwU+V/1QSy16rNXVYEg9vZjYmQR/MA=; b=PZG N5JgbU+S6SM4cqCXUzYbaTgsndl4+beuVBgr7Oedu38FG5vpx1nm8R6sZuCzZkc9WpAh2K792Fhgo khdiNaKqsXBbgcgGpiKj1yBLlYGt7r0b20yyS9zJsmi21MWyV+0X/3MkMOZTzOD2MVup8xBp8RDW/ 3++LKxLyCIaTabfy8z+XVZtyDDhgsri2LS6eibll2rjzJ9jCJjfukW1neXePmkV2RPfargGu+Swd/ //8SVGxd5mDfYbADoMJe9Dn7vE1rC+uB3T7o8x1osxd1CZ21Kg56qV449czU48Zsw8D2XmklSeZQm tgqWxANLuvGjO3FnGfnwoV5+6Eh2fZw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gDUDD-0004oF-Ua; Fri, 19 Oct 2018 12:49:07 +0000 Received: from merlin.infradead.org ([2001:8b0:10b:1231::1]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gDUBA-0003uD-4D for linux-arm-kernel@bombadil.infradead.org; Fri, 19 Oct 2018 12:47:00 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=merlin.20170209; h=Date:Message-Id:In-Reply-To:Subject:Cc: To:From:Sender:Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:References:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=cBywXQcIdxdmts9uSYu0AjsuySiX7ihxshDNSaC2mRg=; b=qd1KqkucOMpU/MFuYPtC/PknIF SJ3yki/QRdxk++IbrP1Ietr4bbGQDT7R95A/8t3MBIiqFHc4+b6oa+3CjW94AQmSpdRLtl1jVd0jA RHJcNSxDsTr3HLw6ZMnzVDsEBK/FpsY9uFjDTlBaPcJ+9DicEQVfVkACtLKbpn7W5aGhLdw0EHdPF jibFKxuoJUrJ+fi41/e7SEecbr8wf6+tS/Mn9SK3lTa8o5AHzsCAd7tXwfHkIy1D7GzK2R49TQAnx we1M/hB5l4IGGHT1h+iYG19LObeL5hj9eZOmJZUuB4Go6gW4uxICyTbCOOPn0A0/mOpoUkiskT8nd XcWTW/gw==; Received: from heliosphere.sirena.org.uk ([2a01:7e01::f03c:91ff:fed4:a3b6]) by merlin.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gDTux-00055Z-Fu for linux-arm-kernel@lists.infradead.org; Fri, 19 Oct 2018 12:30:16 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sirena.org.uk; s=20170815-heliosphere; h=Date:Message-Id:In-Reply-To: Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Id:List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner: List-Archive; bh=cBywXQcIdxdmts9uSYu0AjsuySiX7ihxshDNSaC2mRg=; b=jPbP2xsy6KXg BclaCuGD9UpJHxIEuIUgUtf6w2YAaFfkOPBXWBNiBBB880uymuIurqESAJ5A2RKqPsSLImmpieOoz H6zdZAqGihXyW2wc1aecEhCUpzFE9PUEQqJcG690XHPETsbgt28mi0Jxcml7D4VhbNhCkrm4vGKBX TdpMw=; Received: from cpc102320-sgyl38-2-0-cust46.18-2.cable.virginm.net ([82.37.168.47] helo=debutante.sirena.org.uk) by heliosphere.sirena.org.uk with esmtpa (Exim 4.89) (envelope-from ) id 1gDTug-00005F-L7; Fri, 19 Oct 2018 12:29:58 +0000 Received: by debutante.sirena.org.uk (Postfix, from userid 1000) id 67B8D1122548; Fri, 19 Oct 2018 13:29:58 +0100 (BST) From: Mark Brown To: Ludovic Barre Subject: Applied "dt-bindings: spi: add stm32 qspi controller" to the spi tree In-Reply-To: <1538725383-19781-2-git-send-email-ludovic.Barre@st.com> Message-Id: <20181019122958.67B8D1122548@debutante.sirena.org.uk> Date: Fri, 19 Oct 2018 13:29:58 +0100 (BST) X-Bad-Reply: In-Reply-To but no 'Re:' in Subject. X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181019_083015_670158_41DA62CB X-CRM114-Status: GOOD ( 17.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Alexandre Torgue , Boris Brezillon , linux-kernel@vger.kernel.org, Rob Herring , linux-spi@vger.kernel.org, Marek Vasut , Mark Brown , Maxime Coquelin , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The patch dt-bindings: spi: add stm32 qspi controller has been applied to the spi tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark From 0c0eb3ba9186138b0ffed91e994d473d0f0960cf Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Fri, 5 Oct 2018 09:43:02 +0200 Subject: [PATCH] dt-bindings: spi: add stm32 qspi controller This patch adds the documentation of device tree bindings for the STM32 QSPI controller. It is a specialized communication interface targeting single, dual or quad SPI Flash memories (NOR/NAND). Signed-off-by: Ludovic Barre Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- .../bindings/spi/spi-stm32-qspi.txt | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-stm32-qspi.txt diff --git a/Documentation/devicetree/bindings/spi/spi-stm32-qspi.txt b/Documentation/devicetree/bindings/spi/spi-stm32-qspi.txt new file mode 100644 index 000000000000..adeeb63e84b9 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-stm32-qspi.txt @@ -0,0 +1,44 @@ +* STMicroelectronics Quad Serial Peripheral Interface(QSPI) + +Required properties: +- compatible: should be "st,stm32f469-qspi" +- reg: the first contains the register location and length. + the second contains the memory mapping address and length +- reg-names: should contain the reg names "qspi" "qspi_mm" +- interrupts: should contain the interrupt for the device +- clocks: the phandle of the clock needed by the QSPI controller +- A pinctrl must be defined to set pins in mode of operation for QSPI transfer + +Optional properties: +- resets: must contain the phandle to the reset controller. + +A spi flash (NOR/NAND) must be a child of spi node and could have some +properties. Also see jedec,spi-nor.txt. + +Required properties: +- reg: chip-Select number (QSPI controller may connect 2 flashes) +- spi-max-frequency: max frequency of spi bus + +Optional property: +- spi-rx-bus-width: see ./spi-bus.txt for the description + +Example: + +qspi: spi@a0001000 { + compatible = "st,stm32f469-qspi"; + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = <91>; + resets = <&rcc STM32F4_AHB3_RESET(QSPI)>; + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + ... + }; +};