From patchwork Wed Aug 12 09:37:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VuYmluIE1laSAo5qKF5paH5b2sKQ==?= X-Patchwork-Id: 11710539 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E376614E3 for ; Wed, 12 Aug 2020 09:38:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CB37D21744 for ; Wed, 12 Aug 2020 09:38:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="lEdPDb2l" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727123AbgHLJib (ORCPT ); Wed, 12 Aug 2020 05:38:31 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:5035 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726942AbgHLJib (ORCPT ); Wed, 12 Aug 2020 05:38:31 -0400 X-UUID: 816964cb39464f43bae2a25323e408b8-20200812 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=nJC5LfTN/6T01ytb031u5VjOdx8ebwn9dtG+2//ns3g=; b=lEdPDb2lT6tbgtVqTakidShlXPgybWACU6rz/tWRveWJ305LCU9p+zao+SrVO0uSuQC4zdVj148sESgr0ReUC/XI48oRWVOJ8SN7czXJtOxURRxdVc3pb7MfKMKJ+J9miruu7KERgFX6jNefj/utHjmbhi4mdJhpXvj7+C97oRs=; X-UUID: 816964cb39464f43bae2a25323e408b8-20200812 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1470046484; Wed, 12 Aug 2020 17:38:27 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 Aug 2020 17:38:25 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 12 Aug 2020 17:38:24 +0800 From: Wenbin Mei To: Ulf Hansson , Rob Herring CC: Chaotian Jing , Matthias Brugger , Philipp Zabel , , , , , , , Wenbin Mei Subject: [PATCH 1/3] mmc: dt-bindings: Add resets/reset-names for Mediatek MMC bindings Date: Wed, 12 Aug 2020 17:37:24 +0800 Message-ID: <20200812093726.10123-2-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200812093726.10123-1-wenbin.mei@mediatek.com> References: <20200812093726.10123-1-wenbin.mei@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add description for resets/reset-names. Signed-off-by: Wenbin Mei --- Documentation/devicetree/bindings/mmc/mtk-sd.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt index 8a532f4453f2..35da72de7aac 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -49,6 +49,8 @@ Optional properties: error caused by stop clock(fifo full) Valid range = [0:0x7]. if not present, default value is 0. applied to compatible "mediatek,mt2701-mmc". +- resets: Phandle and reset specifier pair to softreset line of MSDC IP. +- reset-names: Reset names for MSDC. Examples: mmc0: mmc@11230000 { From patchwork Wed Aug 12 09:37:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VuYmluIE1laSAo5qKF5paH5b2sKQ==?= X-Patchwork-Id: 11710545 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05A0C138C for ; Wed, 12 Aug 2020 09:38:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DEDA9208A9 for ; Wed, 12 Aug 2020 09:38:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="csPrVxKC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727808AbgHLJin (ORCPT ); Wed, 12 Aug 2020 05:38:43 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:29638 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727017AbgHLJib (ORCPT ); Wed, 12 Aug 2020 05:38:31 -0400 X-UUID: 3c61768a41c345b8939f8af611591b97-20200812 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ogFDjQCtEcopOszOYsMoc/JjscsAanywEY3yR0IlUMY=; b=csPrVxKCxTe5smr0IUeJCXH0eXxwjE4Gi1a0opIDhGIanfnvckAiYSEXULkadEVK2WTUB6mMl/t3CTWTrd2gZSaAHNshDpnOlLzE1mqmcslzErWAv0glO9RzBIi7maZTNyGabNB5aYVLVG2at2f2pqejHI6zZ5gX0Ixg2ZduhXs=; X-UUID: 3c61768a41c345b8939f8af611591b97-20200812 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 178852734; Wed, 12 Aug 2020 17:38:27 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 Aug 2020 17:38:26 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 12 Aug 2020 17:38:25 +0800 From: Wenbin Mei To: Ulf Hansson , Rob Herring CC: Chaotian Jing , Matthias Brugger , Philipp Zabel , , , , , , , Wenbin Mei Subject: [PATCH 2/3] arm64: dts: mt7622: add reset node for mmc device Date: Wed, 12 Aug 2020 17:37:25 +0800 Message-ID: <20200812093726.10123-3-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200812093726.10123-1-wenbin.mei@mediatek.com> References: <20200812093726.10123-1-wenbin.mei@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This commit adds reset node for mmc device. Signed-off-by: Wenbin Mei Tested-By: Frank Wunderlich --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 1a39e0ef776b..5b9ec032ce8d 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -686,6 +686,8 @@ clocks = <&pericfg CLK_PERI_MSDC30_0_PD>, <&topckgen CLK_TOP_MSDC50_0_SEL>; clock-names = "source", "hclk"; + resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>; + reset-names = "hrst"; status = "disabled"; }; From patchwork Wed Aug 12 09:37:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VuYmluIE1laSAo5qKF5paH5b2sKQ==?= X-Patchwork-Id: 11710537 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D691A138C for ; Wed, 12 Aug 2020 09:38:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BE93122B43 for ; Wed, 12 Aug 2020 09:38:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="MBy7+yIr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726942AbgHLJif (ORCPT ); Wed, 12 Aug 2020 05:38:35 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:26618 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727808AbgHLJie (ORCPT ); Wed, 12 Aug 2020 05:38:34 -0400 X-UUID: cc2330fe2d444d0c914485b9a5d50b91-20200812 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=n8qTjuU/K0cDmRH8kbn9OnRMWaTi0JfPivM4HICkFOk=; b=MBy7+yIrK00Juy+njlK/GuqyFo2Wz4/pImlPVYvMJWBqW7dMfSrJl77l0G7NZkw9z7nZ53LguO9CYEgiGylQK1p7gIkKu0YJFCYJbg55t/7ufx8eSh+C6ahv2sXpeHOixTRv/xWeuNN7Yc1JDh3vjdPvnUGprrSHQsV0BkxR35g=; X-UUID: cc2330fe2d444d0c914485b9a5d50b91-20200812 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 2102756466; Wed, 12 Aug 2020 17:38:29 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 12 Aug 2020 17:38:26 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 12 Aug 2020 17:38:26 +0800 From: Wenbin Mei To: Ulf Hansson , Rob Herring CC: Chaotian Jing , Matthias Brugger , Philipp Zabel , , , , , , , Wenbin Mei Subject: [PATCH 3/3] mmc: mediatek: add optional module reset property Date: Wed, 12 Aug 2020 17:37:26 +0800 Message-ID: <20200812093726.10123-4-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200812093726.10123-1-wenbin.mei@mediatek.com> References: <20200812093726.10123-1-wenbin.mei@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This patch adds a optional reset management for msdc. Sometimes the bootloader does not bring msdc register to default state, so need reset the msdc controller. Signed-off-by: Wenbin Mei Tested-By: Frank Wunderlich Reviewed-by: Philipp Zabel --- drivers/mmc/host/mtk-sd.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 39e7fc54c438..2b243c03c9b2 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -434,6 +435,7 @@ struct msdc_host { struct msdc_save_para save_para; /* used when gate HCLK */ struct msdc_tune_para def_tune_para; /* default tune setting */ struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ + struct reset_control *reset; }; static const struct mtk_mmc_compatible mt8135_compat = { @@ -1516,6 +1518,12 @@ static void msdc_init_hw(struct msdc_host *host) u32 val; u32 tune_reg = host->dev_comp->pad_tune_reg; + if (!IS_ERR(host->reset)) { + reset_control_assert(host->reset); + usleep_range(10, 50); + reset_control_deassert(host->reset); + } + /* Configure to MMC/SD mode, clock free running */ sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); @@ -2273,6 +2281,11 @@ static int msdc_drv_probe(struct platform_device *pdev) if (IS_ERR(host->src_clk_cg)) host->src_clk_cg = NULL; + host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, + "hrst"); + if (PTR_ERR(host->reset) == -EPROBE_DEFER) + return PTR_ERR(host->reset); + host->irq = platform_get_irq(pdev, 0); if (host->irq < 0) { ret = -EINVAL;