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Mon, 17 Aug 2020 03:48:42 -0700 (PDT) From: Gene Chen To: lee.jones@linaro.org, matthias.bgg@gmail.com Subject: [PATCH v4 1/9] mfd: mt6360: Rearrange include file Date: Mon, 17 Aug 2020 18:47:49 +0800 Message-Id: <1597661277-27862-2-git-send-email-gene.chen.richtek@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> References: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200817_064845_158231_5630345D X-CRM114-Status: GOOD ( 11.71 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:541 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [gene.chen.richtek[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gene_chen@richtek.com, linux-kernel@vger.kernel.org, cy_huang@richtek.com, benjamin.chao@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, shufan_lee@richtek.com MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: Gene Chen Rearrange include file without sorting by alphabet. Signed-off-by: Gene Chen --- drivers/mfd/mt6360-core.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c index e9cacc2..c7a955f 100644 --- a/drivers/mfd/mt6360-core.c +++ b/drivers/mfd/mt6360-core.c @@ -5,15 +5,14 @@ * Author: Gene Chen */ +#include #include -#include #include #include #include #include -#include -#include -#include +#include +#include #include From patchwork Mon Aug 17 10:47:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gene Chen X-Patchwork-Id: 11717947 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1898314F6 for ; Mon, 17 Aug 2020 10:49:07 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D6FB820758 for ; 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Mon, 17 Aug 2020 03:48:46 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:577:c217:67e6:a40c:a3bf:1945]) by smtp.gmail.com with ESMTPSA id k12sm16976528pjp.38.2020.08.17.03.48.43 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Aug 2020 03:48:45 -0700 (PDT) From: Gene Chen To: lee.jones@linaro.org, matthias.bgg@gmail.com Subject: [PATCH v4 2/9] mfd: mt6360: Remove redundant brackets around raw numbers Date: Mon, 17 Aug 2020 18:47:50 +0800 Message-Id: <1597661277-27862-3-git-send-email-gene.chen.richtek@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> References: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200817_064848_707595_C68E3589 X-CRM114-Status: GOOD ( 13.02 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:534 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [gene.chen.richtek[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gene_chen@richtek.com, linux-kernel@vger.kernel.org, cy_huang@richtek.com, benjamin.chao@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, shufan_lee@richtek.com MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: Gene Chen Remove redundant brackets around raw numbers. Signed-off-by: Gene Chen Acked-for-MFD-by: Lee Jones --- drivers/mfd/mt6360-core.c | 172 +++++++++---------- include/linux/mfd/mt6360.h | 410 ++++++++++++++++++++++----------------------- 2 files changed, 291 insertions(+), 291 deletions(-) diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c index c7a955f..befee70 100644 --- a/drivers/mfd/mt6360-core.c +++ b/drivers/mfd/mt6360-core.c @@ -17,107 +17,107 @@ #include /* reg 0 -> 0 ~ 7 */ -#define MT6360_CHG_TREG_EVT (4) -#define MT6360_CHG_AICR_EVT (5) -#define MT6360_CHG_MIVR_EVT (6) -#define MT6360_PWR_RDY_EVT (7) +#define MT6360_CHG_TREG_EVT 4 +#define MT6360_CHG_AICR_EVT 5 +#define MT6360_CHG_MIVR_EVT 6 +#define MT6360_PWR_RDY_EVT 7 /* REG 1 -> 8 ~ 15 */ -#define MT6360_CHG_BATSYSUV_EVT (9) -#define MT6360_FLED_CHG_VINOVP_EVT (11) -#define MT6360_CHG_VSYSUV_EVT (12) -#define MT6360_CHG_VSYSOV_EVT (13) -#define MT6360_CHG_VBATOV_EVT (14) -#define MT6360_CHG_VBUSOV_EVT (15) +#define MT6360_CHG_BATSYSUV_EVT 9 +#define MT6360_FLED_CHG_VINOVP_EVT 11 +#define MT6360_CHG_VSYSUV_EVT 12 +#define MT6360_CHG_VSYSOV_EVT 13 +#define MT6360_CHG_VBATOV_EVT 14 +#define MT6360_CHG_VBUSOV_EVT 15 /* REG 2 -> 16 ~ 23 */ /* REG 3 -> 24 ~ 31 */ -#define MT6360_WD_PMU_DET (25) -#define MT6360_WD_PMU_DONE (26) -#define MT6360_CHG_TMRI (27) -#define MT6360_CHG_ADPBADI (29) -#define MT6360_CHG_RVPI (30) -#define MT6360_OTPI (31) +#define MT6360_WD_PMU_DET 25 +#define MT6360_WD_PMU_DONE 26 +#define MT6360_CHG_TMRI 27 +#define MT6360_CHG_ADPBADI 29 +#define MT6360_CHG_RVPI 30 +#define MT6360_OTPI 31 /* REG 4 -> 32 ~ 39 */ -#define MT6360_CHG_AICCMEASL (32) -#define MT6360_CHGDET_DONEI (34) -#define MT6360_WDTMRI (35) -#define MT6360_SSFINISHI (36) -#define MT6360_CHG_RECHGI (37) -#define MT6360_CHG_TERMI (38) -#define MT6360_CHG_IEOCI (39) +#define MT6360_CHG_AICCMEASL 32 +#define MT6360_CHGDET_DONEI 34 +#define MT6360_WDTMRI 35 +#define MT6360_SSFINISHI 36 +#define MT6360_CHG_RECHGI 37 +#define MT6360_CHG_TERMI 38 +#define MT6360_CHG_IEOCI 39 /* REG 5 -> 40 ~ 47 */ -#define MT6360_PUMPX_DONEI (40) -#define MT6360_BAT_OVP_ADC_EVT (41) -#define MT6360_TYPEC_OTP_EVT (42) -#define MT6360_ADC_WAKEUP_EVT (43) -#define MT6360_ADC_DONEI (44) -#define MT6360_BST_BATUVI (45) -#define MT6360_BST_VBUSOVI (46) -#define MT6360_BST_OLPI (47) +#define MT6360_PUMPX_DONEI 40 +#define MT6360_BAT_OVP_ADC_EVT 41 +#define MT6360_TYPEC_OTP_EVT 42 +#define MT6360_ADC_WAKEUP_EVT 43 +#define MT6360_ADC_DONEI 44 +#define MT6360_BST_BATUVI 45 +#define MT6360_BST_VBUSOVI 46 +#define MT6360_BST_OLPI 47 /* REG 6 -> 48 ~ 55 */ -#define MT6360_ATTACH_I (48) -#define MT6360_DETACH_I (49) -#define MT6360_QC30_STPDONE (51) -#define MT6360_QC_VBUSDET_DONE (52) -#define MT6360_HVDCP_DET (53) -#define MT6360_CHGDETI (54) -#define MT6360_DCDTI (55) +#define MT6360_ATTACH_I 48 +#define MT6360_DETACH_I 49 +#define MT6360_QC30_STPDONE 51 +#define MT6360_QC_VBUSDET_DONE 52 +#define MT6360_HVDCP_DET 53 +#define MT6360_CHGDETI 54 +#define MT6360_DCDTI 55 /* REG 7 -> 56 ~ 63 */ -#define MT6360_FOD_DONE_EVT (56) -#define MT6360_FOD_OV_EVT (57) -#define MT6360_CHRDET_UVP_EVT (58) -#define MT6360_CHRDET_OVP_EVT (59) -#define MT6360_CHRDET_EXT_EVT (60) -#define MT6360_FOD_LR_EVT (61) -#define MT6360_FOD_HR_EVT (62) -#define MT6360_FOD_DISCHG_FAIL_EVT (63) +#define MT6360_FOD_DONE_EVT 56 +#define MT6360_FOD_OV_EVT 57 +#define MT6360_CHRDET_UVP_EVT 58 +#define MT6360_CHRDET_OVP_EVT 59 +#define MT6360_CHRDET_EXT_EVT 60 +#define MT6360_FOD_LR_EVT 61 +#define MT6360_FOD_HR_EVT 62 +#define MT6360_FOD_DISCHG_FAIL_EVT 63 /* REG 8 -> 64 ~ 71 */ -#define MT6360_USBID_EVT (64) -#define MT6360_APWDTRST_EVT (65) -#define MT6360_EN_EVT (66) -#define MT6360_QONB_RST_EVT (67) -#define MT6360_MRSTB_EVT (68) -#define MT6360_OTP_EVT (69) -#define MT6360_VDDAOV_EVT (70) -#define MT6360_SYSUV_EVT (71) +#define MT6360_USBID_EVT 64 +#define MT6360_APWDTRST_EVT 65 +#define MT6360_EN_EVT 66 +#define MT6360_QONB_RST_EVT 67 +#define MT6360_MRSTB_EVT 68 +#define MT6360_OTP_EVT 69 +#define MT6360_VDDAOV_EVT 70 +#define MT6360_SYSUV_EVT 71 /* REG 9 -> 72 ~ 79 */ -#define MT6360_FLED_STRBPIN_EVT (72) -#define MT6360_FLED_TORPIN_EVT (73) -#define MT6360_FLED_TX_EVT (74) -#define MT6360_FLED_LVF_EVT (75) -#define MT6360_FLED2_SHORT_EVT (78) -#define MT6360_FLED1_SHORT_EVT (79) +#define MT6360_FLED_STRBPIN_EVT 72 +#define MT6360_FLED_TORPIN_EVT 73 +#define MT6360_FLED_TX_EVT 74 +#define MT6360_FLED_LVF_EVT 75 +#define MT6360_FLED2_SHORT_EVT 78 +#define MT6360_FLED1_SHORT_EVT 79 /* REG 10 -> 80 ~ 87 */ -#define MT6360_FLED2_STRB_EVT (80) -#define MT6360_FLED1_STRB_EVT (81) -#define MT6360_FLED2_STRB_TO_EVT (82) -#define MT6360_FLED1_STRB_TO_EVT (83) -#define MT6360_FLED2_TOR_EVT (84) -#define MT6360_FLED1_TOR_EVT (85) +#define MT6360_FLED2_STRB_EVT 80 +#define MT6360_FLED1_STRB_EVT 81 +#define MT6360_FLED2_STRB_TO_EVT 82 +#define MT6360_FLED1_STRB_TO_EVT 83 +#define MT6360_FLED2_TOR_EVT 84 +#define MT6360_FLED1_TOR_EVT 85 /* REG 11 -> 88 ~ 95 */ /* REG 12 -> 96 ~ 103 */ -#define MT6360_BUCK1_PGB_EVT (96) -#define MT6360_BUCK1_OC_EVT (100) -#define MT6360_BUCK1_OV_EVT (101) -#define MT6360_BUCK1_UV_EVT (102) +#define MT6360_BUCK1_PGB_EVT 96 +#define MT6360_BUCK1_OC_EVT 100 +#define MT6360_BUCK1_OV_EVT 101 +#define MT6360_BUCK1_UV_EVT 102 /* REG 13 -> 104 ~ 111 */ -#define MT6360_BUCK2_PGB_EVT (104) -#define MT6360_BUCK2_OC_EVT (108) -#define MT6360_BUCK2_OV_EVT (109) -#define MT6360_BUCK2_UV_EVT (110) +#define MT6360_BUCK2_PGB_EVT 104 +#define MT6360_BUCK2_OC_EVT 108 +#define MT6360_BUCK2_OV_EVT 109 +#define MT6360_BUCK2_UV_EVT 110 /* REG 14 -> 112 ~ 119 */ -#define MT6360_LDO1_OC_EVT (113) -#define MT6360_LDO2_OC_EVT (114) -#define MT6360_LDO3_OC_EVT (115) -#define MT6360_LDO5_OC_EVT (117) -#define MT6360_LDO6_OC_EVT (118) -#define MT6360_LDO7_OC_EVT (119) +#define MT6360_LDO1_OC_EVT 113 +#define MT6360_LDO2_OC_EVT 114 +#define MT6360_LDO3_OC_EVT 115 +#define MT6360_LDO5_OC_EVT 117 +#define MT6360_LDO6_OC_EVT 118 +#define MT6360_LDO7_OC_EVT 119 /* REG 15 -> 120 ~ 127 */ -#define MT6360_LDO1_PGB_EVT (121) -#define MT6360_LDO2_PGB_EVT (122) -#define MT6360_LDO3_PGB_EVT (123) -#define MT6360_LDO5_PGB_EVT (125) -#define MT6360_LDO6_PGB_EVT (126) -#define MT6360_LDO7_PGB_EVT (127) +#define MT6360_LDO1_PGB_EVT 121 +#define MT6360_LDO2_PGB_EVT 122 +#define MT6360_LDO3_PGB_EVT 123 +#define MT6360_LDO5_PGB_EVT 125 +#define MT6360_LDO6_PGB_EVT 126 +#define MT6360_LDO7_PGB_EVT 127 static const struct regmap_irq mt6360_pmu_irqs[] = { REGMAP_IRQ_REG_LINE(MT6360_CHG_TREG_EVT, 8), diff --git a/include/linux/mfd/mt6360.h b/include/linux/mfd/mt6360.h index ea13040..72edf13 100644 --- a/include/linux/mfd/mt6360.h +++ b/include/linux/mfd/mt6360.h @@ -16,10 +16,10 @@ enum { MT6360_SLAVE_MAX, }; -#define MT6360_PMU_SLAVEID (0x34) -#define MT6360_PMIC_SLAVEID (0x1A) -#define MT6360_LDO_SLAVEID (0x64) -#define MT6360_TCPC_SLAVEID (0x4E) +#define MT6360_PMU_SLAVEID 0x34 +#define MT6360_PMIC_SLAVEID 0x1A +#define MT6360_LDO_SLAVEID 0x64 +#define MT6360_TCPC_SLAVEID 0x4E struct mt6360_pmu_data { struct i2c_client *i2c[MT6360_SLAVE_MAX]; @@ -30,211 +30,211 @@ struct mt6360_pmu_data { }; /* PMU register defininition */ -#define MT6360_PMU_DEV_INFO (0x00) -#define MT6360_PMU_CORE_CTRL1 (0x01) -#define MT6360_PMU_RST1 (0x02) -#define MT6360_PMU_CRCEN (0x03) -#define MT6360_PMU_RST_PAS_CODE1 (0x04) -#define MT6360_PMU_RST_PAS_CODE2 (0x05) -#define MT6360_PMU_CORE_CTRL2 (0x06) -#define MT6360_PMU_TM_PAS_CODE1 (0x07) -#define MT6360_PMU_TM_PAS_CODE2 (0x08) -#define MT6360_PMU_TM_PAS_CODE3 (0x09) -#define MT6360_PMU_TM_PAS_CODE4 (0x0A) -#define MT6360_PMU_IRQ_IND (0x0B) -#define MT6360_PMU_IRQ_MASK (0x0C) -#define MT6360_PMU_IRQ_SET (0x0D) -#define MT6360_PMU_SHDN_CTRL (0x0E) -#define MT6360_PMU_TM_INF (0x0F) -#define MT6360_PMU_I2C_CTRL (0x10) -#define MT6360_PMU_CHG_CTRL1 (0x11) -#define MT6360_PMU_CHG_CTRL2 (0x12) -#define MT6360_PMU_CHG_CTRL3 (0x13) -#define MT6360_PMU_CHG_CTRL4 (0x14) -#define MT6360_PMU_CHG_CTRL5 (0x15) -#define MT6360_PMU_CHG_CTRL6 (0x16) -#define MT6360_PMU_CHG_CTRL7 (0x17) -#define MT6360_PMU_CHG_CTRL8 (0x18) -#define MT6360_PMU_CHG_CTRL9 (0x19) -#define MT6360_PMU_CHG_CTRL10 (0x1A) -#define MT6360_PMU_CHG_CTRL11 (0x1B) -#define MT6360_PMU_CHG_CTRL12 (0x1C) -#define MT6360_PMU_CHG_CTRL13 (0x1D) -#define MT6360_PMU_CHG_CTRL14 (0x1E) -#define MT6360_PMU_CHG_CTRL15 (0x1F) -#define MT6360_PMU_CHG_CTRL16 (0x20) -#define MT6360_PMU_CHG_AICC_RESULT (0x21) -#define MT6360_PMU_DEVICE_TYPE (0x22) -#define MT6360_PMU_QC_CONTROL1 (0x23) -#define MT6360_PMU_QC_CONTROL2 (0x24) -#define MT6360_PMU_QC30_CONTROL1 (0x25) -#define MT6360_PMU_QC30_CONTROL2 (0x26) -#define MT6360_PMU_USB_STATUS1 (0x27) -#define MT6360_PMU_QC_STATUS1 (0x28) -#define MT6360_PMU_QC_STATUS2 (0x29) -#define MT6360_PMU_CHG_PUMP (0x2A) -#define MT6360_PMU_CHG_CTRL17 (0x2B) -#define MT6360_PMU_CHG_CTRL18 (0x2C) -#define MT6360_PMU_CHRDET_CTRL1 (0x2D) -#define MT6360_PMU_CHRDET_CTRL2 (0x2E) -#define MT6360_PMU_DPDN_CTRL (0x2F) -#define MT6360_PMU_CHG_HIDDEN_CTRL1 (0x30) -#define MT6360_PMU_CHG_HIDDEN_CTRL2 (0x31) -#define MT6360_PMU_CHG_HIDDEN_CTRL3 (0x32) -#define MT6360_PMU_CHG_HIDDEN_CTRL4 (0x33) -#define MT6360_PMU_CHG_HIDDEN_CTRL5 (0x34) -#define MT6360_PMU_CHG_HIDDEN_CTRL6 (0x35) -#define MT6360_PMU_CHG_HIDDEN_CTRL7 (0x36) -#define MT6360_PMU_CHG_HIDDEN_CTRL8 (0x37) -#define MT6360_PMU_CHG_HIDDEN_CTRL9 (0x38) -#define MT6360_PMU_CHG_HIDDEN_CTRL10 (0x39) -#define MT6360_PMU_CHG_HIDDEN_CTRL11 (0x3A) -#define MT6360_PMU_CHG_HIDDEN_CTRL12 (0x3B) -#define MT6360_PMU_CHG_HIDDEN_CTRL13 (0x3C) -#define MT6360_PMU_CHG_HIDDEN_CTRL14 (0x3D) -#define MT6360_PMU_CHG_HIDDEN_CTRL15 (0x3E) -#define MT6360_PMU_CHG_HIDDEN_CTRL16 (0x3F) -#define MT6360_PMU_CHG_HIDDEN_CTRL17 (0x40) -#define MT6360_PMU_CHG_HIDDEN_CTRL18 (0x41) -#define MT6360_PMU_CHG_HIDDEN_CTRL19 (0x42) -#define MT6360_PMU_CHG_HIDDEN_CTRL20 (0x43) -#define MT6360_PMU_CHG_HIDDEN_CTRL21 (0x44) -#define MT6360_PMU_CHG_HIDDEN_CTRL22 (0x45) -#define MT6360_PMU_CHG_HIDDEN_CTRL23 (0x46) -#define MT6360_PMU_CHG_HIDDEN_CTRL24 (0x47) -#define MT6360_PMU_CHG_HIDDEN_CTRL25 (0x48) -#define MT6360_PMU_BC12_CTRL (0x49) -#define MT6360_PMU_CHG_STAT (0x4A) -#define MT6360_PMU_RESV1 (0x4B) -#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEH (0x4E) -#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEL (0x4F) -#define MT6360_PMU_TYPEC_OTP_HYST_TH (0x50) -#define MT6360_PMU_TYPEC_OTP_CTRL (0x51) -#define MT6360_PMU_ADC_BAT_DATA_H (0x52) -#define MT6360_PMU_ADC_BAT_DATA_L (0x53) -#define MT6360_PMU_IMID_BACKBST_ON (0x54) -#define MT6360_PMU_IMID_BACKBST_OFF (0x55) -#define MT6360_PMU_ADC_CONFIG (0x56) -#define MT6360_PMU_ADC_EN2 (0x57) -#define MT6360_PMU_ADC_IDLE_T (0x58) -#define MT6360_PMU_ADC_RPT_1 (0x5A) -#define MT6360_PMU_ADC_RPT_2 (0x5B) -#define MT6360_PMU_ADC_RPT_3 (0x5C) -#define MT6360_PMU_ADC_RPT_ORG1 (0x5D) -#define MT6360_PMU_ADC_RPT_ORG2 (0x5E) -#define MT6360_PMU_BAT_OVP_TH_SEL_CODEH (0x5F) -#define MT6360_PMU_BAT_OVP_TH_SEL_CODEL (0x60) -#define MT6360_PMU_CHG_CTRL19 (0x61) -#define MT6360_PMU_VDDASUPPLY (0x62) -#define MT6360_PMU_BC12_MANUAL (0x63) -#define MT6360_PMU_CHGDET_FUNC (0x64) -#define MT6360_PMU_FOD_CTRL (0x65) -#define MT6360_PMU_CHG_CTRL20 (0x66) -#define MT6360_PMU_CHG_HIDDEN_CTRL26 (0x67) -#define MT6360_PMU_CHG_HIDDEN_CTRL27 (0x68) -#define MT6360_PMU_RESV2 (0x69) -#define MT6360_PMU_USBID_CTRL1 (0x6D) -#define MT6360_PMU_USBID_CTRL2 (0x6E) -#define MT6360_PMU_USBID_CTRL3 (0x6F) -#define MT6360_PMU_FLED_CFG (0x70) -#define MT6360_PMU_RESV3 (0x71) -#define MT6360_PMU_FLED1_CTRL (0x72) -#define MT6360_PMU_FLED_STRB_CTRL (0x73) -#define MT6360_PMU_FLED1_STRB_CTRL2 (0x74) -#define MT6360_PMU_FLED1_TOR_CTRL (0x75) -#define MT6360_PMU_FLED2_CTRL (0x76) -#define MT6360_PMU_RESV4 (0x77) -#define MT6360_PMU_FLED2_STRB_CTRL2 (0x78) -#define MT6360_PMU_FLED2_TOR_CTRL (0x79) -#define MT6360_PMU_FLED_VMIDTRK_CTRL1 (0x7A) -#define MT6360_PMU_FLED_VMID_RTM (0x7B) -#define MT6360_PMU_FLED_VMIDTRK_CTRL2 (0x7C) -#define MT6360_PMU_FLED_PWSEL (0x7D) -#define MT6360_PMU_FLED_EN (0x7E) -#define MT6360_PMU_FLED_Hidden1 (0x7F) -#define MT6360_PMU_RGB_EN (0x80) -#define MT6360_PMU_RGB1_ISNK (0x81) -#define MT6360_PMU_RGB2_ISNK (0x82) -#define MT6360_PMU_RGB3_ISNK (0x83) -#define MT6360_PMU_RGB_ML_ISNK (0x84) -#define MT6360_PMU_RGB1_DIM (0x85) -#define MT6360_PMU_RGB2_DIM (0x86) -#define MT6360_PMU_RGB3_DIM (0x87) -#define MT6360_PMU_RESV5 (0x88) -#define MT6360_PMU_RGB12_Freq (0x89) -#define MT6360_PMU_RGB34_Freq (0x8A) -#define MT6360_PMU_RGB1_Tr (0x8B) -#define MT6360_PMU_RGB1_Tf (0x8C) -#define MT6360_PMU_RGB1_TON_TOFF (0x8D) -#define MT6360_PMU_RGB2_Tr (0x8E) -#define MT6360_PMU_RGB2_Tf (0x8F) -#define MT6360_PMU_RGB2_TON_TOFF (0x90) -#define MT6360_PMU_RGB3_Tr (0x91) -#define MT6360_PMU_RGB3_Tf (0x92) -#define MT6360_PMU_RGB3_TON_TOFF (0x93) -#define MT6360_PMU_RGB_Hidden_CTRL1 (0x94) -#define MT6360_PMU_RGB_Hidden_CTRL2 (0x95) -#define MT6360_PMU_RESV6 (0x97) -#define MT6360_PMU_SPARE1 (0x9A) -#define MT6360_PMU_SPARE2 (0xA0) -#define MT6360_PMU_SPARE3 (0xB0) -#define MT6360_PMU_SPARE4 (0xC0) -#define MT6360_PMU_CHG_IRQ1 (0xD0) -#define MT6360_PMU_CHG_IRQ2 (0xD1) -#define MT6360_PMU_CHG_IRQ3 (0xD2) -#define MT6360_PMU_CHG_IRQ4 (0xD3) -#define MT6360_PMU_CHG_IRQ5 (0xD4) -#define MT6360_PMU_CHG_IRQ6 (0xD5) -#define MT6360_PMU_QC_IRQ (0xD6) -#define MT6360_PMU_FOD_IRQ (0xD7) -#define MT6360_PMU_BASE_IRQ (0xD8) -#define MT6360_PMU_FLED_IRQ1 (0xD9) -#define MT6360_PMU_FLED_IRQ2 (0xDA) -#define MT6360_PMU_RGB_IRQ (0xDB) -#define MT6360_PMU_BUCK1_IRQ (0xDC) -#define MT6360_PMU_BUCK2_IRQ (0xDD) -#define MT6360_PMU_LDO_IRQ1 (0xDE) -#define MT6360_PMU_LDO_IRQ2 (0xDF) -#define MT6360_PMU_CHG_STAT1 (0xE0) -#define MT6360_PMU_CHG_STAT2 (0xE1) -#define MT6360_PMU_CHG_STAT3 (0xE2) -#define MT6360_PMU_CHG_STAT4 (0xE3) -#define MT6360_PMU_CHG_STAT5 (0xE4) -#define MT6360_PMU_CHG_STAT6 (0xE5) -#define MT6360_PMU_QC_STAT (0xE6) -#define MT6360_PMU_FOD_STAT (0xE7) -#define MT6360_PMU_BASE_STAT (0xE8) -#define MT6360_PMU_FLED_STAT1 (0xE9) -#define MT6360_PMU_FLED_STAT2 (0xEA) -#define MT6360_PMU_RGB_STAT (0xEB) -#define MT6360_PMU_BUCK1_STAT (0xEC) -#define MT6360_PMU_BUCK2_STAT (0xED) -#define MT6360_PMU_LDO_STAT1 (0xEE) -#define MT6360_PMU_LDO_STAT2 (0xEF) -#define MT6360_PMU_CHG_MASK1 (0xF0) -#define MT6360_PMU_CHG_MASK2 (0xF1) -#define MT6360_PMU_CHG_MASK3 (0xF2) -#define MT6360_PMU_CHG_MASK4 (0xF3) -#define MT6360_PMU_CHG_MASK5 (0xF4) -#define MT6360_PMU_CHG_MASK6 (0xF5) -#define MT6360_PMU_QC_MASK (0xF6) -#define MT6360_PMU_FOD_MASK (0xF7) -#define MT6360_PMU_BASE_MASK (0xF8) -#define MT6360_PMU_FLED_MASK1 (0xF9) -#define MT6360_PMU_FLED_MASK2 (0xFA) -#define MT6360_PMU_FAULTB_MASK (0xFB) -#define MT6360_PMU_BUCK1_MASK (0xFC) -#define MT6360_PMU_BUCK2_MASK (0xFD) -#define MT6360_PMU_LDO_MASK1 (0xFE) -#define MT6360_PMU_LDO_MASK2 (0xFF) -#define MT6360_PMU_MAXREG (MT6360_PMU_LDO_MASK2) +#define MT6360_PMU_DEV_INFO 0x00 +#define MT6360_PMU_CORE_CTRL1 0x01 +#define MT6360_PMU_RST1 0x02 +#define MT6360_PMU_CRCEN 0x03 +#define MT6360_PMU_RST_PAS_CODE1 0x04 +#define MT6360_PMU_RST_PAS_CODE2 0x05 +#define MT6360_PMU_CORE_CTRL2 0x06 +#define MT6360_PMU_TM_PAS_CODE1 0x07 +#define MT6360_PMU_TM_PAS_CODE2 0x08 +#define MT6360_PMU_TM_PAS_CODE3 0x09 +#define MT6360_PMU_TM_PAS_CODE4 0x0A +#define MT6360_PMU_IRQ_IND 0x0B +#define MT6360_PMU_IRQ_MASK 0x0C +#define MT6360_PMU_IRQ_SET 0x0D +#define MT6360_PMU_SHDN_CTRL 0x0E +#define MT6360_PMU_TM_INF 0x0F +#define MT6360_PMU_I2C_CTRL 0x10 +#define MT6360_PMU_CHG_CTRL1 0x11 +#define MT6360_PMU_CHG_CTRL2 0x12 +#define MT6360_PMU_CHG_CTRL3 0x13 +#define MT6360_PMU_CHG_CTRL4 0x14 +#define MT6360_PMU_CHG_CTRL5 0x15 +#define MT6360_PMU_CHG_CTRL6 0x16 +#define MT6360_PMU_CHG_CTRL7 0x17 +#define MT6360_PMU_CHG_CTRL8 0x18 +#define MT6360_PMU_CHG_CTRL9 0x19 +#define MT6360_PMU_CHG_CTRL10 0x1A +#define MT6360_PMU_CHG_CTRL11 0x1B +#define MT6360_PMU_CHG_CTRL12 0x1C +#define MT6360_PMU_CHG_CTRL13 0x1D +#define MT6360_PMU_CHG_CTRL14 0x1E +#define MT6360_PMU_CHG_CTRL15 0x1F +#define MT6360_PMU_CHG_CTRL16 0x20 +#define MT6360_PMU_CHG_AICC_RESULT 0x21 +#define MT6360_PMU_DEVICE_TYPE 0x22 +#define MT6360_PMU_QC_CONTROL1 0x23 +#define MT6360_PMU_QC_CONTROL2 0x24 +#define MT6360_PMU_QC30_CONTROL1 0x25 +#define MT6360_PMU_QC30_CONTROL2 0x26 +#define MT6360_PMU_USB_STATUS1 0x27 +#define MT6360_PMU_QC_STATUS1 0x28 +#define MT6360_PMU_QC_STATUS2 0x29 +#define MT6360_PMU_CHG_PUMP 0x2A +#define MT6360_PMU_CHG_CTRL17 0x2B +#define MT6360_PMU_CHG_CTRL18 0x2C +#define MT6360_PMU_CHRDET_CTRL1 0x2D +#define MT6360_PMU_CHRDET_CTRL2 0x2E +#define MT6360_PMU_DPDN_CTRL 0x2F +#define MT6360_PMU_CHG_HIDDEN_CTRL1 0x30 +#define MT6360_PMU_CHG_HIDDEN_CTRL2 0x31 +#define MT6360_PMU_CHG_HIDDEN_CTRL3 0x32 +#define MT6360_PMU_CHG_HIDDEN_CTRL4 0x33 +#define MT6360_PMU_CHG_HIDDEN_CTRL5 0x34 +#define MT6360_PMU_CHG_HIDDEN_CTRL6 0x35 +#define MT6360_PMU_CHG_HIDDEN_CTRL7 0x36 +#define MT6360_PMU_CHG_HIDDEN_CTRL8 0x37 +#define MT6360_PMU_CHG_HIDDEN_CTRL9 0x38 +#define MT6360_PMU_CHG_HIDDEN_CTRL10 0x39 +#define MT6360_PMU_CHG_HIDDEN_CTRL11 0x3A +#define MT6360_PMU_CHG_HIDDEN_CTRL12 0x3B +#define MT6360_PMU_CHG_HIDDEN_CTRL13 0x3C +#define MT6360_PMU_CHG_HIDDEN_CTRL14 0x3D +#define MT6360_PMU_CHG_HIDDEN_CTRL15 0x3E +#define MT6360_PMU_CHG_HIDDEN_CTRL16 0x3F +#define MT6360_PMU_CHG_HIDDEN_CTRL17 0x40 +#define MT6360_PMU_CHG_HIDDEN_CTRL18 0x41 +#define MT6360_PMU_CHG_HIDDEN_CTRL19 0x42 +#define MT6360_PMU_CHG_HIDDEN_CTRL20 0x43 +#define MT6360_PMU_CHG_HIDDEN_CTRL21 0x44 +#define MT6360_PMU_CHG_HIDDEN_CTRL22 0x45 +#define MT6360_PMU_CHG_HIDDEN_CTRL23 0x46 +#define MT6360_PMU_CHG_HIDDEN_CTRL24 0x47 +#define MT6360_PMU_CHG_HIDDEN_CTRL25 0x48 +#define MT6360_PMU_BC12_CTRL 0x49 +#define MT6360_PMU_CHG_STAT 0x4A +#define MT6360_PMU_RESV1 0x4B +#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEH 0x4E +#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEL 0x4F +#define MT6360_PMU_TYPEC_OTP_HYST_TH 0x50 +#define MT6360_PMU_TYPEC_OTP_CTRL 0x51 +#define MT6360_PMU_ADC_BAT_DATA_H 0x52 +#define MT6360_PMU_ADC_BAT_DATA_L 0x53 +#define MT6360_PMU_IMID_BACKBST_ON 0x54 +#define MT6360_PMU_IMID_BACKBST_OFF 0x55 +#define MT6360_PMU_ADC_CONFIG 0x56 +#define MT6360_PMU_ADC_EN2 0x57 +#define MT6360_PMU_ADC_IDLE_T 0x58 +#define MT6360_PMU_ADC_RPT_1 0x5A +#define MT6360_PMU_ADC_RPT_2 0x5B +#define MT6360_PMU_ADC_RPT_3 0x5C +#define MT6360_PMU_ADC_RPT_ORG1 0x5D +#define MT6360_PMU_ADC_RPT_ORG2 0x5E +#define MT6360_PMU_BAT_OVP_TH_SEL_CODEH 0x5F +#define MT6360_PMU_BAT_OVP_TH_SEL_CODEL 0x60 +#define MT6360_PMU_CHG_CTRL19 0x61 +#define MT6360_PMU_VDDASUPPLY 0x62 +#define MT6360_PMU_BC12_MANUAL 0x63 +#define MT6360_PMU_CHGDET_FUNC 0x64 +#define MT6360_PMU_FOD_CTRL 0x65 +#define MT6360_PMU_CHG_CTRL20 0x66 +#define MT6360_PMU_CHG_HIDDEN_CTRL26 0x67 +#define MT6360_PMU_CHG_HIDDEN_CTRL27 0x68 +#define MT6360_PMU_RESV2 0x69 +#define MT6360_PMU_USBID_CTRL1 0x6D +#define MT6360_PMU_USBID_CTRL2 0x6E +#define MT6360_PMU_USBID_CTRL3 0x6F +#define MT6360_PMU_FLED_CFG 0x70 +#define MT6360_PMU_RESV3 0x71 +#define MT6360_PMU_FLED1_CTRL 0x72 +#define MT6360_PMU_FLED_STRB_CTRL 0x73 +#define MT6360_PMU_FLED1_STRB_CTRL2 0x74 +#define MT6360_PMU_FLED1_TOR_CTRL 0x75 +#define MT6360_PMU_FLED2_CTRL 0x76 +#define MT6360_PMU_RESV4 0x77 +#define MT6360_PMU_FLED2_STRB_CTRL2 0x78 +#define MT6360_PMU_FLED2_TOR_CTRL 0x79 +#define MT6360_PMU_FLED_VMIDTRK_CTRL1 0x7A +#define MT6360_PMU_FLED_VMID_RTM 0x7B +#define MT6360_PMU_FLED_VMIDTRK_CTRL2 0x7C +#define MT6360_PMU_FLED_PWSEL 0x7D +#define MT6360_PMU_FLED_EN 0x7E +#define MT6360_PMU_FLED_Hidden1 0x7F +#define MT6360_PMU_RGB_EN 0x80 +#define MT6360_PMU_RGB1_ISNK 0x81 +#define MT6360_PMU_RGB2_ISNK 0x82 +#define MT6360_PMU_RGB3_ISNK 0x83 +#define MT6360_PMU_RGB_ML_ISNK 0x84 +#define MT6360_PMU_RGB1_DIM 0x85 +#define MT6360_PMU_RGB2_DIM 0x86 +#define MT6360_PMU_RGB3_DIM 0x87 +#define MT6360_PMU_RESV5 0x88 +#define MT6360_PMU_RGB12_Freq 0x89 +#define MT6360_PMU_RGB34_Freq 0x8A +#define MT6360_PMU_RGB1_Tr 0x8B +#define MT6360_PMU_RGB1_Tf 0x8C +#define MT6360_PMU_RGB1_TON_TOFF 0x8D +#define MT6360_PMU_RGB2_Tr 0x8E +#define MT6360_PMU_RGB2_Tf 0x8F +#define MT6360_PMU_RGB2_TON_TOFF 0x90 +#define MT6360_PMU_RGB3_Tr 0x91 +#define MT6360_PMU_RGB3_Tf 0x92 +#define MT6360_PMU_RGB3_TON_TOFF 0x93 +#define MT6360_PMU_RGB_Hidden_CTRL1 0x94 +#define MT6360_PMU_RGB_Hidden_CTRL2 0x95 +#define MT6360_PMU_RESV6 0x97 +#define MT6360_PMU_SPARE1 0x9A +#define MT6360_PMU_SPARE2 0xA0 +#define MT6360_PMU_SPARE3 0xB0 +#define MT6360_PMU_SPARE4 0xC0 +#define MT6360_PMU_CHG_IRQ1 0xD0 +#define MT6360_PMU_CHG_IRQ2 0xD1 +#define MT6360_PMU_CHG_IRQ3 0xD2 +#define MT6360_PMU_CHG_IRQ4 0xD3 +#define MT6360_PMU_CHG_IRQ5 0xD4 +#define MT6360_PMU_CHG_IRQ6 0xD5 +#define MT6360_PMU_QC_IRQ 0xD6 +#define MT6360_PMU_FOD_IRQ 0xD7 +#define MT6360_PMU_BASE_IRQ 0xD8 +#define MT6360_PMU_FLED_IRQ1 0xD9 +#define MT6360_PMU_FLED_IRQ2 0xDA +#define MT6360_PMU_RGB_IRQ 0xDB +#define MT6360_PMU_BUCK1_IRQ 0xDC +#define MT6360_PMU_BUCK2_IRQ 0xDD +#define MT6360_PMU_LDO_IRQ1 0xDE +#define MT6360_PMU_LDO_IRQ2 0xDF +#define MT6360_PMU_CHG_STAT1 0xE0 +#define MT6360_PMU_CHG_STAT2 0xE1 +#define MT6360_PMU_CHG_STAT3 0xE2 +#define MT6360_PMU_CHG_STAT4 0xE3 +#define MT6360_PMU_CHG_STAT5 0xE4 +#define MT6360_PMU_CHG_STAT6 0xE5 +#define MT6360_PMU_QC_STAT 0xE6 +#define MT6360_PMU_FOD_STAT 0xE7 +#define MT6360_PMU_BASE_STAT 0xE8 +#define MT6360_PMU_FLED_STAT1 0xE9 +#define MT6360_PMU_FLED_STAT2 0xEA +#define MT6360_PMU_RGB_STAT 0xEB +#define MT6360_PMU_BUCK1_STAT 0xEC +#define MT6360_PMU_BUCK2_STAT 0xED +#define MT6360_PMU_LDO_STAT1 0xEE +#define MT6360_PMU_LDO_STAT2 0xEF +#define MT6360_PMU_CHG_MASK1 0xF0 +#define MT6360_PMU_CHG_MASK2 0xF1 +#define MT6360_PMU_CHG_MASK3 0xF2 +#define MT6360_PMU_CHG_MASK4 0xF3 +#define MT6360_PMU_CHG_MASK5 0xF4 +#define MT6360_PMU_CHG_MASK6 0xF5 +#define MT6360_PMU_QC_MASK 0xF6 +#define MT6360_PMU_FOD_MASK 0xF7 +#define MT6360_PMU_BASE_MASK 0xF8 +#define MT6360_PMU_FLED_MASK1 0xF9 +#define MT6360_PMU_FLED_MASK2 0xFA +#define MT6360_PMU_FAULTB_MASK 0xFB +#define MT6360_PMU_BUCK1_MASK 0xFC +#define MT6360_PMU_BUCK2_MASK 0xFD +#define MT6360_PMU_LDO_MASK1 0xFE +#define MT6360_PMU_LDO_MASK2 0xFF +#define MT6360_PMU_MAXREG MT6360_PMU_LDO_MASK2 /* MT6360_PMU_IRQ_SET */ #define MT6360_PMU_IRQ_REGNUM (MT6360_PMU_LDO_IRQ2 - MT6360_PMU_CHG_IRQ1 + 1) #define MT6360_IRQ_RETRIG BIT(2) -#define CHIP_VEN_MASK (0xF0) -#define CHIP_VEN_MT6360 (0x50) -#define CHIP_REV_MASK (0x0F) +#define CHIP_VEN_MASK 0xF0 +#define CHIP_VEN_MT6360 0x50 +#define CHIP_REV_MASK 0x0F #endif /* __MT6360_H__ */ From patchwork Mon Aug 17 10:47:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gene Chen X-Patchwork-Id: 11717951 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 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Subject: [PATCH v4 3/9] mfd: mt6360: Indicate sub-dev compatible name by using "-" Date: Mon, 17 Aug 2020 18:47:51 +0800 Message-Id: <1597661277-27862-4-git-send-email-gene.chen.richtek@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> References: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200817_064851_566269_3F2E1A33 X-CRM114-Status: GOOD ( 12.66 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:442 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [gene.chen.richtek[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gene_chen@richtek.com, linux-kernel@vger.kernel.org, cy_huang@richtek.com, benjamin.chao@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, shufan_lee@richtek.com MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: Gene Chen Indicate sub-dev compatible name by using "-". Signed-off-by: Gene Chen Acked-for-MFD-by: Lee Jones --- drivers/mfd/mt6360-core.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c index befee70..692e47b 100644 --- a/drivers/mfd/mt6360-core.c +++ b/drivers/mfd/mt6360-core.c @@ -292,18 +292,18 @@ static const struct resource mt6360_ldo_resources[] = { }; static const struct mfd_cell mt6360_devs[] = { - OF_MFD_CELL("mt6360_adc", mt6360_adc_resources, - NULL, 0, 0, "mediatek,mt6360_adc"), - OF_MFD_CELL("mt6360_chg", mt6360_chg_resources, - NULL, 0, 0, "mediatek,mt6360_chg"), - OF_MFD_CELL("mt6360_led", mt6360_led_resources, - NULL, 0, 0, "mediatek,mt6360_led"), - OF_MFD_CELL("mt6360_pmic", mt6360_pmic_resources, - NULL, 0, 0, "mediatek,mt6360_pmic"), - OF_MFD_CELL("mt6360_ldo", mt6360_ldo_resources, - NULL, 0, 0, "mediatek,mt6360_ldo"), - OF_MFD_CELL("mt6360_tcpc", NULL, - NULL, 0, 0, "mediatek,mt6360_tcpc"), + OF_MFD_CELL("mt6360-adc", mt6360_adc_resources, + NULL, 0, 0, "mediatek,mt6360-adc"), + OF_MFD_CELL("mt6360-chg", mt6360_chg_resources, + NULL, 0, 0, "mediatek,mt6360-chg"), + OF_MFD_CELL("mt6360-led", mt6360_led_resources, + NULL, 0, 0, "mediatek,mt6360-led"), + OF_MFD_CELL("mt6360-pmic", mt6360_pmic_resources, + NULL, 0, 0, "mediatek,mt6360-pmic"), + OF_MFD_CELL("mt6360-ldo", mt6360_ldo_resources, + NULL, 0, 0, "mediatek,mt6360-ldo"), + OF_MFD_CELL("mt6360-tcpc", NULL, + NULL, 0, 0, "mediatek,mt6360-tcpc"), }; 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Mon, 17 Aug 2020 03:48:51 -0700 (PDT) From: Gene Chen To: lee.jones@linaro.org, matthias.bgg@gmail.com Subject: [PATCH v4 4/9] mfd: mt6360: Combine mt6360 pmic/ldo resources into mt6360 regulator resources Date: Mon, 17 Aug 2020 18:47:52 +0800 Message-Id: <1597661277-27862-5-git-send-email-gene.chen.richtek@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> References: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200817_064854_040835_5B3FC784 X-CRM114-Status: GOOD ( 13.55 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:444 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [gene.chen.richtek[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gene_chen@richtek.com, linux-kernel@vger.kernel.org, cy_huang@richtek.com, benjamin.chao@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, shufan_lee@richtek.com MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: Gene Chen Combine mt6360 pmic/ldo resources into mt6360 regulator resources to simplify the similar resources object. Signed-off-by: Gene Chen --- drivers/mfd/mt6360-core.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c index 692e47b..5119e51 100644 --- a/drivers/mfd/mt6360-core.c +++ b/drivers/mfd/mt6360-core.c @@ -265,7 +265,7 @@ static const struct resource mt6360_led_resources[] = { DEFINE_RES_IRQ_NAMED(MT6360_FLED1_STRB_TO_EVT, "fled1_strb_to_evt"), }; -static const struct resource mt6360_pmic_resources[] = { +static const struct resource mt6360_regulator_resources[] = { DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_PGB_EVT, "buck1_pgb_evt"), DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OC_EVT, "buck1_oc_evt"), DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OV_EVT, "buck1_ov_evt"), @@ -278,9 +278,6 @@ static const struct resource mt6360_pmic_resources[] = { DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"), DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"), DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"), -}; - -static const struct resource mt6360_ldo_resources[] = { DEFINE_RES_IRQ_NAMED(MT6360_LDO1_OC_EVT, "ldo1_oc_evt"), DEFINE_RES_IRQ_NAMED(MT6360_LDO2_OC_EVT, "ldo2_oc_evt"), DEFINE_RES_IRQ_NAMED(MT6360_LDO3_OC_EVT, "ldo3_oc_evt"), @@ -298,10 +295,8 @@ static const struct mfd_cell mt6360_devs[] = { NULL, 0, 0, "mediatek,mt6360-chg"), OF_MFD_CELL("mt6360-led", mt6360_led_resources, NULL, 0, 0, "mediatek,mt6360-led"), - OF_MFD_CELL("mt6360-pmic", mt6360_pmic_resources, - NULL, 0, 0, "mediatek,mt6360-pmic"), - OF_MFD_CELL("mt6360-ldo", mt6360_ldo_resources, - NULL, 0, 0, "mediatek,mt6360-ldo"), + OF_MFD_CELL("mt6360-regulator", mt6360_regulator_resources, + NULL, 0, 0, "mediatek,mt6360-regulator"), OF_MFD_CELL("mt6360-tcpc", NULL, NULL, 0, 0, "mediatek,mt6360-tcpc"), }; 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Mon, 17 Aug 2020 03:48:54 -0700 (PDT) From: Gene Chen To: lee.jones@linaro.org, matthias.bgg@gmail.com Subject: [PATCH v4 5/9] mfd: mt6360: Rename mt6360_pmu_data by mt6360_ddata Date: Mon, 17 Aug 2020 18:47:53 +0800 Message-Id: <1597661277-27862-6-git-send-email-gene.chen.richtek@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> References: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200817_064857_526672_AEAB8548 X-CRM114-Status: GOOD ( 17.92 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:644 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [gene.chen.richtek[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gene_chen@richtek.com, linux-kernel@vger.kernel.org, cy_huang@richtek.com, benjamin.chao@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, shufan_lee@richtek.com MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: Gene Chen Rename mt6360_pmu_data by mt6360_ddata because of including not only PMU part, but also entire MT6360 IC. Signed-off-by: Gene Chen Acked-for-MFD-by: Lee Jones --- drivers/mfd/mt6360-core.c | 44 ++++++++++++++++++++++---------------------- include/linux/mfd/mt6360.h | 2 +- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c index 5119e51..332eb5d 100644 --- a/drivers/mfd/mt6360-core.c +++ b/drivers/mfd/mt6360-core.c @@ -210,9 +210,9 @@ static const struct regmap_irq mt6360_pmu_irqs[] = { static int mt6360_pmu_handle_post_irq(void *irq_drv_data) { - struct mt6360_pmu_data *mpd = irq_drv_data; + struct mt6360_ddata *ddata = irq_drv_data; - return regmap_update_bits(mpd->regmap, + return regmap_update_bits(ddata->regmap, MT6360_PMU_IRQ_SET, MT6360_IRQ_RETRIG, MT6360_IRQ_RETRIG); } @@ -310,61 +310,61 @@ static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = { static int mt6360_pmu_probe(struct i2c_client *client) { - struct mt6360_pmu_data *mpd; + struct mt6360_ddata *ddata; unsigned int reg_data; int i, ret; - mpd = devm_kzalloc(&client->dev, sizeof(*mpd), GFP_KERNEL); - if (!mpd) + ddata = devm_kzalloc(&client->dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) return -ENOMEM; - mpd->dev = &client->dev; - i2c_set_clientdata(client, mpd); + ddata->dev = &client->dev; + i2c_set_clientdata(client, ddata); - mpd->regmap = devm_regmap_init_i2c(client, &mt6360_pmu_regmap_config); - if (IS_ERR(mpd->regmap)) { + ddata->regmap = devm_regmap_init_i2c(client, &mt6360_pmu_regmap_config); + if (IS_ERR(ddata->regmap)) { dev_err(&client->dev, "Failed to register regmap\n"); - return PTR_ERR(mpd->regmap); + return PTR_ERR(ddata->regmap); } - ret = regmap_read(mpd->regmap, MT6360_PMU_DEV_INFO, ®_data); + ret = regmap_read(ddata->regmap, MT6360_PMU_DEV_INFO, ®_data); if (ret) { dev_err(&client->dev, "Device not found\n"); return ret; } - mpd->chip_rev = reg_data & CHIP_REV_MASK; - if (mpd->chip_rev != CHIP_VEN_MT6360) { + ddata->chip_rev = reg_data & CHIP_REV_MASK; + if (ddata->chip_rev != CHIP_VEN_MT6360) { dev_err(&client->dev, "Device not supported\n"); return -ENODEV; } - mt6360_pmu_irq_chip.irq_drv_data = mpd; - ret = devm_regmap_add_irq_chip(&client->dev, mpd->regmap, client->irq, + mt6360_pmu_irq_chip.irq_drv_data = ddata; + ret = devm_regmap_add_irq_chip(&client->dev, ddata->regmap, client->irq, IRQF_TRIGGER_FALLING, 0, - &mt6360_pmu_irq_chip, &mpd->irq_data); + &mt6360_pmu_irq_chip, &ddata->irq_data); if (ret) { dev_err(&client->dev, "Failed to add Regmap IRQ Chip\n"); return ret; } - mpd->i2c[0] = client; + ddata->i2c[0] = client; for (i = 1; i < MT6360_SLAVE_MAX; i++) { - mpd->i2c[i] = devm_i2c_new_dummy_device(&client->dev, + ddata->i2c[i] = devm_i2c_new_dummy_device(&client->dev, client->adapter, mt6360_slave_addr[i]); - if (IS_ERR(mpd->i2c[i])) { + if (IS_ERR(ddata->i2c[i])) { dev_err(&client->dev, "Failed to get new dummy I2C device for address 0x%x", mt6360_slave_addr[i]); - return PTR_ERR(mpd->i2c[i]); + return PTR_ERR(ddata->i2c[i]); } - i2c_set_clientdata(mpd->i2c[i], mpd); + i2c_set_clientdata(ddata->i2c[i], ddata); } ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, mt6360_devs, ARRAY_SIZE(mt6360_devs), NULL, - 0, regmap_irq_get_domain(mpd->irq_data)); + 0, regmap_irq_get_domain(ddata->irq_data)); if (ret) { dev_err(&client->dev, "Failed to register subordinate devices\n"); diff --git a/include/linux/mfd/mt6360.h b/include/linux/mfd/mt6360.h index 72edf13..fbe106c 100644 --- a/include/linux/mfd/mt6360.h +++ b/include/linux/mfd/mt6360.h @@ -21,7 +21,7 @@ enum { #define MT6360_LDO_SLAVEID 0x64 #define MT6360_TCPC_SLAVEID 0x4E -struct mt6360_pmu_data { +struct mt6360_data { struct i2c_client *i2c[MT6360_SLAVE_MAX]; struct device *dev; struct regmap *regmap; From patchwork Mon Aug 17 10:47:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gene Chen X-Patchwork-Id: 11717959 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2988C109B for ; Mon, 17 Aug 2020 10:49:47 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 024FA20758 for ; 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Mon, 17 Aug 2020 03:48:57 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:577:c217:67e6:a40c:a3bf:1945]) by smtp.gmail.com with ESMTPSA id k12sm16976528pjp.38.2020.08.17.03.48.55 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Aug 2020 03:48:57 -0700 (PDT) From: Gene Chen To: lee.jones@linaro.org, matthias.bgg@gmail.com Subject: [PATCH v4 6/9] mfd: mt6360: Rename mt6360_pmu by mt6360 Date: Mon, 17 Aug 2020 18:47:54 +0800 Message-Id: <1597661277-27862-7-git-send-email-gene.chen.richtek@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> References: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200817_064900_153287_B530EC49 X-CRM114-Status: GOOD ( 15.62 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1042 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [gene.chen.richtek[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gene_chen@richtek.com, linux-kernel@vger.kernel.org, cy_huang@richtek.com, benjamin.chao@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, shufan_lee@richtek.com MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: Gene Chen Rename mt6360_pmu by mt6360, because of including not only PMU part, but also entire MT6360 IC Signed-off-by: Gene Chen Acked-for-MFD-by: Lee Jones --- drivers/mfd/mt6360-core.c | 41 ++++++++++++++++++++--------------------- 1 file changed, 20 insertions(+), 21 deletions(-) diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c index 332eb5d..f75122b 100644 --- a/drivers/mfd/mt6360-core.c +++ b/drivers/mfd/mt6360-core.c @@ -119,7 +119,7 @@ #define MT6360_LDO6_PGB_EVT 126 #define MT6360_LDO7_PGB_EVT 127 -static const struct regmap_irq mt6360_pmu_irqs[] = { +static const struct regmap_irq mt6360_irqs[] = { REGMAP_IRQ_REG_LINE(MT6360_CHG_TREG_EVT, 8), REGMAP_IRQ_REG_LINE(MT6360_CHG_AICR_EVT, 8), REGMAP_IRQ_REG_LINE(MT6360_CHG_MIVR_EVT, 8), @@ -216,9 +216,9 @@ static int mt6360_pmu_handle_post_irq(void *irq_drv_data) MT6360_PMU_IRQ_SET, MT6360_IRQ_RETRIG, MT6360_IRQ_RETRIG); } -static struct regmap_irq_chip mt6360_pmu_irq_chip = { - .irqs = mt6360_pmu_irqs, - .num_irqs = ARRAY_SIZE(mt6360_pmu_irqs), +static struct regmap_irq_chip mt6360_irq_chip = { + .irqs = mt6360_irqs, + .num_irqs = ARRAY_SIZE(mt6360_irqs), .num_regs = MT6360_PMU_IRQ_REGNUM, .mask_base = MT6360_PMU_CHG_MASK1, .status_base = MT6360_PMU_CHG_IRQ1, @@ -308,7 +308,7 @@ static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = { MT6360_TCPC_SLAVEID, }; -static int mt6360_pmu_probe(struct i2c_client *client) +static int mt6360_probe(struct i2c_client *client) { struct mt6360_ddata *ddata; unsigned int reg_data; @@ -339,10 +339,10 @@ static int mt6360_pmu_probe(struct i2c_client *client) return -ENODEV; } - mt6360_pmu_irq_chip.irq_drv_data = ddata; + mt6360_irq_chip.irq_drv_data = ddata; ret = devm_regmap_add_irq_chip(&client->dev, ddata->regmap, client->irq, IRQF_TRIGGER_FALLING, 0, - &mt6360_pmu_irq_chip, &ddata->irq_data); + &mt6360_irq_chip, &ddata->irq_data); if (ret) { dev_err(&client->dev, "Failed to add Regmap IRQ Chip\n"); return ret; @@ -374,7 +374,7 @@ static int mt6360_pmu_probe(struct i2c_client *client) return 0; } -static int __maybe_unused mt6360_pmu_suspend(struct device *dev) +static int __maybe_unused mt6360_suspend(struct device *dev) { struct i2c_client *i2c = to_i2c_client(dev); @@ -384,7 +384,7 @@ static int __maybe_unused mt6360_pmu_suspend(struct device *dev) return 0; } -static int __maybe_unused mt6360_pmu_resume(struct device *dev) +static int __maybe_unused mt6360_resume(struct device *dev) { struct i2c_client *i2c = to_i2c_client(dev); @@ -395,25 +395,24 @@ static int __maybe_unused mt6360_pmu_resume(struct device *dev) return 0; } -static SIMPLE_DEV_PM_OPS(mt6360_pmu_pm_ops, - mt6360_pmu_suspend, mt6360_pmu_resume); +static SIMPLE_DEV_PM_OPS(mt6360_pm_ops, mt6360_suspend, mt6360_resume); -static const struct of_device_id __maybe_unused mt6360_pmu_of_id[] = { - { .compatible = "mediatek,mt6360_pmu", }, +static const struct of_device_id __maybe_unused mt6360_of_id[] = { + { .compatible = "mediatek,mt6360", }, {}, }; -MODULE_DEVICE_TABLE(of, mt6360_pmu_of_id); +MODULE_DEVICE_TABLE(of, mt6360_of_id); -static struct i2c_driver mt6360_pmu_driver = { +static struct i2c_driver mt6360_driver = { .driver = { - .name = "mt6360_pmu", - .pm = &mt6360_pmu_pm_ops, - .of_match_table = of_match_ptr(mt6360_pmu_of_id), + .name = "mt6360", + .pm = &mt6360_pm_ops, + .of_match_table = of_match_ptr(mt6360_of_id), }, - .probe_new = mt6360_pmu_probe, + .probe_new = mt6360_probe, }; -module_i2c_driver(mt6360_pmu_driver); +module_i2c_driver(mt6360_driver); MODULE_AUTHOR("Gene Chen "); -MODULE_DESCRIPTION("MT6360 PMU I2C Driver"); +MODULE_DESCRIPTION("MT6360 I2C Driver"); MODULE_LICENSE("GPL v2"); From patchwork Mon Aug 17 10:47:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gene Chen X-Patchwork-Id: 11717963 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1670B109B for ; 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Mon, 17 Aug 2020 03:49:00 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:577:c217:67e6:a40c:a3bf:1945]) by smtp.gmail.com with ESMTPSA id k12sm16976528pjp.38.2020.08.17.03.48.57 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Aug 2020 03:49:00 -0700 (PDT) From: Gene Chen To: lee.jones@linaro.org, matthias.bgg@gmail.com Subject: [PATCH v4 7/9] mfd: mt6360: Remove handle_post_irq callback function Date: Mon, 17 Aug 2020 18:47:55 +0800 Message-Id: <1597661277-27862-8-git-send-email-gene.chen.richtek@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> References: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200817_064904_954052_C18B64BF X-CRM114-Status: GOOD ( 17.41 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:642 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [gene.chen.richtek[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gene_chen@richtek.com, linux-kernel@vger.kernel.org, cy_huang@richtek.com, benjamin.chao@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, shufan_lee@richtek.com MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: Gene Chen Remove handle_post_irq which is used to retrigger IRQ. Set IRQ level low trigger in dtsi to keep IRQ always be handled. Signed-off-by: Gene Chen Acked-for-MFD-by: Lee Jones --- drivers/mfd/mt6360-core.c | 17 ++++------------- include/linux/mfd/mt6360.h | 2 +- 2 files changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c index f75122b..2356d99 100644 --- a/drivers/mfd/mt6360-core.c +++ b/drivers/mfd/mt6360-core.c @@ -208,15 +208,8 @@ static const struct regmap_irq mt6360_irqs[] = { REGMAP_IRQ_REG_LINE(MT6360_LDO7_PGB_EVT, 8), }; -static int mt6360_pmu_handle_post_irq(void *irq_drv_data) -{ - struct mt6360_ddata *ddata = irq_drv_data; - - return regmap_update_bits(ddata->regmap, - MT6360_PMU_IRQ_SET, MT6360_IRQ_RETRIG, MT6360_IRQ_RETRIG); -} - -static struct regmap_irq_chip mt6360_irq_chip = { +static const struct regmap_irq_chip mt6360_irq_chip = { + .name = "mt6360_irqs", .irqs = mt6360_irqs, .num_irqs = ARRAY_SIZE(mt6360_irqs), .num_regs = MT6360_PMU_IRQ_REGNUM, @@ -225,7 +218,6 @@ static struct regmap_irq_chip mt6360_irq_chip = { .ack_base = MT6360_PMU_CHG_IRQ1, .init_ack_masked = true, .use_ack = true, - .handle_post_irq = mt6360_pmu_handle_post_irq, }; static const struct regmap_config mt6360_pmu_regmap_config = { @@ -339,10 +331,9 @@ static int mt6360_probe(struct i2c_client *client) return -ENODEV; } - mt6360_irq_chip.irq_drv_data = ddata; ret = devm_regmap_add_irq_chip(&client->dev, ddata->regmap, client->irq, - IRQF_TRIGGER_FALLING, 0, - &mt6360_irq_chip, &ddata->irq_data); + 0, 0, &mt6360_irq_chip, + &ddata->irq_data); if (ret) { dev_err(&client->dev, "Failed to add Regmap IRQ Chip\n"); return ret; diff --git a/include/linux/mfd/mt6360.h b/include/linux/mfd/mt6360.h index fbe106c..da0fb5c 100644 --- a/include/linux/mfd/mt6360.h +++ b/include/linux/mfd/mt6360.h @@ -230,7 +230,7 @@ struct mt6360_data { #define MT6360_PMU_MAXREG MT6360_PMU_LDO_MASK2 /* MT6360_PMU_IRQ_SET */ -#define MT6360_PMU_IRQ_REGNUM (MT6360_PMU_LDO_IRQ2 - MT6360_PMU_CHG_IRQ1 + 1) +#define MT6360_PMU_IRQ_REGNUM 16 #define MT6360_IRQ_RETRIG BIT(2) #define CHIP_VEN_MASK 0xF0 From patchwork Mon Aug 17 10:47:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gene Chen X-Patchwork-Id: 11717965 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 17BDF109B for ; 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Mon, 17 Aug 2020 03:49:03 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:577:c217:67e6:a40c:a3bf:1945]) by smtp.gmail.com with ESMTPSA id k12sm16976528pjp.38.2020.08.17.03.49.01 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Aug 2020 03:49:03 -0700 (PDT) From: Gene Chen To: lee.jones@linaro.org, matthias.bgg@gmail.com Subject: [PATCH v4 8/9] mfd: mt6360: Fix flow which is used to check ic exist Date: Mon, 17 Aug 2020 18:47:56 +0800 Message-Id: <1597661277-27862-9-git-send-email-gene.chen.richtek@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> References: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200817_064905_697299_66B62B90 X-CRM114-Status: GOOD ( 16.13 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:641 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [gene.chen.richtek[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gene_chen@richtek.com, linux-kernel@vger.kernel.org, cy_huang@richtek.com, benjamin.chao@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, shufan_lee@richtek.com MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: Gene Chen Fix flow which is used to check ic exist. Signed-off-by: Gene Chen --- drivers/mfd/mt6360-core.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c index 2356d99..677c974 100644 --- a/drivers/mfd/mt6360-core.c +++ b/drivers/mfd/mt6360-core.c @@ -293,6 +293,25 @@ static const struct mfd_cell mt6360_devs[] = { NULL, 0, 0, "mediatek,mt6360-tcpc"), }; +static int mt6360_check_vendor_info(struct mt6360_ddata *ddata) +{ + u32 info; + int ret; + + ret = regmap_read(ddata->regmap, MT6360_PMU_DEV_INFO, &info); + if (ret < 0) + return ret; + + if ((info & CHIP_VEN_MASK) != CHIP_VEN_MT6360) { + dev_err(&client->dev, "Device not supported\n"); + return -ENODEV; + } + + ddata->chip_rev = info & CHIP_REV_MASK; + + return 0; +} + static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = { MT6360_PMU_SLAVEID, MT6360_PMIC_SLAVEID, @@ -303,7 +322,6 @@ static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = { static int mt6360_probe(struct i2c_client *client) { struct mt6360_ddata *ddata; - unsigned int reg_data; int i, ret; ddata = devm_kzalloc(&client->dev, sizeof(*ddata), GFP_KERNEL); @@ -319,17 +337,9 @@ static int mt6360_probe(struct i2c_client *client) return PTR_ERR(ddata->regmap); } - ret = regmap_read(ddata->regmap, MT6360_PMU_DEV_INFO, ®_data); - if (ret) { - dev_err(&client->dev, "Device not found\n"); + ret = mt6360_check_vendor_info(ddata); + if (ret) return ret; - } - - ddata->chip_rev = reg_data & CHIP_REV_MASK; - if (ddata->chip_rev != CHIP_VEN_MT6360) { - dev_err(&client->dev, "Device not supported\n"); - return -ENODEV; - } ret = devm_regmap_add_irq_chip(&client->dev, ddata->regmap, client->irq, 0, 0, &mt6360_irq_chip, From patchwork Mon Aug 17 10:47:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gene Chen X-Patchwork-Id: 11717969 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3B88E13A4 for ; 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Mon, 17 Aug 2020 03:49:06 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:577:c217:67e6:a40c:a3bf:1945]) by smtp.gmail.com with ESMTPSA id k12sm16976528pjp.38.2020.08.17.03.49.03 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Aug 2020 03:49:06 -0700 (PDT) From: Gene Chen To: lee.jones@linaro.org, matthias.bgg@gmail.com Subject: [PATCH v4 9/9] mfd: mt6360: Merge different sub-devices I2C read/write Date: Mon, 17 Aug 2020 18:47:57 +0800 Message-Id: <1597661277-27862-10-git-send-email-gene.chen.richtek@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> References: <1597661277-27862-1-git-send-email-gene.chen.richtek@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200817_064909_474872_218BDE5D X-CRM114-Status: GOOD ( 25.98 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:642 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [gene.chen.richtek[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gene_chen@richtek.com, linux-kernel@vger.kernel.org, cy_huang@richtek.com, benjamin.chao@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, shufan_lee@richtek.com MIME-Version: 1.0 Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org From: Gene Chen Remove unuse register definition. Merge different sub-devices I2C read/write functions into one Regmap, because PMIC and LDO part need CRC bits for access protection. Signed-off-by: Gene Chen --- drivers/mfd/Kconfig | 1 + drivers/mfd/mt6360-core.c | 260 +++++++++++++++++++++++++++++++++++++++------ include/linux/mfd/mt6360.h | 240 ----------------------------------------- 3 files changed, 226 insertions(+), 275 deletions(-) delete mode 100644 include/linux/mfd/mt6360.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index a37d7d1..0684ddc 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -913,6 +913,7 @@ config MFD_MT6360 select MFD_CORE select REGMAP_I2C select REGMAP_IRQ + select CRC8 depends on I2C help Say Y here to enable MT6360 PMU/PMIC/LDO functional support. diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c index 677c974..e995220 100644 --- a/drivers/mfd/mt6360-core.c +++ b/drivers/mfd/mt6360-core.c @@ -14,7 +14,53 @@ #include #include -#include +enum { + MT6360_SLAVE_TCPC = 0, + MT6360_SLAVE_PMIC, + MT6360_SLAVE_LDO, + MT6360_SLAVE_PMU, + MT6360_SLAVE_MAX, +}; + +struct mt6360_ddata { + struct i2c_client *i2c[MT6360_SLAVE_MAX]; + struct device *dev; + struct regmap *regmap; + struct regmap_irq_chip_data *irq_data; + unsigned int chip_rev; + u8 crc8_tbl[CRC8_TABLE_SIZE]; +}; + +#define MT6360_TCPC_SLAVEID 0x4E +#define MT6360_PMIC_SLAVEID 0x1A +#define MT6360_LDO_SLAVEID 0x64 +#define MT6360_PMU_SLAVEID 0x34 + +#define MT6360_REG_TCPCSTART 0x00 +#define MT6360_REG_TCPCEND 0xFF +#define MT6360_REG_PMICSTART 0x100 +#define MT6360_REG_PMICEND 0x13B +#define MT6360_REG_LDOSTART 0x200 +#define MT6360_REG_LDOEND 0x21C +#define MT6360_REG_PMUSTART 0x300 +#define MT6360_PMU_DEV_INFO 0x300 +#define MT6360_PMU_CHG_IRQ1 0x3D0 +#define MT6360_PMU_CHG_MASK1 0x3F0 +#define MT6360_REG_PMUEND 0x3FF + +#define MT6360_PMU_IRQ_REGNUM 16 + +#define CHIP_VEN_MASK 0xF0 +#define CHIP_VEN_MT6360 0x50 +#define CHIP_REV_MASK 0x0F + +#define MT6360_ADDRESS_MASK 0x3F +#define MT6360_DATA_SIZE_1_BYTE 0x00 +#define MT6360_DATA_SIZE_2_BYTES 0x40 +#define MT6360_DATA_SIZE_3_BYTES 0x80 +#define MT6360_DATA_SIZE_4_BYTES 0xC0 + +#define MT6360_CRC8_POLYNOMIAL 0x7 /* reg 0 -> 0 ~ 7 */ #define MT6360_CHG_TREG_EVT 4 @@ -220,12 +266,6 @@ static const struct regmap_irq_chip mt6360_irq_chip = { .use_ack = true, }; -static const struct regmap_config mt6360_pmu_regmap_config = { - .reg_bits = 8, - .val_bits = 8, - .max_register = MT6360_PMU_MAXREG, -}; - static const struct resource mt6360_adc_resources[] = { DEFINE_RES_IRQ_NAMED(MT6360_ADC_DONEI, "adc_donei"), }; @@ -303,7 +343,7 @@ static int mt6360_check_vendor_info(struct mt6360_ddata *ddata) return ret; if ((info & CHIP_VEN_MASK) != CHIP_VEN_MT6360) { - dev_err(&client->dev, "Device not supported\n"); + dev_err(ddata->dev, "Device not supported\n"); return -ENODEV; } @@ -312,11 +352,163 @@ static int mt6360_check_vendor_info(struct mt6360_ddata *ddata) return 0; } -static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = { - MT6360_PMU_SLAVEID, +static const u16 mt6360_slave_addrs[MT6360_SLAVE_MAX] = { + MT6360_TCPC_SLAVEID, MT6360_PMIC_SLAVEID, MT6360_LDO_SLAVEID, - MT6360_TCPC_SLAVEID, + MT6360_PMU_SLAVEID, +}; + +static int mt6360_xlate_pmicldo_addr(u8 *addr, int rw_size) +{ + /* Address is already in encoded [5:0] */ + *addr &= MT6360_ADDRESS_MASK; + + switch (rw_size) { + case 1: + *addr |= MT6360_DATA_SIZE_1_BYTE; + break; + case 2: + *addr |= MT6360_DATA_SIZE_2_BYTES; + break; + case 3: + *addr |= MT6360_DATA_SIZE_3_BYTES; + break; + case 4: + *addr |= MT6360_DATA_SIZE_4_BYTES; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int mt6360_regmap_read(void *context, const void *reg, size_t reg_size, + void *val, size_t val_size) +{ + struct mt6360_ddata *ddata = context; + u8 bank = *(u8 *)reg, reg_addr = *(u8 *)(reg + 1); + struct i2c_client *i2c = ddata->i2c[bank]; + bool crc_needed = false; + u8 *buf; + /* first two is i2c_addr + reg_addr , last is crc8 */ + int alloc_size = 2 + val_size + 1, read_size = val_size; + u8 crc; + int ret; + + if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) { + crc_needed = true; + ret = mt6360_xlate_pmicldo_addr(®_addr, val_size); + if (ret < 0) + return ret; + read_size += 1; + } + + buf = kzalloc(alloc_size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + /* 7 bit slave addr + read bit */ + buf[0] = ((i2c->addr & 0x7f) << 1) + 1; + buf[1] = reg_addr; + + ret = i2c_smbus_read_i2c_block_data(i2c, reg_addr, read_size, buf + 2); + + if (ret == read_size) { + memcpy(val, buf + 2, val_size); + if (crc_needed) { + crc = crc8(ddata->crc8_tbl, buf, val_size + 2, 0); + if (crc != buf[val_size + 2]) + ret = -EIO; + } + } + + kfree(buf); + + if (ret < 0) + return ret; + else if (ret != read_size) + return -EIO; + + return 0; +} + +static int mt6360_regmap_write(void *context, const void *val, size_t val_size) +{ + struct mt6360_ddata *ddata = context; + u8 bank = *(u8 *)val, reg_addr = *(u8 *)(val + 1); + struct i2c_client *i2c = ddata->i2c[bank]; + bool crc_needed = false; + u8 *buf; + /* first two is i2c_addr + reg_addr , last crc8 + dummy */ + int alloc_size = 2 + val_size + 2, write_size = val_size - 2; + int ret; + + if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) { + crc_needed = true; + ret = mt6360_xlate_pmicldo_addr(®_addr, val_size - 2); + if (ret < 0) + return ret; + } + + buf = kzalloc(alloc_size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + /* 7 bit slave addr + write bit */ + buf[0] = ((i2c->addr & 0x7f) << 1); + buf[1] = reg_addr; + /* val need to minus regaddr 16bit */ + memcpy(buf + 2, val + 2, write_size); + + if (crc_needed) { + buf[val_size] = crc8(ddata->crc8_tbl, buf, val_size, 0); + write_size += 2; + } + + ret = i2c_smbus_write_i2c_block_data(i2c, reg_addr, write_size, buf + 2); + + kfree(buf); + + if (ret < 0) + return ret; + + return 0; +} + +static const struct regmap_bus mt6360_regmap_bus = { + .read = mt6360_regmap_read, + .write = mt6360_regmap_write, + + /* due to pmic and ldo crc access size limit */ + .max_raw_read = 4, + .max_raw_write = 4, +}; + +static bool mt6360_is_readwrite_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MT6360_REG_TCPCSTART ... MT6360_REG_TCPCEND: + fallthrough; + case MT6360_REG_PMICSTART ... MT6360_REG_PMICEND: + fallthrough; + case MT6360_REG_LDOSTART ... MT6360_REG_LDOEND: + fallthrough; + case MT6360_REG_PMUSTART ... MT6360_REG_PMUEND: + return true; + } + + return false; +} + +static const struct regmap_config mt6360_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .max_register = MT6360_REG_PMUEND, + .writeable_reg = mt6360_is_readwrite_reg, + .readable_reg = mt6360_is_readwrite_reg, }; static int mt6360_probe(struct i2c_client *client) @@ -329,9 +521,23 @@ static int mt6360_probe(struct i2c_client *client) return -ENOMEM; ddata->dev = &client->dev; - i2c_set_clientdata(client, ddata); - ddata->regmap = devm_regmap_init_i2c(client, &mt6360_pmu_regmap_config); + for (i = 0; i < MT6360_SLAVE_MAX - 1; i++) { + ddata->i2c[i] = devm_i2c_new_dummy_device(&client->dev, + client->adapter, + mt6360_slave_addrs[i]); + if (IS_ERR(ddata->i2c[i])) { + dev_err(&client->dev, + "Failed to get new dummy I2C device for address 0x%x", + mt6360_slave_addrs[i]); + return PTR_ERR(ddata->i2c[i]); + } + } + ddata->i2c[MT6360_SLAVE_MAX - 1] = client; + + crc8_populate_msb(ddata->crc8_tbl, MT6360_CRC8_POLYNOMIAL); + ddata->regmap = __devm_regmap_init(ddata->dev, &mt6360_regmap_bus, ddata, + &mt6360_regmap_config, NULL, NULL); if (IS_ERR(ddata->regmap)) { dev_err(&client->dev, "Failed to register regmap\n"); return PTR_ERR(ddata->regmap); @@ -341,34 +547,18 @@ static int mt6360_probe(struct i2c_client *client) if (ret) return ret; - ret = devm_regmap_add_irq_chip(&client->dev, ddata->regmap, client->irq, - 0, 0, &mt6360_irq_chip, - &ddata->irq_data); + ret = devm_regmap_add_irq_chip(&client->dev, ddata->regmap, client->irq, 0, 0, + &mt6360_irq_chip, &ddata->irq_data); if (ret) { dev_err(&client->dev, "Failed to add Regmap IRQ Chip\n"); return ret; } - ddata->i2c[0] = client; - for (i = 1; i < MT6360_SLAVE_MAX; i++) { - ddata->i2c[i] = devm_i2c_new_dummy_device(&client->dev, - client->adapter, - mt6360_slave_addr[i]); - if (IS_ERR(ddata->i2c[i])) { - dev_err(&client->dev, - "Failed to get new dummy I2C device for address 0x%x", - mt6360_slave_addr[i]); - return PTR_ERR(ddata->i2c[i]); - } - i2c_set_clientdata(ddata->i2c[i], ddata); - } - - ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, - mt6360_devs, ARRAY_SIZE(mt6360_devs), NULL, - 0, regmap_irq_get_domain(ddata->irq_data)); + ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, mt6360_devs, + ARRAY_SIZE(mt6360_devs), NULL, 0, + regmap_irq_get_domain(ddata->irq_data)); if (ret) { - dev_err(&client->dev, - "Failed to register subordinate devices\n"); + dev_err(&client->dev, "Failed to register subordinate devices\n"); return ret; } diff --git a/include/linux/mfd/mt6360.h b/include/linux/mfd/mt6360.h deleted file mode 100644 index da0fb5c..0000000 --- a/include/linux/mfd/mt6360.h +++ /dev/null @@ -1,240 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 MediaTek Inc. - */ - -#ifndef __MT6360_H__ -#define __MT6360_H__ - -#include - -enum { - MT6360_SLAVE_PMU = 0, - MT6360_SLAVE_PMIC, - MT6360_SLAVE_LDO, - MT6360_SLAVE_TCPC, - MT6360_SLAVE_MAX, -}; - -#define MT6360_PMU_SLAVEID 0x34 -#define MT6360_PMIC_SLAVEID 0x1A -#define MT6360_LDO_SLAVEID 0x64 -#define MT6360_TCPC_SLAVEID 0x4E - -struct mt6360_data { - struct i2c_client *i2c[MT6360_SLAVE_MAX]; - struct device *dev; - struct regmap *regmap; - struct regmap_irq_chip_data *irq_data; - unsigned int chip_rev; -}; - -/* PMU register defininition */ -#define MT6360_PMU_DEV_INFO 0x00 -#define MT6360_PMU_CORE_CTRL1 0x01 -#define MT6360_PMU_RST1 0x02 -#define MT6360_PMU_CRCEN 0x03 -#define MT6360_PMU_RST_PAS_CODE1 0x04 -#define MT6360_PMU_RST_PAS_CODE2 0x05 -#define MT6360_PMU_CORE_CTRL2 0x06 -#define MT6360_PMU_TM_PAS_CODE1 0x07 -#define MT6360_PMU_TM_PAS_CODE2 0x08 -#define MT6360_PMU_TM_PAS_CODE3 0x09 -#define MT6360_PMU_TM_PAS_CODE4 0x0A -#define MT6360_PMU_IRQ_IND 0x0B -#define MT6360_PMU_IRQ_MASK 0x0C -#define MT6360_PMU_IRQ_SET 0x0D -#define MT6360_PMU_SHDN_CTRL 0x0E -#define MT6360_PMU_TM_INF 0x0F -#define MT6360_PMU_I2C_CTRL 0x10 -#define MT6360_PMU_CHG_CTRL1 0x11 -#define MT6360_PMU_CHG_CTRL2 0x12 -#define MT6360_PMU_CHG_CTRL3 0x13 -#define MT6360_PMU_CHG_CTRL4 0x14 -#define MT6360_PMU_CHG_CTRL5 0x15 -#define MT6360_PMU_CHG_CTRL6 0x16 -#define MT6360_PMU_CHG_CTRL7 0x17 -#define MT6360_PMU_CHG_CTRL8 0x18 -#define MT6360_PMU_CHG_CTRL9 0x19 -#define MT6360_PMU_CHG_CTRL10 0x1A -#define MT6360_PMU_CHG_CTRL11 0x1B -#define MT6360_PMU_CHG_CTRL12 0x1C -#define MT6360_PMU_CHG_CTRL13 0x1D -#define MT6360_PMU_CHG_CTRL14 0x1E -#define MT6360_PMU_CHG_CTRL15 0x1F -#define MT6360_PMU_CHG_CTRL16 0x20 -#define MT6360_PMU_CHG_AICC_RESULT 0x21 -#define MT6360_PMU_DEVICE_TYPE 0x22 -#define MT6360_PMU_QC_CONTROL1 0x23 -#define MT6360_PMU_QC_CONTROL2 0x24 -#define MT6360_PMU_QC30_CONTROL1 0x25 -#define MT6360_PMU_QC30_CONTROL2 0x26 -#define MT6360_PMU_USB_STATUS1 0x27 -#define MT6360_PMU_QC_STATUS1 0x28 -#define MT6360_PMU_QC_STATUS2 0x29 -#define MT6360_PMU_CHG_PUMP 0x2A -#define MT6360_PMU_CHG_CTRL17 0x2B -#define MT6360_PMU_CHG_CTRL18 0x2C -#define MT6360_PMU_CHRDET_CTRL1 0x2D -#define MT6360_PMU_CHRDET_CTRL2 0x2E -#define MT6360_PMU_DPDN_CTRL 0x2F -#define MT6360_PMU_CHG_HIDDEN_CTRL1 0x30 -#define MT6360_PMU_CHG_HIDDEN_CTRL2 0x31 -#define MT6360_PMU_CHG_HIDDEN_CTRL3 0x32 -#define MT6360_PMU_CHG_HIDDEN_CTRL4 0x33 -#define MT6360_PMU_CHG_HIDDEN_CTRL5 0x34 -#define MT6360_PMU_CHG_HIDDEN_CTRL6 0x35 -#define MT6360_PMU_CHG_HIDDEN_CTRL7 0x36 -#define MT6360_PMU_CHG_HIDDEN_CTRL8 0x37 -#define MT6360_PMU_CHG_HIDDEN_CTRL9 0x38 -#define MT6360_PMU_CHG_HIDDEN_CTRL10 0x39 -#define MT6360_PMU_CHG_HIDDEN_CTRL11 0x3A -#define MT6360_PMU_CHG_HIDDEN_CTRL12 0x3B -#define MT6360_PMU_CHG_HIDDEN_CTRL13 0x3C -#define MT6360_PMU_CHG_HIDDEN_CTRL14 0x3D -#define MT6360_PMU_CHG_HIDDEN_CTRL15 0x3E -#define MT6360_PMU_CHG_HIDDEN_CTRL16 0x3F -#define MT6360_PMU_CHG_HIDDEN_CTRL17 0x40 -#define MT6360_PMU_CHG_HIDDEN_CTRL18 0x41 -#define MT6360_PMU_CHG_HIDDEN_CTRL19 0x42 -#define MT6360_PMU_CHG_HIDDEN_CTRL20 0x43 -#define MT6360_PMU_CHG_HIDDEN_CTRL21 0x44 -#define MT6360_PMU_CHG_HIDDEN_CTRL22 0x45 -#define MT6360_PMU_CHG_HIDDEN_CTRL23 0x46 -#define MT6360_PMU_CHG_HIDDEN_CTRL24 0x47 -#define MT6360_PMU_CHG_HIDDEN_CTRL25 0x48 -#define MT6360_PMU_BC12_CTRL 0x49 -#define MT6360_PMU_CHG_STAT 0x4A -#define MT6360_PMU_RESV1 0x4B -#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEH 0x4E -#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEL 0x4F -#define MT6360_PMU_TYPEC_OTP_HYST_TH 0x50 -#define MT6360_PMU_TYPEC_OTP_CTRL 0x51 -#define MT6360_PMU_ADC_BAT_DATA_H 0x52 -#define MT6360_PMU_ADC_BAT_DATA_L 0x53 -#define MT6360_PMU_IMID_BACKBST_ON 0x54 -#define MT6360_PMU_IMID_BACKBST_OFF 0x55 -#define MT6360_PMU_ADC_CONFIG 0x56 -#define MT6360_PMU_ADC_EN2 0x57 -#define MT6360_PMU_ADC_IDLE_T 0x58 -#define MT6360_PMU_ADC_RPT_1 0x5A -#define MT6360_PMU_ADC_RPT_2 0x5B -#define MT6360_PMU_ADC_RPT_3 0x5C -#define MT6360_PMU_ADC_RPT_ORG1 0x5D -#define MT6360_PMU_ADC_RPT_ORG2 0x5E -#define MT6360_PMU_BAT_OVP_TH_SEL_CODEH 0x5F -#define MT6360_PMU_BAT_OVP_TH_SEL_CODEL 0x60 -#define MT6360_PMU_CHG_CTRL19 0x61 -#define MT6360_PMU_VDDASUPPLY 0x62 -#define MT6360_PMU_BC12_MANUAL 0x63 -#define MT6360_PMU_CHGDET_FUNC 0x64 -#define MT6360_PMU_FOD_CTRL 0x65 -#define MT6360_PMU_CHG_CTRL20 0x66 -#define MT6360_PMU_CHG_HIDDEN_CTRL26 0x67 -#define MT6360_PMU_CHG_HIDDEN_CTRL27 0x68 -#define MT6360_PMU_RESV2 0x69 -#define MT6360_PMU_USBID_CTRL1 0x6D -#define MT6360_PMU_USBID_CTRL2 0x6E -#define MT6360_PMU_USBID_CTRL3 0x6F -#define MT6360_PMU_FLED_CFG 0x70 -#define MT6360_PMU_RESV3 0x71 -#define MT6360_PMU_FLED1_CTRL 0x72 -#define MT6360_PMU_FLED_STRB_CTRL 0x73 -#define MT6360_PMU_FLED1_STRB_CTRL2 0x74 -#define MT6360_PMU_FLED1_TOR_CTRL 0x75 -#define MT6360_PMU_FLED2_CTRL 0x76 -#define MT6360_PMU_RESV4 0x77 -#define MT6360_PMU_FLED2_STRB_CTRL2 0x78 -#define MT6360_PMU_FLED2_TOR_CTRL 0x79 -#define MT6360_PMU_FLED_VMIDTRK_CTRL1 0x7A -#define MT6360_PMU_FLED_VMID_RTM 0x7B -#define MT6360_PMU_FLED_VMIDTRK_CTRL2 0x7C -#define MT6360_PMU_FLED_PWSEL 0x7D -#define MT6360_PMU_FLED_EN 0x7E -#define MT6360_PMU_FLED_Hidden1 0x7F -#define MT6360_PMU_RGB_EN 0x80 -#define MT6360_PMU_RGB1_ISNK 0x81 -#define MT6360_PMU_RGB2_ISNK 0x82 -#define MT6360_PMU_RGB3_ISNK 0x83 -#define MT6360_PMU_RGB_ML_ISNK 0x84 -#define MT6360_PMU_RGB1_DIM 0x85 -#define MT6360_PMU_RGB2_DIM 0x86 -#define MT6360_PMU_RGB3_DIM 0x87 -#define MT6360_PMU_RESV5 0x88 -#define MT6360_PMU_RGB12_Freq 0x89 -#define MT6360_PMU_RGB34_Freq 0x8A -#define MT6360_PMU_RGB1_Tr 0x8B -#define MT6360_PMU_RGB1_Tf 0x8C -#define MT6360_PMU_RGB1_TON_TOFF 0x8D -#define MT6360_PMU_RGB2_Tr 0x8E -#define MT6360_PMU_RGB2_Tf 0x8F -#define MT6360_PMU_RGB2_TON_TOFF 0x90 -#define MT6360_PMU_RGB3_Tr 0x91 -#define MT6360_PMU_RGB3_Tf 0x92 -#define MT6360_PMU_RGB3_TON_TOFF 0x93 -#define MT6360_PMU_RGB_Hidden_CTRL1 0x94 -#define MT6360_PMU_RGB_Hidden_CTRL2 0x95 -#define MT6360_PMU_RESV6 0x97 -#define MT6360_PMU_SPARE1 0x9A -#define MT6360_PMU_SPARE2 0xA0 -#define MT6360_PMU_SPARE3 0xB0 -#define MT6360_PMU_SPARE4 0xC0 -#define MT6360_PMU_CHG_IRQ1 0xD0 -#define MT6360_PMU_CHG_IRQ2 0xD1 -#define MT6360_PMU_CHG_IRQ3 0xD2 -#define MT6360_PMU_CHG_IRQ4 0xD3 -#define MT6360_PMU_CHG_IRQ5 0xD4 -#define MT6360_PMU_CHG_IRQ6 0xD5 -#define MT6360_PMU_QC_IRQ 0xD6 -#define MT6360_PMU_FOD_IRQ 0xD7 -#define MT6360_PMU_BASE_IRQ 0xD8 -#define MT6360_PMU_FLED_IRQ1 0xD9 -#define MT6360_PMU_FLED_IRQ2 0xDA -#define MT6360_PMU_RGB_IRQ 0xDB -#define MT6360_PMU_BUCK1_IRQ 0xDC -#define MT6360_PMU_BUCK2_IRQ 0xDD -#define MT6360_PMU_LDO_IRQ1 0xDE -#define MT6360_PMU_LDO_IRQ2 0xDF -#define MT6360_PMU_CHG_STAT1 0xE0 -#define MT6360_PMU_CHG_STAT2 0xE1 -#define MT6360_PMU_CHG_STAT3 0xE2 -#define MT6360_PMU_CHG_STAT4 0xE3 -#define MT6360_PMU_CHG_STAT5 0xE4 -#define MT6360_PMU_CHG_STAT6 0xE5 -#define MT6360_PMU_QC_STAT 0xE6 -#define MT6360_PMU_FOD_STAT 0xE7 -#define MT6360_PMU_BASE_STAT 0xE8 -#define MT6360_PMU_FLED_STAT1 0xE9 -#define MT6360_PMU_FLED_STAT2 0xEA -#define MT6360_PMU_RGB_STAT 0xEB -#define MT6360_PMU_BUCK1_STAT 0xEC -#define MT6360_PMU_BUCK2_STAT 0xED -#define MT6360_PMU_LDO_STAT1 0xEE -#define MT6360_PMU_LDO_STAT2 0xEF -#define MT6360_PMU_CHG_MASK1 0xF0 -#define MT6360_PMU_CHG_MASK2 0xF1 -#define MT6360_PMU_CHG_MASK3 0xF2 -#define MT6360_PMU_CHG_MASK4 0xF3 -#define MT6360_PMU_CHG_MASK5 0xF4 -#define MT6360_PMU_CHG_MASK6 0xF5 -#define MT6360_PMU_QC_MASK 0xF6 -#define MT6360_PMU_FOD_MASK 0xF7 -#define MT6360_PMU_BASE_MASK 0xF8 -#define MT6360_PMU_FLED_MASK1 0xF9 -#define MT6360_PMU_FLED_MASK2 0xFA -#define MT6360_PMU_FAULTB_MASK 0xFB -#define MT6360_PMU_BUCK1_MASK 0xFC -#define MT6360_PMU_BUCK2_MASK 0xFD -#define MT6360_PMU_LDO_MASK1 0xFE -#define MT6360_PMU_LDO_MASK2 0xFF -#define MT6360_PMU_MAXREG MT6360_PMU_LDO_MASK2 - -/* MT6360_PMU_IRQ_SET */ -#define MT6360_PMU_IRQ_REGNUM 16 -#define MT6360_IRQ_RETRIG BIT(2) - -#define CHIP_VEN_MASK 0xF0 -#define CHIP_VEN_MT6360 0x50 -#define CHIP_REV_MASK 0x0F - -#endif /* __MT6360_H__ */