From patchwork Mon Aug 17 12:24:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhukeqian X-Patchwork-Id: 11718139 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 24240618 for ; Mon, 17 Aug 2020 12:26:05 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F120B20658 for ; Mon, 17 Aug 2020 12:26:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="aP35p9Cw" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F120B20658 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=VA9KDxJkC1RJY5y/CI/hiZLc9GAq0OsVMIDnTRFQHCU=; b=aP35p9Cwkbef6VT3EnC6BsF9n eh8xwfgbjs+Uy6RYi7fVOsiIY7IaJLM6bgzFNLANN0Ikz00T/2pkjG+n5GROkQQghTNW/gEvOGMtT zC8mdyKRm36y7A0/XCOCBGSEQ6nOOdf1LUjyE6x5KDubQ4ZgUB8Le9Ld8Otc9WnJqfKZDabr030E9 AySc4mYrjd8uYOCg195F5GVILu+/0tU/MnJKeO8HPqPxOtIiF45MSTeoaoN5F2B99Hhj9dLC4Ozyp 7Q26hDq2mT/U2WBMLJ4dRMkaM0SYSXxtBzXugWCblad2oeMQhLC2KK0kq9Ts2EuwhxjBcbHZK5JfN woBtF/BWg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k7eBl-0002uX-AS; Mon, 17 Aug 2020 12:24:33 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k7eBj-0002u4-Gt for linux-arm-kernel@lists.infradead.org; Mon, 17 Aug 2020 12:24:32 +0000 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 6AFAA26378CE36048E93; Mon, 17 Aug 2020 20:24:25 +0800 (CST) Received: from DESKTOP-5IS4806.china.huawei.com (10.174.187.22) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.487.0; Mon, 17 Aug 2020 20:24:19 +0800 From: Keqian Zhu To: , , , Subject: [PATCH 1/2] clocksource: arm_arch_timer: Simplify and fix count reader code logic Date: Mon, 17 Aug 2020 20:24:14 +0800 Message-ID: <20200817122415.6568-2-zhukeqian1@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20200817122415.6568-1-zhukeqian1@huawei.com> References: <20200817122415.6568-1-zhukeqian1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.22] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200817_082431_816534_DD142525 X-CRM114-Status: GOOD ( 14.14 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [45.249.212.35 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [45.249.212.35 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Suzuki K Poulose , Marc Zyngier , Keqian Zhu , Steven Price , James Morse , Catalin Marinas , wanghaibin.wang@huawei.com, Will Deacon Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org In commit 0ea415390cd3 (clocksource/arm_arch_timer: Use arch_timer_read_counter to access stable counters), we separate stable and normal count reader. Actually the stable reader can correctly lead us to normal reader if we has no workaround. Besides, in erratum_set_next_event_tval_generic(), we use normal reader, it is obviously wrong, so just revert this commit to solve this problem by the way. Signed-off-by: Keqian Zhu --- arch/arm/include/asm/arch_timer.h | 14 ++---------- arch/arm64/include/asm/arch_timer.h | 24 ++------------------ drivers/clocksource/arm_arch_timer.c | 43 ++---------------------------------- 3 files changed, 6 insertions(+), 75 deletions(-) diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index 9917581..d022614 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -84,7 +84,7 @@ static inline u32 arch_timer_get_cntfrq(void) return val; } -static inline u64 __arch_counter_get_cntpct(void) +static inline u64 arch_counter_get_cntpct(void) { u64 cval; @@ -93,12 +93,7 @@ static inline u64 __arch_counter_get_cntpct(void) return cval; } -static inline u64 __arch_counter_get_cntpct_stable(void) -{ - return __arch_counter_get_cntpct(); -} - -static inline u64 __arch_counter_get_cntvct(void) +static inline u64 arch_counter_get_cntvct(void) { u64 cval; @@ -107,11 +102,6 @@ static inline u64 __arch_counter_get_cntvct(void) return cval; } -static inline u64 __arch_counter_get_cntvct_stable(void) -{ - return __arch_counter_get_cntvct(); -} - static inline u32 arch_timer_get_cntkctl(void) { u32 cntkctl; diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index 9f0ec21..08f7b0a 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -184,7 +184,7 @@ static inline void arch_timer_set_cntkctl(u32 cntkctl) : "=r" (tmp) : "r" (_val)); \ } while (0) -static __always_inline u64 __arch_counter_get_cntpct_stable(void) +static __always_inline u64 arch_counter_get_cntpct(void) { u64 cnt; @@ -194,17 +194,7 @@ static __always_inline u64 __arch_counter_get_cntpct_stable(void) return cnt; } -static __always_inline u64 __arch_counter_get_cntpct(void) -{ - u64 cnt; - - isb(); - cnt = read_sysreg(cntpct_el0); - arch_counter_enforce_ordering(cnt); - return cnt; -} - -static __always_inline u64 __arch_counter_get_cntvct_stable(void) +static __always_inline u64 arch_counter_get_cntvct(void) { u64 cnt; @@ -214,16 +204,6 @@ static __always_inline u64 __arch_counter_get_cntvct_stable(void) return cnt; } -static __always_inline u64 __arch_counter_get_cntvct(void) -{ - u64 cnt; - - isb(); - cnt = read_sysreg(cntvct_el0); - arch_counter_enforce_ordering(cnt); - return cnt; -} - #undef arch_counter_enforce_ordering static inline int arch_timer_arch_init(void) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 6c3e841..6e11c60 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -150,26 +150,6 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, return val; } -static notrace u64 arch_counter_get_cntpct_stable(void) -{ - return __arch_counter_get_cntpct_stable(); -} - -static notrace u64 arch_counter_get_cntpct(void) -{ - return __arch_counter_get_cntpct(); -} - -static notrace u64 arch_counter_get_cntvct_stable(void) -{ - return __arch_counter_get_cntvct_stable(); -} - -static notrace u64 arch_counter_get_cntvct(void) -{ - return __arch_counter_get_cntvct(); -} - /* * Default to cp15 based access because arm64 uses this function for * sched_clock() before DT is probed and the cp15 method is guaranteed @@ -383,8 +363,6 @@ static u32 notrace sun50i_a64_read_cntv_tval_el0(void) DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround); EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); -static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0); - static void erratum_set_next_event_tval_generic(const int access, unsigned long evt, struct clock_event_device *clk) { @@ -562,9 +540,6 @@ void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa per_cpu(timer_unstable_counter_workaround, i) = wa; } - if (wa->read_cntvct_el0 || wa->read_cntpct_el0) - atomic_set(&timer_unstable_counter_workaround_in_use, 1); - /* * Don't use the vdso fastpath if errata require using the * out-of-line counter accessor. We may change our mind pretty @@ -625,14 +600,9 @@ static bool arch_timer_this_cpu_has_cntvct_wa(void) return has_erratum_handler(read_cntvct_el0); } -static bool arch_timer_counter_has_wa(void) -{ - return atomic_read(&timer_unstable_counter_workaround_in_use); -} #else #define arch_timer_check_ool_workaround(t,a) do { } while(0) #define arch_timer_this_cpu_has_cntvct_wa() ({false;}) -#define arch_timer_counter_has_wa() ({false;}) #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ static __always_inline irqreturn_t timer_handler(const int access, @@ -989,22 +959,13 @@ static void __init arch_counter_register(unsigned type) /* Register the CP15 based counter if we have one */ if (type & ARCH_TIMER_TYPE_CP15) { - u64 (*rd)(void); - if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) || arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) { - if (arch_timer_counter_has_wa()) - rd = arch_counter_get_cntvct_stable; - else - rd = arch_counter_get_cntvct; + arch_timer_read_counter = arch_counter_get_cntvct; } else { - if (arch_timer_counter_has_wa()) - rd = arch_counter_get_cntpct_stable; - else - rd = arch_counter_get_cntpct; + arch_timer_read_counter = arch_counter_get_cntpct; } - arch_timer_read_counter = rd; clocksource_counter.vdso_clock_mode = vdso_default; } else { arch_timer_read_counter = arch_counter_get_cntvct_mem; From patchwork Mon Aug 17 12:24:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhukeqian X-Patchwork-Id: 11718135 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13A55618 for ; Mon, 17 Aug 2020 12:24:50 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DE4F420658 for ; Mon, 17 Aug 2020 12:24:49 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k7eBr-0002wA-Tf; Mon, 17 Aug 2020 12:24:39 +0000 Received: from szxga05-in.huawei.com ([45.249.212.191] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k7eBm-0002uD-3k for linux-arm-kernel@lists.infradead.org; Mon, 17 Aug 2020 12:24:35 +0000 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 832306C4C976C8803297; Mon, 17 Aug 2020 20:24:30 +0800 (CST) Received: from DESKTOP-5IS4806.china.huawei.com (10.174.187.22) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.487.0; Mon, 17 Aug 2020 20:24:20 +0800 From: Keqian Zhu To: , , , Subject: [PATCH 2/2] clocksource: arm_arch_timer: Correct fault programming of CNTKCTL_EL1.EVNTI Date: Mon, 17 Aug 2020 20:24:15 +0800 Message-ID: <20200817122415.6568-3-zhukeqian1@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20200817122415.6568-1-zhukeqian1@huawei.com> References: <20200817122415.6568-1-zhukeqian1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.22] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200817_082434_959442_99447128 X-CRM114-Status: GOOD ( 11.36 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [45.249.212.191 listed in wl.mailspike.net] -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [45.249.212.191 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Suzuki K Poulose , Marc Zyngier , Keqian Zhu , Steven Price , James Morse , Catalin Marinas , wanghaibin.wang@huawei.com, Will Deacon Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org ARM virtual counter supports event stream, it can only trigger an event when the trigger bit (the value of CNTKCTL_EL1.EVNTI) of CNTVCT_EL0 changes, so the actual period of event stream is 2^(cntkctl_evnti + 1). For example, when the trigger bit is 0, then virtual counter trigger an event for every two cycles. Signed-off-by: Marc Zyngier Signed-off-by: Keqian Zhu --- drivers/clocksource/arm_arch_timer.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 6e11c60..4140a37 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -794,10 +794,14 @@ static void arch_timer_configure_evtstream(void) { int evt_stream_div, pos; - /* Find the closest power of two to the divisor */ - evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ; + /* + * Find the closest power of two to the divisor. As the event + * stream can at most be generated at half the frequency of the + * counter, use half the frequency when computing the divider. + */ + evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2; pos = fls(evt_stream_div); - if (pos > 1 && !(evt_stream_div & (1 << (pos - 2)))) + if ((pos == 1) || (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))) pos--; /* enable event stream */ arch_timer_evtstrm_enable(min(pos, 15));