From patchwork Sun Oct 21 20:54:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651609 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF73013A4 for ; Sun, 21 Oct 2018 20:58:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B6EE9287F3 for ; Sun, 21 Oct 2018 20:58:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 923DD287FD; Sun, 21 Oct 2018 20:58:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 11DB7287F3 for ; Sun, 21 Oct 2018 20:58:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728290AbeJVFNp (ORCPT ); Mon, 22 Oct 2018 01:13:45 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:38242 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728191AbeJVFNo (ORCPT ); Mon, 22 Oct 2018 01:13:44 -0400 Received: by mail-lj1-f196.google.com with SMTP id k11-v6so3122699lja.5; Sun, 21 Oct 2018 13:58:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NrTw1iWYFqStGSAXz8HRkl720Yd7i09+fJLQHCGG5JE=; b=Lbx/RwVIciT1o16jxmqr1uTLUGkwmKqFAIDWNvdLOKbgZugbq+gpXv5n+Uv/v9rI/x XU5xl63XlmmakNvs4fEqSqpL4GnuZDVEVUUpnucjHONNaxB3y9IVndMoyA9fyMLWcyYO Onc8L+J+IJsNbhTm/VrvpDmhiwwgsSsqKgW0KUHOnkn9acFiCBWghM4ZPok9TdmwcQ8d Li64Xh6GapR6hENzwyU/1BirRlfteJWrk3WMTDhoRkQunTrI/y3533hy0cYc3jVNW2ei FRhWMUr+a5R2jv1C2EifmPhk1OSH6+uhV4jVbI2OajYWSXLzJs7AvCYgsR7o1/oQ1Cgw s9LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NrTw1iWYFqStGSAXz8HRkl720Yd7i09+fJLQHCGG5JE=; b=HiXvKuezOoGoTPQzJv/kSeyBXNFtUpiZq6jHr26QZXS7U1qUcD5S9mQj0J8zLDoJpV q0PmM4F0Qct1wjjs3Al/wiOpxqE0/hvJ3nMBRJVNlJDDm2HU8iQ9JLCjxiBl/MBQwx86 5m+V7uFO6jkO2D+j3TnBkOwv7TU+WtirpKvxm9PwNIJW7bNUfDNY/kdr/zmSP3XPH0v3 IXD7Ssno4lSjOcWpoIdDZz485WA+eSKYs582cByWP+UTcDpuB/46lNzTWHPQTvyhwRl6 dQ7I/OJDDsWMDwGmyKtfNXEJ4FuY5ngLHOPVy9sN1IIjt6ZBcUHZ5DUR1kWErb7AhJEN +NbQ== X-Gm-Message-State: ABuFfohSj/L0waAw9LTa6CosTt9OyZszXhOHN7pvsJOImoBfvVjMVHja RbOrvTdCdciXxuBjNGOqurs= X-Google-Smtp-Source: AJdET5fepY2Z7Voi2NqHPLZ4IejaaipfS8ryhTu/Z40IQAVm14TzjsgJLRS+excJEacWIOqRYrI9yA== X-Received: by 2002:a2e:7217:: with SMTP id n23-v6mr5582964ljc.71.1540155484934; Sun, 21 Oct 2018 13:58:04 -0700 (PDT) Received: from localhost.localdomain (109-252-91-118.nat.spd-mgts.ru. [109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:04 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 01/17] OPP: Allow to request stub voltage regulators Date: Sun, 21 Oct 2018 23:54:45 +0300 Message-Id: <20181021205501.23943-2-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Voltage regulators may be not available on some variations of HW, allow to request stub voltage regulators by OPP core in a such case to reduce code churning within drivers. Signed-off-by: Dmitry Osipenko --- drivers/cpufreq/cpufreq-dt.c | 2 +- drivers/cpufreq/ti-cpufreq.c | 3 ++- drivers/opp/core.c | 9 +++++++-- include/linux/pm_opp.h | 4 ++-- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c index e58bfcb1169e..6ebca472ec76 100644 --- a/drivers/cpufreq/cpufreq-dt.c +++ b/drivers/cpufreq/cpufreq-dt.c @@ -196,7 +196,7 @@ static int cpufreq_init(struct cpufreq_policy *policy) */ name = find_supply_name(cpu_dev); if (name) { - opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1); + opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1, false); if (IS_ERR(opp_table)) { ret = PTR_ERR(opp_table); dev_err(cpu_dev, "Failed to set regulator for cpu%d: %d\n", diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index 3f0e2a14895a..9099c8cdf447 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -268,7 +268,8 @@ static int ti_cpufreq_probe(struct platform_device *pdev) if (opp_data->soc_data->multi_regulator) { ti_opp_table = dev_pm_opp_set_regulators(opp_data->cpu_dev, reg_names, - ARRAY_SIZE(reg_names)); + ARRAY_SIZE(reg_names), + false); if (IS_ERR(ti_opp_table)) { dev_pm_opp_put_supported_hw(opp_data->opp_table); ret = PTR_ERR(ti_opp_table); diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 2c2df4e4fc14..fba1d7a1eb7c 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -1365,6 +1365,7 @@ static void _free_set_opp_data(struct opp_table *opp_table) * @dev: Device for which regulator name is being set. * @names: Array of pointers to the names of the regulator. * @count: Number of regulators. + * @allow_stub_regulator: Some or all regulators can be missed. * * In order to support OPP switching, OPP layer needs to know the name of the * device's regulators, as the core would be required to switch voltages as @@ -1374,7 +1375,8 @@ static void _free_set_opp_data(struct opp_table *opp_table) */ struct opp_table *dev_pm_opp_set_regulators(struct device *dev, const char * const names[], - unsigned int count) + unsigned int count, + bool allow_stub_regulator) { struct opp_table *opp_table; struct regulator *reg; @@ -1403,7 +1405,10 @@ struct opp_table *dev_pm_opp_set_regulators(struct device *dev, } for (i = 0; i < count; i++) { - reg = regulator_get_optional(dev, names[i]); + if (allow_stub_regulator) + reg = regulator_get(dev, names[i]); + else + reg = regulator_get_optional(dev, names[i]); if (IS_ERR(reg)) { ret = PTR_ERR(reg); if (ret != -EPROBE_DEFER) diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index 5d399eeef172..480666b0a008 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -120,7 +120,7 @@ struct opp_table *dev_pm_opp_set_supported_hw(struct device *dev, const u32 *ver void dev_pm_opp_put_supported_hw(struct opp_table *opp_table); struct opp_table *dev_pm_opp_set_prop_name(struct device *dev, const char *name); void dev_pm_opp_put_prop_name(struct opp_table *opp_table); -struct opp_table *dev_pm_opp_set_regulators(struct device *dev, const char * const names[], unsigned int count); +struct opp_table *dev_pm_opp_set_regulators(struct device *dev, const char * const names[], unsigned int count, bool allow_stub_regulator); void dev_pm_opp_put_regulators(struct opp_table *opp_table); struct opp_table *dev_pm_opp_set_clkname(struct device *dev, const char * name); void dev_pm_opp_put_clkname(struct opp_table *opp_table); @@ -258,7 +258,7 @@ static inline struct opp_table *dev_pm_opp_set_prop_name(struct device *dev, con static inline void dev_pm_opp_put_prop_name(struct opp_table *opp_table) {} -static inline struct opp_table *dev_pm_opp_set_regulators(struct device *dev, const char * const names[], unsigned int count) +static inline struct opp_table *dev_pm_opp_set_regulators(struct device *dev, const char * const names[], unsigned int count, bool allow_stub_regulator) { return ERR_PTR(-ENOTSUPP); } From patchwork Sun Oct 21 20:54:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651641 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8055C14E2 for ; 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[109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:05 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 02/17] soc/tegra: fuse: Export tegra_get_chip_id() Date: Sun, 21 Oct 2018 23:54:46 +0300 Message-Id: <20181021205501.23943-3-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This function is used by tegra20-cpufreq driver which can be built as a kernel module. Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/fuse/tegra-apbmisc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index e5a4d8f98b10..c94dccf3eb30 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -51,6 +51,7 @@ u8 tegra_get_chip_id(void) { return (tegra_read_chipid() >> 8) & 0xff; } +EXPORT_SYMBOL_GPL(tegra_get_chip_id); u32 tegra_read_straps(void) { From patchwork Sun Oct 21 20:54:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651639 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B75A414E2 for ; Sun, 21 Oct 2018 20:59:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A73E8287FD for ; Sun, 21 Oct 2018 20:59:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9BC4928800; Sun, 21 Oct 2018 20:59:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3577C287FD for ; Sun, 21 Oct 2018 20:59:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728309AbeJVFNq (ORCPT ); Mon, 22 Oct 2018 01:13:46 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:33239 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727256AbeJVFNq (ORCPT ); Mon, 22 Oct 2018 01:13:46 -0400 Received: by mail-lj1-f193.google.com with SMTP id z21-v6so35130781ljz.0; Sun, 21 Oct 2018 13:58:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5nLsZqyhHcgyJIEH7t62KCL1JMNL5JZ/y2YC9VXvUuI=; b=T1lFZOh4TRVdynOXKoQSbHTUJTynY7zpKMOfqYxUSi5xWo9+iiY4YarpVntsbwLl/e 1bY19g+PDW94/S/3F5j1MOWafG00EGQ2FI0HpEcm0nzVqDJc36vrDOj3ljwCXlyFuuta 3fcOjfC4upmbSd5Z3JwLZQq8Aj9l5Vgsi9bgnno/bxpqKht9T+/Dj8EerJNiRLuqUE3t fH99LCNKPIEozCg2xeAE4zZcsyb6VO/WyIilU3lGhyh+LDsL/RQBH/pxUDPWW44rLxFq wYHberQiRG2abpdedOTX3xW0RIFaqQJUNvcS7iyFuj5BvGPqoVi3UbjFNpbEMGDGI4f1 erCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5nLsZqyhHcgyJIEH7t62KCL1JMNL5JZ/y2YC9VXvUuI=; b=FscftJR9SH7vw7BzsFA/43+t/zGaOThXfF1U3Ia3T6eZNVrI4Yf4lE66KRXRikLb+q Fmmwf/QLx5gjbKRCDrBSgB9I1RFhmpTBZkugSjoCQfRF6v5GJci2Ixt+ZvmpZ207Asys uuL/VtLtOV9WYNrfjlYHupZWHEBrS2sk+RuybpKu2zAzGa9W+69GpUQ9orK1+Ge08rQK td3bwPMgBzoW4XZtaiGR7exv3VQ+0IEqnMZSSZNmgp53lZl0QsqMSeM5yewkYp9WQlaf vO/aSK0kRIUf8aueBOwOdcpCeJND1ELIVgOzPAZOG4UdPcyyNR3p40VqenPr5PIIfby0 oMLg== X-Gm-Message-State: ABuFfohigP+mlWgUfLe2WWCWFjefOekinkX7f55bHfnxs+ikWPExYxP/ gDqfNMQXJ8GYvSOXVCAhxt0= X-Google-Smtp-Source: ACcGV60EYidnyzxsqvbhYK59uRgBQPBE+HwsMNENgcxFaJM7iDWFerBF3A7oPFTOUArhppSwq9YEDQ== X-Received: by 2002:a2e:2205:: with SMTP id i5-v6mr24166652lji.15.1540155487006; Sun, 21 Oct 2018 13:58:07 -0700 (PDT) Received: from localhost.localdomain (109-252-91-118.nat.spd-mgts.ru. [109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:06 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 03/17] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Date: Sun, 21 Oct 2018 23:54:47 +0300 Message-Id: <20181021205501.23943-4-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoC's. Signed-off-by: Dmitry Osipenko --- .../cpufreq/nvidia,tegra20-cpufreq.txt | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file mode 100644 index 000000000000..a8023ea7a99f --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt @@ -0,0 +1,96 @@ +Binding for NVIDIA Tegra20 CPUFreq +================================== + +Required properties: +- clocks: Must contain an entry for each entry in clock-names. + See ../clocks/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - pll_x: main-parent for CPU clock, must be the first entry + - intermediate: intermediate-parent for CPU clock + - cclk: the CPU clock +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: Two bitfields indicating: + On Tegra20: + 1. CPU process ID mask + 2. SoC speedo ID mask + + On Tegra30: + 1. CPU process ID mask + 2. CPU speedo ID mask + + A bitwise AND is performed against these values and if any bit + matches, the OPP gets enabled. + +- opp-microvolt: CPU voltage triplet. + +Optional properties: +- cpu-supply: Phandle to the CPU power supply. +- core-supply: Phandle to the CORE power supply. +- rtc-supply: Phandle to the RTC power supply, required only for Tegra20. + +Voltage supply requirements: +- Tegra20: + CORE and RTC regulators must be coupled using the regulator-coupled-with + property and regulator-coupled-max-spread property must be set to no + more than 170mV. + + See ../regulator/regulator.txt for more detail about the properties. + +- Tegra30: + CORE and CPU regulators must be coupled using the regulator-coupled-with + property and regulator-coupled-max-spread property must be set to no + more than 300mV. Each of CORE and CPU regulators must set + regulator-max-step-microvolt property to no more than 100mV. + + See ../regulator/regulator.txt for more detail about the properties. + + +Example: + regulators { + cpu_reg: regulator0 { + regulator-name = "vdd_cpu"; + }; + + core_reg: regulator1 { + regulator-name = "vdd_core"; + regulator-coupled-with = <&rtc_reg>; + regulator-coupled-max-spread = <170000>; + }; + + rtc_reg: regulator2 { + regulator-name = "vdd_rtc"; + regulator-coupled-with = <&core_reg>; + regulator-coupled-max-spread = <170000>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@456000000 { + clock-latency-ns = <125000>; + opp-microvolt = <825000 825000 1125000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <456000000>; + }; + + ... + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + clocks = <&tegra_car TEGRA20_CLK_PLL_X>, + <&tegra_car TEGRA20_CLK_PLL_P>, + <&tegra_car TEGRA20_CLK_CCLK>; + clock-names = "pll_x", "intermediate", "cclk"; + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&cpu_reg>; + core-supply = <&core_reg>; + rtc-supply = <&rtc_reg>; + #cooling-cells = <2>; + }; + }; From patchwork Sun Oct 21 20:54:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651635 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4487E14E2 for ; Sun, 21 Oct 2018 20:59:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3198A287FD for ; Sun, 21 Oct 2018 20:59:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 25A3D28800; Sun, 21 Oct 2018 20:59:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7E5A7287FD for ; Sun, 21 Oct 2018 20:59:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728374AbeJVFNv (ORCPT ); Mon, 22 Oct 2018 01:13:51 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:38243 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728191AbeJVFNv (ORCPT ); Mon, 22 Oct 2018 01:13:51 -0400 Received: by mail-lj1-f194.google.com with SMTP id k11-v6so3122751lja.5; Sun, 21 Oct 2018 13:58:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8/fgFmXtBak1Bd1yGq4kzY0apIYIQmbImrdzBLqCEb0=; b=drGtZ/LK7XNX3S4gel0xUBHqBAjDpTMvwLPMHQqVCs0doxfSQR2NUKpNphDHaBKmhl XXmM0nLykT7/452k5pYh3OIvL3SA4CQS2uZAbeTwfO6PQbk+K/mkzghDnMgx1Ed2oLXI z53hq7HHe7xmVy+eH9YSDPmyZXEk/j4zOwNfJ0UvPiADUI4fFnkVUvrkh78Xr6wLWpS+ xLW0iDzuNmAvHXZR4Xzw4vwXnhloXMgZuilq88llzWmQD8jJM0IPpj/p5UUbmTUXruhQ u5aLj4tQzC1MvSnd2uVI3VfsJ1bEnxzCM6ZhrtWE1c6U6musSXlgT5uC97O9aPQ1LPoo 7f0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8/fgFmXtBak1Bd1yGq4kzY0apIYIQmbImrdzBLqCEb0=; b=jWYpiwAfF7rAM023P25BbaYJY6ttBSVsObrP7NBF6LWP3zBf6gCxmjdgvwujnnRkFi SWJ3aYDQ5TUQzb9LuOtk1v1xQNGseaT5JjcXpN2nYvlcCKvSTLR/ICOARpJ0DXXfNPvK pW8qxoP32Ak2shJH0T61TvyzKWvtaCcAwm2m77sCq8fiF/A1J5omWYIaq2KRrGGvGFhH 4JrWleDYuYKCXvVOR2Kq9DP5wi1WrQjVqAlr1SLpaZ1G2EorwsDw6Twq8Y/ejlY1Gr8Z dP0v8Ks61Lk/aRs4uIz60gvDju6k4HYy/TVZmWIZVZ5dRKQwmb9FV4JtgzOwDHrZ26EO OVAA== X-Gm-Message-State: ABuFfogc0k7ZaxaHpykZn1fbbEEWF0lcrowfvk5d+JKeybKpDcfRgXxe Ftfl5TQju8oo6U+gbiucCB2PbrtD X-Google-Smtp-Source: ACcGV61cQL3QIW5dYxsewRDfHnU+WHe3fanBKBNbuYgKxaYcCCSl4whuzXobW0sO0UUoTEeHSZmBRA== X-Received: by 2002:a2e:6d0a:: with SMTP id i10-v6mr30206347ljc.14.1540155488279; Sun, 21 Oct 2018 13:58:08 -0700 (PDT) Received: from localhost.localdomain (109-252-91-118.nat.spd-mgts.ru. [109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:07 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 04/17] cpufreq: tegra20: Support OPP, thermal cooling, DVFS and Tegra30 Date: Sun, 21 Oct 2018 23:54:48 +0300 Message-Id: <20181021205501.23943-5-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for thermal throttling, Operating Performance Points and DVFS. Driver now relies on OPP's supplied via device tree and therefore will work only on devices that use the updated device tree. The generalization of the driver allows to transparently support Tegra30. Signed-off-by: Dmitry Osipenko --- drivers/cpufreq/Kconfig.arm | 2 + drivers/cpufreq/cpufreq-dt-platdev.c | 2 + drivers/cpufreq/tegra20-cpufreq.c | 832 +++++++++++++++++++++++---- 3 files changed, 734 insertions(+), 102 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 0cd8eb76ad59..78795d108f5e 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -262,7 +262,9 @@ config ARM_TANGO_CPUFREQ config ARM_TEGRA20_CPUFREQ tristate "Tegra20 CPUFreq support" + depends on !CPU_THERMAL || THERMAL depends on ARCH_TEGRA + select PM_OPP default y help This adds the CPUFreq driver support for Tegra20 SOCs. diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index b1c5468dca16..ecc4d3d14850 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -118,6 +118,8 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "mediatek,mt8173", }, { .compatible = "mediatek,mt8176", }, + { .compatible = "nvidia,tegra20", }, + { .compatible = "nvidia,tegra30", }, { .compatible = "nvidia,tegra124", }, { .compatible = "qcom,apq8096", }, diff --git a/drivers/cpufreq/tegra20-cpufreq.c b/drivers/cpufreq/tegra20-cpufreq.c index 05f57dcd5215..a7d1c2899e3c 100644 --- a/drivers/cpufreq/tegra20-cpufreq.c +++ b/drivers/cpufreq/tegra20-cpufreq.c @@ -17,220 +17,848 @@ */ #include +#include +#include #include #include #include #include +#include #include +#include +#include #include +#include -static struct cpufreq_frequency_table freq_table[] = { - { .frequency = 216000 }, - { .frequency = 312000 }, - { .frequency = 456000 }, - { .frequency = 608000 }, - { .frequency = 760000 }, - { .frequency = 816000 }, - { .frequency = 912000 }, - { .frequency = 1000000 }, - { .frequency = CPUFREQ_TABLE_END }, -}; +#include + +#define PLLX_PREPARE BIT(0) +#define PLLX_PREPARED BIT(1) -struct tegra20_cpufreq { +struct tegra_cpufreq { struct device *dev; + struct device *cpu_dev; + struct regulator *reg_cpu; + struct regulator *reg_core; + struct regulator *reg_rtc; + struct opp_table *opp_table; struct cpufreq_driver driver; + struct thermal_cooling_device *cdev; + struct cpufreq_frequency_table *freq_table; struct clk *cpu_clk; struct clk *pll_x_clk; - struct clk *pll_p_clk; - bool pll_x_prepared; + struct clk *intermediate_clk; + unsigned long intermediate_rate; + unsigned int state; + unsigned int chip; + int cpu_speedo_id; + + /* deferred voltage change */ + struct delayed_work work; + struct dev_pm_opp_supply supply_cpu; + unsigned long actual_cpu_uV; }; +static unsigned int voltage_drop_interval_ms = 500; + static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy, unsigned int index) { - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; + struct tegra_cpufreq *cpufreq = cpufreq_get_driver_data(); + struct clk *cpu_parent = clk_get_parent(cpufreq->cpu_clk); + unsigned long new_rate = cpufreq->freq_table[index].frequency * 1000; + int err; /* - * Don't switch to intermediate freq if: - * - we are already at it, i.e. policy->cur == ifreq - * - index corresponds to ifreq + * Make sure that intermediate clock rate stays consistent during + * transition by entering into critical section of the intermediate + * clock. */ - if (freq_table[index].frequency == ifreq || policy->cur == ifreq) + err = clk_rate_exclusive_get(cpufreq->intermediate_clk); + /* this shouldn't fail */ + WARN_ON_ONCE(err); + + /* + * When target rate is equal to intermediate rate, we don't need to + * switch to intermediate clock and so the intermediate routine isn't + * called. Also, we wouldn't be using PLLX anymore and must not + * take extra reference to it, as it can be disabled to save some + * power. + */ + cpufreq->intermediate_rate = clk_get_rate(cpufreq->intermediate_clk); + + if (new_rate == cpufreq->intermediate_rate) + cpufreq->state &= ~PLLX_PREPARE; + else + cpufreq->state |= PLLX_PREPARE; + + /* don't switch to intermediate freq if we are already at it */ + if (clk_is_match(cpu_parent, cpufreq->intermediate_clk)) return 0; - return ifreq; + return cpufreq->intermediate_rate / 1000; } static int tegra_target_intermediate(struct cpufreq_policy *policy, unsigned int index) { - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - int ret; + struct tegra_cpufreq *cpufreq = cpufreq_get_driver_data(); + unsigned int state = cpufreq->state; + int err; /* - * Take an extra reference to the main pll so it doesn't turn - * off when we move the cpu off of it as enabling it again while we - * switch to it from tegra_target() would take additional time. - * - * When target-freq is equal to intermediate freq we don't need to - * switch to an intermediate freq and so this routine isn't called. - * Also, we wouldn't be using pll_x anymore and must not take extra - * reference to it, as it can be disabled now to save some power. + * Take an extra reference to the main PLLX so it doesn't turn off + * when we move the CPU clock to intermediate clock as enabling it + * again while we switch to it from tegra_target() would take + * additional time. */ - clk_prepare_enable(cpufreq->pll_x_clk); + if ((state & (PLLX_PREPARED | PLLX_PREPARE)) == PLLX_PREPARE) { + err = clk_prepare_enable(cpufreq->pll_x_clk); + if (WARN_ON_ONCE(err)) + goto err_exclusive_put; - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); - if (ret) + cpufreq->state |= PLLX_PREPARED; + } + + err = clk_set_parent(cpufreq->cpu_clk, cpufreq->intermediate_clk); + if (WARN_ON_ONCE(err)) + goto err_exclusive_put; + + return 0; + +err_exclusive_put: + clk_rate_exclusive_put(cpufreq->intermediate_clk); + + if (cpufreq->state & PLLX_PREPARED) { clk_disable_unprepare(cpufreq->pll_x_clk); - else - cpufreq->pll_x_prepared = true; + cpufreq->state &= ~PLLX_PREPARED; + } - return ret; + return err; } static int tegra_target(struct cpufreq_policy *policy, unsigned int index) { - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); - unsigned long rate = freq_table[index].frequency; - unsigned int ifreq = clk_get_rate(cpufreq->pll_p_clk) / 1000; + struct tegra_cpufreq *cpufreq = cpufreq_get_driver_data(); + unsigned long new_rate = cpufreq->freq_table[index].frequency * 1000; + unsigned int state = cpufreq->state; int ret; /* - * target freq == pll_p, don't need to take extra reference to pll_x_clk - * as it isn't used anymore. + * Drop refcount to PLLX only if we switched to intermediate clock + * earlier during transitioning to a target frequency and we are going + * to stay with the intermediate clock. */ - if (rate == ifreq) - return clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_p_clk); + if ((state & (PLLX_PREPARED | PLLX_PREPARE)) == PLLX_PREPARED) { + clk_disable_unprepare(cpufreq->pll_x_clk); + state &= ~PLLX_PREPARED; + } - ret = clk_set_rate(cpufreq->pll_x_clk, rate * 1000); - /* Restore to earlier frequency on error, i.e. pll_x */ + /* + * Switch to new OPP, note that this will change PLLX rate and + * not the CCLK. + */ + ret = dev_pm_opp_set_rate(cpufreq->cpu_dev, new_rate); if (ret) - dev_err(cpufreq->dev, "Failed to change pll_x to %lu\n", rate); + goto exclusive_put; - ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_x_clk); - /* This shouldn't fail while changing or restoring */ - WARN_ON(ret); + /* + * Target rate == intermediate rate leaves PLLX turned off, CPU is + * kept running off the intermediate clock. This should save us some + * power by keeping one more PLL disabled because the intermediate + * clock assumed to be always-on. In this case PLLX_PREPARE flag will + * be omitted. + */ + if (state & PLLX_PREPARE) { + /* + * CCF doesn't return error if clock-enabling fails on + * re-parent, hence enable it now. + */ + ret = clk_prepare_enable(cpufreq->pll_x_clk); + if (WARN_ON_ONCE(ret)) + goto exclusive_put; + + ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->pll_x_clk); + + clk_disable_unprepare(cpufreq->pll_x_clk); + } /* - * Drop count to pll_x clock only if we switched to intermediate freq - * earlier while transitioning to a target frequency. + * Drop refcount to PLLX only if we switched to intermediate clock + * earlier during transitioning to a target frequency. */ - if (cpufreq->pll_x_prepared) { + if (state & PLLX_PREPARED) { clk_disable_unprepare(cpufreq->pll_x_clk); - cpufreq->pll_x_prepared = false; + state &= ~PLLX_PREPARED; } +exclusive_put: + clk_rate_exclusive_put(cpufreq->intermediate_clk); + + cpufreq->state = state; + return ret; } -static int tegra_cpu_init(struct cpufreq_policy *policy) +static int tegra_cpu_opp_set_core_voltage(struct tegra_cpufreq *cpufreq, + struct dev_pm_opp_supply *cpu_supply) +{ + int min_core_uV = INT_MAX, max_core_uV = INT_MIN; + int min_rtc_uV = INT_MAX, max_rtc_uV = INT_MIN; + int err; + + if (cpufreq->chip == TEGRA20) { + /* only Tegra20 require to adjust RTC domain voltage */ + min_core_uV = cpu_supply->u_volt_min + 125000; + max_core_uV = 1300000; + min_rtc_uV = cpu_supply->u_volt_min + 125000; + max_rtc_uV = 1300000; + } else { + /* + * On Tegra30 min CORE voltage vary depending on the CPU + * voltage and grade of HW. Note that we assume here that + * the default (validated) CPU voltages are being used. + */ + switch (cpu_supply->u_volt_min) { + case 0 ... 799999: + min_core_uV = 950000; + break; + + case 800000 ... 899999: + min_core_uV = 1000000; + break; + + case 900000 ... 999999: + min_core_uV = 1100000; + break; + + case 1000000 ... 1099999: + min_core_uV = 1200000; + break; + + case 1100000 ... 1250000: + switch (cpufreq->cpu_speedo_id) { + case 0 ... 1: + case 4: + case 7: + case 8: + min_core_uV = 1200000; + break; + + default: + min_core_uV = 1300000; + break; + } + break; + + default: + return -EINVAL; + } + + max_core_uV = 1350000; + } + + /* + * TODO: CORE and RTC voltages also depend on the status of + * different peripherals in the system. Currently DVFS is + * implemented only for CPU in the kernel, hence limit CORE + * and RTC voltages to the max for now and remove the + * limitations once system-wide DVFS will become available. + */ + min_core_uV = max_core_uV; + min_rtc_uV = max_rtc_uV; + + err = regulator_set_voltage(cpufreq->reg_core, + min_core_uV, max_core_uV); + if (err) { + dev_err(cpufreq->dev, + "Failed to set CORE voltage (%d %d): %d\n", + min_core_uV, max_core_uV, err); + return err; + } + + if (cpufreq->chip == TEGRA20) { + err = regulator_set_voltage(cpufreq->reg_rtc, + min_rtc_uV, max_rtc_uV); + if (err) { + dev_err(cpufreq->dev, + "Failed to set RTC voltage (%d %d): %d\n", + min_rtc_uV, max_rtc_uV, err); + return err; + } + } + + return 0; +} + +static int tegra_cpu_opp_set_cpu_voltage(struct tegra_cpufreq *cpufreq, + struct dev_pm_opp_supply *supply) { - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); int ret; - clk_prepare_enable(cpufreq->cpu_clk); + ret = regulator_set_voltage_triplet(cpufreq->reg_cpu, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + if (ret) + dev_err(cpufreq->dev, + "Failed to set CPU voltage (%lu %lu %lu mV): %d\n", + supply->u_volt_min, supply->u_volt, + supply->u_volt_max, ret); - /* FIXME: what's the actual transition time? */ - ret = cpufreq_generic_init(policy, freq_table, 300 * 1000); - if (ret) { - clk_disable_unprepare(cpufreq->cpu_clk); - return ret; + return ret; +} + +static void tegra_cpu_deferred_voltage_drop(struct work_struct *work) +{ + struct tegra_cpufreq *cpufreq = container_of(work, struct tegra_cpufreq, + work.work); + int err; + + err = tegra_cpu_opp_set_cpu_voltage(cpufreq, &cpufreq->supply_cpu); + if (err) + return; + + err = tegra_cpu_opp_set_core_voltage(cpufreq, &cpufreq->supply_cpu); + if (err) + return; + + cpufreq->actual_cpu_uV = cpufreq->supply_cpu.u_volt; +} + +static int tegra_cpu_opp_raise_voltage(struct tegra_cpufreq *cpufreq, + struct dev_pm_opp_supply *supply_cpu) +{ + int err; + + err = tegra_cpu_opp_set_core_voltage(cpufreq, supply_cpu); + if (err) + return err; + + err = tegra_cpu_opp_set_cpu_voltage(cpufreq, supply_cpu); + if (err) + return err; + + cpufreq->actual_cpu_uV = supply_cpu->u_volt; + + return 0; +} + +static void tegra_cpu_opp_schedule_voltage_drop( + struct tegra_cpufreq *cpufreq, + struct dev_pm_opp_supply *supply_cpu) +{ + cpufreq->supply_cpu = *supply_cpu; + + schedule_delayed_work(&cpufreq->work, + msecs_to_jiffies(voltage_drop_interval_ms)); +} + +static int tegra_cpu_set_opp(struct dev_pm_set_opp_data *data) +{ + struct tegra_cpufreq *cpufreq = cpufreq_get_driver_data(); + struct dev_pm_opp_supply *supply_cpu; + int err; + + cancel_delayed_work_sync(&cpufreq->work); + + supply_cpu = &data->new_opp.supplies[0]; + + /* Scaling up? Scale voltage before frequency */ + if (data->old_opp.rate < data->new_opp.rate) { + if (cpufreq->actual_cpu_uV < supply_cpu->u_volt) { + err = tegra_cpu_opp_raise_voltage(cpufreq, supply_cpu); + if (err) + return err; + } else { + tegra_cpu_opp_schedule_voltage_drop(cpufreq, + supply_cpu); + } } - policy->clk = cpufreq->cpu_clk; - policy->suspend_freq = freq_table[0].frequency; + err = clk_set_rate(data->clk, data->new_opp.rate); + if (err) { + dev_err(cpufreq->dev, "Failed to change PLLX clock rate: %d\n", + err); + return err; + } + + if (data->old_opp.rate > data->new_opp.rate) + tegra_cpu_opp_schedule_voltage_drop(cpufreq, supply_cpu); + return 0; } -static int tegra_cpu_exit(struct cpufreq_policy *policy) +static int tegra_cpu_setup_opp(struct tegra_cpufreq *cpufreq) { - struct tegra20_cpufreq *cpufreq = cpufreq_get_driver_data(); + const char * const regulators[] = { "cpu" }; + struct device *dev = cpufreq->cpu_dev; + struct opp_table *opp_table; + u32 versions[2]; + int err; + + if (cpufreq->chip == TEGRA20) { + versions[0] = BIT(tegra_sku_info.cpu_process_id); + versions[1] = BIT(tegra_sku_info.soc_speedo_id); + } else { + versions[0] = BIT(tegra_sku_info.cpu_process_id); + versions[1] = BIT(tegra_sku_info.cpu_speedo_id); + } + + cpufreq->opp_table = dev_pm_opp_set_supported_hw(dev, versions, 2); + if (IS_ERR(cpufreq->opp_table)) { + err = PTR_ERR(cpufreq->opp_table); + dev_err(cpufreq->dev, + "Failed to setup OPP supported HW: %d\n", err); + return err; + } + + opp_table = dev_pm_opp_set_regulators(dev, regulators, 1, true); + if (IS_ERR(opp_table)) { + err = PTR_ERR(opp_table); + dev_err(dev, + "Failed to setup OPP regulators: %d\n", err); + goto err_put_supported_hw; + } + + opp_table = dev_pm_opp_register_set_opp_helper(dev, tegra_cpu_set_opp); + if (IS_ERR(opp_table)) { + err = PTR_ERR(opp_table); + dev_err(cpufreq->dev, + "Failed to set OPP helper: %d\n", err); + goto err_put_regulators; + } + + err = dev_pm_opp_of_cpumask_add_table(cpu_possible_mask); + if (err) { + dev_err(cpufreq->dev, "Failed to add OPP table: %d\n", err); + goto err_unregister_opp_helper; + } + + err = dev_pm_opp_init_cpufreq_table(dev, &cpufreq->freq_table); + if (err) { + dev_err(cpufreq->dev, + "Failed to initialize OPP table: %d\n", err); + goto err_remove_table; + } - clk_disable_unprepare(cpufreq->cpu_clk); return 0; + +err_remove_table: + dev_pm_opp_of_cpumask_remove_table(cpu_possible_mask); + +err_unregister_opp_helper: + dev_pm_opp_unregister_set_opp_helper(cpufreq->opp_table); + +err_put_regulators: + dev_pm_opp_put_regulators(cpufreq->opp_table); + +err_put_supported_hw: + dev_pm_opp_put_supported_hw(cpufreq->opp_table); + + return err; } -static int tegra20_cpufreq_probe(struct platform_device *pdev) +static void tegra_cpu_release_opp(struct tegra_cpufreq *cpufreq) +{ + dev_pm_opp_free_cpufreq_table(cpufreq->cpu_dev, &cpufreq->freq_table); + dev_pm_opp_of_cpumask_remove_table(cpu_possible_mask); + dev_pm_opp_unregister_set_opp_helper(cpufreq->opp_table); + dev_pm_opp_put_regulators(cpufreq->opp_table); + dev_pm_opp_put_supported_hw(cpufreq->opp_table); +} + +static int tegra_cpu_init_clocks(struct tegra_cpufreq *cpufreq) +{ + unsigned long intermediate_rate; + int ret; + + ret = clk_rate_exclusive_get(cpufreq->intermediate_clk); + if (ret) { + dev_err(cpufreq->dev, + "Failed to make intermediate clock exclusive: %d\n", + ret); + goto err_exclusive_put_intermediate; + } + + ret = clk_set_parent(cpufreq->cpu_clk, cpufreq->intermediate_clk); + if (ret) { + dev_err(cpufreq->dev, + "Failed to switch CPU to intermediate clock: %d\n", + ret); + goto err_exclusive_put_intermediate; + } + + intermediate_rate = clk_get_rate(cpufreq->intermediate_clk); + + /* + * The CCLK has its own clock divider, that divider isn't getting + * disabled on clock reparent. Hence set CCLK parent to intermediate + * clock in order to disable the divider if it happens to be enabled, + * otherwise clk_set_rate() has no effect. + */ + ret = clk_set_rate(cpufreq->cpu_clk, intermediate_rate); + if (ret) { + dev_err(cpufreq->dev, + "Failed to change CPU clock rate: %d\n", ret); + goto err_exclusive_put_intermediate; + } + +err_exclusive_put_intermediate: + clk_rate_exclusive_put(cpufreq->intermediate_clk); + + return ret; +} + +static int tegra_cpu_get_regulators(struct tegra_cpufreq *cpufreq) { - struct tegra20_cpufreq *cpufreq; int err; - cpufreq = devm_kzalloc(&pdev->dev, sizeof(*cpufreq), GFP_KERNEL); - if (!cpufreq) - return -ENOMEM; + cpufreq->reg_cpu = regulator_get(cpufreq->cpu_dev, "cpu"); + if (IS_ERR(cpufreq->reg_cpu)) { + err = PTR_ERR(cpufreq->reg_cpu); + dev_err(cpufreq->dev, + "Failed to get CPU regulator: %d\n", err); + return err; + } + + cpufreq->reg_core = regulator_get(cpufreq->cpu_dev, "core"); + if (IS_ERR(cpufreq->reg_core)) { + err = PTR_ERR(cpufreq->reg_core); + dev_err(cpufreq->dev, + "Failed to get CORE regulator: %d\n", err); + goto err_reg_cpu_put; + } + + if (cpufreq->chip == TEGRA20) { + cpufreq->reg_rtc = regulator_get(cpufreq->cpu_dev, "rtc"); + if (IS_ERR(cpufreq->reg_rtc)) { + err = PTR_ERR(cpufreq->reg_rtc); + dev_err(cpufreq->dev, + "Failed to get RTC regulator: %d\n", err); + goto err_reg_core_put; + } + } + + return 0; + +err_reg_core_put: + regulator_put(cpufreq->reg_core); + +err_reg_cpu_put: + regulator_put(cpufreq->reg_cpu); - cpufreq->cpu_clk = clk_get_sys(NULL, "cclk"); - if (IS_ERR(cpufreq->cpu_clk)) - return PTR_ERR(cpufreq->cpu_clk); + return err; +} + +static void tegra_cpu_put_regulators(struct tegra_cpufreq *cpufreq) +{ + if (cpufreq->chip == TEGRA20) + regulator_put(cpufreq->reg_rtc); + + regulator_put(cpufreq->reg_core); + regulator_put(cpufreq->reg_cpu); +} + +static int tegra_cpu_enable_regulators(struct tegra_cpufreq *cpufreq) +{ + int err; + + if (cpufreq->chip == TEGRA20) { + err = regulator_enable(cpufreq->reg_rtc); + if (err) { + dev_err(cpufreq->dev, + "Failed to enable RTC regulator: %d\n", err); + return err; + } + } + + err = regulator_enable(cpufreq->reg_core); + if (err) { + dev_err(cpufreq->dev, + "Failed to enable CORE regulator: %d\n", err); + goto err_reg_rtc_disable; + } + + err = regulator_enable(cpufreq->reg_cpu); + if (err) { + dev_err(cpufreq->dev, + "Failed to enable CPU regulator: %d\n", err); + goto err_reg_core_disable; + } + + return 0; + +err_reg_rtc_disable: + if (cpufreq->chip == TEGRA20) + regulator_put(cpufreq->reg_rtc); - cpufreq->pll_x_clk = clk_get_sys(NULL, "pll_x"); +err_reg_core_disable: + regulator_put(cpufreq->reg_core); + + return err; +} + +static void tegra_cpu_disable_regulators(struct tegra_cpufreq *cpufreq) +{ + regulator_disable(cpufreq->reg_cpu); + regulator_disable(cpufreq->reg_core); + + if (cpufreq->chip == TEGRA20) + regulator_disable(cpufreq->reg_rtc); +} + +static int tegra_cpu_get_clocks(struct tegra_cpufreq *cpufreq) +{ + int err; + + cpufreq->cpu_clk = clk_get(cpufreq->cpu_dev, "cclk"); + if (IS_ERR(cpufreq->cpu_clk)) { + err = PTR_ERR(cpufreq->cpu_clk); + dev_err(cpufreq->dev, "Failed to get CPU clock: %d\n", err); + dev_err(cpufreq->dev, "Please update your device tree\n"); + return err; + } + + cpufreq->pll_x_clk = clk_get(cpufreq->cpu_dev, "pll_x"); if (IS_ERR(cpufreq->pll_x_clk)) { err = PTR_ERR(cpufreq->pll_x_clk); - goto put_cpu; + dev_err(cpufreq->dev, "Failed to get PLLX clock: %d\n", err); + goto err_clk_cpu_put; + } + + cpufreq->intermediate_clk = clk_get(cpufreq->cpu_dev, "intermediate"); + if (IS_ERR(cpufreq->intermediate_clk)) { + err = PTR_ERR(cpufreq->intermediate_clk); + dev_err(cpufreq->dev, "Failed to get intermediate clock: %d\n", + err); + goto err_clk_pll_x_put; + } + + return 0; + +err_clk_pll_x_put: + clk_put(cpufreq->pll_x_clk); + +err_clk_cpu_put: + clk_put(cpufreq->cpu_clk); + + return err; +} + +static void tegra_cpu_put_clocks(struct tegra_cpufreq *cpufreq) +{ + clk_put(cpufreq->intermediate_clk); + clk_put(cpufreq->pll_x_clk); + clk_put(cpufreq->cpu_clk); +} + +static int tegra_cpu_enable_clocks(struct tegra_cpufreq *cpufreq) +{ + int err; + + err = clk_prepare_enable(cpufreq->cpu_clk); + if (err) { + dev_err(cpufreq->dev, + "Failed to enable CPU clock: %d\n", err); + return err; } - cpufreq->pll_p_clk = clk_get_sys(NULL, "pll_p"); - if (IS_ERR(cpufreq->pll_p_clk)) { - err = PTR_ERR(cpufreq->pll_p_clk); - goto put_pll_x; + err = clk_prepare_enable(cpufreq->intermediate_clk); + if (err) { + dev_err(cpufreq->dev, + "Failed to enable intermediate clock: %d\n", err); + goto err_clk_cpu_disable; } + return 0; + +err_clk_cpu_disable: + clk_disable_unprepare(cpufreq->cpu_clk); + + return err; +} + +static void tegra_cpu_disable_clocks(struct tegra_cpufreq *cpufreq) +{ + clk_disable_unprepare(cpufreq->intermediate_clk); + clk_disable_unprepare(cpufreq->cpu_clk); +} + +static int tegra_cpu_get_resources(struct tegra_cpufreq *cpufreq) +{ + int err; + + err = tegra_cpu_get_clocks(cpufreq); + if (err) + return err; + + err = tegra_cpu_enable_clocks(cpufreq); + if (err) + goto err_put_clocks; + + err = tegra_cpu_get_regulators(cpufreq); + if (err) + goto err_disable_clocks; + + err = tegra_cpu_enable_regulators(cpufreq); + if (err) + goto err_put_regulators; + + err = tegra_cpu_init_clocks(cpufreq); + if (err) + goto err_disable_regulators; + + return 0; + +err_disable_regulators: + tegra_cpu_disable_regulators(cpufreq); + +err_put_regulators: + tegra_cpu_put_regulators(cpufreq); + +err_disable_clocks: + tegra_cpu_disable_clocks(cpufreq); + +err_put_clocks: + tegra_cpu_put_clocks(cpufreq); + + return err; +} + +static void tegra_cpu_release_resources(struct tegra_cpufreq *cpufreq) +{ + tegra_cpu_disable_regulators(cpufreq); + tegra_cpu_put_regulators(cpufreq); + tegra_cpu_disable_clocks(cpufreq); + tegra_cpu_put_clocks(cpufreq); +} + +static int tegra_cpu_init(struct cpufreq_policy *policy) +{ + struct tegra_cpufreq *cpufreq = cpufreq_get_driver_data(); + struct device *cpu = cpufreq->cpu_dev; + int err; + + err = tegra_cpu_get_resources(cpufreq); + if (err) + return err; + + err = tegra_cpu_setup_opp(cpufreq); + if (err) + goto err_release_resources; + + err = cpufreq_generic_init(policy, cpufreq->freq_table, + dev_pm_opp_get_max_clock_latency(cpu)); + if (err) + goto err_release_opp; + + policy->clk = cpufreq->cpu_clk; + policy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu) / 1000; + + return 0; + +err_release_opp: + tegra_cpu_release_opp(cpufreq); + +err_release_resources: + tegra_cpu_release_resources(cpufreq); + + return err; +} + +static int tegra_cpu_exit(struct cpufreq_policy *policy) +{ + struct tegra_cpufreq *cpufreq = cpufreq_get_driver_data(); + + flush_delayed_work(&cpufreq->work); + cpufreq_cooling_unregister(cpufreq->cdev); + tegra_cpu_release_opp(cpufreq); + tegra_cpu_release_resources(cpufreq); + + return 0; +} + +static void tegra_cpu_ready(struct cpufreq_policy *policy) +{ + struct tegra_cpufreq *cpufreq = cpufreq_get_driver_data(); + + cpufreq->cdev = of_cpufreq_cooling_register(policy); +} + +static int tegra_cpu_suspend(struct cpufreq_policy *policy) +{ + struct tegra_cpufreq *cpufreq = cpufreq_get_driver_data(); + int err; + + err = cpufreq_generic_suspend(policy); + if (err) + return err; + + flush_delayed_work(&cpufreq->work); + + return 0; +} + +static int tegra_cpufreq_probe(struct platform_device *pdev) +{ + struct tegra_cpufreq *cpufreq; + int err; + + cpufreq = devm_kzalloc(&pdev->dev, sizeof(*cpufreq), GFP_KERNEL); + if (!cpufreq) + return -ENOMEM; + cpufreq->dev = &pdev->dev; + cpufreq->cpu_dev = get_cpu_device(0); + cpufreq->cpu_speedo_id = tegra_sku_info.cpu_speedo_id; + cpufreq->chip = tegra_get_chip_id(); cpufreq->driver.get = cpufreq_generic_get; cpufreq->driver.attr = cpufreq_generic_attr; cpufreq->driver.init = tegra_cpu_init; cpufreq->driver.exit = tegra_cpu_exit; + cpufreq->driver.ready = tegra_cpu_ready; cpufreq->driver.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK; cpufreq->driver.verify = cpufreq_generic_frequency_table_verify; - cpufreq->driver.suspend = cpufreq_generic_suspend; + cpufreq->driver.suspend = tegra_cpu_suspend; cpufreq->driver.driver_data = cpufreq; cpufreq->driver.target_index = tegra_target; cpufreq->driver.get_intermediate = tegra_get_intermediate; cpufreq->driver.target_intermediate = tegra_target_intermediate; snprintf(cpufreq->driver.name, CPUFREQ_NAME_LEN, "tegra"); + INIT_DELAYED_WORK(&cpufreq->work, tegra_cpu_deferred_voltage_drop); err = cpufreq_register_driver(&cpufreq->driver); if (err) - goto put_pll_p; + return err; platform_set_drvdata(pdev, cpufreq); return 0; - -put_pll_p: - clk_put(cpufreq->pll_p_clk); -put_pll_x: - clk_put(cpufreq->pll_x_clk); -put_cpu: - clk_put(cpufreq->cpu_clk); - - return err; } -static int tegra20_cpufreq_remove(struct platform_device *pdev) +static int tegra_cpufreq_remove(struct platform_device *pdev) { - struct tegra20_cpufreq *cpufreq = platform_get_drvdata(pdev); + struct tegra_cpufreq *cpufreq = platform_get_drvdata(pdev); cpufreq_unregister_driver(&cpufreq->driver); - clk_put(cpufreq->pll_p_clk); - clk_put(cpufreq->pll_x_clk); - clk_put(cpufreq->cpu_clk); - return 0; } -static struct platform_driver tegra20_cpufreq_driver = { - .probe = tegra20_cpufreq_probe, - .remove = tegra20_cpufreq_remove, +static struct platform_driver tegra_cpufreq_driver = { + .probe = tegra_cpufreq_probe, + .remove = tegra_cpufreq_remove, .driver = { .name = "tegra20-cpufreq", }, }; -module_platform_driver(tegra20_cpufreq_driver); +module_platform_driver(tegra_cpufreq_driver); + +module_param(voltage_drop_interval_ms, uint, 0644); MODULE_ALIAS("platform:tegra20-cpufreq"); MODULE_AUTHOR("Colin Cross "); +MODULE_AUTHOR("Dmitry Osipenko "); MODULE_DESCRIPTION("NVIDIA Tegra20 cpufreq driver"); MODULE_LICENSE("GPL"); From patchwork Sun Oct 21 20:54:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651637 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7263D13A4 for ; Sun, 21 Oct 2018 20:59:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 61ABD287FF for ; Sun, 21 Oct 2018 20:59:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 56530287FD; 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[109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:08 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 05/17] ARM: tegra: Create tegra20-cpufreq device on Tegra30 Date: Sun, 21 Oct 2018 23:54:49 +0300 Message-Id: <20181021205501.23943-6-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra20-cpufreq driver require a platform device in order to be loaded, instantiate a simple platform device for the driver during of the machines late initialization. Driver now supports Tegra30 SoC's, hence create the device on Tegra30 machines. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 67d8ae60ac67..b559e22eab76 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -111,6 +111,10 @@ static void __init tegra_dt_init_late(void) if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("nvidia,tegra20")) platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); + + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && + of_machine_is_compatible("nvidia,tegra30")) + platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); } static const char * const tegra_dt_board_compat[] = { From patchwork Sun Oct 21 20:54:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651631 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2A33313A4 for ; Sun, 21 Oct 2018 20:59:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1AD9B287FD for ; Sun, 21 Oct 2018 20:59:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0F1CF28800; Sun, 21 Oct 2018 20:59:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 561EE287FD for ; Sun, 21 Oct 2018 20:59:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728420AbeJVFNw (ORCPT ); Mon, 22 Oct 2018 01:13:52 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:41536 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728337AbeJVFNv (ORCPT ); Mon, 22 Oct 2018 01:13:51 -0400 Received: by mail-lj1-f196.google.com with SMTP id u21-v6so35084164lja.8; Sun, 21 Oct 2018 13:58:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zvXilCKoG7Om0U54BXuHpSWpsgo6GxzP/ylvX2mhmdo=; b=Yr0LVjLQISIRtWyrIZMlk0S+pteqPJKNyNmXQaZnCZtPPBPSAGkIFSZODTMQ3yIPG3 v76ioNFDxLOHB5d/5i8VacG6UvbhoqpWGSUrqV6kxCA/w0wX2mHg54cdKHT22KlP27cg ScOAqcnzg0YhLVTtlxqbhZslwQ7j9NB1c0ADCg89ytpb2xjoTptHgcaAC5Hc3lhw+Eve Ljip9RIszy8vSPwMTpUkfN0YY7jEfVHzY+X92nJXwLCzK6Ra1Mp8wssoJT+fNAhgBkUJ CHLdO2StVqKpsxIPQsMkpnr8u/qQFtwCfyRBO3YWR4C5M6NMFQq+iZbC3hCvUirvHfWO dPKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zvXilCKoG7Om0U54BXuHpSWpsgo6GxzP/ylvX2mhmdo=; b=ENKn8oBWQVbv2xgmg06P5w3Iu2zZBg3q8rksu6VSOSTq4KZ+YcZJmDKIO4iPtJvlpf 5lUlruu86R6PDxdWuj2DDCUo6EuBmCy1jKrq6XJLrIgB7DRBq6AWB3PnU7ju8WMKYmDi MMScU1fnkAuwwmSYeX4KSbQkPIWiX7Ubq1XMeRfsSo0/n55doeHjaxKwitDeKAlvovEx Iy1seK4GmoOIkFFBVGfhW1KddoEiSXyOWEiBAVsAHSBHE7RqIWMQEqdsQ/yAlS9YbnIV jWNrfxV0RM9iM+rsf/ttNMNGPa1WMoC9VU+DDnSX/1gGz40Iwln0+xI63umQHXegJOEn PlUQ== X-Gm-Message-State: AGRZ1gJYNHHNSHXdTUTQ8D1pwuQ2qDCT8p+KZGjux8Jm6cF64ayLIH9p HjLvvO9ad2KJGdTodVzt1nM= X-Google-Smtp-Source: AJdET5esKiGu8kBPREV6pfoUjej/APKwYyQM0eZVtLN9MJtzFEgSkmpdA9tsvphUESMEIWG8Dk54cA== X-Received: by 2002:a2e:908b:: with SMTP id l11-v6mr9303228ljg.25.1540155490399; Sun, 21 Oct 2018 13:58:10 -0700 (PDT) Received: from localhost.localdomain (109-252-91-118.nat.spd-mgts.ru. [109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:09 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 06/17] ARM: dts: tegra20: Add CPU Operating Performance Points Date: Sun, 21 Oct 2018 23:54:50 +0300 Message-Id: <20181021205501.23943-7-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add CPU's Operating Performance Points to the device tree, they are used by the CPUFreq driver and allow to setup thermal throttling for the boards by linking the cooling device (CPU) with thermal sensors via thermal-zones description. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 277 +++++++++++++++++++++++++++++++++ 1 file changed, 277 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 185cd074eeff..51ffb5d2b974 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -859,6 +859,271 @@ status = "disabled"; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@216000000_750 { + clock-latency-ns = <2000>; + opp-microvolt = <750000 750000 1125000>; + opp-supported-hw = <0xFF 0xFFFF>; + opp-hz = /bits/ 64 <216000000>; + opp-suspend; + }; + + opp@314000000_750 { + clock-latency-ns = <125000>; + opp-microvolt = <750000 750000 1125000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <314000000>; + }; + + opp@380000000_750 { + clock-latency-ns = <125000>; + opp-microvolt = <750000 750000 1125000>; + opp-supported-hw = <0x01 0x0002>; + opp-hz = /bits/ 64 <380000000>; + }; + + opp@389000000_750 { + clock-latency-ns = <125000>; + opp-microvolt = <750000 750000 1125000>; + opp-supported-hw = <0x02 0x0002>; + opp-hz = /bits/ 64 <389000000>; + }; + + opp@456000000_825 { + clock-latency-ns = <125000>; + opp-microvolt = <825000 825000 1125000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp@494000000_750 { + clock-latency-ns = <125000>; + opp-microvolt = <750000 750000 1125000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <494000000>; + }; + + opp@503000000_800 { + clock-latency-ns = <125000>; + opp-microvolt = <800000 800000 1125000>; + opp-supported-hw = <0x03 0x0002>; + opp-hz = /bits/ 64 <503000000>; + }; + + opp@598000000_750 { + clock-latency-ns = <125000>; + opp-microvolt = <750000 750000 1125000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <598000000>; + }; + + opp@608000000_900 { + clock-latency-ns = <125000>; + opp-microvolt = <900000 900000 1125000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp@618000000_900 { + clock-latency-ns = <125000>; + opp-microvolt = <900000 900000 1125000>; + opp-supported-hw = <0x02 0x0001>; + opp-hz = /bits/ 64 <618000000>; + }; + + opp@655000000_850 { + clock-latency-ns = <125000>; + opp-microvolt = <850000 850000 1125000>; + opp-supported-hw = <0x03 0x0002>; + opp-hz = /bits/ 64 <655000000>; + }; + + opp@675000000_825 { + clock-latency-ns = <125000>; + opp-microvolt = <825000 825000 1125000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <675000000>; + }; + + opp@730000000_750 { + clock-latency-ns = <125000>; + opp-microvolt = <750000 750000 1125000>; + opp-supported-hw = <0x08 0x0003>; + opp-hz = /bits/ 64 <730000000>; + }; + + opp@750000000_800 { + clock-latency-ns = <125000>; + opp-microvolt = <800000 800000 1125000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <750000000>; + }; + + opp@760000000_775 { + clock-latency-ns = <125000>; + opp-microvolt = <775000 775000 1125000>; + opp-supported-hw = <0x08 0x0003>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_875 { + clock-latency-ns = <125000>; + opp-microvolt = <875000 875000 1125000>; + opp-supported-hw = <0x02 0x0002>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@760000000_975 { + clock-latency-ns = <125000>; + opp-microvolt = <975000 975000 1125000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@770000000_975 { + clock-latency-ns = <125000>; + opp-microvolt = <975000 975000 1125000>; + opp-supported-hw = <0x02 0x0001>; + opp-hz = /bits/ 64 <770000000>; + }; + + opp@798000000_900 { + clock-latency-ns = <125000>; + opp-microvolt = <900000 900000 1125000>; + opp-supported-hw = <0x03 0x0002>; + opp-hz = /bits/ 64 <798000000>; + }; + + opp@817000000_875 { + clock-latency-ns = <125000>; + opp-microvolt = <875000 875000 1125000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <817000000>; + }; + + opp@817000000_1000 { + clock-latency-ns = <125000>; + opp-microvolt = <1000000 1000000 1125000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <817000000>; + }; + + opp@827000000_1000 { + clock-latency-ns = <125000>; + opp-microvolt = <1000000 1000000 1125000>; + opp-supported-hw = <0x02 0x0001>; + opp-hz = /bits/ 64 <827000000>; + }; + + opp@845000000_800 { + clock-latency-ns = <125000>; + opp-microvolt = <800000 800000 1125000>; + opp-supported-hw = <0x08 0x0003>; + opp-hz = /bits/ 64 <845000000>; + }; + + opp@893000000_850 { + clock-latency-ns = <125000>; + opp-microvolt = <850000 850000 1125000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <893000000>; + }; + + opp@902000000_950 { + clock-latency-ns = <125000>; + opp-microvolt = <950000 950000 1125000>; + opp-supported-hw = <0x01 0x0002>; + opp-hz = /bits/ 64 <902000000>; + }; + + opp@912000000_1050 { + clock-latency-ns = <125000>; + opp-microvolt = <1050000 1050000 1125000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp@922000000_925 { + clock-latency-ns = <125000>; + opp-microvolt = <925000 925000 1125000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <922000000>; + }; + + opp@922000000_1050 { + clock-latency-ns = <125000>; + opp-microvolt = <1050000 1050000 1125000>; + opp-supported-hw = <0x02 0x0001>; + opp-hz = /bits/ 64 <922000000>; + }; + + opp@940000000_850 { + clock-latency-ns = <125000>; + opp-microvolt = <850000 850000 1125000>; + opp-supported-hw = <0x08 0x0003>; + opp-hz = /bits/ 64 <940000000>; + }; + + opp@950000000_950 { + clock-latency-ns = <125000>; + opp-microvolt = <950000 950000 1125000>; + opp-supported-hw = <0x02 0x0002>; + opp-hz = /bits/ 64 <950000000>; + }; + + opp@960000000_1000 { + clock-latency-ns = <125000>; + opp-microvolt = <1000000 1000000 1125000>; + opp-supported-hw = <0x01 0x0002>; + opp-hz = /bits/ 64 <960000000>; + }; + + opp@1000000000_875 { + clock-latency-ns = <125000>; + opp-microvolt = <875000 875000 1125000>; + opp-supported-hw = <0x08 0x0003>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_900 { + clock-latency-ns = <125000>; + opp-microvolt = <900000 900000 1125000>; + opp-supported-hw = <0x04 0x0002>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_975 { + clock-latency-ns = <125000>; + opp-microvolt = <975000 975000 1125000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_1000 { + clock-latency-ns = <125000>; + opp-microvolt = <1000000 1000000 1125000>; + opp-supported-hw = <0x02 0x0002>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_1025 { + clock-latency-ns = <125000>; + opp-microvolt = <1025000 1025000 1125000>; + opp-supported-hw = <0x01 0x0002>; + opp-hz = /bits/ 64 <1000000000>; + }; + + opp@1000000000_1100 { + clock-latency-ns = <125000>; + opp-microvolt = <1100000 1100000 1125000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <1000000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -867,12 +1132,24 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&tegra_car TEGRA20_CLK_PLL_X>, + <&tegra_car TEGRA20_CLK_PLL_P>, + <&tegra_car TEGRA20_CLK_CCLK>; + clock-names = "pll_x", "intermediate", "cclk"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&tegra_car TEGRA20_CLK_PLL_X>, + <&tegra_car TEGRA20_CLK_PLL_P>, + <&tegra_car TEGRA20_CLK_CCLK>; + clock-names = "pll_x", "intermediate", "cclk"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; }; From patchwork Sun Oct 21 20:54:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651629 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B1DC313A4 for ; Sun, 21 Oct 2018 20:59:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9D359287FD for ; Sun, 21 Oct 2018 20:59:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8D2B728800; Sun, 21 Oct 2018 20:59:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 52A98287FD for ; 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[109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:10 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 07/17] ARM: dts: tegra30: Add CPU Operating Performance Points Date: Sun, 21 Oct 2018 23:54:51 +0300 Message-Id: <20181021205501.23943-8-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add CPU's Operating Performance Points to the device tree, they are used by the CPUFreq driver and allow to setup thermal throttling for the boards by linking the cooling device (CPU) with thermal sensors via thermal-zones description. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30.dtsi | 688 +++++++++++++++++++++++++++++++++ 1 file changed, 688 insertions(+) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 790d3fa7e6d2..0aefc8d9efab 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -980,6 +980,670 @@ status = "disabled"; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@408000000_800 { + clock-latency-ns = <2000>; + opp-microvolt = <800000 800000 1250000>; + opp-supported-hw = <0xFF 0xFFFF>; + opp-hz = /bits/ 64 <408000000>; + opp-suspend; + }; + + opp@460000000_800 { + clock-latency-ns = <50000>; + opp-microvolt = <800000 800000 1250000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <460000000>; + }; + + opp@480000000_800 { + clock-latency-ns = <50000>; + opp-microvolt = <800000 800000 1250000>; + opp-supported-hw = <0x02 0x019E>; + opp-hz = /bits/ 64 <480000000>; + }; + + opp@520000000_800 { + clock-latency-ns = <50000>; + opp-microvolt = <800000 800000 1250000>; + opp-supported-hw = <0x04 0x019E>; + opp-hz = /bits/ 64 <520000000>; + }; + + opp@550000000_800 { + clock-latency-ns = <50000>; + opp-microvolt = <800000 800000 1250000>; + opp-supported-hw = <0x18 0x31FE>; + opp-hz = /bits/ 64 <550000000>; + }; + + opp@550000000_850 { + clock-latency-ns = <50000>; + opp-microvolt = <850000 850000 1250000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <550000000>; + }; + + opp@600000000_850 { + clock-latency-ns = <50000>; + opp-microvolt = <850000 850000 1250000>; + opp-supported-hw = <0x1F 0x0800>; + opp-hz = /bits/ 64 <600000000>; + }; + + opp@650000000_850 { + clock-latency-ns = <50000>; + opp-microvolt = <850000 850000 1250000>; + opp-supported-hw = <0x02 0x019E>; + opp-hz = /bits/ 64 <650000000>; + }; + + opp@680000000_900 { + clock-latency-ns = <50000>; + opp-microvolt = <900000 900000 1250000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <680000000>; + }; + + opp@684000000_850 { + clock-latency-ns = <50000>; + opp-microvolt = <850000 850000 1250000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <684000000>; + }; + + opp@700000000_850 { + clock-latency-ns = <50000>; + opp-microvolt = <850000 850000 1250000>; + opp-supported-hw = <0x04 0x019E>; + opp-hz = /bits/ 64 <700000000>; + }; + + opp@770000000_850 { + clock-latency-ns = <50000>; + opp-microvolt = <850000 850000 1250000>; + opp-supported-hw = <0x18 0x31FE>; + opp-hz = /bits/ 64 <770000000>; + }; + + opp@780000000_900 { + clock-latency-ns = <50000>; + opp-microvolt = <900000 900000 1250000>; + opp-supported-hw = <0x02 0x019E>; + opp-hz = /bits/ 64 <780000000>; + }; + + opp@807000000_850 { + clock-latency-ns = <50000>; + opp-microvolt = <850000 850000 1250000>; + opp-supported-hw = <0x02 0x0001>; + opp-hz = /bits/ 64 <807000000>; + }; + + opp@817000000_900 { + clock-latency-ns = <50000>; + opp-microvolt = <900000 900000 1250000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <817000000>; + }; + + opp@820000000_975 { + clock-latency-ns = <50000>; + opp-microvolt = <975000 975000 1250000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <820000000>; + }; + + opp@860000000_900 { + clock-latency-ns = <50000>; + opp-microvolt = <900000 900000 1250000>; + opp-supported-hw = <0x04 0x019E>; + opp-hz = /bits/ 64 <860000000>; + }; + + opp@883000000_850 { + clock-latency-ns = <50000>; + opp-microvolt = <850000 850000 1250000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <883000000>; + }; + + opp@900000000_850 { + clock-latency-ns = <50000>; + opp-microvolt = <850000 850000 1250000>; + opp-supported-hw = <0x1F 0x0400>; + opp-hz = /bits/ 64 <900000000>; + }; + + opp@900000000_912 { + clock-latency-ns = <50000>; + opp-microvolt = <912000 912000 1250000>; + opp-supported-hw = <0x1F 0x0200>; + opp-hz = /bits/ 64 <900000000>; + }; + + opp@910000000_900 { + clock-latency-ns = <50000>; + opp-microvolt = <900000 900000 1250000>; + opp-supported-hw = <0x08 0x31FE>; + opp-hz = /bits/ 64 <910000000>; + }; + + opp@931000000_850 { + clock-latency-ns = <50000>; + opp-microvolt = <850000 850000 1250000>; + opp-supported-hw = <0x08 0x0001>; + opp-hz = /bits/ 64 <931000000>; + }; + + opp@940000000_900 { + clock-latency-ns = <50000>; + opp-microvolt = <900000 900000 1250000>; + opp-supported-hw = <0x10 0x31E0>; + opp-hz = /bits/ 64 <940000000>; + }; + + opp@948000000_900 { + clock-latency-ns = <50000>; + opp-microvolt = <900000 900000 1250000>; + opp-supported-hw = <0x02 0x0001>; + opp-hz = /bits/ 64 <948000000>; + }; + + opp@970000000_1000 { + clock-latency-ns = <50000>; + opp-microvolt = <1000000 1000000 1250000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <970000000>; + }; + + opp@990000000_975 { + clock-latency-ns = <50000>; + opp-microvolt = <975000 975000 1250000>; + opp-supported-hw = <0x02 0x019E>; + opp-hz = /bits/ 64 <990000000>; + }; + + opp@1026000000_975 { + clock-latency-ns = <50000>; + opp-microvolt = <975000 975000 1250000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <1026000000>; + }; + + opp@1039000000_900 { + clock-latency-ns = <50000>; + opp-microvolt = <900000 900000 1250000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <1039000000>; + }; + + opp@1040000000_1000 { + clock-latency-ns = <50000>; + opp-microvolt = <1000000 1000000 1250000>; + opp-supported-hw = <0x02 0x019E>; + opp-hz = /bits/ 64 <1040000000>; + }; + + opp@1040000000_1025 { + clock-latency-ns = <50000>; + opp-microvolt = <1025000 1025000 1250000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <1040000000>; + }; + + opp@1050000000_975 { + clock-latency-ns = <50000>; + opp-microvolt = <975000 975000 1250000>; + opp-supported-hw = <0x04 0x019E>; + opp-hz = /bits/ 64 <1050000000>; + }; + + opp@1080000000_1050 { + clock-latency-ns = <50000>; + opp-microvolt = <1050000 1050000 1250000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <1080000000>; + }; + + opp@1100000000_1025 { + clock-latency-ns = <50000>; + opp-microvolt = <1025000 1025000 1250000>; + opp-supported-hw = <0x02 0x019E>; + opp-hz = /bits/ 64 <1100000000>; + }; + + opp@1102000000_900 { + clock-latency-ns = <50000>; + opp-microvolt = <900000 900000 1250000>; + opp-supported-hw = <0x08 0x0001>; + opp-hz = /bits/ 64 <1102000000>; + }; + + opp@1102000000_1000 { + clock-latency-ns = <50000>; + opp-microvolt = <1000000 1000000 1250000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <1102000000>; + }; + + opp@1117000000_975 { + clock-latency-ns = <50000>; + opp-microvolt = <975000 975000 1250000>; + opp-supported-hw = <0x02 0x0001>; + opp-hz = /bits/ 64 <1117000000>; + }; + + opp@1149000000_1025 { + clock-latency-ns = <50000>; + opp-microvolt = <1025000 1025000 1250000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <1149000000>; + }; + + opp@1150000000_975 { + clock-latency-ns = <50000>; + opp-microvolt = <975000 975000 1250000>; + opp-supported-hw = <0x08 0x31FE>; + opp-hz = /bits/ 64 <1150000000>; + }; + + opp@1150000000_1000 { + clock-latency-ns = <50000>; + opp-microvolt = <1000000 1000000 1250000>; + opp-supported-hw = <0x04 0x019E>; + opp-hz = /bits/ 64 <1150000000>; + }; + + opp@1150000000_1075 { + clock-latency-ns = <50000>; + opp-microvolt = <1075000 1075000 1250000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <1150000000>; + }; + + opp@1160000000_975 { + clock-latency-ns = <50000>; + opp-microvolt = <975000 975000 1250000>; + opp-supported-hw = <0x10 0x31E0>; + opp-hz = /bits/ 64 <1160000000>; + }; + + opp@1171000000_1000 { + clock-latency-ns = <50000>; + opp-microvolt = <1000000 1000000 1250000>; + opp-supported-hw = <0x02 0x0001>; + opp-hz = /bits/ 64 <1171000000>; + }; + + opp@1178000000_975 { + clock-latency-ns = <50000>; + opp-microvolt = <975000 975000 1250000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <1178000000>; + }; + + opp@1187000000_1050 { + clock-latency-ns = <50000>; + opp-microvolt = <1050000 1050000 1250000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <1187000000>; + }; + + opp@1200000000_1025 { + clock-latency-ns = <50000>; + opp-microvolt = <1025000 1025000 1250000>; + opp-supported-hw = <0x04 0x019E>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1050 { + clock-latency-ns = <50000>; + opp-microvolt = <1050000 1050000 1250000>; + opp-supported-hw = <0x02 0x019E>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1200000000_1100 { + clock-latency-ns = <50000>; + opp-microvolt = <1100000 1100000 1250000>; + opp-supported-hw = <0x01 0x0192>; + opp-hz = /bits/ 64 <1200000000>; + }; + + opp@1206000000_1000 { + clock-latency-ns = <50000>; + opp-microvolt = <1000000 1000000 1250000>; + opp-supported-hw = <0x04 0x0001>; + opp-hz = /bits/ 64 <1206000000>; + }; + + opp@1206000000_1025 { + clock-latency-ns = <50000>; + opp-microvolt = <1025000 1025000 1250000>; + opp-supported-hw = <0x02 0x0001>; + opp-hz = /bits/ 64 <1206000000>; + }; + + opp@1216000000_975 { + clock-latency-ns = <50000>; + opp-microvolt = <975000 975000 1250000>; + opp-supported-hw = <0x08 0x0001>; + opp-hz = /bits/ 64 <1216000000>; + }; + + opp@1225000000_1075 { + clock-latency-ns = <50000>; + opp-microvolt = <1075000 1075000 1250000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <1225000000>; + }; + + opp@1230000000_1000 { + clock-latency-ns = <50000>; + opp-microvolt = <1000000 1000000 1250000>; + opp-supported-hw = <0x08 0x31FE>; + opp-hz = /bits/ 64 <1230000000>; + }; + + opp@1240000000_1000 { + clock-latency-ns = <50000>; + opp-microvolt = <1000000 1000000 1250000>; + opp-supported-hw = <0x10 0x3060>; + opp-hz = /bits/ 64 <1240000000>; + }; + + opp@1240000000_1125 { + clock-latency-ns = <50000>; + opp-microvolt = <1125000 1125000 1250000>; + opp-supported-hw = <0x01 0x0010>; + opp-hz = /bits/ 64 <1240000000>; + }; + + opp@1250000000_1075 { + clock-latency-ns = <50000>; + opp-microvolt = <1075000 1075000 1250000>; + opp-supported-hw = <0x02 0x001C>; + opp-hz = /bits/ 64 <1250000000>; + }; + + opp@1280000000_1025 { + clock-latency-ns = <50000>; + opp-microvolt = <1025000 1025000 1250000>; + opp-supported-hw = <0x18 0x307C>; + opp-hz = /bits/ 64 <1280000000>; + }; + + opp@1280000000_1050 { + clock-latency-ns = <50000>; + opp-microvolt = <1050000 1050000 1250000>; + opp-supported-hw = <0x04 0x001C>; + opp-hz = /bits/ 64 <1280000000>; + }; + + opp@1280000000_1125 { + clock-latency-ns = <50000>; + opp-microvolt = <1125000 1125000 1250000>; + opp-supported-hw = <0x01 0x0182>; + opp-hz = /bits/ 64 <1280000000>; + }; + + opp@1280000000_1150 { + clock-latency-ns = <50000>; + opp-microvolt = <1150000 1150000 1250000>; + opp-supported-hw = <0x01 0x0010>; + opp-hz = /bits/ 64 <1280000000>; + }; + + opp@1282000000_1100 { + clock-latency-ns = <50000>; + opp-microvolt = <1100000 1100000 1250000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <1282000000>; + }; + + opp@1300000000_1000 { + clock-latency-ns = <50000>; + opp-microvolt = <1000000 1000000 1250000>; + opp-supported-hw = <0x18 0x0181>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1025 { + clock-latency-ns = <50000>; + opp-microvolt = <1025000 1025000 1250000>; + opp-supported-hw = <0x0C 0x0183>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1050 { + clock-latency-ns = <50000>; + opp-microvolt = <1050000 1050000 1250000>; + opp-supported-hw = <0x0E 0x018F>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1075 { + clock-latency-ns = <50000>; + opp-microvolt = <1075000 1075000 1250000>; + opp-supported-hw = <0x06 0x019E>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1100 { + clock-latency-ns = <50000>; + opp-microvolt = <1100000 1100000 1250000>; + opp-supported-hw = <0x02 0x001C>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1125 { + clock-latency-ns = <50000>; + opp-microvolt = <1125000 1125000 1250000>; + opp-supported-hw = <0x01 0x0001>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1300000000_1150 { + clock-latency-ns = <50000>; + opp-microvolt = <1150000 1150000 1250000>; + opp-supported-hw = <0x01 0x0182>; + opp-hz = /bits/ 64 <1300000000>; + }; + + opp@1320000000_1175 { + clock-latency-ns = <50000>; + opp-microvolt = <1175000 1175000 1250000>; + opp-supported-hw = <0x01 0x0010>; + opp-hz = /bits/ 64 <1320000000>; + }; + + opp@1330000000_1050 { + clock-latency-ns = <50000>; + opp-microvolt = <1050000 1050000 1250000>; + opp-supported-hw = <0x08 0x3070>; + opp-hz = /bits/ 64 <1330000000>; + }; + + opp@1330000000_1125 { + clock-latency-ns = <50000>; + opp-microvolt = <1125000 1125000 1250000>; + opp-supported-hw = <0x02 0x001C>; + opp-hz = /bits/ 64 <1330000000>; + }; + + opp@1340000000_1100 { + clock-latency-ns = <50000>; + opp-microvolt = <1100000 1100000 1250000>; + opp-supported-hw = <0x04 0x0010>; + opp-hz = /bits/ 64 <1340000000>; + }; + + opp@1350000000_1075 { + clock-latency-ns = <50000>; + opp-microvolt = <1075000 1075000 1250000>; + opp-supported-hw = <0x08 0x000C>; + opp-hz = /bits/ 64 <1350000000>; + }; + + opp@1350000000_1100 { + clock-latency-ns = <50000>; + opp-microvolt = <1100000 1100000 1250000>; + opp-supported-hw = <0x04 0x000C>; + opp-hz = /bits/ 64 <1350000000>; + }; + + opp@1360000000_1050 { + clock-latency-ns = <50000>; + opp-microvolt = <1050000 1050000 1250000>; + opp-supported-hw = <0x10 0x3060>; + opp-hz = /bits/ 64 <1360000000>; + }; + + opp@1360000000_1150 { + clock-latency-ns = <50000>; + opp-microvolt = <1150000 1150000 1250000>; + opp-supported-hw = <0x02 0x0010>; + opp-hz = /bits/ 64 <1360000000>; + }; + + opp@1360000000_1200 { + clock-latency-ns = <50000>; + opp-microvolt = <1200000 1200000 1250000>; + opp-supported-hw = <0x01 0x0010>; + opp-hz = /bits/ 64 <1360000000>; + }; + + opp@1370000000_1075 { + clock-latency-ns = <50000>; + opp-microvolt = <1075000 1075000 1250000>; + opp-supported-hw = <0x08 0x3070>; + opp-hz = /bits/ 64 <1370000000>; + }; + + opp@1380000000_1125 { + clock-latency-ns = <50000>; + opp-microvolt = <1125000 1125000 1250000>; + opp-supported-hw = <0x04 0x0010>; + opp-hz = /bits/ 64 <1380000000>; + }; + + opp@1390000000_1075 { + clock-latency-ns = <50000>; + opp-microvolt = <1075000 1075000 1250000>; + opp-supported-hw = <0x10 0x3060>; + opp-hz = /bits/ 64 <1390000000>; + }; + + opp@1400000000_1100 { + clock-latency-ns = <50000>; + opp-microvolt = <1100000 1100000 1250000>; + opp-supported-hw = <0x08 0x307C>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp@1400000000_1125 { + clock-latency-ns = <50000>; + opp-microvolt = <1125000 1125000 1250000>; + opp-supported-hw = <0x04 0x000C>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp@1400000000_1150 { + clock-latency-ns = <50000>; + opp-microvolt = <1150000 1150000 1250000>; + opp-supported-hw = <0x02 0x000C>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp@1400000000_1175 { + clock-latency-ns = <50000>; + opp-microvolt = <1175000 1175000 1250000>; + opp-supported-hw = <0x02 0x0010>; + opp-hz = /bits/ 64 <1400000000>; + }; + + opp@1470000000_1100 { + clock-latency-ns = <50000>; + opp-microvolt = <1100000 1100000 1250000>; + opp-supported-hw = <0x10 0x3060>; + opp-hz = /bits/ 64 <1470000000>; + }; + + opp@1470000000_1125 { + clock-latency-ns = <50000>; + opp-microvolt = <1125000 1125000 1250000>; + opp-supported-hw = <0x08 0x3060>; + opp-hz = /bits/ 64 <1470000000>; + }; + + opp@1500000000_1125 { + clock-latency-ns = <50000>; + opp-microvolt = <1125000 1125000 1250000>; + opp-supported-hw = <0x18 0x3070>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1150 { + clock-latency-ns = <50000>; + opp-microvolt = <1150000 1150000 1250000>; + opp-supported-hw = <0x0C 0x3070>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1200 { + clock-latency-ns = <50000>; + opp-microvolt = <1200000 1200000 1250000>; + opp-supported-hw = <0x02 0x0010>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1500000000_1237 { + clock-latency-ns = <50000>; + opp-microvolt = <1237000 1237000 1250000>; + opp-supported-hw = <0x01 0x0010>; + opp-hz = /bits/ 64 <1500000000>; + }; + + opp@1520000000_1150 { + clock-latency-ns = <50000>; + opp-microvolt = <1150000 1150000 1250000>; + opp-supported-hw = <0x10 0x3060>; + opp-hz = /bits/ 64 <1520000000>; + }; + + opp@1540000000_1200 { + clock-latency-ns = <50000>; + opp-microvolt = <1200000 1200000 1250000>; + opp-supported-hw = <0x08 0x3060>; + opp-hz = /bits/ 64 <1540000000>; + }; + + opp@1590000000_1200 { + clock-latency-ns = <50000>; + opp-microvolt = <1200000 1200000 1250000>; + opp-supported-hw = <0x10 0x3060>; + opp-hz = /bits/ 64 <1590000000>; + }; + + opp@1700000000_1212 { + clock-latency-ns = <50000>; + opp-microvolt = <1212000 1212000 1250000>; + opp-supported-hw = <0x10 0x3060>; + opp-hz = /bits/ 64 <1700000000>; + }; + + opp@1700000000_1237 { + clock-latency-ns = <50000>; + opp-microvolt = <1237000 1237000 1250000>; + opp-supported-hw = <0x08 0x3060>; + opp-hz = /bits/ 64 <1700000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -988,24 +1652,48 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&tegra_car TEGRA30_CLK_PLL_X>, + <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_CCLK_G>; + clock-names = "pll_x", "intermediate", "cclk"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&tegra_car TEGRA30_CLK_PLL_X>, + <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_CCLK_G>; + clock-names = "pll_x", "intermediate", "cclk"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + clocks = <&tegra_car TEGRA30_CLK_PLL_X>, + <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_CCLK_G>; + clock-names = "pll_x", "intermediate", "cclk"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + clocks = <&tegra_car TEGRA30_CLK_PLL_X>, + <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_CCLK_G>; + clock-names = "pll_x", "intermediate", "cclk"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; }; From patchwork Sun Oct 21 20:54:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651633 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D128014E2 for ; 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[109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:11 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 08/17] ARM: dts: tegra20: colibri: Setup voltage regulators for DVFS Date: Sun, 21 Oct 2018 23:54:52 +0300 Message-Id: <20181021205501.23943-9-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20-colibri.dtsi | 31 ++++++++++++++++++-------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 6162d193e12c..5b3155dbf47a 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -495,17 +495,19 @@ regulator-always-on; }; - sm0 { + core_vdd_reg: sm0 { regulator-name = "VDD_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd_reg>; + regulator-coupled-max-spread = <150000>; regulator-always-on; }; - sm1 { + cpu_vdd_reg: sm1 { regulator-name = "VDD_CPU_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; regulator-always-on; }; @@ -530,10 +532,13 @@ regulator-always-on; }; - ldo2 { + rtc_vdd_reg: ldo2 { regulator-name = "VDD_RTC_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <150000>; + regulator-always-on; }; /* LDO3 is not connected to anything */ @@ -740,6 +745,14 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&cpu_vdd_reg>; + core-supply = <&core_vdd_reg>; + rtc-supply = <&rtc_vdd_reg>; + }; + }; }; &gpio { From patchwork Sun Oct 21 20:54:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651625 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B85014E2 for ; Sun, 21 Oct 2018 20:59:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7B0A6287FD for ; Sun, 21 Oct 2018 20:59:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6F24228800; Sun, 21 Oct 2018 20:59:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1CEAA287FD for ; Sun, 21 Oct 2018 20:59:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728470AbeJVFNy (ORCPT ); Mon, 22 Oct 2018 01:13:54 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:41486 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727256AbeJVFNx (ORCPT ); Mon, 22 Oct 2018 01:13:53 -0400 Received: by mail-lf1-f65.google.com with SMTP id q39-v6so28782390lfi.8; Sun, 21 Oct 2018 13:58:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lD5gQWDai5qk2fHLTBuMFPsuyYW/QrRx1ZMqTJ219kA=; b=cA8sG5GRUrZLF4q5mqmNpb4lNS6GSSWcwEzUikW3pY5rVnowbn8xJ5r3VH4aVvcGc4 eo+YQEJ9fOF01UZd0XVJmc0Ur6TT5GSHeXesHnN2voyhDSY1jcg0FkPXkWOphsY9BUF5 DKzFFofkBApc9SW2B0tikDBITiZOuovK1r4SxJne93fnkIbSRb1sdMM6bV8wqFpQIxbD U2vzVRwGhnt4NIOycjdWbcykJEfMqmmgWmlGuIpaWeWaXcPgyaQpRHLcu99/+N9a7/4o vwTcO+si4PJAGd49la491S1PER4zqlSYA3B0Do2hGolQ5nSHuXjLxiOsVb1Z3RwpY3kf dMgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lD5gQWDai5qk2fHLTBuMFPsuyYW/QrRx1ZMqTJ219kA=; b=cSSCq8D+knP+l0kzI4r2P/eZEOxdiS4BuEXv76tp4cf6NYQhmsf7fVxx83ZyTu/oBN t8/lcBmnovSQI4ZO7an+lL5v6oSG/QCzHyz57iKEg/LGRYRPvN0nSZgl8CsD4tYo301D FA7qgJcOkuCZtdo5s60xvM/IfkevNWUrVcihnKFPs1VKRhaiRKXo7mAeXnv/vXoQWCkj uSDjE98w6cymzELIs5ThDy61wmezr01zth3FWWD6wxyIRzywi1GlzmadDGi4dl3+2asR 3eWcdukJcnNHxw53ATVpP6NJWfNYtP3JejNU0TQYGh1PXogcPMMS2AHU0L0Y3n8B14gY P/FQ== X-Gm-Message-State: ABuFfoiJHD+ojrCskjaOsQ/g7M5hcZocsmekMwBV/61DE4EN5gfGWOUt JF30Us/7AWrjXzXqR47A/gI= X-Google-Smtp-Source: ACcGV60sUQzYL79YaCR1qHIltNtJAWU7+yPYcI8cL/GqLatXhsjUxJ+cAUTJ8Taesl1ciA9G84a/cQ== X-Received: by 2002:a19:6719:: with SMTP id b25mr5618971lfc.38.1540155493600; Sun, 21 Oct 2018 13:58:13 -0700 (PDT) Received: from localhost.localdomain (109-252-91-118.nat.spd-mgts.ru. [109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:13 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 09/17] ARM: dts: tegra20: harmony: Setup voltage regulators for DVFS Date: Sun, 21 Oct 2018 23:54:53 +0300 Message-Id: <20181021205501.23943-10-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20-harmony.dts | 31 +++++++++++++++++++-------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 1d96d92b72a7..9d720743fd4e 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -339,17 +339,19 @@ regulator-always-on; }; - sm0 { + core_vdd_reg: sm0 { regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd_reg>; + regulator-coupled-max-spread = <150000>; regulator-always-on; }; - sm1 { + cpu_vdd_reg: sm1 { regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; regulator-always-on; }; @@ -373,10 +375,13 @@ regulator-always-on; }; - ldo2 { + rtc_vdd_reg: ldo2 { regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <150000>; + regulator-always-on; }; ldo3 { @@ -779,4 +784,12 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&cpu_vdd_reg>; + core-supply = <&core_vdd_reg>; + rtc-supply = <&rtc_vdd_reg>; + }; + }; }; From patchwork Sun Oct 21 20:54:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651627 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5450514E2 for ; Sun, 21 Oct 2018 20:59:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 431C4287FD for ; Sun, 21 Oct 2018 20:59:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3769B28800; Sun, 21 Oct 2018 20:59:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D17E0287FD for ; Sun, 21 Oct 2018 20:59:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728484AbeJVFOp (ORCPT ); Mon, 22 Oct 2018 01:14:45 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:35677 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728398AbeJVFNy (ORCPT ); Mon, 22 Oct 2018 01:13:54 -0400 Received: by mail-lj1-f193.google.com with SMTP id o14-v6so35129790ljj.2; Sun, 21 Oct 2018 13:58:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fmGkAu4XHZNOq56DlvZJAZH2wGLRNDClSYlgkU+I3vs=; b=cJ6J03W7VcdH2AT2dD3h7QavYUFpBTwp35ZL9Ech6FWutxSCh/sWNi/KyFubYGVQ7y YIzSxDAK/e8a08f+ECQkwyMHUpkZMV+UsJSm5Cvg0/yqrJhIzoC+tNr35WfqjvpbxAOc L88rSIBdqwzNun7IhUvBLLzm5h1fIY0+5/kh1qPYGw7Lh1a/KPtykQhDTk63l/huonx9 N7ldTMyTljBWjMC5SphoaKSJH9q0It/V5RuTmokR9ItXWOApjGMJHUZFAa80c231yb/K 6btp9w4wxxGJXcvh7v+YgHHByq6tC1drjJXgq1/DnDZmsqUCbjEqiVFBGkancQ7tVf1w x7rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fmGkAu4XHZNOq56DlvZJAZH2wGLRNDClSYlgkU+I3vs=; b=EDM2xKpXoheDv3gW9ZKqs0zyZR7bBicRaidxYrrKGh6AAlGEog42axKxtQPa7p+pRb owvxwk1FpxheQWc7rP2XWnNl5gKSuLHjAVN2MxjQC5NSzRafn0Wv54zVm7/sQYstug2D IzCcZ+/ARP5m4IalDb1YHLFivQo+4X9MK2bn3dk55I/IYj6QOUWIsbI+5E9T/Akiyl+1 YPK/Tu87CY79d4dnmJyq6+7LyxkJbXpbQVxx3Gi0CgZXTvZESM75Yxr1ZSWWb2rsnFIG G3adawNEwPzQnpudYR+hERXMCtvArS/rbG9RuxKYdM5Pr8HSGIQwEG7KC08L8SVIUhsW casw== X-Gm-Message-State: AGRZ1gKWDkl7aTqGotGOIK5guVJC07Jmpeh39iSzMg7VRMGD0CnvwcwH S0VdFalnjhb91//yi7xyMC4= X-Google-Smtp-Source: ACcGV639oMkaHMpChbwibtF+UeUvYVZGh5z5uDQsjzfp4+Sj9QWMCSI9KBi1RR/k+b3pOYyey/jsHg== X-Received: by 2002:a2e:1642:: with SMTP id 2-v6mr9360327ljw.56.1540155494568; Sun, 21 Oct 2018 13:58:14 -0700 (PDT) Received: from localhost.localdomain (109-252-91-118.nat.spd-mgts.ru. [109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:14 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 10/17] ARM: dts: tegra20: paz00: Setup voltage regulators for DVFS Date: Sun, 21 Oct 2018 23:54:54 +0300 Message-Id: <20181021205501.23943-11-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20-paz00.dts | 31 ++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 8861e0976e37..51a09ae99f3a 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -337,17 +337,19 @@ regulator-always-on; }; - sm0 { + core_vdd_reg: sm0 { regulator-name = "+1.2vs_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd_reg>; + regulator-coupled-max-spread = <150000>; regulator-always-on; }; - sm1 { + cpu_vdd_reg: sm1 { regulator-name = "+1.0vs_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; regulator-always-on; }; @@ -367,10 +369,13 @@ regulator-always-on; }; - ldo2 { + rtc_vdd_reg: ldo2 { regulator-name = "+1.2vs_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <150000>; + regulator-always-on; }; ldo3 { @@ -603,4 +608,12 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&cpu_vdd_reg>; + core-supply = <&core_vdd_reg>; + rtc-supply = <&rtc_vdd_reg>; + }; + }; }; From patchwork Sun Oct 21 20:54:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651623 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8FD9813A4 for ; Sun, 21 Oct 2018 20:59:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 806B9287FD for ; Sun, 21 Oct 2018 20:59:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7218E28802; Sun, 21 Oct 2018 20:59:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 09163287FF for ; Sun, 21 Oct 2018 20:59:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728513AbeJVFN4 (ORCPT ); Mon, 22 Oct 2018 01:13:56 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:34600 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728340AbeJVFNz (ORCPT ); Mon, 22 Oct 2018 01:13:55 -0400 Received: by mail-lf1-f66.google.com with SMTP id n26-v6so10114619lfl.1; Sun, 21 Oct 2018 13:58:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VV4rw/xYMg2pa62uyvB1i95nBFrBi4ce9oWUqNOKKUU=; b=KvfzulwXHavT5aTRXatTkyfZAO+pGdMBHMw6eDjismX26LIE1rhBdCaWGbjHJUDU5K ZrUH/pe1kZiK9VAyHCT13dO30El7UA5TYGEW5KF5eyRUNW2Q4/5JB/33oUYZwpfKm6X9 MB1fpFQ4bRibnjwgWTNo9iLUUbABUVPGcxbSxvDGaXOXoTJvdThD/sWd020QhPUTOaBb lT5xxuMMkkXZ/fTRZv0OJM+ZrjJw336o5NC7E4VbD3p84etRensu2a/gS3fVhTPrElwQ On5IY1FQ/ywWZgqc4NXcHDlwWftIIBkbUBmVVKXIaNYFJgVhoNzh7S8Y5Cf//JukXRvP 8X3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VV4rw/xYMg2pa62uyvB1i95nBFrBi4ce9oWUqNOKKUU=; b=Kf7+Q3uTkzhOxpB/yDsoedvgEFuiWlrw9qgyVR97c8NQyJaiM/CIvPbNppJh5QQYOw OYTw4ZXypNLzlOUbcsMR+BYqqPe2E55HKklYWYmnB6ibv2ZPpmtEuZJAkV8LEjvXbJ1K 3QJZhrzeH6eH8mnwUCY0nwfG6MGVo1A6F5z0whLnljRfDg+M/1V0LxNUir7zJLPHbwfL IK91WjokiN055Qq2cSLNKNJLbVlF5ltv2j86iknlRL9geOygou33NRVf0ChNml2qU7KG mXiK5XQ+3N5Y7bujAuyY0ezmm2GnYulG3JFy8JZDhnDCj95xRbZ0np8bEH9eSG9lDUQX tGjg== X-Gm-Message-State: ABuFfog8Tbb3CjIwDuFGz6dqVOW96iaBc+peTM44C7auO0zlYuXZ0Pyc T7hM/22/ghKdFyHQ7QVFmmY= X-Google-Smtp-Source: ACcGV63oZKQhMq6L4ecaR+Natn6WjQNsB+L530XB48yYXu+DGQPKcG+GS70G57alH8HZjuRjAWO+IA== X-Received: by 2002:a19:ae11:: with SMTP id f17-v6mr8340920lfc.86.1540155495716; Sun, 21 Oct 2018 13:58:15 -0700 (PDT) Received: from localhost.localdomain (109-252-91-118.nat.spd-mgts.ru. [109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:15 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 11/17] ARM: dts: tegra20: seaboard: Setup voltage regulators for DVFS Date: Sun, 21 Oct 2018 23:54:55 +0300 Message-Id: <20181021205501.23943-12-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20-seaboard.dts | 27 +++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index f91441683aad..85bf7e89ebbe 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -444,16 +444,18 @@ regulator-always-on; }; - sm0 { + core_vdd_reg: sm0 { regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1300000>; + regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd_reg>; + regulator-coupled-max-spread = <150000>; regulator-always-on; }; - sm1 { + cpu_vdd_reg: sm1 { regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1125000>; + regulator-min-microvolt = <750000>; regulator-max-microvolt = <1125000>; regulator-always-on; }; @@ -474,10 +476,13 @@ regulator-always-on; }; - ldo2 { + rtc_vdd_reg: ldo2 { regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <150000>; + regulator-always-on; }; ldo3 { @@ -938,4 +943,12 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&cpu_vdd_reg>; + core-supply = <&core_vdd_reg>; + rtc-supply = <&rtc_vdd_reg>; + }; + }; }; From patchwork Sun Oct 21 20:54:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651621 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8D5E313A4 for ; Sun, 21 Oct 2018 20:58:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 788CE287FA for ; Sun, 21 Oct 2018 20:58:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 68084287FD; Sun, 21 Oct 2018 20:58:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 14FE628702 for ; Sun, 21 Oct 2018 20:58:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728583AbeJVFN5 (ORCPT ); Mon, 22 Oct 2018 01:13:57 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:41538 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727256AbeJVFN4 (ORCPT ); Mon, 22 Oct 2018 01:13:56 -0400 Received: by mail-lj1-f195.google.com with SMTP id u21-v6so35084253lja.8; Sun, 21 Oct 2018 13:58:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CudL+sqy6LcsG39kWf5I1sBXk5eo3KjjAKTeKlnP6Sc=; b=X4gKYmYSYAxTORwqZ5El88V8xslhxEKeGFTGQ+rZBeg/+7R4+kB21IWGzAhxGZgNHl aI9kp/jGNL+3w4UkK462JcBwOaL8pdXCr7n3BHHhOXFIu9x8SvM2HnDVLUOKs62sYGN2 j11OO4sf5t2pjBCrvA4OfQaxsrFMqR/CGlUhWrpb1Vvz2IAnDfy4wuyJZVqT4p1U1D/D l4Go0Y2ZBavpSVZr+fbrbRR7v/TWa5kq6uMc/xgGjHc6drusn7n7rnv2XybUxowLpWIW rE0Oppnj5eqI4ahmIqZUp8knzw5fIQEea6CSUS9oj1QHL5smRl25D9xmfrJghrGAgwuS MhIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CudL+sqy6LcsG39kWf5I1sBXk5eo3KjjAKTeKlnP6Sc=; b=EsXO6CNydWZFlxCljsHnX2/5jmoq0VWfTb8jrDimfnmnE8D41785t2tXvIjsQ7m0zv 2tmcWKTztNc6Xl919lWzomu6pHD3QK3piLQCHBA4PEPm3yFpDMdHtn7UtDAchC8sL9dD 9akeh5JIR1CnYRBcXfsHpThTEprfzY9e6VJJ22I34+Pr2E/O6vzj2k6Ybs8RWn52gLAy 6ApvKbWJafL27rypZMH1kRNvwPdiLu5n8Zt8kTx0ZC6eK6PTwvBlTHHCWpV84JhtHXKi 9fe7l9jB0BjDgf5HejU8V40PXDybuoZrjKopiBWPXlShtFHXmz4zuJvm0YFpHk1M19UA z/zQ== X-Gm-Message-State: ABuFfoiCGU9cklM1fdOKqfQTsJ99lCf4mk+mLPBO2drRVfUPfXHBA5jA p/GWy0C0920+1T2/0V8axTc= X-Google-Smtp-Source: ACcGV63tanBERBQyhVICl2eVygFKIOtkfovUzOqqiHlYUrty3Lzib1wDT3m6jYUy0amSTm0Z0Gbpyw== X-Received: by 2002:a2e:7017:: with SMTP id l23-v6mr22937686ljc.160.1540155496742; Sun, 21 Oct 2018 13:58:16 -0700 (PDT) Received: from localhost.localdomain (109-252-91-118.nat.spd-mgts.ru. [109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:16 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 12/17] ARM: dts: tegra20: tamonten: Setup voltage regulators for DVFS Date: Sun, 21 Oct 2018 23:54:56 +0300 Message-Id: <20181021205501.23943-13-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20-tamonten.dtsi | 31 ++++++++++++++++++------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 20137fc578b1..e9db60f4c317 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -357,17 +357,19 @@ regulator-always-on; }; - sm0 { + core_vdd_reg: sm0 { regulator-name = "vdd_sys_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd_reg>; + regulator-coupled-max-spread = <150000>; regulator-always-on; }; - sm1 { + cpu_vdd_reg: sm1 { regulator-name = "vdd_sys_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; regulator-always-on; }; @@ -391,10 +393,13 @@ regulator-always-on; }; - ldo2 { + rtc_vdd_reg: ldo2 { regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <150000>; + regulator-always-on; }; ldo3 { @@ -531,4 +536,12 @@ enable-active-high; }; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&cpu_vdd_reg>; + core-supply = <&core_vdd_reg>; + rtc-supply = <&rtc_vdd_reg>; + }; + }; }; From patchwork Sun Oct 21 20:54:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651619 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 956CA14E2 for ; Sun, 21 Oct 2018 20:58:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 84CFA28702 for ; Sun, 21 Oct 2018 20:58:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7917928708; Sun, 21 Oct 2018 20:58:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 26DBA28702 for ; Sun, 21 Oct 2018 20:58:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728592AbeJVFN6 (ORCPT ); Mon, 22 Oct 2018 01:13:58 -0400 Received: from mail-lf1-f67.google.com ([209.85.167.67]:38950 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728508AbeJVFN4 (ORCPT ); Mon, 22 Oct 2018 01:13:56 -0400 Received: by mail-lf1-f67.google.com with SMTP id p11-v6so2376835lfc.6; Sun, 21 Oct 2018 13:58:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1tWzv0d5FugDUKV37/6bOSJudJz4wanydeDntdPB6yA=; b=SpFlil4e7QeqcqOyx63r0+UTqCHuOGGKvveCc7JG9SsgXuFDJMjfkVjXcc8bjOJzlu nvWhGe3bK7fgz8Vja3tc5ftYeo9V5TYG+PQtNwi2BVgVPjpTPmkAtXBYGzs/A2Mg6Jo0 IqubQcti7tC6ck9GrR/iSXcdZ+SN5M0E2k9J8PadJ4DbpnNLbxxKpuNceoLRJyQ3eFrV l8ex3/dlIMA8TIRDjzMkat1RRr3u0y/zhIGtRrl3P5oDfhTWPUYiTOARITJhBHgkxGZM m28hrCr+JyyrsAFCVtXTZBZTXZGSY4Fn4RPGHqGSW3RfsZ/+WlRxWAFXTqoWlv8cGRHX g44g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1tWzv0d5FugDUKV37/6bOSJudJz4wanydeDntdPB6yA=; b=JLe5eNnCBKnT3JPLMI2TDr1V4vFTrh0Sf2ZjjNvRSssZRZcgzX5DVw/i+KUGu78mKC v4hOn4iu77RTVw5qQOUgMKDPavp7yuiULXLoerSk6PJi/NIkwWsjYqnnOM5TDaHbvb3W 5qygZ81A1robNLIR1hLR/2S0G/PfCFrnR/cJHDk82pyLtOXHP/SYIu7ZJ40URlzYUvBq 1qnf7nGEoOA6ZMiAHpbS1A1sZAtYSzSLNM6wCR4mYfYY1y2+HeQsKxfHu+7mp1LNy4d9 zewJAvj/yIPqbzNnfC03hwPoDnopvZNwhDWCYz28F/RJ6WXVa3jZfoiXsUzQobLUjiPV Tevg== X-Gm-Message-State: ABuFfojOTrdLNPMBV48gDJoinBkXN3QoLOVTSIdPKmL69mUQwAL5x6f+ XgABNpsVBLFveWpFkWhBsf7Kpeoy X-Google-Smtp-Source: ACcGV62H4kTBYKEqjCqMav6OTCRVrTfoLcv9xBdUhFway8rBWBpMuAySkLLK5PakdPAc1Svax1A25w== X-Received: by 2002:a19:4f04:: with SMTP id d4-v6mr7376798lfb.121.1540155497776; Sun, 21 Oct 2018 13:58:17 -0700 (PDT) Received: from localhost.localdomain (109-252-91-118.nat.spd-mgts.ru. [109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:17 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 13/17] ARM: dts: tegra20: ventana: Setup voltage regulators for DVFS Date: Sun, 21 Oct 2018 23:54:57 +0300 Message-Id: <20181021205501.23943-14-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20-ventana.dts | 31 +++++++++++++++++++-------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index f44551e2d9d0..ef9cdd7335ae 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -419,17 +419,19 @@ regulator-always-on; }; - sm0 { + core_vdd_reg: sm0 { regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd_reg>; + regulator-coupled-max-spread = <150000>; regulator-always-on; }; - sm1 { + cpu_vdd_reg: sm1 { regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; regulator-always-on; }; @@ -449,10 +451,13 @@ regulator-always-on; }; - ldo2 { + rtc_vdd_reg: ldo2 { regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <150000>; + regulator-always-on; }; ldo3 { @@ -704,4 +709,12 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&cpu_vdd_reg>; + core-supply = <&core_vdd_reg>; + rtc-supply = <&rtc_vdd_reg>; + }; + }; }; From patchwork Sun Oct 21 20:54:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651617 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F2E8D14E2 for ; Sun, 21 Oct 2018 20:58:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6453727D0C for ; Sun, 21 Oct 2018 20:58:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 584E62859F; Sun, 21 Oct 2018 20:58:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 075F827D0C for ; Sun, 21 Oct 2018 20:58:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728638AbeJVFN6 (ORCPT ); Mon, 22 Oct 2018 01:13:58 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:44990 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728340AbeJVFN6 (ORCPT ); Mon, 22 Oct 2018 01:13:58 -0400 Received: by mail-lf1-f66.google.com with SMTP id m18-v6so28807909lfl.11; Sun, 21 Oct 2018 13:58:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dCr7GO7Iq5Y7bRaR7BM38wZmN8Gdtnzq1YAYU5cFX8w=; b=sAM5zKnEloKH4E7B1p0tOi0MR1Z0KVDoHZooz+DptlYqoEA4nJhalQ+G2t8q4q0UUS bsJJkIPq0i8gX85xC8cn6wokAi1u6u3CEtpUz4BIoD2JV6q0tC3afip+AC09sbNSamie hvRQTSlTzXbAU8RlkzhuuCoiqqT9He5mxM3+1IDHYLkwvWHCjov4y7K+IsCF5/aa8UHs pUTPK8bQMp5KYuEWgsn8RJk3fP1lZ1K39RV7Z3NN4JPXEH824gu5wV0hkQ/9i7OCO8hy Y4qKT1kcjcv+O/rM05ecQVNaKQG0xQqPxIzNjNRHYSxB9TVUMd1iBQjkZJ4quaxaLOlF Hycg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dCr7GO7Iq5Y7bRaR7BM38wZmN8Gdtnzq1YAYU5cFX8w=; b=m975hGKeabKcYMO/LmBRw2bJf8xcZn7F1qcqP3beIAah+C46/2+Gtbtl/n/gk0TX+7 EeHZfPz8M52MhbvxlRA/EX2wsCLs6fSHQQXGaLzjtHrd987z0TecwSciP7qxlNLurs/u 5F1K2eXuo2CtJvBMITqV1OGcT/z0RB/209HliMF+JmtOQx2rNp4IPOLQtHINd6deetAF BzfDxATKpR/gpZAWjgBD5wLSXv1kFrTVm8Me8luF+2A01WaBHOA9p5n7mzE4Sdo8TDV0 OXPWNg3jm2vNH4Sl0tKTYQUdy4QIGkosJINkuRisAycuawF9GrmpxF4Vw0jVamnjV15e XIpA== X-Gm-Message-State: ABuFfogvVxNiNRkqTk6MHhT8ha65x9dSjzyi38juYtR7RPO8a5KQbdgD LZCSkWpThGEOO8SfVeNOv0tbn2qA X-Google-Smtp-Source: ACcGV63ykze29jsaL4SPe6FdBA/hyZ4qiqg66/Jr+b4ZAJ/irigoIwRJ9oI9KNi0lArXNqmb949a+w== X-Received: by 2002:a19:2b54:: with SMTP id r81mr1515429lfr.34.1540155498798; Sun, 21 Oct 2018 13:58:18 -0700 (PDT) Received: from localhost.localdomain (109-252-91-118.nat.spd-mgts.ru. [109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:18 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 14/17] ARM: dts: tegra30: apalis: Setup voltage regulators for DVFS Date: Sun, 21 Oct 2018 23:54:58 +0300 Message-Id: <20181021205501.23943-15-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-apalis.dtsi | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 7f112f192fe9..1ca9bec8380f 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -890,8 +890,11 @@ vddctrl_reg: vddctrl { regulator-name = "+V1.0_VDD_CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; }; @@ -1013,13 +1016,16 @@ }; /* SW: +V1.2_VDD_CORE */ - regulator@60 { + core_vdd_reg: regulator@60 { compatible = "ti,tps62362"; reg = <0x60>; regulator-name = "tps62362-vout"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-low; @@ -1168,4 +1174,11 @@ <&tegra_car TEGRA30_CLK_EXTERN1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + core-supply = <&core_vdd_reg>; + }; + }; }; From patchwork Sun Oct 21 20:54:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651615 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A47813A4 for ; Sun, 21 Oct 2018 20:58:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2A8022624B for ; Sun, 21 Oct 2018 20:58:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1E10327F3E; Sun, 21 Oct 2018 20:58:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C197A2624B for ; Sun, 21 Oct 2018 20:58:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728708AbeJVFOA (ORCPT ); Mon, 22 Oct 2018 01:14:00 -0400 Received: from mail-lj1-f195.google.com ([209.85.208.195]:35682 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728576AbeJVFN7 (ORCPT ); Mon, 22 Oct 2018 01:13:59 -0400 Received: by mail-lj1-f195.google.com with SMTP id o14-v6so35129879ljj.2; Sun, 21 Oct 2018 13:58:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bfPxAABb1jDJ2Qsfc7iJcf6o4lAj7GKSnk+3Z0pbBag=; b=hvukRxzSmBceCx29ruL0uS8bUhVtVE88aU/eK0GdgRuVcsnqbm/Xt/Rw444+RvX1zw +xZ8rZUOxFZ6z6baEoEb+t53r1w2qk5HM5y12heW48zmlkW0TzP3UcJ3W7obMqFwcGRs /21v/4kGv7weSfwWSzi/kJREmhMP58wnlrbnLV0Z+WVR3AqpJbFccR6gYK6IEA/HiDd4 kv0Os9Lz1h8aXEboS+4JWKvKx384pPUFdd6wGscIV9zuouA+jcombYRURwW72ZTPADKw PbX5VzFZYiqBOTjbxskBhtl3md2hqyUACKLC3Ycs0St5XSfGBaM+xGWtIGYvPyO/Y3oz m1XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bfPxAABb1jDJ2Qsfc7iJcf6o4lAj7GKSnk+3Z0pbBag=; b=l3SoDDcyMWvvLTBxI30SgVxeqT9eofuQ45RDKyU8KhyLdLrhdsgM/d1/7r3guMtOrO qooTBfe5cviauEF1/Eg48AzT7LLVVF1XhLSlniZugzp84JOb3lw6cu3PziWbtSpqkbxb nMbBMah5SOmlBZw1c7XLOHpvuGV0wOQZum3cTUe26XVM3jtipOvPiwh5UztwdGQW4mc/ eHrkiY++NiJgg8oq9P2j4hejsBiGuG/HEcIa1eEg5+zAsYmR/ny5BCpucYxbjVZHvJdC EfmTaFNU5+ByTePolgmlLi8Zsn1ZX22i2o4xvAMPcXuxlKfCc5JZxYjdz6z441JWcd3/ phSw== X-Gm-Message-State: ABuFfoi+GjgIB5wJL5fAb6j0IkmyAifz30JQ2dKPUU8jymQg18+g4KzP bd+Z7FwnH1gp0YkuOSOUc9U= X-Google-Smtp-Source: ACcGV617gDeztmpy07CUUkfYimgYscBKieRM1rLip1b18NhqVlZ0eHMHL4KEaGiTHcDFQRx3vKo1cw== X-Received: by 2002:a2e:50e:: with SMTP id 14-v6mr13217260ljf.152.1540155499872; Sun, 21 Oct 2018 13:58:19 -0700 (PDT) Received: from localhost.localdomain (109-252-91-118.nat.spd-mgts.ru. [109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:19 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 15/17] ARM: dts: tegra30: beaver: Setup voltage regulators for DVFS Date: Sun, 21 Oct 2018 23:54:59 +0300 Message-Id: <20181021205501.23943-16-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-beaver.dts | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index b0d40ac8ac6e..39941489d005 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1806,8 +1806,11 @@ vddctrl_reg: vddctrl { regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; }; @@ -1868,13 +1871,16 @@ }; }; - tps62361@60 { + core_vdd_reg: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; regulator-name = "tps62361-vout"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-high; @@ -2114,4 +2120,11 @@ <&tegra_car TEGRA30_CLK_EXTERN1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + core-supply = <&core_vdd_reg>; + }; + }; }; From patchwork Sun Oct 21 20:55:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651613 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AF3AE14E2 for ; Sun, 21 Oct 2018 20:58:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9E3442624B for ; Sun, 21 Oct 2018 20:58:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 91D1727F3E; Sun, 21 Oct 2018 20:58:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 121CD2624B for ; Sun, 21 Oct 2018 20:58:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728736AbeJVFOB (ORCPT ); Mon, 22 Oct 2018 01:14:01 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:34603 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728508AbeJVFOA (ORCPT ); Mon, 22 Oct 2018 01:14:00 -0400 Received: by mail-lf1-f68.google.com with SMTP id n26-v6so10114682lfl.1; Sun, 21 Oct 2018 13:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1tOE86fX1OZR0BOmROk+U9leFQPqWVeFiGsncXg6ozE=; b=aPXlXionNPzTk6cCxVe2cWd6m4h+8p09fWzVARc9jDstvYvp1QNp58uvdmdMg8lhIx lNK9+3Df7ObXngqjPRG1pzhuEqk5iHG7fGp9IGjkyHQt28ep4FnowdIaXzyM6Nvpz62S k0jX6nSHzFiVF3+idJxDf0yCnh/lIZtSzYfj4A9BjLKhsgph/XJwJjIdCFEyBcTvsnmu ASHYhaD+NuCF4QYzXdM5EezNEAS3YfLVf9IV1K1p8uVSEsldpCIHeltV5j+0MQ9sCH2u SJh4eWD4s93NfGlHnrzFookzbrGgXxUlw3LPQWLiyTy+iRHrhmiZzKA5t7yST206dQmf rcqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1tOE86fX1OZR0BOmROk+U9leFQPqWVeFiGsncXg6ozE=; b=Ajnbgieb04ZYxNSNlpSlctZXE2TmNS1mMAROLpfDtz5tS/+eve6U4yPb1lPNSrrlqG qVTY250QLoYCtDUMRxVRZBAwYMpwSXY5rrKv8nQ2Qu2hob5ynsjFk0Woz7aHtWxzKK1O WQJXxU0In37i/RwPk72lvEBUakm8110gikDuuB7NVVBkJ22YIlbMFR9ED3XxvK4mIjPF PpYAKXh0KS8mQE8HIBow57oOKlRGXv2Lwr1Dpg5tLl2wdjwpk8cgOh7S7jRJZFpii5gV NJIvnU0RTNziAKgbzLeKvvawMbH7VmM8eKEXKJAr3ohHY9TYIJVWrvyQ1yRDL8Q4QFHW CO3A== X-Gm-Message-State: ABuFfoifAHPmTqBjQdlY70293quwW87laCkMNXBueRwWxvzs52UXZ0rh lSDO2c1tOHfG98xgfJ5wwWD0KqsI X-Google-Smtp-Source: ACcGV63q+YtjgaYu2LMgtbLsXqiSy7zJQ4rseMS6iMdp3vJJdAcvLxcuEkxWcF27T6KMXeo7wUJ6aw== X-Received: by 2002:a19:8d11:: with SMTP id p17-v6mr7280174lfd.116.1540155500915; Sun, 21 Oct 2018 13:58:20 -0700 (PDT) Received: from localhost.localdomain (109-252-91-118.nat.spd-mgts.ru. [109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:20 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 16/17] ARM: dts: tegra30: cardhu: Setup voltage regulators for DVFS Date: Sun, 21 Oct 2018 23:55:00 +0300 Message-Id: <20181021205501.23943-17-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-cardhu.dtsi | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index fb9222b479d2..5fcf5ac09530 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -272,8 +272,11 @@ vddctrl_reg: vddctrl { regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; }; @@ -342,13 +345,16 @@ interrupts = ; }; - tps62361@60 { + core_vdd_reg: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; regulator-name = "tps62361-vout"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-high; @@ -649,4 +655,11 @@ debounce-interval = <10>; }; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + core-supply = <&core_vdd_reg>; + }; + }; }; From patchwork Sun Oct 21 20:55:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10651611 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5922F14E2 for ; Sun, 21 Oct 2018 20:58:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 444B22624B for ; Sun, 21 Oct 2018 20:58:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3422F27F3E; Sun, 21 Oct 2018 20:58:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D1B462624B for ; Sun, 21 Oct 2018 20:58:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728764AbeJVFOC (ORCPT ); Mon, 22 Oct 2018 01:14:02 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:36132 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728340AbeJVFOB (ORCPT ); Mon, 22 Oct 2018 01:14:01 -0400 Received: by mail-lf1-f65.google.com with SMTP id l1-v6so9019994lfc.3; Sun, 21 Oct 2018 13:58:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kLoLfunpsOiImN7+1Ii2rXCFU/3rlLKOsyCDj2PWwm8=; b=dWKltCBGLkEuudqS5ANR2CITe6jmsLugzJ0x2UuWc3xbXkndi7JyZRqCU10kPw9KJv usnB0a0zBoSGtFq2uJjTHsWpzDOqZFgWXGycgi8Di84tXIaLlCuCIfCTilogOMsIBvNt Fdvry2PEUBhSECYWWk+pUFkZHtc6mYVfnOx4+M/q81RxkeYEQzY4djFqUnGNo2RiA9pH OkDU4VgyENEU5rK5jKXGOf9SDWLyKhjv+hE+BM5oqe5LvMB9nzQEOIg6fzKFq0UtZQ6Z vHJPTDiYhb/CNi7ejQHYJQK4PY4uR7iXRvpRo/AsHnGML7RV3sqgIzbnY+w2ppHWp9dm whWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kLoLfunpsOiImN7+1Ii2rXCFU/3rlLKOsyCDj2PWwm8=; b=fStFdEA3ysJSqHZeXvJAnUAJVwCgzpTGSAB4cUmCI3Tdi6Wxi9qSqXPVRBTTJLcUN+ DTCRR8XRCb+YeNCraJqoSWf5hHA442fnSA6AFNgeL9cef/0OPn4MGFHR3Gl63yeiy0EK H53ItyvaSygenJvzErtT04mlQv1x4i7hX+z9mrk8kvPPjgMMq22H8KwmzKiuVbeB2td2 s+IxeVrBhxrkrQ+paflXygDXjo2RCh0SVr5fGpxawwjdfbNiu2V+m+mFtic70WZjzA0A ZqGzeg8vXL1ftRnEjxo1+6PLkuEH1227+EOKjOaHrxHwEEFSQ/P4zOUwmHUT7qjUYJvt mxpw== X-Gm-Message-State: ABuFfogY5laubHICgMAdPYyd9RWJxFzpKTgUVqXxOJQWaN50b/7CnNqE 6lgSPibWKmha0TWVeAwyWsE= X-Google-Smtp-Source: ACcGV625xOxSNSRRK1ANM3OHEY3c6Q/90Z/n1G2JL8oAg6fHMdKtE6ue7hMk6lFlmlcDrk4dY2S6HQ== X-Received: by 2002:a19:274b:: with SMTP id n72-v6mr7433059lfn.153.1540155501931; Sun, 21 Oct 2018 13:58:21 -0700 (PDT) Received: from localhost.localdomain (109-252-91-118.nat.spd-mgts.ru. [109.252.91.118]) by smtp.gmail.com with ESMTPSA id p63-v6sm6515919lfg.46.2018.10.21.13.58.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 13:58:21 -0700 (PDT) From: Dmitry Osipenko To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Thierry Reding , Jonathan Hunter , Nishanth Menon , Stephen Boyd , Marcel Ziswiler Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 17/17] ARM: dts: tegra30: colibri: Setup voltage regulators for DVFS Date: Sun, 21 Oct 2018 23:55:01 +0300 Message-Id: <20181021205501.23943-18-digetx@gmail.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181021205501.23943-1-digetx@gmail.com> References: <20181021205501.23943-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra30-colibri.dtsi | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 35af03ca9e90..c59099c1e2c3 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -763,8 +763,11 @@ vddctrl_reg: vddctrl { regulator-name = "+V1.0_VDD_CPU"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; }; @@ -882,13 +885,16 @@ }; /* SW: +V1.2_VDD_CORE */ - regulator@60 { + core_vdd_reg: regulator@60 { compatible = "ti,tps62362"; reg = <0x60>; regulator-name = "tps62362-vout"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1400000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-low; @@ -1027,6 +1033,13 @@ <&tegra_car TEGRA30_CLK_EXTERN1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + core-supply = <&core_vdd_reg>; + }; + }; }; &gpio {