From patchwork Fri Aug 21 09:42:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729069 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7A6E1109B for ; Fri, 21 Aug 2020 10:58:35 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 554592072D for ; Fri, 21 Aug 2020 10:58:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="CXCWKTQ2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 554592072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5180+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id CahnYY4521763x9WIX3ArUdo; Fri, 21 Aug 2020 03:58:35 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.130425.1598002998984331784 for ; Fri, 21 Aug 2020 02:43:19 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="55170273" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:18 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id BE313423205B; Fri, 21 Aug 2020 18:43:16 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 01/36] dt-bindings: power: Add r8a774e1 SYSC power domain definitions Date: Fri, 21 Aug 2020 10:42:37 +0100 Message-Id: <20200821094312.3249-2-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: 4NHBN3QquFo6AtEPQlC6NGP4x4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007515; bh=/faPQN8o88kiLF/BqG6Acu33HnhliSJOmWmieizdlFs=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=CXCWKTQ26YLJRdiA8aqxN/yAYBhTQ/mcxAEKI/mB8DPfxPsMA5oc+mjS1IIM8uHHtw/ iros23vGlmx9HHaTgAXV/GfyMWmAbq4rEytWKKCPFh2Kj41ESZL2qotvqQ0pfFR7oTy9s UG+GHThIxgRkL8p787YDpDatW5QMxCETZDY= From: Marian-Cristian Rotariu commit e24779649c840ce1ecb638a30e7c821075630184 upstream. This patch adds power domain indices for the RZ/G2H (r8a774e1) SoC. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- include/dt-bindings/power/r8a774e1-sysc.h | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 include/dt-bindings/power/r8a774e1-sysc.h diff --git a/include/dt-bindings/power/r8a774e1-sysc.h b/include/dt-bindings/power/r8a774e1-sysc.h new file mode 100644 index 000000000000..7edb8161db36 --- /dev/null +++ b/include/dt-bindings/power/r8a774e1-sysc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774E1_PD_CA57_CPU0 0 +#define R8A774E1_PD_CA57_CPU1 1 +#define R8A774E1_PD_CA57_CPU2 2 +#define R8A774E1_PD_CA57_CPU3 3 +#define R8A774E1_PD_CA53_CPU0 5 +#define R8A774E1_PD_CA53_CPU1 6 +#define R8A774E1_PD_CA53_CPU2 7 +#define R8A774E1_PD_CA53_CPU3 8 +#define R8A774E1_PD_A3VP 9 +#define R8A774E1_PD_CA57_SCU 12 +#define R8A774E1_PD_A3VC 14 +#define R8A774E1_PD_3DG_A 17 +#define R8A774E1_PD_3DG_B 18 +#define R8A774E1_PD_3DG_C 19 +#define R8A774E1_PD_3DG_D 20 +#define R8A774E1_PD_CA53_SCU 21 +#define R8A774E1_PD_3DG_E 22 +#define R8A774E1_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774E1_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */ From patchwork Fri Aug 21 09:42:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729083 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DB8BA109B for ; Fri, 21 Aug 2020 10:58:36 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B64062072D for ; Fri, 21 Aug 2020 10:58:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="A4rFBwWh" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B64062072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5193+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id pHm3YY4521763xJKeDnDwPSt; Fri, 21 Aug 2020 03:58:36 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web11.130424.1598002997752220163 for ; Fri, 21 Aug 2020 02:43:20 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954525" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:20 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9EB514231AD9; Fri, 21 Aug 2020 18:43:18 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 02/36] dt-bindings: power: renesas,rcar-sysc: Document r8a774e1 SYSC binding Date: Fri, 21 Aug 2020 10:42:38 +0100 Message-Id: <20200821094312.3249-3-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: UZmFD0J8YZ2tQBdvkVtA5bhNx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007516; bh=a+Rz3DrUpYIHxM+On5GjiawB2wogBmOiYxKT5zrUTdw=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=A4rFBwWhC9dvhK8eNJHHnA9gP0IJ9Xmvd6sZSnph/Eu3dHSvwc2ufiO+uys4rfHK7zu Y/NpkrS8rtOXno9UovdZ0Dk0aeObne7FgIQQbg56+XUQIfkKLDP+AhczSdSnXtKhc+olQ CT8oGgKK1VQmmg/3CEmi4sEk3RCs1p+3DcU= From: Marian-Cristian Rotariu commit f639fb66d17e2e25049503b7c2c568457a9b5c6f upstream. Document bindings for the RZ/G2H (aka R8A774E1) SYSC block. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [biju: Patched text version of bindings file] Signed-off-by: Biju Das --- Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt index 20008c8d33d3..9194e696a9b7 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt @@ -13,6 +13,7 @@ Required properties: - "renesas,r8a774a1-sysc" (RZ/G2M) - "renesas,r8a774b1-sysc" (RZ/G2N) - "renesas,r8a774c0-sysc" (RZ/G2E) + - "renesas,r8a774e1-sysc" (RZ/G2H) - "renesas,r8a7779-sysc" (R-Car H1) - "renesas,r8a7790-sysc" (R-Car H2) - "renesas,r8a7791-sysc" (R-Car M2-W) From patchwork Fri Aug 21 09:42:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729085 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE65517CF for ; Fri, 21 Aug 2020 10:58:36 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B64FA2078D for ; Fri, 21 Aug 2020 10:58:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="cnq0spys" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B64FA2078D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5194+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id Kpr1YY4521763xOVUN59Y5rh; Fri, 21 Aug 2020 03:58:36 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web11.130424.1598002997752220163 for ; Fri, 21 Aug 2020 02:43:22 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954529" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:21 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 72B574231AD9; Fri, 21 Aug 2020 18:43:20 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 03/36] soc: renesas: rcar-sysc: Add r8a774e1 support Date: Fri, 21 Aug 2020 10:42:39 +0100 Message-Id: <20200821094312.3249-4-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: spC942Iz2B1lc9bbl0l03Pvtx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007516; bh=n54vZuLOgK6xuofaTsfsj7NVwUaVBpR2hlCLRT/bqrc=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=cnq0spysdOqzkDKE/grKFakN1O90nZ3en4aNmvOQ8LSqSBnbeRhZIZ3NvsTDnIdhUqn ql9LV0Y7k+qvXKCObc1lsuLAdI23LEZeerw8sSVf2umdEWbmUoaOPVN/E+eN1miViHl3P Cd20u3hIkPfxJXsO7rj7B+uN6JbBqgttghE= From: Marian-Cristian Rotariu commit f446ade0952aed929186139f3643d714d9d2a855 upstream Add support for RZ/G2H (R8A774E1) SoC power areas to the R-Car SYSC driver. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-6-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [Biju: Added SYSC_R8A774E1 in Kconfig to enable the sysc driver in 4.19.y-cip kernel] Signed-off-by: Biju Das --- drivers/soc/renesas/Kconfig | 5 ++++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r8a774e1-sysc.c | 43 +++++++++++++++++++++++++++++ drivers/soc/renesas/rcar-sysc.c | 3 ++ drivers/soc/renesas/rcar-sysc.h | 1 + 5 files changed, 53 insertions(+) create mode 100644 drivers/soc/renesas/r8a774e1-sysc.c diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index f3727aa60aac..3b33e091ccff 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -13,6 +13,7 @@ config SOC_RENESAS select SYSC_R8A774A1 if ARCH_R8A774A1 select SYSC_R8A774B1 if ARCH_R8A774B1 select SYSC_R8A774C0 if ARCH_R8A774C0 + select SYSC_R8A774E1 if ARCH_R8A774E1 select SYSC_R8A7779 if ARCH_R8A7779 select SYSC_R8A7790 if ARCH_R8A7790 select SYSC_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793 @@ -53,6 +54,10 @@ config SYSC_R8A774C0 bool "RZ/G2E System Controller support" if COMPILE_TEST select SYSC_RCAR +config SYSC_R8A774E1 + bool "RZ/G2H System Controller support" if COMPILE_TEST + select SYSC_RCAR + config SYSC_R8A7779 bool "R-Car H1 System Controller support" if COMPILE_TEST select SYSC_RCAR diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index c2263f446921..2e43e2b5dc0e 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o obj-$(CONFIG_SYSC_R8A774A1) += r8a774a1-sysc.o obj-$(CONFIG_SYSC_R8A774B1) += r8a774b1-sysc.o obj-$(CONFIG_SYSC_R8A774C0) += r8a774c0-sysc.o +obj-$(CONFIG_SYSC_R8A774E1) += r8a774e1-sysc.o obj-$(CONFIG_SYSC_R8A7779) += r8a7779-sysc.o obj-$(CONFIG_SYSC_R8A7790) += r8a7790-sysc.o obj-$(CONFIG_SYSC_R8A7791) += r8a7791-sysc.o diff --git a/drivers/soc/renesas/r8a774e1-sysc.c b/drivers/soc/renesas/r8a774e1-sysc.c new file mode 100644 index 000000000000..18449f746455 --- /dev/null +++ b/drivers/soc/renesas/r8a774e1-sysc.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2H System Controller + * Copyright (C) 2020 Renesas Electronics Corp. + * + * Based on Renesas R-Car H3 System Controller + * Copyright (C) 2016-2017 Glider bvba + */ + +#include + +#include + +#include "rcar-sysc.h" + +static const struct rcar_sysc_area r8a774e1_areas[] __initconst = { + { "always-on", 0, 0, R8A774E1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, + { "ca57-scu", 0x1c0, 0, R8A774E1_PD_CA57_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU }, + { "ca57-cpu0", 0x80, 0, R8A774E1_PD_CA57_CPU0, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, + { "ca57-cpu1", 0x80, 1, R8A774E1_PD_CA57_CPU1, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, + { "ca57-cpu2", 0x80, 2, R8A774E1_PD_CA57_CPU2, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, + { "ca57-cpu3", 0x80, 3, R8A774E1_PD_CA57_CPU3, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR }, + { "ca53-scu", 0x140, 0, R8A774E1_PD_CA53_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU }, + { "ca53-cpu0", 0x200, 0, R8A774E1_PD_CA53_CPU0, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, + { "ca53-cpu1", 0x200, 1, R8A774E1_PD_CA53_CPU1, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, + { "ca53-cpu2", 0x200, 2, R8A774E1_PD_CA53_CPU2, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, + { "ca53-cpu3", 0x200, 3, R8A774E1_PD_CA53_CPU3, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR }, + { "a3vp", 0x340, 0, R8A774E1_PD_A3VP, R8A774E1_PD_ALWAYS_ON }, + { "a3vc", 0x380, 0, R8A774E1_PD_A3VC, R8A774E1_PD_ALWAYS_ON }, + { "a2vc1", 0x3c0, 1, R8A774E1_PD_A2VC1, R8A774E1_PD_A3VC }, + { "3dg-a", 0x100, 0, R8A774E1_PD_3DG_A, R8A774E1_PD_ALWAYS_ON }, + { "3dg-b", 0x100, 1, R8A774E1_PD_3DG_B, R8A774E1_PD_3DG_A }, + { "3dg-c", 0x100, 2, R8A774E1_PD_3DG_C, R8A774E1_PD_3DG_B }, + { "3dg-d", 0x100, 3, R8A774E1_PD_3DG_D, R8A774E1_PD_3DG_C }, + { "3dg-e", 0x100, 4, R8A774E1_PD_3DG_E, R8A774E1_PD_3DG_D }, +}; + +const struct rcar_sysc_info r8a774e1_sysc_info __initconst = { + .areas = r8a774e1_areas, + .num_areas = ARRAY_SIZE(r8a774e1_areas), + .extmask_offs = 0x2f8, + .extmask_val = BIT(0), +}; diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c index 061ea1be940e..54ea9bb8fca2 100644 --- a/drivers/soc/renesas/rcar-sysc.c +++ b/drivers/soc/renesas/rcar-sysc.c @@ -295,6 +295,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = { #ifdef CONFIG_SYSC_R8A774C0 { .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info }, #endif +#ifdef CONFIG_SYSC_R8A774E1 + { .compatible = "renesas,r8a774e1-sysc", .data = &r8a774e1_sysc_info }, +#endif #ifdef CONFIG_SYSC_R8A7779 { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info }, #endif diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h index f32b501c93d5..0864ff0a53d8 100644 --- a/drivers/soc/renesas/rcar-sysc.h +++ b/drivers/soc/renesas/rcar-sysc.h @@ -58,6 +58,7 @@ extern const struct rcar_sysc_info r8a77470_sysc_info; extern const struct rcar_sysc_info r8a774a1_sysc_info; extern const struct rcar_sysc_info r8a774b1_sysc_info; extern const struct rcar_sysc_info r8a774c0_sysc_info; +extern const struct rcar_sysc_info r8a774e1_sysc_info; extern const struct rcar_sysc_info r8a7779_sysc_info; extern const struct rcar_sysc_info r8a7790_sysc_info; extern const struct rcar_sysc_info r8a7791_sysc_info; From patchwork Fri Aug 21 09:42:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729059 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B41517D4 for ; Fri, 21 Aug 2020 10:58:34 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 662A6207BB for ; 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Fri, 21 Aug 2020 18:43:22 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 04/36] soc: renesas: Add Renesas R8A774E1 config option Date: Fri, 21 Aug 2020 10:42:40 +0100 Message-Id: <20200821094312.3249-5-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: VBMhPE2tDb1gLUP4DT75HqyOx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007514; bh=P/rrHK1PEIY4aJ8iXsj6fipwh86YTztqbryaJvVecQg=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=O6KruFcIUt1NTYBvcXgbT53wXqNA1sEVOOfgPhw87f/1g0kbxbCeUaEjFKcDX9VDPvh dd5TYr5Z8UeBDZm3jfZ1ClNmVSt0anALAdi1kQ75c1BBufPG72Z7ahNn+/p/a8jv7sn8l AzMjr0G/yPv5g0uF4PbsZYzIjqqOYzk3LCc= From: Marian-Cristian Rotariu commit b88fc411e0e9c38058f6e3d2afdc96aaced4e72c upstream. Add configuration option for the RZ/G2H (R8A774E1) SoC. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [biju: Moved the configuration option from drivers/soc/renesas/Kconfig to here inorder to support the same in 4.19.y-cip kernel] Signed-off-by: Biju Das --- arch/arm64/Kconfig.platforms | 6 ++++++ drivers/soc/renesas/Kconfig | 6 +++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index b624ccee11b8..f744814b0a33 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -207,6 +207,12 @@ config ARCH_R8A774C0 help This enables support for the Renesas RZ/G2E SoC. +config ARCH_R8A774E1 + bool "Renesas RZ/G2H SoC Platform" + depends on ARCH_RENESAS + help + This enables support for the Renesas RZ/G2H SoC. + config ARCH_R8A7795 bool "Renesas R-Car H3 SoC Platform" depends on ARCH_RENESAS diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 3b33e091ccff..0afb4b8c3e6f 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -4,9 +4,9 @@ config SOC_RENESAS select SOC_BUS select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \ ARCH_R8A774A1 || ARCH_R8A774B1 || ARCH_R8A774C0 || \ - ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77965 || \ - ARCH_R8A77970 || ARCH_R8A77980 || ARCH_R8A77990 || \ - ARCH_R8A77995 + ARCH_R8A774E1 || ARCH_R8A7795 || ARCH_R8A7796 || \ + ARCH_R8A77965 || ARCH_R8A77970 || ARCH_R8A77980 || \ + ARCH_R8A77990 || ARCH_R8A77995 select SYSC_R8A7743 if ARCH_R8A7743 select SYSC_R8A7745 if ARCH_R8A7745 select SYSC_R8A77470 if ARCH_R8A77470 From patchwork Fri Aug 21 09:42:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729075 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF21617CF for ; Fri, 21 Aug 2020 10:58:35 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C93732072D for ; Fri, 21 Aug 2020 10:58:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="Uxj+5IKr" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C93732072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5188+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id RLNlYY4521763xe0Za2FldOn; Fri, 21 Aug 2020 03:58:35 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web11.130424.1598002997752220163 for ; Fri, 21 Aug 2020 02:43:26 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954536" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:25 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 17D784232061; Fri, 21 Aug 2020 18:43:23 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 05/36] dt-bindings: arm: renesas: Document RZ/G2H SoC DT bindings Date: Fri, 21 Aug 2020 10:42:41 +0100 Message-Id: <20200821094312.3249-6-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: n8atx4mUEkxWBrsG8eflEXoVx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007515; bh=LgEDr8fSHioEK+VNPl1xdrG91mruMHcQSbS7Onf26BE=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Uxj+5IKrvUWC0mI0uaJFk1XyOFltmSr4M6Samqp3Mhh3NJB9u8H5jMfywy90G0rUe2J K7DrJV21xQrqdKcjhpaALvnalPa7XhS+O5+sRg/+7KRh5b8Axj20BA7qUwI1cbdiNLO6n g4aTsAb++vEB02ca1ercYS3LlhHjvuBgRWc= From: Marian-Cristian Rotariu commit 1f52719bb71f6ead0bcf19c212a30f05c2237058 upstream. Add device tree bindings documentation for the Renesas RZ/G2H (r8a774e1) SoC. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138368-16449-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [biju: Patched to shmobile.txt] Signed-off-by: Biju Das --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 7b83c02998d4..58a9c5194c36 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -29,6 +29,8 @@ SoCs: compatible = "renesas,r8a774b1" - RZ/G2E (R8A774C0) compatible = "renesas,r8a774c0" + - RZ/G2H (R8A774E1) + compatible = "renesas,r8a774e1" - R-Car M1A (R8A77781) compatible = "renesas,r8a7778" - R-Car H1 (R8A77790) From patchwork Fri Aug 21 09:42:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729057 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 881C817F0 for ; Fri, 21 Aug 2020 10:58:34 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 637A22078D for ; Fri, 21 Aug 2020 10:58:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="HJ32aT53" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 637A22078D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5181+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id mwLRYY4521763xpSQ8RT4PEA; Fri, 21 Aug 2020 03:58:34 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web11.130425.1598002998984331784 for ; Fri, 21 Aug 2020 02:43:27 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="55170291" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:27 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id E0879423205B; Fri, 21 Aug 2020 18:43:25 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 06/36] soc: renesas: Identify RZ/G2H Date: Fri, 21 Aug 2020 10:42:42 +0100 Message-Id: <20200821094312.3249-7-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: EtexX2ryVNSwrFBZyH7fYoY9x4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007514; bh=PwpCYsmzGGlDTE39mK5RJlGtn7S7UiZn7fTLmGWUtVc=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=HJ32aT53ltIuZskBItEU7kzOHilhupPPbBhmeaC2IxPiYre0q5gp4dzUYT8AtzJ/41W zwbs30+A3Jas9y8g9EetfRCgHB/9MyVJF9m6MsZVPmPn+6Z/fQL4WJEX6IBQJ/YObu7JB tmOFRiPktllMP8KCTaTr4CE1aNIvSPeuYMk= From: Marian-Cristian Rotariu commit 5b83cc42cf871d3079cc370432de6b5925c71ce5 upstream. This patch adds support for identifying the RZ/G2H (r8a774e1) SoC. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/soc/renesas/renesas-soc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 1a40c1e7ba27..7f29182a1d08 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -125,6 +125,11 @@ static const struct renesas_soc soc_rz_g2e __initconst __maybe_unused = { .id = 0x57, }; +static const struct renesas_soc soc_rz_g2h __initconst __maybe_unused = { + .family = &fam_rzg2, + .id = 0x4f, +}; + static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = { .family = &fam_rcar_gen1, }; @@ -234,6 +239,9 @@ static const struct of_device_id renesas_socs[] __initconst = { #ifdef CONFIG_ARCH_R8A774C0 { .compatible = "renesas,r8a774c0", .data = &soc_rz_g2e }, #endif +#ifdef CONFIG_ARCH_R8A774E1 + { .compatible = "renesas,r8a774e1", .data = &soc_rz_g2h }, +#endif #ifdef CONFIG_ARCH_R8A7778 { .compatible = "renesas,r8a7778", .data = &soc_rcar_m1a }, #endif From patchwork Fri Aug 21 09:42:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729065 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2ECFB17CF for ; Fri, 21 Aug 2020 10:58:35 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 098A420656 for ; Fri, 21 Aug 2020 10:58:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="sQSrl7m1" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 098A420656 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5176+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id 2QMwYY4521763xgb1sWhTS8n; Fri, 21 Aug 2020 03:58:34 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web11.130424.1598002997752220163 for ; Fri, 21 Aug 2020 02:43:29 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954542" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:29 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id AEB97423205B; Fri, 21 Aug 2020 18:43:27 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 07/36] dt-bindings: reset: rcar-rst: Document r8a774e1 reset module Date: Fri, 21 Aug 2020 10:42:43 +0100 Message-Id: <20200821094312.3249-8-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: LEroiEGFpgexib6203p99z5vx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007514; bh=xBvVF8hVX9F4vSuqu0eXsHdWYDGgGOsBfgh0/NuKnDw=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=sQSrl7m1ljThBjZZWnOBXcDThZpryiEi3bxdTz9ubGAPXyxUZlC2i02us+QJvDxQtEj 6iQrpFEIgm9rml3EpnntRNMhdiSv4ViIyeVwvBCYLVhdR0KUAGju+XqWa45Nh5CsFaTs2 XUa/vZJiYN06OWP14sGcbbMkYHfuvwreKuc= From: Marian-Cristian Rotariu commit 4d938a27e18d9c9a85041bb9a94f645a0a132f37 upstream. Document bindings for the RZ/G2H (R8A774E1) reset module. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [biju: Patched text version of bindings file] Signed-off-by: Biju Das --- Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt index 99d093084519..beb56db6393e 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.txt +++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt @@ -21,6 +21,7 @@ Required properties: - "renesas,r8a774a1-rst" (RZ/G2M) - "renesas,r8a774b1-rst" (RZ/G2N) - "renesas,r8a774c0-rst" (RZ/G2E) + - "renesas,r8a774e1-rst" (RZ/G2H) - "renesas,r8a7778-reset-wdt" (R-Car M1A) - "renesas,r8a7779-reset-wdt" (R-Car H1) - "renesas,r8a7790-rst" (R-Car H2) From patchwork Fri Aug 21 09:42:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729073 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CD44B17D4 for ; Fri, 21 Aug 2020 10:58:35 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A737F2078D for ; Fri, 21 Aug 2020 10:58:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="lXKwq5z+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A737F2078D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5189+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id jVBRYY4521763xVFZeESz6Ue; Fri, 21 Aug 2020 03:58:35 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web11.130425.1598002998984331784 for ; Fri, 21 Aug 2020 02:43:31 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="55170296" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:30 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 81905423206E; Fri, 21 Aug 2020 18:43:29 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 08/36] soc: renesas: rcar-rst: Add support for RZ/G2H Date: Fri, 21 Aug 2020 10:42:44 +0100 Message-Id: <20200821094312.3249-9-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: eJ3HJmJo6SqleMrxjLPtgEkdx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007515; bh=bu0sTes7Fx/hXZT3ivfYmItbftsYPcffaXyXdId0FXc=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=lXKwq5z+0kLdNBzK2dZZeBZ1ihixIwaJKJ0ImHw1WyI0B3jvCMkESwXWZjgBVf8qWwK 3yBz+6zNCU/UAE8eVTukwHnc2FlVzH3Jmx4TSzLcpY2LxtviTF2I9pQxfQT3sRHSQCLZG giPpBk2JEPhHrWdIHuV7BiWM6UXu9GMiqw0= From: Marian-Cristian Rotariu commit 7f8fa833dc739c4a28574c335eb08dbde2cb23d0 upstream. Add support for RZ/G2H (R8A774E1) to the R-Car RST driver. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/soc/renesas/rcar-rst.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c index 6c17ec510586..09a1e418a5e2 100644 --- a/drivers/soc/renesas/rcar-rst.c +++ b/drivers/soc/renesas/rcar-rst.c @@ -49,6 +49,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = { { .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 }, { .compatible = "renesas,r8a774b1-rst", .data = &rcar_rst_gen3 }, { .compatible = "renesas,r8a774c0-rst", .data = &rcar_rst_gen3 }, + { .compatible = "renesas,r8a774e1-rst", .data = &rcar_rst_gen3 }, /* R-Car Gen1 */ { .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 }, { .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 }, From patchwork Fri Aug 21 09:42:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729049 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EC2651575 for ; Fri, 21 Aug 2020 10:58:33 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5B88D2078D for ; Fri, 21 Aug 2020 10:58:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="ITQcp6mH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5B88D2078D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5177+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id 7qUGYY4521763xqWnvBEmU27; Fri, 21 Aug 2020 03:58:32 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web11.130425.1598002998984331784 for ; Fri, 21 Aug 2020 02:43:33 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="55170304" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:32 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 49DB2423206E; Fri, 21 Aug 2020 18:43:31 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 09/36] clk: renesas: rcar-gen3: Add RPC clocks Date: Fri, 21 Aug 2020 10:42:45 +0100 Message-Id: <20200821094312.3249-10-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: 94e8IKaX33A2IgNRC3BQA9Odx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007512; bh=wFdXEXiz36vj/rrwWyXZikxcDiWtfN0WJ7bFxbymPpU=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=ITQcp6mHmoZioBv+dQy2Mmebv7jZrxWvy0A0t+wC1C4e53/ilPw4D3dSKkCGtn1GzD9 Tx06sTKM3RkldfH9CoixNKBWpUvvuJKx6jFL1O6zh4lFCumC866HbXAbL7AUQAs2M78wb /rxhfKVvL6R6TGcDqXkikZnzIN9xlL9wuj4= From: Sergei Shtylyov commit db4a0073cc82a95d8d1a9b05fde82355fcce77d8 upstream. The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field is different between SoCs; it makes sense to support the most common case of this encoding in the R-Car gen3 CPG driver... After adding the RPCSRC clock, we can add the RPC[D2] clocks derived from it and controlled by the RPCCKCR register on all the R-Car gen3 SoCs except V3M (R8A77970); the composite clock driver seems handy for this task, using the spinlock added in the previous patch... Signed-off-by: Sergei Shtylyov Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/clk/renesas/rcar-gen3-cpg.c | 101 ++++++++++++++++++++++++++++ drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++ 2 files changed, 105 insertions(+) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 0b96b4bc3997..e8fc3b8a875a 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -424,6 +424,92 @@ static struct clk * __init cpg_sd_clk_register(const char *name, return clk; } +struct rpc_clock { + struct clk_divider div; + struct clk_gate gate; + /* + * One notifier covers both RPC and RPCD2 clocks as they are both + * controlled by the same RPCCKCR register... + */ + struct cpg_simple_notifier csn; +}; + +static const struct clk_div_table cpg_rpcsrc_div_table[] = { + { 2, 5 }, { 3, 6 }, { 0, 0 }, +}; + +static const struct clk_div_table cpg_rpc_div_table[] = { + { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 }, +}; + +static struct clk * __init cpg_rpc_clk_register(const char *name, + void __iomem *base, const char *parent_name, + struct raw_notifier_head *notifiers) +{ + struct rpc_clock *rpc; + struct clk *clk; + + rpc = kzalloc(sizeof(*rpc), GFP_KERNEL); + if (!rpc) + return ERR_PTR(-ENOMEM); + + rpc->div.reg = base + CPG_RPCCKCR; + rpc->div.width = 3; + rpc->div.table = cpg_rpc_div_table; + rpc->div.lock = &cpg_lock; + + rpc->gate.reg = base + CPG_RPCCKCR; + rpc->gate.bit_idx = 8; + rpc->gate.flags = CLK_GATE_SET_TO_DISABLE; + rpc->gate.lock = &cpg_lock; + + rpc->csn.reg = base + CPG_RPCCKCR; + + clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, + &rpc->div.hw, &clk_divider_ops, + &rpc->gate.hw, &clk_gate_ops, 0); + if (IS_ERR(clk)) { + kfree(rpc); + return clk; + } + + cpg_simple_notifier_register(notifiers, &rpc->csn); + return clk; +} + +struct rpcd2_clock { + struct clk_fixed_factor fixed; + struct clk_gate gate; +}; + +static struct clk * __init cpg_rpcd2_clk_register(const char *name, + void __iomem *base, + const char *parent_name) +{ + struct rpcd2_clock *rpcd2; + struct clk *clk; + + rpcd2 = kzalloc(sizeof(*rpcd2), GFP_KERNEL); + if (!rpcd2) + return ERR_PTR(-ENOMEM); + + rpcd2->fixed.mult = 1; + rpcd2->fixed.div = 2; + + rpcd2->gate.reg = base + CPG_RPCCKCR; + rpcd2->gate.bit_idx = 9; + rpcd2->gate.flags = CLK_GATE_SET_TO_DISABLE; + rpcd2->gate.lock = &cpg_lock; + + clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, + &rpcd2->fixed.hw, &clk_fixed_factor_ops, + &rpcd2->gate.hw, &clk_gate_ops, 0); + if (IS_ERR(clk)) + kfree(rpcd2); + + return clk; +} + static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; static unsigned int cpg_clk_extalr __initdata; @@ -598,6 +684,21 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, } break; + case CLK_TYPE_GEN3_RPCSRC: + return clk_register_divider_table(NULL, core->name, + __clk_get_name(parent), 0, + base + CPG_RPCCKCR, 3, 2, 0, + cpg_rpcsrc_div_table, + &cpg_lock); + + case CLK_TYPE_GEN3_RPC: + return cpg_rpc_clk_register(core->name, base, + __clk_get_name(parent), notifiers); + + case CLK_TYPE_GEN3_RPCD2: + return cpg_rpcd2_clk_register(core->name, base, + __clk_get_name(parent)); + default: return ERR_PTR(-EINVAL); } diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 131ede2fd8ca..2b39499c855c 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -25,6 +25,9 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_Z, CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ + CLK_TYPE_GEN3_RPCSRC, + CLK_TYPE_GEN3_RPC, + CLK_TYPE_GEN3_RPCD2, }; #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ @@ -59,6 +62,7 @@ struct rcar_gen3_cpg_pll_config { u8 osc_prediv; }; +#define CPG_RPCCKCR 0x238 #define CPG_RCKCR 0x240 struct clk *rcar_gen3_cpg_clk_register(struct device *dev, From patchwork Fri Aug 21 09:42:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729077 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 278791575 for ; Fri, 21 Aug 2020 10:58:36 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0207D20656 for ; Fri, 21 Aug 2020 10:58:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="bXYdTq1X" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0207D20656 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5190+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id dCY3YY4521763xrkQMct1vfN; Fri, 21 Aug 2020 03:58:35 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web11.130425.1598002998984331784 for ; Fri, 21 Aug 2020 02:43:34 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="55170311" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:34 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1A5034231AD9; Fri, 21 Aug 2020 18:43:32 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 10/36] clk: renesas: Add r8a774e1 CPG Core Clock Definitions Date: Fri, 21 Aug 2020 10:42:46 +0100 Message-Id: <20200821094312.3249-11-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: K4micThBdogB8iUsNTeIpugDx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007515; bh=JyN4oCTyfTNNkXIlnGEc97cFKno7GV+B2Jt3rZ08FWQ=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=bXYdTq1Xu33lt8KYYsLJoovjdRQ0REAi2StjPG21wLH5IZD/j217HwGLNjZHVi2a5LC 8kjCSnScqSMgsUz+kMr5m4uMqDAdY7SsvGm/760uzOxEol9gau6BUH07U0lZP0B9fSf93 L4sToGsUcsUwgsWBSEHJAS5vcx4kg0mtXwU= From: Marian-Cristian Rotariu commit ef1c9924287d11660cfc7900aeeeb4732188743e upstream. Add all RZ/G2H Clock Pulse Generator Core Clock Outputs, as listed in Table 11.2 ("List of Clocks [RZ/G2H]") of the RZ/G2H Hardware User's Manual. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- include/dt-bindings/clock/r8a774e1-cpg-mssr.h | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 include/dt-bindings/clock/r8a774e1-cpg-mssr.h diff --git a/include/dt-bindings/clock/r8a774e1-cpg-mssr.h b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h new file mode 100644 index 000000000000..b2fc1d1c3c47 --- /dev/null +++ b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ + +#include + +/* R8A774E1 CPG Core Clocks */ +#define R8A774E1_CLK_Z 0 +#define R8A774E1_CLK_Z2 1 +#define R8A774E1_CLK_ZG 2 +#define R8A774E1_CLK_ZTR 3 +#define R8A774E1_CLK_ZTRD2 4 +#define R8A774E1_CLK_ZT 5 +#define R8A774E1_CLK_ZX 6 +#define R8A774E1_CLK_S0D1 7 +#define R8A774E1_CLK_S0D2 8 +#define R8A774E1_CLK_S0D3 9 +#define R8A774E1_CLK_S0D4 10 +#define R8A774E1_CLK_S0D6 11 +#define R8A774E1_CLK_S0D8 12 +#define R8A774E1_CLK_S0D12 13 +#define R8A774E1_CLK_S1D2 14 +#define R8A774E1_CLK_S1D4 15 +#define R8A774E1_CLK_S2D1 16 +#define R8A774E1_CLK_S2D2 17 +#define R8A774E1_CLK_S2D4 18 +#define R8A774E1_CLK_S3D1 19 +#define R8A774E1_CLK_S3D2 20 +#define R8A774E1_CLK_S3D4 21 +#define R8A774E1_CLK_LB 22 +#define R8A774E1_CLK_CL 23 +#define R8A774E1_CLK_ZB3 24 +#define R8A774E1_CLK_ZB3D2 25 +#define R8A774E1_CLK_ZB3D4 26 +#define R8A774E1_CLK_CR 27 +#define R8A774E1_CLK_CRD2 28 +#define R8A774E1_CLK_SD0H 29 +#define R8A774E1_CLK_SD0 30 +#define R8A774E1_CLK_SD1H 31 +#define R8A774E1_CLK_SD1 32 +#define R8A774E1_CLK_SD2H 33 +#define R8A774E1_CLK_SD2 34 +#define R8A774E1_CLK_SD3H 35 +#define R8A774E1_CLK_SD3 36 +#define R8A774E1_CLK_RPC 37 +#define R8A774E1_CLK_RPCD2 38 +#define R8A774E1_CLK_MSO 39 +#define R8A774E1_CLK_HDMI 40 +#define R8A774E1_CLK_CSI0 41 +#define R8A774E1_CLK_CP 42 +#define R8A774E1_CLK_CPEX 43 +#define R8A774E1_CLK_R 44 +#define R8A774E1_CLK_OSC 45 +#define R8A774E1_CLK_CANFD 46 + +#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */ From patchwork Fri Aug 21 09:42:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729063 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE8681575 for ; Fri, 21 Aug 2020 10:58:34 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B8BE62072D for ; Fri, 21 Aug 2020 10:58:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="U5SyYSGT" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B8BE62072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5178+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id BVjvYY4521763x6Q4iKql0dF; Fri, 21 Aug 2020 03:58:34 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.131152.1598003016916343991 for ; Fri, 21 Aug 2020 02:43:37 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954561" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:36 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id E70344232061; Fri, 21 Aug 2020 18:43:34 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 11/36] clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks Date: Fri, 21 Aug 2020 10:42:47 +0100 Message-Id: <20200821094312.3249-12-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: Ee1G06PwBDgb8IBDclPK97IDx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007514; bh=57miL7FXinTLePJUS8Td2n13RCSZ2sGbpVkHFbVGZWY=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=U5SyYSGT+clbhbPRBu32Y73H7ByowCEJUQKylAzuyffM0z3wGiOIRmtLlgZNJ3Wndm8 8qkyfYRzczSUAULEpKhtwAckVKHTP0t8vohEJaOf2Nc6VxfscIa7zR06Lk77Y/EMheeWX XsnHFE+S2igpZ/VBHEuel6WXCVc35bdit7Q= From: Sergei Shtylyov commit 0d67c0340a60829c5c1b7d09629d23bbd67696f3 upstream. I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to clk_register_composite() when registering the RPC[D2] clocks... Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks") Signed-off-by: Sergei Shtylyov Link: https://lore.kernel.org/r/be27a344-d8bf-9e0c-8950-2d1b48498496@cogentembedded.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/clk/renesas/rcar-gen3-cpg.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index e8fc3b8a875a..6230a7c40244 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -467,7 +467,8 @@ static struct clk * __init cpg_rpc_clk_register(const char *name, clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, &rpc->div.hw, &clk_divider_ops, - &rpc->gate.hw, &clk_gate_ops, 0); + &rpc->gate.hw, &clk_gate_ops, + CLK_SET_RATE_PARENT); if (IS_ERR(clk)) { kfree(rpc); return clk; @@ -503,7 +504,8 @@ static struct clk * __init cpg_rpcd2_clk_register(const char *name, clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, &rpcd2->fixed.hw, &clk_fixed_factor_ops, - &rpcd2->gate.hw, &clk_gate_ops, 0); + &rpcd2->gate.hw, &clk_gate_ops, + CLK_SET_RATE_PARENT); if (IS_ERR(clk)) kfree(rpcd2); From patchwork Fri Aug 21 09:42:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729067 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 581BB175D for ; Fri, 21 Aug 2020 10:58:35 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3228F2078D for ; Fri, 21 Aug 2020 10:58:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="eI/2GUfv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3228F2078D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5187+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id PeEmYY4521763xCHieWhUYQr; Fri, 21 Aug 2020 03:58:34 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.131152.1598003016916343991 for ; Fri, 21 Aug 2020 02:43:38 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954565" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:38 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id C084A4231AD9; Fri, 21 Aug 2020 18:43:36 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 12/36] clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot Date: Fri, 21 Aug 2020 10:42:48 +0100 Message-Id: <20200821094312.3249-13-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: H2Fcwnh8IMq5wAZhybyyTOuux4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007514; bh=gtO09si3k7mDAB74vrpNwbzbwoYT+0B6k2LQaHjellc=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=eI/2GUfv6c/DzWRDVN5QCv6juDPX1fLTNpAcBhIPCGARZJw15ARpnJT5lk/zWbhvsFb KBntMaHEMGeHw0chNTeMu7sE6/MGQ+2YZrd+SGUJEc8uG3LNMdH5czRkBP9Nmm8XLaghL QqCuEv+TzauxO11EQ2OZmK5SSXAsIaIos6k= From: Ulrich Hecht commit ed4a11807d2a35ccfc0d00371f20b826f670b5f2 upstream. This allows us to add the RWDT clock to the list of critical clocks without keeping it enabled needlessly if not used. Changing the semantics of crit_mod_clks in this way is safe for the current user (INTC-AP) because it is never off at boot time. Signed-off-by: Ulrich Hecht Link: https://lore.kernel.org/r/20200616162626.27944-2-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/clk/renesas/renesas-cpg-mssr.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index f59700e38ba9..1e2a55385859 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -378,14 +378,6 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, init.name = mod->name; init.ops = &cpg_mstp_clock_ops; init.flags = CLK_SET_RATE_PARENT; - for (i = 0; i < info->num_crit_mod_clks; i++) - if (id == info->crit_mod_clks[i]) { - dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", - mod->name); - init.flags |= CLK_IS_CRITICAL; - break; - } - parent_name = __clk_get_name(parent); init.parent_names = &parent_name; init.num_parents = 1; @@ -394,6 +386,15 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, clock->priv = priv; clock->hw.init = &init; + for (i = 0; i < info->num_crit_mod_clks; i++) + if (id == info->crit_mod_clks[i] && + cpg_mstp_clock_is_enabled(&clock->hw)) { + dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", + mod->name); + init.flags |= CLK_IS_CRITICAL; + break; + } + clk = clk_register(NULL, &clock->hw); if (IS_ERR(clk)) goto fail; From patchwork Fri Aug 21 09:42:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729061 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D4F39722 for ; Fri, 21 Aug 2020 10:58:34 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AFB2E20656 for ; Fri, 21 Aug 2020 10:58:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="HB6WJkVx" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AFB2E20656 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5185+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id rglmYY4521763xLVVFAru1lf; Fri, 21 Aug 2020 03:58:34 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.131152.1598003016916343991 for ; Fri, 21 Aug 2020 02:43:40 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954570" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:40 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 965B94231AD9; Fri, 21 Aug 2020 18:43:38 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 13/36] clk: renesas: rzg2: Mark RWDT clocks as critical Date: Fri, 21 Aug 2020 10:42:49 +0100 Message-Id: <20200821094312.3249-14-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: xOROMwYsb7cn7QHsv7PpaGb1x4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007514; bh=ATnp/sk4xD8GmLPwW52SJPPFgCs+af2rcja8W3F8KaM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=HB6WJkVxeVcMEvo2371A1hD/KBVWdNsI5+P8e0T8tz4ZuiRrDyG2ialhBt9wvIDB2cs T20n1m7lGaIQZJ3hvAuABN8xJx8HAZt/Ec8tZtJji/jlXn1nqG0xSblECzCnd3tmOtboA fhkQXaVZmoKVxUeFxGvQ13siIcHzeaDZN+s= From: Ulrich Hecht commit 52bc5ea6edde35bc65ed6ecd7639534e78002c74 upstream. Ensures RWDT remains alert throughout the boot process if enabled. This patch applies the change to the following SoCs: r8a774a1, r8a774b1 and r8a774c0. Signed-off-by: Ulrich Hecht Link: https://lore.kernel.org/r/20200616162626.27944-4-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/clk/renesas/r8a774a1-cpg-mssr.c | 1 + drivers/clk/renesas/r8a774b1-cpg-mssr.c | 1 + drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 + 3 files changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index e05bfa200480..fd54b9f625da 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -237,6 +237,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { }; static const unsigned int r8a774a1_crit_mod_clks[] __initconst = { + MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-AP (GIC) */ }; diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c index c9af70917312..f436691271ec 100644 --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c @@ -233,6 +233,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = { }; static const unsigned int r8a774b1_crit_mod_clks[] __initconst = { + MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-AP (GIC) */ }; diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index f91e7a484753..9fc9fa9e531a 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -238,6 +238,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { }; static const unsigned int r8a774c0_crit_mod_clks[] __initconst = { + MOD_CLK_ID(402), /* RWDT */ MOD_CLK_ID(408), /* INTC-AP (GIC) */ }; From patchwork Fri Aug 21 09:42:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729087 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2F641722 for ; Fri, 21 Aug 2020 10:58:37 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0B1302072D for ; Fri, 21 Aug 2020 10:58:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="axfbImqh" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0B1302072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5195+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id gxrNYY4521763xNUU0sGQoXl; Fri, 21 Aug 2020 03:58:36 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.131152.1598003016916343991 for ; Fri, 21 Aug 2020 02:43:42 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954575" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:41 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 61AFC423206F; Fri, 21 Aug 2020 18:43:40 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 14/36] dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1 Date: Fri, 21 Aug 2020 10:42:50 +0100 Message-Id: <20200821094312.3249-15-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: rL95ExPy6pz2hRu13HpNb9Jtx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007516; bh=4UcD67SqzHP0nX017z9x28PMdv2pL1ZRR9SviwJ1snE=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=axfbImqhGA6KBnYk6ubXXG8uH3fBr6pcRCmTh0hK7UHKvlPJZCsSURtKjG5vMh1+Qw0 I5ZRVmrdoGYX8gunOKHtF/CPaL+WgpSHBk0Zx/WWZyA31QJ5iCgeYYM5nIwpjC5SbnR7M TTlyzgbp+yvq5581WjdFiXr/xdq/VENaGI4= From: Marian-Cristian Rotariu commit 668a8187e8b7875d515eacab88cef7f97fb4a1b3 upstream. Add binding documentation for the RZ/G2H (R8A774E1) Clock Pulse Generator driver. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [biju: Patched text version of bindings file] Signed-off-by: Biju Das --- Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index 113d45be1e37..6b565779ded3 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt @@ -19,6 +19,7 @@ Required Properties: - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M) - "renesas,r8a774b1-cpg-mssr" for the r8a774a1 SoC (RZ/G2N) - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E) + - "renesas,r8a774e1-cpg-mssr" for the r8a774e1 SoC (RZ/G2H) - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2) - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W) - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H) From patchwork Fri Aug 21 09:42:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729055 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3FDFB109B for ; Fri, 21 Aug 2020 10:58:34 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1ABA12078D for ; Fri, 21 Aug 2020 10:58:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="Qcdyt48E" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1ABA12078D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5186+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id d0AdYY4521763xvZIoZKvtq4; Fri, 21 Aug 2020 03:58:33 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.131152.1598003016916343991 for ; Fri, 21 Aug 2020 02:43:44 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954579" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:43 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 2E4DB4231AD9; Fri, 21 Aug 2020 18:43:41 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 15/36] clk: renesas: cpg-mssr: Add r8a774e1 support Date: Fri, 21 Aug 2020 10:42:51 +0100 Message-Id: <20200821094312.3249-16-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: 7tbNHcBXuMKhijTKylT77pjmx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007513; bh=m+EGJ1xWjOhCt9JH7JY/cqAYJtwL2i4NuJIQ1k/Lf90=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Qcdyt48Eit5KgpKolWYE5bWmwTNqMZW9khkXD7kKhEQyinygBZDY5rgIrRJ8W+x19pq K0gmvDizo1IM1FcR7S8da1p2qx1mjb9Sd3ypa3J5pYkc574Fi4T5yW2dYUGgh0VrVZC50 zj9npHGNkluK5k5ibRnaV1Hv4e/eiNhJGkQ= From: Marian-Cristian Rotariu commit c8a53fa1d211936ddcabf82ff991c18672b3d63a upstream. Add support for the RZ/G2H (R8A774E1) SoC to the Renesas Clock Pulse Generator / Module Standby and Software Reset driver. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com [geert: Mark RWDT critical, cfr. commit f23f1101ad0ef1ac ("clk: renesas: rcar-gen3: Mark RWDT clocks as critical")] Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a774e1-cpg-mssr.c | 349 ++++++++++++++++++++++++ drivers/clk/renesas/renesas-cpg-mssr.c | 6 + drivers/clk/renesas/renesas-cpg-mssr.h | 1 + 5 files changed, 362 insertions(+) create mode 100644 drivers/clk/renesas/r8a774e1-cpg-mssr.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 1ea3b31ecea0..51500d153a9f 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -11,6 +11,7 @@ config CLK_RENESAS select CLK_R8A774A1 if ARCH_R8A774A1 select CLK_R8A774B1 if ARCH_R8A774B1 select CLK_R8A774C0 if ARCH_R8A774C0 + select CLK_R8A774E1 if ARCH_R8A774E1 select CLK_R8A7778 if ARCH_R8A7778 select CLK_R8A7779 if ARCH_R8A7779 select CLK_R8A7790 if ARCH_R8A7790 @@ -82,6 +83,10 @@ config CLK_R8A774C0 bool "RZ/G2E clock support" if COMPILE_TEST select CLK_RCAR_GEN3_CPG +config CLK_R8A774E1 + bool "RZ/G2H clock support" if COMPILE_TEST + select CLK_RCAR_GEN3_CPG + config CLK_R8A7778 bool "R-Car M1A clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 350016cda2c3..b30025b31b41 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o +obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c new file mode 100644 index 000000000000..b96c486abb44 --- /dev/null +++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * r8a774e1 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2020 Renesas Electronics Corp. + * + * Based on r8a7795-cpg-mssr.c + * + * Copyright (C) 2015 Glider bvba + */ + +#include +#include +#include +#include + +#include + +#include "renesas-cpg-mssr.h" +#include "rcar-gen3-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A774E1_CLK_CANFD, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL4, + CLK_PLL1_DIV2, + CLK_PLL1_DIV4, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + CLK_SDSRC, + CLK_RPCSRC, + CLK_RINT, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), + DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), + DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), + DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), + + DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A774E1_CLK_RPC), + + DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), + + /* Core Clock Outputs */ + DEF_GEN3_Z("z", R8A774E1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("z2", R8A774E1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), + DEF_FIXED("ztr", R8A774E1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED("ztrd2", R8A774E1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), + DEF_FIXED("zt", R8A774E1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED("zx", R8A774E1_CLK_ZX, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED("s0d1", R8A774E1_CLK_S0D1, CLK_S0, 1, 1), + DEF_FIXED("s0d2", R8A774E1_CLK_S0D2, CLK_S0, 2, 1), + DEF_FIXED("s0d3", R8A774E1_CLK_S0D3, CLK_S0, 3, 1), + DEF_FIXED("s0d4", R8A774E1_CLK_S0D4, CLK_S0, 4, 1), + DEF_FIXED("s0d6", R8A774E1_CLK_S0D6, CLK_S0, 6, 1), + DEF_FIXED("s0d8", R8A774E1_CLK_S0D8, CLK_S0, 8, 1), + DEF_FIXED("s0d12", R8A774E1_CLK_S0D12, CLK_S0, 12, 1), + DEF_FIXED("s1d2", R8A774E1_CLK_S1D2, CLK_S1, 2, 1), + DEF_FIXED("s1d4", R8A774E1_CLK_S1D4, CLK_S1, 4, 1), + DEF_FIXED("s2d1", R8A774E1_CLK_S2D1, CLK_S2, 1, 1), + DEF_FIXED("s2d2", R8A774E1_CLK_S2D2, CLK_S2, 2, 1), + DEF_FIXED("s2d4", R8A774E1_CLK_S2D4, CLK_S2, 4, 1), + DEF_FIXED("s3d1", R8A774E1_CLK_S3D1, CLK_S3, 1, 1), + DEF_FIXED("s3d2", R8A774E1_CLK_S3D2, CLK_S3, 2, 1), + DEF_FIXED("s3d4", R8A774E1_CLK_S3D4, CLK_S3, 4, 1), + + DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, CLK_SDSRC, 0x074), + DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, CLK_SDSRC, 0x078), + DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, CLK_SDSRC, 0x268), + DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, CLK_SDSRC, 0x26c), + + DEF_FIXED("cl", R8A774E1_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cr", R8A774E1_CLK_CR, CLK_PLL1_DIV4, 2, 1), + DEF_FIXED("cp", R8A774E1_CLK_CP, CLK_EXTAL, 2, 1), + DEF_FIXED("cpex", R8A774E1_CLK_CPEX, CLK_EXTAL, 2, 1), + + DEF_DIV6P1("canfd", R8A774E1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), + DEF_DIV6P1("csi0", R8A774E1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), + DEF_DIV6P1("mso", R8A774E1_CLK_MSO, CLK_PLL1_DIV4, 0x014), + DEF_DIV6P1("hdmi", R8A774E1_CLK_HDMI, CLK_PLL1_DIV4, 0x250), + + DEF_GEN3_OSC("osc", R8A774E1_CLK_OSC, CLK_EXTAL, 8), + + DEF_BASE("r", R8A774E1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), +}; + +static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = { + DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1), + DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1), + DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6), + DEF_MOD("tmu3", 122, R8A774E1_CLK_S3D2), + DEF_MOD("tmu2", 123, R8A774E1_CLK_S3D2), + DEF_MOD("tmu1", 124, R8A774E1_CLK_S3D2), + DEF_MOD("tmu0", 125, R8A774E1_CLK_CP), + DEF_MOD("vcplf", 130, R8A774E1_CLK_S2D1), + DEF_MOD("vdpb", 131, R8A774E1_CLK_S2D1), + DEF_MOD("scif5", 202, R8A774E1_CLK_S3D4), + DEF_MOD("scif4", 203, R8A774E1_CLK_S3D4), + DEF_MOD("scif3", 204, R8A774E1_CLK_S3D4), + DEF_MOD("scif1", 206, R8A774E1_CLK_S3D4), + DEF_MOD("scif0", 207, R8A774E1_CLK_S3D4), + DEF_MOD("msiof3", 208, R8A774E1_CLK_MSO), + DEF_MOD("msiof2", 209, R8A774E1_CLK_MSO), + DEF_MOD("msiof1", 210, R8A774E1_CLK_MSO), + DEF_MOD("msiof0", 211, R8A774E1_CLK_MSO), + DEF_MOD("sys-dmac2", 217, R8A774E1_CLK_S3D1), + DEF_MOD("sys-dmac1", 218, R8A774E1_CLK_S3D1), + DEF_MOD("sys-dmac0", 219, R8A774E1_CLK_S0D3), + DEF_MOD("cmt3", 300, R8A774E1_CLK_R), + DEF_MOD("cmt2", 301, R8A774E1_CLK_R), + DEF_MOD("cmt1", 302, R8A774E1_CLK_R), + DEF_MOD("cmt0", 303, R8A774E1_CLK_R), + DEF_MOD("tpu0", 304, R8A774E1_CLK_S3D4), + DEF_MOD("scif2", 310, R8A774E1_CLK_S3D4), + DEF_MOD("sdif3", 311, R8A774E1_CLK_SD3), + DEF_MOD("sdif2", 312, R8A774E1_CLK_SD2), + DEF_MOD("sdif1", 313, R8A774E1_CLK_SD1), + DEF_MOD("sdif0", 314, R8A774E1_CLK_SD0), + DEF_MOD("pcie1", 318, R8A774E1_CLK_S3D1), + DEF_MOD("pcie0", 319, R8A774E1_CLK_S3D1), + DEF_MOD("usb3-if0", 328, R8A774E1_CLK_S3D1), + DEF_MOD("usb-dmac0", 330, R8A774E1_CLK_S3D1), + DEF_MOD("usb-dmac1", 331, R8A774E1_CLK_S3D1), + DEF_MOD("rwdt", 402, R8A774E1_CLK_R), + DEF_MOD("intc-ex", 407, R8A774E1_CLK_CP), + DEF_MOD("intc-ap", 408, R8A774E1_CLK_S0D3), + DEF_MOD("audmac1", 501, R8A774E1_CLK_S1D2), + DEF_MOD("audmac0", 502, R8A774E1_CLK_S1D2), + DEF_MOD("hscif4", 516, R8A774E1_CLK_S3D1), + DEF_MOD("hscif3", 517, R8A774E1_CLK_S3D1), + DEF_MOD("hscif2", 518, R8A774E1_CLK_S3D1), + DEF_MOD("hscif1", 519, R8A774E1_CLK_S3D1), + DEF_MOD("hscif0", 520, R8A774E1_CLK_S3D1), + DEF_MOD("thermal", 522, R8A774E1_CLK_CP), + DEF_MOD("pwm", 523, R8A774E1_CLK_S0D12), + DEF_MOD("fcpvd1", 602, R8A774E1_CLK_S0D2), + DEF_MOD("fcpvd0", 603, R8A774E1_CLK_S0D2), + DEF_MOD("fcpvb1", 606, R8A774E1_CLK_S0D1), + DEF_MOD("fcpvb0", 607, R8A774E1_CLK_S0D1), + DEF_MOD("fcpvi1", 610, R8A774E1_CLK_S0D1), + DEF_MOD("fcpvi0", 611, R8A774E1_CLK_S0D1), + DEF_MOD("fcpf1", 614, R8A774E1_CLK_S0D1), + DEF_MOD("fcpf0", 615, R8A774E1_CLK_S0D1), + DEF_MOD("fcpcs", 619, R8A774E1_CLK_S0D1), + DEF_MOD("vspd1", 622, R8A774E1_CLK_S0D2), + DEF_MOD("vspd0", 623, R8A774E1_CLK_S0D2), + DEF_MOD("vspbc", 624, R8A774E1_CLK_S0D1), + DEF_MOD("vspbd", 626, R8A774E1_CLK_S0D1), + DEF_MOD("vspi1", 630, R8A774E1_CLK_S0D1), + DEF_MOD("vspi0", 631, R8A774E1_CLK_S0D1), + DEF_MOD("ehci1", 702, R8A774E1_CLK_S3D2), + DEF_MOD("ehci0", 703, R8A774E1_CLK_S3D2), + DEF_MOD("hsusb", 704, R8A774E1_CLK_S3D2), + DEF_MOD("csi20", 714, R8A774E1_CLK_CSI0), + DEF_MOD("csi40", 716, R8A774E1_CLK_CSI0), + DEF_MOD("du3", 721, R8A774E1_CLK_S2D1), + DEF_MOD("du1", 723, R8A774E1_CLK_S2D1), + DEF_MOD("du0", 724, R8A774E1_CLK_S2D1), + DEF_MOD("lvds", 727, R8A774E1_CLK_S0D4), + DEF_MOD("hdmi0", 729, R8A774E1_CLK_HDMI), + DEF_MOD("vin7", 804, R8A774E1_CLK_S0D2), + DEF_MOD("vin6", 805, R8A774E1_CLK_S0D2), + DEF_MOD("vin5", 806, R8A774E1_CLK_S0D2), + DEF_MOD("vin4", 807, R8A774E1_CLK_S0D2), + DEF_MOD("vin3", 808, R8A774E1_CLK_S0D2), + DEF_MOD("vin2", 809, R8A774E1_CLK_S0D2), + DEF_MOD("vin1", 810, R8A774E1_CLK_S0D2), + DEF_MOD("vin0", 811, R8A774E1_CLK_S0D2), + DEF_MOD("etheravb", 812, R8A774E1_CLK_S0D6), + DEF_MOD("sata0", 815, R8A774E1_CLK_S3D2), + DEF_MOD("gpio7", 905, R8A774E1_CLK_S3D4), + DEF_MOD("gpio6", 906, R8A774E1_CLK_S3D4), + DEF_MOD("gpio5", 907, R8A774E1_CLK_S3D4), + DEF_MOD("gpio4", 908, R8A774E1_CLK_S3D4), + DEF_MOD("gpio3", 909, R8A774E1_CLK_S3D4), + DEF_MOD("gpio2", 910, R8A774E1_CLK_S3D4), + DEF_MOD("gpio1", 911, R8A774E1_CLK_S3D4), + DEF_MOD("gpio0", 912, R8A774E1_CLK_S3D4), + DEF_MOD("can-fd", 914, R8A774E1_CLK_S3D2), + DEF_MOD("can-if1", 915, R8A774E1_CLK_S3D4), + DEF_MOD("can-if0", 916, R8A774E1_CLK_S3D4), + DEF_MOD("rpc-if", 917, R8A774E1_CLK_RPCD2), + DEF_MOD("i2c6", 918, R8A774E1_CLK_S0D6), + DEF_MOD("i2c5", 919, R8A774E1_CLK_S0D6), + DEF_MOD("adg", 922, R8A774E1_CLK_S0D1), + DEF_MOD("i2c-dvfs", 926, R8A774E1_CLK_CP), + DEF_MOD("i2c4", 927, R8A774E1_CLK_S0D6), + DEF_MOD("i2c3", 928, R8A774E1_CLK_S0D6), + DEF_MOD("i2c2", 929, R8A774E1_CLK_S3D2), + DEF_MOD("i2c1", 930, R8A774E1_CLK_S3D2), + DEF_MOD("i2c0", 931, R8A774E1_CLK_S3D2), + DEF_MOD("ssi-all", 1005, R8A774E1_CLK_S3D4), + DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), + DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), + DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), + DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), + DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), + DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), + DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), + DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), + DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), + DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), + DEF_MOD("scu-all", 1017, R8A774E1_CLK_S3D4), + DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), + DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), + DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), + DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), + DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), + DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), + DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), + DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), + DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), + DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), + DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), + DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), +}; + +static const unsigned int r8a774e1_crit_mod_clks[] __initconst = { + MOD_CLK_ID(402), /* RWDT */ + MOD_CLK_ID(408), /* INTC-AP (GIC) */ +}; + +/* + * CPG Clock Data + */ + +/* + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC + * 14 13 19 17 (MHz) + *------------------------------------------------------------------------- + * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16 + * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16 + * 0 0 1 0 Prohibited setting + * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16 + * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19 + * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19 + * 0 1 1 0 Prohibited setting + * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19 + * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24 + * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24 + * 1 0 1 0 Prohibited setting + * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24 + * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32 + * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32 + * 1 1 1 0 Prohibited setting + * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ + (((md) & BIT(13)) >> 11) | \ + (((md) & BIT(19)) >> 18) | \ + (((md) & BIT(17)) >> 17)) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { + /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ + { 1, 192, 1, 192, 1, 16, }, + { 1, 192, 1, 128, 1, 16, }, + { 0, /* Prohibited setting */ }, + { 1, 192, 1, 192, 1, 16, }, + { 1, 160, 1, 160, 1, 19, }, + { 1, 160, 1, 106, 1, 19, }, + { 0, /* Prohibited setting */ }, + { 1, 160, 1, 160, 1, 19, }, + { 1, 128, 1, 128, 1, 24, }, + { 1, 128, 1, 84, 1, 24, }, + { 0, /* Prohibited setting */ }, + { 1, 128, 1, 128, 1, 24, }, + { 2, 192, 1, 192, 1, 32, }, + { 2, 192, 1, 128, 1, 32, }, + { 0, /* Prohibited setting */ }, + { 2, 192, 1, 192, 1, 32, }, +}; + +static int __init r8a774e1_cpg_mssr_init(struct device *dev) +{ + const struct rcar_gen3_cpg_pll_config *cpg_pll_config; + u32 cpg_mode; + int error; + + error = rcar_rst_read_mode_pins(&cpg_mode); + if (error) + return error; + + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + if (!cpg_pll_config->extal_div) { + dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); + return -EINVAL; + } + + return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); +} + +const struct cpg_mssr_info r8a774e1_cpg_mssr_info __initconst = { + /* Core Clocks */ + .core_clks = r8a774e1_core_clks, + .num_core_clks = ARRAY_SIZE(r8a774e1_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r8a774e1_mod_clks, + .num_mod_clks = ARRAY_SIZE(r8a774e1_mod_clks), + .num_hw_mod_clks = 12 * 32, + + /* Critical Module Clocks */ + .crit_mod_clks = r8a774e1_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r8a774e1_crit_mod_clks), + + /* Callbacks */ + .init = r8a774e1_cpg_mssr_init, + .cpg_clk_register = rcar_gen3_cpg_clk_register, +}; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 1e2a55385859..fd8c748679fd 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -666,6 +666,12 @@ static const struct of_device_id cpg_mssr_match[] = { .data = &r8a774c0_cpg_mssr_info, }, #endif +#ifdef CONFIG_CLK_R8A774E1 + { + .compatible = "renesas,r8a774e1-cpg-mssr", + .data = &r8a774e1_cpg_mssr_info, + }, +#endif #ifdef CONFIG_CLK_R8A7790 { .compatible = "renesas,r8a7790-cpg-mssr", diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index dde7cf7c7404..c25c27c31f47 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -140,6 +140,7 @@ extern const struct cpg_mssr_info r8a77470_cpg_mssr_info; extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info; extern const struct cpg_mssr_info r8a774b1_cpg_mssr_info; extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info; +extern const struct cpg_mssr_info r8a774e1_cpg_mssr_info; extern const struct cpg_mssr_info r8a7790_cpg_mssr_info; extern const struct cpg_mssr_info r8a7791_cpg_mssr_info; extern const struct cpg_mssr_info r8a7792_cpg_mssr_info; From patchwork Fri Aug 21 09:42:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729079 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 46039175D for ; Fri, 21 Aug 2020 10:58:36 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 215D12072D for ; Fri, 21 Aug 2020 10:58:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="PCKbLrkW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 215D12072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5191+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id 6TJDYY4521763xYxGvegdiJB; Fri, 21 Aug 2020 03:58:35 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.131155.1598003026037330255 for ; Fri, 21 Aug 2020 02:43:46 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="55170326" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:45 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 1B5AF4232061; Fri, 21 Aug 2020 18:43:43 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 16/36] arm64: defconfig: Enable R8A774E1 SoC Date: Fri, 21 Aug 2020 10:42:52 +0100 Message-Id: <20200821094312.3249-17-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: kOsWD1cFwehvJgwtNnYkHKSjx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007515; bh=mSaYx5g0f1UbD7fsw8ZhL+c8K78gLTGpwxkaOlWsmE4=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=PCKbLrkWg8PXyVM3Punth26i0sEPtKzRlLNd+iR9jGc9XWzQSJXYO3b9hq5bfAmplou 0favuW1bxgMjbyfMYHmsbypTuy/l2b3TgfwysXj+yF2bo+4F4cofSG9JZvMzbOuGJRbjf k2cFUdvoYYalD0v8xueFxNohUW53aO/rF7Q= From: Marian-Cristian Rotariu commit 7f8fe81eb75004dca73aa19127093977a3c8a154 upstream. Enable the Renesas RZ/G2H (R8A774E1) SoC in the ARM64 defconfig. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594230511-24790-6-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 64a116b1e98d..ef20c1f308fa 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -53,6 +53,7 @@ CONFIG_ARCH_RENESAS=y CONFIG_ARCH_R8A774A1=y CONFIG_ARCH_R8A774B1=y CONFIG_ARCH_R8A774C0=y +CONFIG_ARCH_R8A774E1=y CONFIG_ARCH_R8A7795=y CONFIG_ARCH_R8A7796=y CONFIG_ARCH_R8A77965=y From patchwork Fri Aug 21 09:42:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729081 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7086C722 for ; Fri, 21 Aug 2020 10:58:36 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4A2CA20656 for ; Fri, 21 Aug 2020 10:58:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="iMvFMLwY" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4A2CA20656 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5192+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id c1JCYY4521763xma15ejYwMm; Fri, 21 Aug 2020 03:58:36 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.131152.1598003016916343991 for ; Fri, 21 Aug 2020 02:43:49 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954588" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:49 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id B6C324232061; Fri, 21 Aug 2020 18:43:47 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 18/36] pinctrl: sh-pfc: r8a7795: Fix VIN versioned groups Date: Fri, 21 Aug 2020 10:42:54 +0100 Message-Id: <20200821094312.3249-19-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: 4znXLW43eRT2TzHtHNWMaE7Ex4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007516; bh=9yJ2JoXM3ejAqTziBKUwjRrVm4NAVsyNgNpn5FEP6Kk=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=iMvFMLwYizbROLwJpO4NjaQG7RVZQDom8GniYNRY2c0l4yVF1ndu8vFez+WbJaYv1d9 dytt9etvybXubrzQh1MH5DlGbayZULfBwEUMTSrF7W4K90B8X7S/rQHQ9bwCLKNAVsIEV f0kz92brWdRlOAAULBna9Z0UOUbMYscApP8= From: Jacopo Mondi commit 184844ccda4138402846bf4b42c28ac5f16a458a upstream. Versioned VIN groups can appear on different sets of pins. Using the VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through an optional 'version' argument. Use the 'version' argument for said macro to fix naming of versioned groups for the R-Car H3 R8A7795 SoC. Fixes: 9942a5b52990 ("pinctrl: sh-pfc: r8a7795: Deduplicate VIN4 pin definitions") Signed-off-by: Jacopo Mondi Reviewed-by: Simon Horman Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 68c55ec618e2..1b497c87a0a4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -4456,20 +4456,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(usb2), SH_PFC_PIN_GROUP(usb2_ch3), SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data_a, 8), - VIN_DATA_PIN_GROUP(vin4_data_a, 10), - VIN_DATA_PIN_GROUP(vin4_data_a, 12), - VIN_DATA_PIN_GROUP(vin4_data_a, 16), + VIN_DATA_PIN_GROUP(vin4_data, 8, _a), + VIN_DATA_PIN_GROUP(vin4_data, 10, _a), + VIN_DATA_PIN_GROUP(vin4_data, 12, _a), + VIN_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data_a, 20), - VIN_DATA_PIN_GROUP(vin4_data_a, 24), - VIN_DATA_PIN_GROUP(vin4_data_b, 8), - VIN_DATA_PIN_GROUP(vin4_data_b, 10), - VIN_DATA_PIN_GROUP(vin4_data_b, 12), - VIN_DATA_PIN_GROUP(vin4_data_b, 16), + VIN_DATA_PIN_GROUP(vin4_data, 20, _a), + VIN_DATA_PIN_GROUP(vin4_data, 24, _a), + VIN_DATA_PIN_GROUP(vin4_data, 8, _b), + VIN_DATA_PIN_GROUP(vin4_data, 10, _b), + VIN_DATA_PIN_GROUP(vin4_data, 12, _b), + VIN_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data_b, 20), - VIN_DATA_PIN_GROUP(vin4_data_b, 24), + VIN_DATA_PIN_GROUP(vin4_data, 20, _b), + VIN_DATA_PIN_GROUP(vin4_data, 24, _b), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), From patchwork Fri Aug 21 09:42:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729051 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 425BB17CF for ; Fri, 21 Aug 2020 10:58:34 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1B2A8207BB for ; Fri, 21 Aug 2020 10:58:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="v8EXARJm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1B2A8207BB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5183+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id 5S12YY4521763xIu8X33z897; Fri, 21 Aug 2020 03:58:33 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.131152.1598003016916343991 for ; Fri, 21 Aug 2020 02:43:51 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954593" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:50 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 84A70423206F; Fri, 21 Aug 2020 18:43:49 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 19/36] pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and functions Date: Fri, 21 Aug 2020 10:42:55 +0100 Message-Id: <20200821094312.3249-20-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: mM7ylEY63ss3rqqihU4AJdDjx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007513; bh=rboAimBKGBv9xFMe4UcuU0cGn+97QLiJ5R2n9oVLzVE=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=v8EXARJmNsLnjQpfrzsFF3vd735HlDh9QBAfJf3Ao8ewtQXpRED0rsvQgl9HyCUkyyP nEcbDT9jZEiovtSB6Knxsr4v/sQqK9i43IraJUy0Jkwd6MgrBW1AjKGNo0Ld7U7cyMbGo 1y+s/YtOqbV5hDZh5kgnD08zL6YtUUmpjQY= From: Takeshi Kihara commit e244ff6f913f6ce4c77a00647462bc34c4221f46 upstream. This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 ES1.x SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by: Takeshi Kihara Signed-off-by: Ulrich Hecht Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 97 ++++++++++++++++++------ 1 file changed, 75 insertions(+), 22 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c index d8404ca600f3..897b7923074f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c @@ -539,6 +539,9 @@ MOD_SEL0_2_1 MOD_SEL1_2 \ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) +#define PINMUX_PHYS \ + FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) + enum { PINMUX_RESERVED = 0, @@ -564,6 +567,7 @@ enum { PINMUX_IPSR PINMUX_MOD_SELS PINMUX_STATIC + PINMUX_PHYS PINMUX_MARK_END, #undef F_ #undef FM @@ -576,9 +580,6 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(AVS2), PINMUX_SINGLE(GP7_02), PINMUX_SINGLE(GP7_03), - PINMUX_SINGLE(I2C_SEL_0_1), - PINMUX_SINGLE(I2C_SEL_3_1), - PINMUX_SINGLE(I2C_SEL_5_1), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -610,13 +611,15 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), - PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), - PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_TANS_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), @@ -666,16 +669,18 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), - PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), - PINMUX_IPSR_GPSR(IP1_23_20, A21), - PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), + PINMUX_IPSR_MSEL(IP1_23_20, A21, I2C_SEL_3_0), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), - PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), - PINMUX_IPSR_GPSR(IP1_27_24, A20), - PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), + PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), PINMUX_IPSR_GPSR(IP1_31_28, A0), PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), @@ -1069,11 +1074,13 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP), PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1), - PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD), - PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP10_19_16, SD1_CD, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP10_19_16, SCL0, I2C_SEL_0_1), - PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP), - PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP10_23_20, SD1_WP, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP10_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP10_27_24, SCK0), PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1), @@ -2250,6 +2257,15 @@ static const unsigned int hscif4_data_b_mux[] = { }; /* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int i2c0_mux[] = { + SCL0_MARK, SDA0_MARK, +}; + static const unsigned int i2c1_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), @@ -2278,6 +2294,25 @@ static const unsigned int i2c2_b_pins[] = { static const unsigned int i2c2_b_mux[] = { SDA2_B_MARK, SCL2_B_MARK, }; + +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; + +static const unsigned int i2c3_mux[] = { + SCL3_MARK, SDA3_MARK, +}; + +static const unsigned int i2c5_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), +}; + +static const unsigned int i2c5_mux[] = { + SCL5_MARK, SDA5_MARK, +}; + static const unsigned int i2c6_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), @@ -3918,10 +3953,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hscif4_clk), SH_PFC_PIN_GROUP(hscif4_ctrl), SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c2_a), SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c5), SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), @@ -4283,6 +4321,10 @@ static const char * const hscif4_groups[] = { "hscif4_data_b", }; +static const char * const i2c0_groups[] = { + "i2c0", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -4293,6 +4335,14 @@ static const char * const i2c2_groups[] = { "i2c2_b", }; +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + static const char * const i2c6_groups[] = { "i2c6_a", "i2c6_b", @@ -4623,8 +4673,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(hscif2), SH_PFC_FUNCTION(hscif3), SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), From patchwork Fri Aug 21 09:42:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729101 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 66C88109B for ; Fri, 21 Aug 2020 10:58:43 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3FF5820656 for ; Fri, 21 Aug 2020 10:58:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="dc75X/4L" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3FF5820656 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5201+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id vVt6YY4521763xM42skg4npQ; Fri, 21 Aug 2020 03:58:43 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.131155.1598003026037330255 for ; Fri, 21 Aug 2020 02:43:53 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="55170343" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:52 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 5DE504232061; Fri, 21 Aug 2020 18:43:51 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 20/36] pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functions Date: Fri, 21 Aug 2020 10:42:56 +0100 Message-Id: <20200821094312.3249-21-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: d4wCtC4DoFDTZ7KHWpjyN6rEx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007523; bh=aRUZ/zt7mZ/6nFe+KvPkkUPjyJyVBEHXk4cXIIPk/DI=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=dc75X/4LjfOugUFqiolVVZYabrqQhKnM9JmZdAVz5jrMaiLQ3CuzB472bKnAku+whZb qVnr3YPOaQa/KtPo9twhjKzxSH9th+65syLOmU3JmFitZvKKIIi8XOLHgKql/iREfyAeq jU0V/Xpd9cSOF9vm/X6dQEldtJKa+aKWJAw= From: Takeshi Kihara commit 100431b61dc5a591913b16971af644d8bf622599 upstream. This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by: Takeshi Kihara Signed-off-by: Ulrich Hecht Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 95 ++++++++++++++++++++++------ 1 file changed, 74 insertions(+), 21 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 1b497c87a0a4..6f5bbdce8fb4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -552,6 +552,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) +#define PINMUX_PHYS \ + FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) + enum { PINMUX_RESERVED = 0, @@ -577,6 +580,7 @@ enum { PINMUX_IPSR PINMUX_MOD_SELS PINMUX_STATIC + PINMUX_PHYS PINMUX_MARK_END, #undef F_ #undef FM @@ -590,9 +594,6 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(CLKOUT), PINMUX_SINGLE(GP7_02), PINMUX_SINGLE(GP7_03), - PINMUX_SINGLE(I2C_SEL_0_1), - PINMUX_SINGLE(I2C_SEL_3_1), - PINMUX_SINGLE(I2C_SEL_5_1), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -616,14 +617,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), - PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), - PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0), + PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), - PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), @@ -676,14 +679,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), - PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), - PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), - PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), - PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), PINMUX_IPSR_GPSR(IP1_31_28, A0), PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), @@ -1115,11 +1120,13 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), - PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), - PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), - PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), - PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP11_27_24, SCK0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), @@ -2332,6 +2339,15 @@ static const unsigned int hscif4_data_b_mux[] = { }; /* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int i2c0_mux[] = { + SCL0_MARK, SDA0_MARK, +}; + static const unsigned int i2c1_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), @@ -2360,6 +2376,25 @@ static const unsigned int i2c2_b_pins[] = { static const unsigned int i2c2_b_mux[] = { SDA2_B_MARK, SCL2_B_MARK, }; + +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; + +static const unsigned int i2c3_mux[] = { + SCL3_MARK, SDA3_MARK, +}; + +static const unsigned int i2c5_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), +}; + +static const unsigned int i2c5_mux[] = { + SCL5_MARK, SDA5_MARK, +}; + static const unsigned int i2c6_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), @@ -4240,10 +4275,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hscif4_clk), SH_PFC_PIN_GROUP(hscif4_ctrl), SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c2_a), SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c5), SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), @@ -4636,6 +4674,10 @@ static const char * const hscif4_groups[] = { "hscif4_data_b", }; +static const char * const i2c0_groups[] = { + "i2c0", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -4646,6 +4688,14 @@ static const char * const i2c2_groups[] = { "i2c2_b", }; +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + static const char * const i2c6_groups[] = { "i2c6_a", "i2c6_b", @@ -5004,8 +5054,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(hscif2), SH_PFC_FUNCTION(hscif3), SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), From patchwork Fri Aug 21 09:42:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729123 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13193175D for ; Fri, 21 Aug 2020 10:58:47 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E0D4F20656 for ; Fri, 21 Aug 2020 10:58:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="RmWVa86H" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E0D4F20656 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5208+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id C8R1YY4521763xnKCv5ejAnZ; Fri, 21 Aug 2020 03:58:46 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.131152.1598003016916343991 for ; Fri, 21 Aug 2020 02:43:55 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954600" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:43:54 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 3E303423206F; Fri, 21 Aug 2020 18:43:53 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 21/36] pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions Date: Fri, 21 Aug 2020 10:42:57 +0100 Message-Id: <20200821094312.3249-22-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: qSnU6KVCxgAmspt8fsjjjHPzx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007526; bh=bUjT/uqmLaQYYBYljvJN0RlzYu+jao8zzmGbOcBC70w=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=RmWVa86HkbIa+r97EAB9eak8lm/xqJ9GZO6RHl3ILMKyMIaVeANk4UgIoB/dkj+PiFk 1FA0hXNA1Roea9zFn1tYBw0WceoUxIshZKoby2XU7+Ht5T3pA2Ym05tvh33Qv3ZZJFPZA 8wmLDiLl7iU6nFs/8wzp78bnEtXBPUbCQus= From: Geert Uytterhoeven commit 99fdb920f5534d1c2f4b30c12eca4224ea260198 upstream. Use union vin_data16 and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions for the VIN5 channel. This reduces kernel size by 240 bytes. Signed-off-by: Geert Uytterhoeven Reviewed-by: Jacopo Mondi Reviewed-by: Simon Horman Reviewed-by: Niklas Söderlund Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 90 ++++++++-------------------- 1 file changed, 26 insertions(+), 64 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 6f5bbdce8fb4..8edeb4d823f0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -4082,67 +4082,29 @@ static const unsigned int vin4_clk_mux[] = { }; /* - VIN5 ------------------------------------------------------------------- */ -static const unsigned int vin5_data8_pins[] = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), -}; -static const unsigned int vin5_data8_mux[] = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, -}; -static const unsigned int vin5_data10_pins[] = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), -}; -static const unsigned int vin5_data10_mux[] = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, - VI5_DATA8_MARK, VI5_DATA9_MARK, -}; -static const unsigned int vin5_data12_pins[] = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), -}; -static const unsigned int vin5_data12_mux[] = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, - VI5_DATA8_MARK, VI5_DATA9_MARK, - VI5_DATA10_MARK, VI5_DATA11_MARK, -}; -static const unsigned int vin5_data16_pins[] = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +static const union vin_data16 vin5_data_pins = { + .data16 = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + }, }; -static const unsigned int vin5_data16_mux[] = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, - VI5_DATA8_MARK, VI5_DATA9_MARK, - VI5_DATA10_MARK, VI5_DATA11_MARK, - VI5_DATA12_MARK, VI5_DATA13_MARK, - VI5_DATA14_MARK, VI5_DATA15_MARK, +static const union vin_data16 vin5_data_mux = { + .data16 = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, + VI5_DATA8_MARK, VI5_DATA9_MARK, + VI5_DATA10_MARK, VI5_DATA11_MARK, + VI5_DATA12_MARK, VI5_DATA13_MARK, + VI5_DATA14_MARK, VI5_DATA15_MARK, + }, }; static const unsigned int vin5_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -4512,10 +4474,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - SH_PFC_PIN_GROUP(vin5_data8), - SH_PFC_PIN_GROUP(vin5_data10), - SH_PFC_PIN_GROUP(vin5_data12), - SH_PFC_PIN_GROUP(vin5_data16), + VIN_DATA_PIN_GROUP(vin5_data, 8), + VIN_DATA_PIN_GROUP(vin5_data, 10), + VIN_DATA_PIN_GROUP(vin5_data, 12), + VIN_DATA_PIN_GROUP(vin5_data, 16), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), From patchwork Fri Aug 21 09:42:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729111 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1C433175D for ; Fri, 21 Aug 2020 10:58:46 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EB81220656 for ; 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Fri, 21 Aug 2020 18:43:54 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 22/36] pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume Date: Fri, 21 Aug 2020 10:42:58 +0100 Message-Id: <20200821094312.3249-23-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: itTVbOOsmRKWX3MgDpCyXUtPx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007525; bh=hASLJdth6kZ7ZET8fF4aRJzQ+115zyRb7OpvRqQvGF0=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=ffyWL8WgwxGgbQs/CnbgTPp+L9fGjlgOc03d7pdMcnYXb0nCZSrx2GZqvKcXCF2JnLY PpB/IzIRctTxHe2Iw6p/Bh+MnewHVnYE+ftGJrBgZ54I26IMc1N+3d8JfsQF5QVLnp1XA JgiQ963vkjogpiAWbUdp6cDm3UJeCR6DMcE= From: Marek Vasut commit d92ee9cf8ec8d7fe1d7dbc4b3ee459419b1e5533 upstream. The TDSELCTRL register is responsible for configuring the SDHI/MMC clock return path delay and may be adjusted by the bootloader. Retain the value across suspend/resume to prevent hardware instability after resume. Signed-off-by: Marek Vasut Signed-off-by: Geert Uytterhoeven [Biju: Removed R8A77970 and R8A77980 related changes] Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 2 ++ drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 2 ++ drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 2 ++ drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 10 ++++++++++ 4 files changed, 16 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c index 897b7923074f..d92c979dfb98 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c @@ -5521,10 +5521,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { enum ioctrl_regs { POCCTRL, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 8edeb4d823f0..944dfd943541 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -5872,10 +5872,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { enum ioctrl_regs { POCCTRL, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c index 816341230c08..6616f5210b9d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c @@ -6126,10 +6126,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { enum ioctrl_regs { POCCTRL, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c index 104ba4b51c9f..20b58e4602c9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c @@ -2470,6 +2470,15 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po return bit; } +enum ioctrl_regs { + TDSELCTRL, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [TDSELCTRL] = { 0xe60603c0, }, + { /* sentinel */ }, +}; + static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { .pin_to_pocctrl = r8a77995_pin_to_pocctrl, }; @@ -2489,6 +2498,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), From patchwork Fri Aug 21 09:42:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729109 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C745A1575 for ; Fri, 21 Aug 2020 10:58:45 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A1C6D20656 for ; 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Fri, 21 Aug 2020 18:43:56 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 23/36] pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions Date: Fri, 21 Aug 2020 10:42:59 +0100 Message-Id: <20200821094312.3249-24-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: lgSpY2ZhE6x944kFJdpNVctEx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007525; bh=28KogWb1h8R9d2IZuZ5F2skMgeaX2jbUjcJacskC3Bw=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=N6GUNgyD5uXPZmpBfoNPiNGig/jf7KfMf+jCMghiBHCfuMlED7t4/GVu2d+O5NY6eOu TnSqKjt7HDGrdC4QscmH6oXFx9fOedXzPxFfUkrWMVnbuisV7Lt41VTE9j6mlpMV5Gj8G r2EA+JUuPe2Ce9Vr+GvkG043sz1Wii/8NFI= From: Takeshi Kihara commit 624a7a12cc0cc776c9c82347ffe5ddce7218eeca upstream. According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb 12, 2019, the RTS{0,1,3,4}_#/TANS pin names defined in the GPSR and IPSR registers are renamed to RTS{0,1,3,4}_#. This patch updates the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara [geert: Update R-Car H3 ES1.x, V3M, V3H, and D3] Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman [Biju: removed E3 related changes since it is already backported] Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 48 ++++++++++++------------ drivers/pinctrl/sh-pfc/pfc-r8a77970.c | 24 ++++++------ drivers/pinctrl/sh-pfc/pfc-r8a77980.c | 32 ++++++++-------- drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 12 +++--- 4 files changed, 58 insertions(+), 58 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c index d92c979dfb98..97a6b0221855 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c @@ -155,11 +155,11 @@ #define GPSR5_11 F_(RX2_A, IP12_7_4) #define GPSR5_10 F_(TX2_A, IP12_3_0) #define GPSR5_9 F_(SCK2, IP11_31_28) -#define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24) +#define GPSR5_8 F_(RTS1_N, IP11_27_24) #define GPSR5_7 F_(CTS1_N, IP11_23_20) #define GPSR5_6 F_(TX1_A, IP11_19_16) #define GPSR5_5 F_(RX1_A, IP11_15_12) -#define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8) +#define GPSR5_4 F_(RTS0_N, IP11_11_8) #define GPSR5_3 F_(CTS0_N, IP11_7_4) #define GPSR5_2 F_(TX0, IP11_3_0) #define GPSR5_1 F_(RX0, IP10_31_28) @@ -212,7 +212,7 @@ #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -234,7 +234,7 @@ #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -250,7 +250,7 @@ #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -263,7 +263,7 @@ #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -301,11 +301,11 @@ #define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -618,7 +618,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), - PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_TANS_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), @@ -758,7 +758,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_7_4, A10), PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), - PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1), + PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), PINMUX_IPSR_GPSR(IP3_11_8, A11), @@ -861,7 +861,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), - PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS), + PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), @@ -942,7 +942,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), - PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), PINMUX_IPSR_GPSR(IP6_31_28, D12), @@ -1114,7 +1114,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2), PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP), - PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N), PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1), @@ -1143,7 +1143,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1), PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA), - PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N), PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2), @@ -3219,7 +3219,7 @@ static const unsigned int scif0_ctrl_pins[] = { RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), }; static const unsigned int scif0_ctrl_mux[] = { - RTS0_N_TANS_MARK, CTS0_N_MARK, + RTS0_N_MARK, CTS0_N_MARK, }; /* - SCIF1 ------------------------------------------------------------------ */ static const unsigned int scif1_data_a_pins[] = { @@ -3241,7 +3241,7 @@ static const unsigned int scif1_ctrl_pins[] = { RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; static const unsigned int scif1_data_b_pins[] = { @@ -3293,7 +3293,7 @@ static const unsigned int scif3_ctrl_pins[] = { RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), }; static const unsigned int scif3_ctrl_mux[] = { - RTS3_N_TANS_MARK, CTS3_N_MARK, + RTS3_N_MARK, CTS3_N_MARK, }; static const unsigned int scif3_data_b_pins[] = { /* RX, TX */ @@ -3322,7 +3322,7 @@ static const unsigned int scif4_ctrl_a_pins[] = { RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), }; static const unsigned int scif4_ctrl_a_mux[] = { - RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, + RTS4_N_A_MARK, CTS4_N_A_MARK, }; static const unsigned int scif4_data_b_pins[] = { /* RX, TX */ @@ -3343,7 +3343,7 @@ static const unsigned int scif4_ctrl_b_pins[] = { RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), }; static const unsigned int scif4_ctrl_b_mux[] = { - RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, + RTS4_N_B_MARK, CTS4_N_B_MARK, }; static const unsigned int scif4_data_c_pins[] = { /* RX, TX */ @@ -3364,7 +3364,7 @@ static const unsigned int scif4_ctrl_c_pins[] = { RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), }; static const unsigned int scif4_ctrl_c_mux[] = { - RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, + RTS4_N_C_MARK, CTS4_N_C_MARK, }; /* - SCIF5 ------------------------------------------------------------------ */ static const unsigned int scif5_data_pins[] = { @@ -5448,11 +5448,11 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { - { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */ + { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ - { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */ + { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ @@ -5700,11 +5700,11 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [13] = RCAR_GP_PIN(5, 1), /* RX0 */ [14] = RCAR_GP_PIN(5, 2), /* TX0 */ [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ - [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */ + [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ - [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */ + [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c index 57859287287c..78159b146e3f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c @@ -180,14 +180,14 @@ #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -206,14 +206,14 @@ #define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -499,7 +499,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0), PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1), - PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS), + PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N), PINMUX_IPSR_GPSR(IP3_15_12, HRX3), PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), @@ -530,7 +530,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7), PINMUX_IPSR_GPSR(IP4_11_8, HRX1), - PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N), PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), @@ -620,7 +620,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5), PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9), - PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS), + PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N), PINMUX_IPSR_GPSR(IP6_23_20, D12), PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6), PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1), @@ -667,7 +667,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1), PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3), PINMUX_IPSR_GPSR(IP7_19_16, WE0_N), - PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N), PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC), PINMUX_IPSR_GPSR(IP7_23_20, SCL2), @@ -1421,7 +1421,7 @@ static const unsigned int scif0_ctrl_pins[] = { RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), }; static const unsigned int scif0_ctrl_mux[] = { - RTS0_N_TANS_MARK, CTS0_N_MARK, + RTS0_N_MARK, CTS0_N_MARK, }; /* - SCIF1 ------------------------------------------------------------------ */ @@ -1444,7 +1444,7 @@ static const unsigned int scif1_ctrl_pins[] = { RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; static const unsigned int scif1_data_b_pins[] = { /* RX, TX */ @@ -1474,7 +1474,7 @@ static const unsigned int scif3_ctrl_pins[] = { RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), }; static const unsigned int scif3_ctrl_mux[] = { - RTS3_N_TANS_MARK, CTS3_N_MARK, + RTS3_N_MARK, CTS3_N_MARK, }; /* - SCIF4 ------------------------------------------------------------------ */ @@ -1497,7 +1497,7 @@ static const unsigned int scif4_ctrl_pins[] = { RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), }; static const unsigned int scif4_ctrl_mux[] = { - RTS4_N_TANS_MARK, CTS4_N_MARK, + RTS4_N_MARK, CTS4_N_MARK, }; /* - TMU -------------------------------------------------------------------- */ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c index 27c4392cbbbd..8c6707f9a335 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c @@ -187,7 +187,7 @@ #define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_19_16 FM(DU_DR6) FM(RTS4_N_TANS) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -210,14 +210,14 @@ #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -243,7 +243,7 @@ #define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -470,7 +470,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP0_15_12, A3), PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6), - PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N_TANS), + PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N), PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN), PINMUX_IPSR_GPSR(IP0_19_16, A4), @@ -580,7 +580,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0), PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1), - PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS), + PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N), PINMUX_IPSR_GPSR(IP3_15_12, HRX3), PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), @@ -609,7 +609,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7), PINMUX_IPSR_GPSR(IP4_11_8, HRX1), - PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N), PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), @@ -728,7 +728,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP7_19_16, SDA1), PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3), PINMUX_IPSR_GPSR(IP7_19_16, WE0_N), - PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N), PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1), PINMUX_IPSR_GPSR(IP7_23_20, SCL2), @@ -1676,11 +1676,11 @@ static const unsigned int scif0_clk_mux[] = { SCK0_MARK, }; static const unsigned int scif0_ctrl_pins[] = { - /* RTS0#/TANS, CTS0# */ + /* RTS0#, CTS0# */ RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), }; static const unsigned int scif0_ctrl_mux[] = { - RTS0_N_TANS_MARK, CTS0_N_MARK, + RTS0_N_MARK, CTS0_N_MARK, }; /* - SCIF1 ------------------------------------------------------------------ */ @@ -1699,11 +1699,11 @@ static const unsigned int scif1_clk_mux[] = { SCK1_MARK, }; static const unsigned int scif1_ctrl_pins[] = { - /* RTS1#/TANS, CTS1# */ + /* RTS1#, CTS1# */ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; static const unsigned int scif1_data_b_pins[] = { /* RX1, TX1 */ @@ -1729,11 +1729,11 @@ static const unsigned int scif3_clk_mux[] = { SCK3_MARK, }; static const unsigned int scif3_ctrl_pins[] = { - /* RTS3#/TANS, CTS3# */ + /* RTS3#, CTS3# */ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), }; static const unsigned int scif3_ctrl_mux[] = { - RTS3_N_TANS_MARK, CTS3_N_MARK, + RTS3_N_MARK, CTS3_N_MARK, }; /* - SCIF4 ------------------------------------------------------------------ */ @@ -1752,11 +1752,11 @@ static const unsigned int scif4_clk_mux[] = { SCK4_MARK, }; static const unsigned int scif4_ctrl_pins[] = { - /* RTS4#/TANS, CTS4# */ + /* RTS4#, CTS4# */ RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), }; static const unsigned int scif4_ctrl_mux[] = { - RTS4_N_TANS_MARK, CTS4_N_MARK, + RTS4_N_MARK, CTS4_N_MARK, }; /* - SCIF Clock ------------------------------------------------------------- */ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c index 20b58e4602c9..6e952fe0818a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c @@ -291,7 +291,7 @@ #define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -302,7 +302,7 @@ /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ #define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -854,7 +854,7 @@ static const u16 pinmux_data[] = { /* IPSR11 */ PINMUX_IPSR_GPSR(IP11_3_0, SDA1), - PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N), PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK), PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1), @@ -889,7 +889,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B), PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0), - PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N), PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B), PINMUX_IPSR_GPSR(IP12_11_8, SCK2), @@ -1418,7 +1418,7 @@ static const unsigned int scif0_ctrl_pins[] = { RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), }; static const unsigned int scif0_ctrl_mux[] = { - RTS0_N_TANS_MARK, CTS0_N_MARK, + RTS0_N_MARK, CTS0_N_MARK, }; /* - SCIF1 ------------------------------------------------------------------ */ static const unsigned int scif1_data_a_pins[] = { @@ -1454,7 +1454,7 @@ static const unsigned int scif1_ctrl_pins[] = { RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; /* - SCIF2 ------------------------------------------------------------------ */ From patchwork Fri Aug 21 09:43:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729103 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 72C28722 for ; Fri, 21 Aug 2020 10:58:45 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4E5042072D for ; Fri, 21 Aug 2020 10:58:45 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relmlir6.idc.renesas.com (Postfix) with ESMTP id DCC5D4231AD9; Fri, 21 Aug 2020 18:43:58 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 24/36] pinctrl: sh-pfc: r8a7795-es1: Add TPU pins, groups and functions Date: Fri, 21 Aug 2020 10:43:00 +0100 Message-Id: <20200821094312.3249-25-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: HX3DvfdFhX1BD72GdI9GgW2Ix4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007525; bh=GtQfGwxegVwEvLANuVpn9jmmNKYCeu0bMvESYLe0Sy0=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Rfk0M/qMTGx7gJxVFvuJhvP3Decuv8asMO9FRp7SRMsGZvjLpfozptmoqzrKweI/Z8P lWcr1qupPJs0/h+5diCPkKjiNfrpaqW+oiJ2Et49u+EkujeAPc5c5c+tW92wjFKC1AX9P Fesu/tTg2gnot26yimgIABMDaXECsbrLcI8= From: Geert Uytterhoeven commit 0cbdf1b876243c73a795783ce69004302e250a43 upstream. Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on revision ES1.x of the R-Car H3 SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 42 ++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c index 97a6b0221855..aea009f40f49 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c @@ -3812,6 +3812,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { TCLK2_B_MARK, }; +/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + /* TPU0TO0 */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int tpu_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + /* TPU0TO1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int tpu_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + /* TPU0TO2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int tpu_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + /* TPU0TO3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int tpu_to3_mux[] = { + TPU0TO3_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PWEN, OVC */ @@ -4165,6 +4195,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), @@ -4635,6 +4669,13 @@ static const char * const tmu_groups[] = { "tmu_tclk2_b", }; +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -4707,6 +4748,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(ssi), SH_PFC_FUNCTION(tmu), + SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), From patchwork Fri Aug 21 09:43:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729121 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C3D561575 for ; Fri, 21 Aug 2020 10:58:46 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9E45E207BB for ; Fri, 21 Aug 2020 10:58:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="Ie8ez7Us" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9E45E207BB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5209+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id GPx1YY4521763x1Q3hNi4Ob5; Fri, 21 Aug 2020 03:58:46 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.130436.1598003042737837811 for ; Fri, 21 Aug 2020 02:44:03 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="55170357" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Aug 2020 18:44:02 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id ABBB94232061; Fri, 21 Aug 2020 18:44:00 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 25/36] pinctrl: sh-pfc: r8a7795: Add TPU pins, groups and functions Date: Fri, 21 Aug 2020 10:43:01 +0100 Message-Id: <20200821094312.3249-26-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: zJstRY3HNHqo4mDcei9N5APVx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007526; bh=bIza8gYcZVXYSeuAu64ayD5BZVhhKTRtdmOh5uaOJgg=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Ie8ez7Us2jmKuCtPgFy+yam5sq8ioSeWjscp2KvDNdHe1/f/2Mzc4b3AleZbPsWuCwo R0ZRyijx+U4W3hZw5ijd4A7PJrQHByXGlp1a1Zr9KLCu6J+1Tf2hILSby2VmYj7vIKiZ9 9oKbq8nG03HZ4FZptrDoh+KvOtk1u4blif8= From: Geert Uytterhoeven commit 9141d4558fcc635c4ec3b5ddd99f24d8df7fe6e0 upstream. Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on revisions ES2.x and later of the R-Car H3 SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 944dfd943541..054fec90eded 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -3901,6 +3901,36 @@ static const unsigned int tmu_tclk2_b_mux[] = { TCLK2_B_MARK, }; +/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + /* TPU0TO0 */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int tpu_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + /* TPU0TO1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int tpu_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + /* TPU0TO2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int tpu_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + /* TPU0TO3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int tpu_to3_mux[] = { + TPU0TO3_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PWEN, OVC */ @@ -4451,6 +4481,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), @@ -4946,6 +4980,13 @@ static const char * const tmu_groups[] = { "tmu_tclk2_b", }; +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -5048,6 +5089,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(ssi), SH_PFC_FUNCTION(tmu), + SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), From patchwork Fri Aug 21 09:43:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729091 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9466A1575 for ; Fri, 21 Aug 2020 10:58:40 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6F7C92072D for ; Fri, 21 Aug 2020 10:58:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="Ncw1kg0f" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6F7C92072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5196+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id 4ZUbYY4521763xAdAewXetO6; Fri, 21 Aug 2020 03:58:40 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.131152.1598003016916343991 for ; Fri, 21 Aug 2020 02:44:04 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954619" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:44:04 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 906B44232078; Fri, 21 Aug 2020 18:44:02 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 26/36] pinctrl: sh-pfc: r8a7795-es1: Use new macros for non-GPIO pins Date: Fri, 21 Aug 2020 10:43:02 +0100 Message-Id: <20200821094312.3249-27-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: uqJxpBSeHwXaFxw3P7PNmJaRx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007520; bh=8WG15dnWAAt3Aj5LSb9m9bV/ssF+FE5NL090xsYrQ0w=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Ncw1kg0fWg3OuQjMmIBHZaQv0Rk+Nmwm1MKRDI/lk2MOizbfZZ1wq+ACmYZf8KyxGHN S91bivNG8saPq0ghj3xv7voZJOGpn/xlwz9Wq9hnxQgNUVs0GHNkBu2LlyHqUAhJh4ZMh hlJQLOu/KAUrhbzDQjTIWlt2RoTFyrBWA6k= From: Geert Uytterhoeven commit 4f062bcb5889722efcaf71eed280439e976a112d upstream. Update the R-Car H3 ES1.x pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H3 ES1.x SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 333 +++++++++++------------ 1 file changed, 163 insertions(+), 170 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c index aea009f40f49..2e565dfbbf33 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c @@ -29,6 +29,53 @@ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(CLKOUT, "CLKOUT", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ + PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -1448,68 +1495,16 @@ static const u16 pinmux_data[] = { }; /* - * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs. - * Physical layout rows: A - AW, cols: 1 - 39. + * Pins not associated with a GPIO port. */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* - * Pins not associated with a GPIO port. - * - * The pin positions are different between different r8a7795 - * packages, all that is needed for the pfc driver is a unique - * number for each pin. To this end use the pin layout from - * R-Car H3SiP to calculate a unique number for each pin. - */ - SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), + PINMUX_NOGP_ALL(), }; /* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1658,7 +1653,7 @@ static const unsigned int avb_phy_int_mux[] = { }; static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */ - RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), + RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, }; static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, @@ -1671,11 +1666,11 @@ static const unsigned int avb_mii_pins[] = { * AVB_RD1, AVB_RD2, AVB_RD3, * AVB_TXCREFCLK */ - PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), - PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), - PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), - PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), - PIN_NUMBER('A', 12), + PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, + PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, + PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, + PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, + PIN_AVB_TXCREFCLK, }; static const unsigned int avb_mii_mux[] = { @@ -3137,22 +3132,21 @@ static const unsigned int pwm6_b_mux[] = { /* - QSPI0 ------------------------------------------------------------------ */ static const unsigned int qspi0_ctrl_pins[] = { /* QSPI0_SPCLK, QSPI0_SSL */ - PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3), + PIN_QSPI0_SPCLK, PIN_QSPI0_SSL, }; static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; static const unsigned int qspi0_data2_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, }; static const unsigned int qspi0_data2_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, }; static const unsigned int qspi0_data4_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */ - PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), - PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6), + PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3, }; static const unsigned int qspi0_data4_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, @@ -3161,22 +3155,21 @@ static const unsigned int qspi0_data4_mux[] = { /* - QSPI1 ------------------------------------------------------------------ */ static const unsigned int qspi1_ctrl_pins[] = { /* QSPI1_SPCLK, QSPI1_SSL */ - PIN_NUMBER('V', 3), PIN_NUMBER('V', 5), + PIN_QSPI1_SPCLK, PIN_QSPI1_SSL, }; static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; static const unsigned int qspi1_data2_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, }; static const unsigned int qspi1_data2_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, }; static const unsigned int qspi1_data4_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */ - PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), - PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3), + PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3, }; static const unsigned int qspi1_data4_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, @@ -5314,44 +5307,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { - { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ - { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ - { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ - { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ - { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ + { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ + { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ + { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ + { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ + { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ + { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ + { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { - { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ - { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ - { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ - { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ - { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ - { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ + { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ + { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ + { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ + { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ + { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ + { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ + { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ + { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ } }, { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { - { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ - { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ - { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ - { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ + { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ + { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ + { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ + { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ + { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ + { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ + { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ + { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { - { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ - { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ - { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ + { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ + { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ + { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ + { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ + { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ + { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ + { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ } }, { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ @@ -5394,7 +5387,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ } }, { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { - { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */ + { PIN_CLKOUT, 28, 3 }, /* CLKOUT */ { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ @@ -5405,7 +5398,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { } }, { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ - { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ + { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ @@ -5424,30 +5417,30 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ } }, { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { - { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ - { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ - { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ - { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ - { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ - { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ + { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ + { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ + { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ + { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ + { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ + { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { - { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */ - { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */ - { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */ - { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ + { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ + { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ + { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ + { PIN_TMS, 4, 2 }, /* TMS */ } }, { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { - { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ - { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ + { PIN_TDO, 28, 2 }, /* TDO */ + { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ + { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ } }, { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ @@ -5516,7 +5509,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ - { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ + { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ } }, { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { @@ -5590,35 +5583,35 @@ static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { - [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ - [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ - [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ - [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ - [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ - [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ - [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ - [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ - [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ - [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ - [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ - [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ - [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ - [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ - [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ - [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ - [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ - [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ - [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ - [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ - [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ - [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ - [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ - [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ - [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ - [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ - [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ - [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ - [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ + [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ + [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ + [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ + [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ + [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ + [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ + [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ + [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ + [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ + [12] = PIN_RPC_INT_N, /* RPC_INT# */ + [13] = PIN_RPC_WP_N, /* RPC_WP# */ + [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ + [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ + [16] = PIN_AVB_RXC, /* AVB_RXC */ + [17] = PIN_AVB_RD0, /* AVB_RD0 */ + [18] = PIN_AVB_RD1, /* AVB_RD1 */ + [19] = PIN_AVB_RD2, /* AVB_RD2 */ + [20] = PIN_AVB_RD3, /* AVB_RD3 */ + [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ + [22] = PIN_AVB_TXC, /* AVB_TXC */ + [23] = PIN_AVB_TD0, /* AVB_TD0 */ + [24] = PIN_AVB_TD1, /* AVB_TD1 */ + [25] = PIN_AVB_TD2, /* AVB_TD2 */ + [26] = PIN_AVB_TD3, /* AVB_TD3 */ + [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ + [28] = PIN_AVB_MDIO, /* AVB_MDIO */ [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ @@ -5658,7 +5651,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [31] = RCAR_GP_PIN(1, 19), /* A19 */ } }, { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { - [ 0] = PIN_NUMBER('F', 1), /* CLKOUT */ + [ 0] = PIN_CLKOUT, /* CLKOUT */ [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */ [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ @@ -5667,7 +5660,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ - [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ [10] = RCAR_GP_PIN(0, 0), /* D0 */ [11] = RCAR_GP_PIN(0, 1), /* D1 */ [12] = RCAR_GP_PIN(0, 2), /* D2 */ @@ -5688,20 +5681,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ - [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ - [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ + [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { - [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */ - [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */ - [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */ - [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ - [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ - [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ - [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ - [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ + [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ + [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ + [ 2] = PIN_FSCLKST_N, /* FSCLKST# */ + [ 3] = PIN_EXTALR, /* EXTALR*/ + [ 4] = PIN_TRST_N, /* TRST# */ + [ 5] = PIN_TCK, /* TCK */ + [ 6] = PIN_TMS, /* TMS */ + [ 7] = PIN_TDI, /* TDI */ [ 8] = SH_PFC_PIN_NONE, - [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [ 9] = PIN_ASEBRK, /* ASEBRK */ [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ @@ -5766,7 +5759,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ - [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 6] = PIN_MLB_REF, /* MLB_REF */ [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ From patchwork Fri Aug 21 09:43:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729117 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77C3317D4 for ; Fri, 21 Aug 2020 10:58:46 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 52E91207BB for ; Fri, 21 Aug 2020 10:58:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="ctx3cwgN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 52E91207BB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5210+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id k8R6YY4521763xfvPwoMZpdM; Fri, 21 Aug 2020 03:58:46 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.131162.1598003046570191988 for ; Fri, 21 Aug 2020 02:44:07 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="55170365" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Aug 2020 18:44:05 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 7BED04232071; Fri, 21 Aug 2020 18:44:04 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 27/36] pinctrl: sh-pfc: r8a7795: Use new macros for non-GPIO pins Date: Fri, 21 Aug 2020 10:43:03 +0100 Message-Id: <20200821094312.3249-28-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: QvCanRvtpmu27QfPTxDfxVr2x4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007526; bh=tnkVZMyRTovBTQqG5eriBQmuicQh6VfJmVC0ixVCDeQ=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=ctx3cwgNX59G6uRObgtFoukgMv9tNB27ROGkARuRYeFmLwzI8SuSeo/2JGVeGfhDRi9 mDdVwGzhdmaP/d3MQ5+dMyA3FrCx0IX3SAjuuclA71Y6EbIAPNIe5FY3iQrXKMVRPgM7N tlX4eLrrAGltogbrIhmfvgArGjreBUthsPk= From: Geert Uytterhoeven commit 42ee6c3395465cea948a462b4605fc7fa53e3704 upstream. Update the R-Car H3 ES2.0 and later pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H3 ES2.0 SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Tested-by: Niklas Söderlund Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 313 +++++++++++++-------------- 1 file changed, 154 insertions(+), 159 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 054fec90eded..3172ef6a9b20 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -30,6 +30,52 @@ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ + PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -1509,67 +1555,16 @@ static const u16 pinmux_data[] = { }; /* - * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs. - * Physical layout rows: A - AW, cols: 1 - 39. + * Pins not associated with a GPIO port. */ -#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) -#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) -#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), - - /* - * Pins not associated with a GPIO port. - * - * The pin positions are different between different r8a7795 - * packages, all that is needed for the pfc driver is a unique - * number for each pin. To this end use the pin layout from - * R-Car H3SiP to calculate a unique number for each pin. - */ - SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP_DOWN), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), - SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), + PINMUX_NOGP_ALL(), }; /* - AUDIO CLOCK ------------------------------------------------------------ */ @@ -1717,7 +1712,7 @@ static const unsigned int avb_phy_int_mux[] = { }; static const unsigned int avb_mdio_pins[] = { /* AVB_MDC, AVB_MDIO */ - RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), + RCAR_GP_PIN(2, 9), PIN_AVB_MDIO, }; static const unsigned int avb_mdio_mux[] = { AVB_MDC_MARK, AVB_MDIO_MARK, @@ -1730,11 +1725,11 @@ static const unsigned int avb_mii_pins[] = { * AVB_RD1, AVB_RD2, AVB_RD3, * AVB_TXCREFCLK */ - PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), - PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), - PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), - PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), - PIN_NUMBER('A', 12), + PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0, + PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3, + PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0, + PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3, + PIN_AVB_TXCREFCLK, }; static const unsigned int avb_mii_mux[] = { @@ -5665,44 +5660,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { - { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ - { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ - { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ - { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ - { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ + { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ + { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ + { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ + { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ + { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ + { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ + { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { - { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ - { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ - { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ - { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ - { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ - { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ + { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ + { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ + { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ + { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ + { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ + { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ + { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ + { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ } }, { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { - { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ - { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ - { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ - { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ + { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ + { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ + { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ + { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ + { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ + { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ + { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ + { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ } }, { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { - { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ - { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ - { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ + { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ + { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ + { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ + { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ + { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ + { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ + { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ } }, { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ @@ -5756,7 +5751,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { } }, { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ - { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ + { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ @@ -5775,30 +5770,30 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ } }, { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { - { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ - { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ - { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ - { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ - { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ - { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ + { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ + { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ + { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ + { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ + { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ + { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { - { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */ - { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */ - { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */ - { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ + { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ + { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ + { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ + { PIN_TMS, 4, 2 }, /* TMS */ } }, { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { - { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ - { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ + { PIN_TDO, 28, 2 }, /* TDO */ + { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ + { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ } }, { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ @@ -5867,7 +5862,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ - { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ + { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ } }, { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { @@ -5940,35 +5935,35 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc static const struct pinmux_bias_reg pinmux_bias_regs[] = { { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { - [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ - [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ - [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ - [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ - [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ - [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ - [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ - [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ - [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ - [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ - [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ - [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ - [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ - [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ - [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ - [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ - [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ - [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ - [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ - [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ - [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ - [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ - [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ - [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ - [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ - [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ - [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ - [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ - [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ + [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ + [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ + [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ + [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ + [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ + [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ + [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ + [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ + [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ + [12] = PIN_RPC_INT_N, /* RPC_INT# */ + [13] = PIN_RPC_WP_N, /* RPC_WP# */ + [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ + [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ + [16] = PIN_AVB_RXC, /* AVB_RXC */ + [17] = PIN_AVB_RD0, /* AVB_RD0 */ + [18] = PIN_AVB_RD1, /* AVB_RD1 */ + [19] = PIN_AVB_RD2, /* AVB_RD2 */ + [20] = PIN_AVB_RD3, /* AVB_RD3 */ + [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ + [22] = PIN_AVB_TXC, /* AVB_TXC */ + [23] = PIN_AVB_TD0, /* AVB_TD0 */ + [24] = PIN_AVB_TD1, /* AVB_TD1 */ + [25] = PIN_AVB_TD2, /* AVB_TD2 */ + [26] = PIN_AVB_TD3, /* AVB_TD3 */ + [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ + [28] = PIN_AVB_MDIO, /* AVB_MDIO */ [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ @@ -6017,7 +6012,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ - [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */ [10] = RCAR_GP_PIN(0, 0), /* D0 */ [11] = RCAR_GP_PIN(0, 1), /* D1 */ [12] = RCAR_GP_PIN(0, 2), /* D2 */ @@ -6038,20 +6033,20 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ - [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ - [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ + [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { - [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */ - [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */ - [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */ - [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ - [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ - [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ - [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ - [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ + [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ + [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ + [ 2] = PIN_FSCLKST_N, /* FSCLKST# */ + [ 3] = PIN_EXTALR, /* EXTALR*/ + [ 4] = PIN_TRST_N, /* TRST# */ + [ 5] = PIN_TCK, /* TCK */ + [ 6] = PIN_TMS, /* TMS */ + [ 7] = PIN_TDI, /* TDI */ [ 8] = SH_PFC_PIN_NONE, - [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [ 9] = PIN_ASEBRK, /* ASEBRK */ [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ @@ -6116,7 +6111,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ - [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 6] = PIN_MLB_REF, /* MLB_REF */ [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ From patchwork Fri Aug 21 09:43:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729119 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B81B5109B for ; Fri, 21 Aug 2020 10:58:46 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9220720656 for ; Fri, 21 Aug 2020 10:58:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="ZbHlaU+h" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9220720656 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5206+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id Az98YY4521763xd1MbAMfeFK; Fri, 21 Aug 2020 03:58:46 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.131162.1598003046570191988 for ; Fri, 21 Aug 2020 02:44:08 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="55170370" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Aug 2020 18:44:08 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 610C84232078; Fri, 21 Aug 2020 18:44:06 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 28/36] pinctrl: sh-pfc: pfc-r8a7795-es1: Fix typo in pinmux macro for SCL3 Date: Fri, 21 Aug 2020 10:43:04 +0100 Message-Id: <20200821094312.3249-29-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: pXlSTeIRKBcFGgF09lwn1n5ix4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007526; bh=/JrrHkrLXkGD8bwnhius06zzr7Dmfo6UTgUfTTNfMQE=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=ZbHlaU+hWTN0JsEPAsW3x+DawG46ft1ai6QNWLeA1zMTJn2cMtVkwnedTYmuV9DVtfO Ps0wooy0yiR+zvfjkB9x6I90kGJIAAwG5KS6zv0FB0MUvpLgZo0hbw/FnBjnlMu/6QOgj h+WIaeyitZ4/oVfREd3VVSvX6Dp+NCNc9Uc= From: Keiya Nobuta commit dcfdaa92a417706c880daa4f94396a1cd53278d0 upstream. SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta Link: https://lore.kernel.org/r/20191008060619.30237-2-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c index 2e565dfbbf33..17f7b1596a62 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c @@ -721,7 +721,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), - PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), + PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0), From patchwork Fri Aug 21 09:43:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729093 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B5722109B for ; Fri, 21 Aug 2020 10:58:40 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 902C9207DF for ; Fri, 21 Aug 2020 10:58:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="sOCKZ0KZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 902C9207DF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5197+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id 8gO4YY4521763xpjsIO8b3LG; Fri, 21 Aug 2020 03:58:40 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.131162.1598003046570191988 for ; Fri, 21 Aug 2020 02:44:10 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="55170374" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Aug 2020 18:44:09 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 79EAD4232061; Fri, 21 Aug 2020 18:44:08 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 29/36] pinctrl: sh-pfc: pfc-r8a7795: Fix typo in pinmux macro for SCL3 Date: Fri, 21 Aug 2020 10:43:05 +0100 Message-Id: <20200821094312.3249-30-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: 0aJgSloNumi49lcaXvBh2WyJx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007520; bh=xF6HsyTB/oYrbNBmNTNAPvxzA2m9atpaHlscnDLuCdE=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=sOCKZ0KZboB1+341kYJXcLyhd5mvvxS2OSbpZd3mfBuyJiOQE0+lAKZw9MrEOs9K5+J Wth2NEzOLsvOYeB069rL45d2W7wHTWIeEIWJcNkqGcHhgv+Hzrt/+7etTpU++kNeKhTba iLcCq/uCEV2vgvVE2NLmy1j61J8WIpVsBEs= From: Keiya Nobuta commit 772f9daf336d047ef018bf41e218cb04df4146e5 upstream. SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta Link: https://lore.kernel.org/r/20191008060619.30237-1-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 3172ef6a9b20..0a2ea9544802 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -729,7 +729,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), - PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), + PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), From patchwork Fri Aug 21 09:43:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729113 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1E62C17F0 for ; Fri, 21 Aug 2020 10:58:46 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ED78F2072D for ; Fri, 21 Aug 2020 10:58:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="AIpZ0Bqt" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ED78F2072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5207+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id Cd7FYY4521763xN1pBVa9N9J; Fri, 21 Aug 2020 03:58:45 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.131167.1598003052343639956 for ; Fri, 21 Aug 2020 02:44:12 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954631" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:44:11 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 4DCA44232061; Fri, 21 Aug 2020 18:44:10 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 30/36] pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers Date: Fri, 21 Aug 2020 10:43:06 +0100 Message-Id: <20200821094312.3249-31-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: u3eu2wldNE04pUZnBe2hXNHfx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007525; bh=EiH+8Iy0ZPwW27YM+Gh3oaaOUdGYPMm7yVQNTKD1ndw=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=AIpZ0BqtJ8sNXIkxt3lhmHD4taoPOqN7Mp1MSsMEy7bSo2BGlcxtfkh2ON4dgj9kR1H oh53O27Ca/1qr497plqW7cpgo00eJ2q++I1CfcggqLt0ku6rLW/FLqS/b028G2M22KfPM wXEInyqMPHpKn0EwGEoxlEg+0SzwJfJYajE= From: Geert Uytterhoeven commit f2bc07562748c23609743ded0630ec965f9e4fec upstream. Despite using the same compatible values ("r8a7795"-based) because of historical reasons, R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+ (R8A77951) are really different SoCs, with different part numbers, and with different Pin Function Controller blocks. Reflect this in the pinctrl configuration, by replacing the existing CONFIG_PINCTRL_PFC_R8A7795 symbol by two new config symbols: CONFIG_PINCTRL_PFC_R8A77950 and CONFIG_PINCTRL_PFC_R8A77951. The latter are selected automatically, depending on the soon-to-be-introduced corresponding SoC-specific config options, and on the current common config option, to relax dependencies. Rename the individual pin control driver source files from pfc-r8a7795-es1.c to pfc-r8a77950.c, and from pfc-r8a7795.c to pfc-r8a77951.c, and make them truly independent. As both SoCs share the same compatible value, special care must be taken to match them to the correct pin control driver, if support for it is included in the running kernel. This will allow making support for early R-Car H3 revisions optional, the largest share of which is taken by the pin control driver. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Reviewed-by: Niklas Söderlund Tested-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20191230083156.19191-1-geert+renesas@glider.be [biju: updated config file for 4.19.y-cip] Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/Kconfig | 9 ++- drivers/pinctrl/sh-pfc/Makefile | 4 +- drivers/pinctrl/sh-pfc/core.c | 57 ++++++++++++++----- .../{pfc-r8a7795-es1.c => pfc-r8a77950.c} | 26 ++++----- .../sh-pfc/{pfc-r8a7795.c => pfc-r8a77951.c} | 39 +++++-------- drivers/pinctrl/sh-pfc/sh_pfc.h | 4 +- 6 files changed, 81 insertions(+), 58 deletions(-) rename drivers/pinctrl/sh-pfc/{pfc-r8a7795-es1.c => pfc-r8a77950.c} (99%) rename drivers/pinctrl/sh-pfc/{pfc-r8a7795.c => pfc-r8a77951.c} (99%) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 2b82f520ccf1..77f606928220 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -99,9 +99,14 @@ config PINCTRL_PFC_R8A7794 depends on ARCH_R8A7794 select PINCTRL_SH_PFC -config PINCTRL_PFC_R8A7795 +config PINCTRL_PFC_R8A77950 def_bool y - depends on ARCH_R8A7795 + depends on (ARCH_R8A77950 || ARCH_R8A7795) + select PINCTRL_SH_PFC + +config PINCTRL_PFC_R8A77951 + def_bool y + depends on (ARCH_R8A77951 || ARCH_R8A7795) select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7796 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 95142f6b8ae4..930be8cf259f 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -17,8 +17,8 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o -obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o -obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o +obj-$(CONFIG_PINCTRL_PFC_R8A77950) += pfc-r8a77950.o +obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a77951.o obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 788ec0e29376..53cb82a7aa5d 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "core.h" @@ -569,18 +570,18 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7794_pinmux_info, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7795 +/* Both r8a7795 entries must be present to make sanity checks work */ +#ifdef CONFIG_PINCTRL_PFC_R8A77950 { .compatible = "renesas,pfc-r8a7795", - .data = &r8a7795_pinmux_info, + .data = &r8a77950_pinmux_info, }, -#ifdef DEBUG +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A77951 { - /* For sanity checks only (nothing matches against this) */ - .compatible = "renesas,pfc-r8a77950", /* R-Car H3 ES1.0 */ - .data = &r8a7795es1_pinmux_info, + .compatible = "renesas,pfc-r8a7795", + .data = &r8a77951_pinmux_info, }, -#endif /* DEBUG */ #endif #ifdef CONFIG_PINCTRL_PFC_R8A7796 { @@ -881,19 +882,49 @@ static void __init sh_pfc_check_driver(const struct platform_driver *pdrv) static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {} #endif /* !DEBUG */ +#ifdef CONFIG_OF +static const void *sh_pfc_quirk_match(void) +{ +#if defined(CONFIG_PINCTRL_PFC_R8A77950) || \ + defined(CONFIG_PINCTRL_PFC_R8A77951) + const struct soc_device_attribute *match; + static const struct soc_device_attribute quirks[] = { + { + .soc_id = "r8a7795", .revision = "ES1.*", + .data = &r8a77950_pinmux_info, + }, + { + .soc_id = "r8a7795", + .data = &r8a77951_pinmux_info, + }, + + { /* sentinel */ } + }; + + match = soc_device_match(quirks); + if (match) + return match->data ?: ERR_PTR(-ENODEV); +#endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */ + + return NULL; +} +#endif /* CONFIG_OF */ + static int sh_pfc_probe(struct platform_device *pdev) { -#ifdef CONFIG_OF - struct device_node *np = pdev->dev.of_node; -#endif const struct sh_pfc_soc_info *info; struct sh_pfc *pfc; int ret; #ifdef CONFIG_OF - if (np) - info = of_device_get_match_data(&pdev->dev); - else + if (pdev->dev.of_node) { + info = sh_pfc_quirk_match(); + if (IS_ERR(info)) + return PTR_ERR(info); + + if (!info) + info = of_device_get_match_data(&pdev->dev); + } else #endif info = (const void *)platform_get_device_id(pdev)->driver_data; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a77950.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c rename to drivers/pinctrl/sh-pfc/pfc-r8a77950.c index 17f7b1596a62..467396ccb091 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77950.c @@ -1,5 +1,5 @@ /* - * R8A7795 ES1.x processor support - PFC hardware block. + * R8A77950 processor support - PFC hardware block. * * Copyright (C) 2015-2017 Renesas Electronics Corporation * @@ -5565,8 +5565,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, + u32 *pocctrl) { int bit = -EINVAL; @@ -5823,8 +5823,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) +static unsigned int r8a77950_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) { const struct pinmux_bias_reg *reg; unsigned int bit; @@ -5841,8 +5841,8 @@ static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc, return PIN_CONFIG_BIAS_PULL_DOWN; } -static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) +static void r8a77950_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) { const struct pinmux_bias_reg *reg; u32 enable, updown; @@ -5864,15 +5864,15 @@ static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, sh_pfc_write(pfc, reg->puen, enable); } -static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = { - .pin_to_pocctrl = r8a7795es1_pin_to_pocctrl, - .get_bias = r8a7795es1_pinmux_get_bias, - .set_bias = r8a7795es1_pinmux_set_bias, +static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = { + .pin_to_pocctrl = r8a77950_pin_to_pocctrl, + .get_bias = r8a77950_pinmux_get_bias, + .set_bias = r8a77950_pinmux_set_bias, }; -const struct sh_pfc_soc_info r8a7795es1_pinmux_info = { +const struct sh_pfc_soc_info r8a77950_pinmux_info = { .name = "r8a77950_pfc", - .ops = &r8a7795es1_pinmux_ops, + .ops = &r8a77950_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a77951.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a7795.c rename to drivers/pinctrl/sh-pfc/pfc-r8a77951.c index 0a2ea9544802..f922aa46dba4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77951.c @@ -1,5 +1,5 @@ /* - * R8A7795 ES2.0+ processor support - PFC hardware block. + * R8A77951 processor support - PFC hardware block. * * Copyright (C) 2015-2019 Renesas Electronics Corporation * @@ -5918,7 +5918,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc, + unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -6175,8 +6176,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) +static unsigned int r8a77951_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) { const struct pinmux_bias_reg *reg; unsigned int bit; @@ -6193,8 +6194,8 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, return PIN_CONFIG_BIAS_PULL_DOWN; } -static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) +static void r8a77951_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) { const struct pinmux_bias_reg *reg; u32 enable, updown; @@ -6216,29 +6217,15 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, sh_pfc_write(pfc, reg->puen, enable); } -static const struct soc_device_attribute r8a7795es1[] = { - { .soc_id = "r8a7795", .revision = "ES1.*" }, - { /* sentinel */ } +static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { + .pin_to_pocctrl = r8a77951_pin_to_pocctrl, + .get_bias = r8a77951_pinmux_get_bias, + .set_bias = r8a77951_pinmux_set_bias, }; -static int r8a7795_pinmux_init(struct sh_pfc *pfc) -{ - if (soc_device_match(r8a7795es1)) - pfc->info = &r8a7795es1_pinmux_info; - - return 0; -} - -static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = { - .init = r8a7795_pinmux_init, - .pin_to_pocctrl = r8a7795_pin_to_pocctrl, - .get_bias = r8a7795_pinmux_get_bias, - .set_bias = r8a7795_pinmux_set_bias, -}; - -const struct sh_pfc_soc_info r8a7795_pinmux_info = { +const struct sh_pfc_soc_info r8a77951_pinmux_info = { .name = "r8a77951_pfc", - .ops = &r8a7795_pinmux_ops, + .ops = &r8a77951_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index e66595940584..e8e1e1a8a7cf 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -320,8 +320,8 @@ extern const struct sh_pfc_soc_info r8a7791_pinmux_info; extern const struct sh_pfc_soc_info r8a7792_pinmux_info; extern const struct sh_pfc_soc_info r8a7793_pinmux_info; extern const struct sh_pfc_soc_info r8a7794_pinmux_info; -extern const struct sh_pfc_soc_info r8a7795_pinmux_info; -extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info; +extern const struct sh_pfc_soc_info r8a77950_pinmux_info __weak; +extern const struct sh_pfc_soc_info r8a77951_pinmux_info __weak; extern const struct sh_pfc_soc_info r8a7796_pinmux_info; extern const struct sh_pfc_soc_info r8a77965_pinmux_info; extern const struct sh_pfc_soc_info r8a77970_pinmux_info; From patchwork Fri Aug 21 09:43:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729095 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E216F17CF for ; Fri, 21 Aug 2020 10:58:40 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BD8492072D for ; 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Fri, 21 Aug 2020 18:44:11 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 31/36] dt-bindings: pinctrl: sh-pfc: Document r8a774e1 PFC support Date: Fri, 21 Aug 2020 10:43:07 +0100 Message-Id: <20200821094312.3249-32-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: deHwUdYq3PY8pesOad4BPT6Qx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007520; bh=m0u1m1m3UIB+R8VNXlwd/XQ25mUrRYLbuXG8JoNyEWM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=C7KDclmxJxKJzmxRi2+ygZCLTpGMWAAQ9SVzhApZcLLoEGsdZ6lcm7lUrv3auFgAQSg e03nnV3S5cuGu7qcG7MPT8NF/es40BTaqjQoFbb7xHDH6o9dr5GNzOySWXrXafNgxv9JY Mf/73g81lg/36nQxw/EbZXPdP4tnAEpKEZE= From: Marian-Cristian Rotariu commit d33cfc2e591a90f540cd696240ff953b8aaba17d upstream. Document PFC support for the RZ/G2H (R8A774E1) SoC. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-12-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- .../devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index 62ef37aa1e18..a06e0e88a3d8 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -19,6 +19,7 @@ Required Properties: - "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller. - "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller. - "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller. + - "renesas,pfc-r8a774e1": for R8A774E1 (RZ/G2H) compatible pin-controller. - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller. - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. From patchwork Fri Aug 21 09:43:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729097 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0F909175D for ; Fri, 21 Aug 2020 10:58:41 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DBE97207BB for ; Fri, 21 Aug 2020 10:58:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="ZHFRAlOi" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DBE97207BB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5199+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id sPymYY4521763xLDp3FoqKHR; Fri, 21 Aug 2020 03:58:40 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.130439.1598003056666915018 for ; Fri, 21 Aug 2020 02:44:17 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="55170383" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 21 Aug 2020 18:44:16 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 030694232078; Fri, 21 Aug 2020 18:44:13 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 32/36] pinctrl: sh-pfc: pfc-r8a77951: Add R8A774E1 PFC support Date: Fri, 21 Aug 2020 10:43:08 +0100 Message-Id: <20200821094312.3249-33-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: l9vV4QtwoyMwYNeT5R3sBTZJx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007520; bh=26ARMcbu65LeBkstJ+847hLHF1k8gCB6KiAmIDKbshA=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=ZHFRAlOiPUQLBoXgKuP+/A+AfpCJfVjdu6U9JaOeFXflwkz2Wsf1dy2Nq8fwg/fFepT 7k8IHnd/YWsJOq70Fn0duJ2PwoV42G1zTR+wRb09m6piaxWcgmstAQX2kh8xPsyuzA9+6 l0PLYXvrNaZZOLdFEVZ6bNCqWmE8kR2eZ5U= From: Lad Prabhakar commit a5e8b53adeb4b458971dfd6232b71299010e981a upstream. Renesas RZ/G2H (r8a774e1) is pin compatible with R-Car H3 (R8A77951), however it doesn't have several automotive specific peripherals. Add automotive-specific pin groups/functions along with common pin groups/functions for supporting both r8a77951 and r8a774e1 SoC. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-13-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [biju: updated config file for 4.19.y-cip] Signed-off-by: Biju Das --- drivers/pinctrl/sh-pfc/Kconfig | 5 + drivers/pinctrl/sh-pfc/Makefile | 1 + drivers/pinctrl/sh-pfc/core.c | 6 + drivers/pinctrl/sh-pfc/pfc-r8a77951.c | 877 ++++++++++++++------------ drivers/pinctrl/sh-pfc/sh_pfc.h | 1 + 5 files changed, 475 insertions(+), 415 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 77f606928220..6161f906668b 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -64,6 +64,11 @@ config PINCTRL_PFC_R8A774C0 depends on ARCH_R8A774C0 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A774E1 + def_bool y + depends on ARCH_R8A774E1 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A7778 def_bool y depends on ARCH_R8A7778 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 930be8cf259f..8f65494b1bff 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77470) += pfc-r8a77470.o obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o obj-$(CONFIG_PINCTRL_PFC_R8A774C0) += pfc-r8a77990.o +obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a77951.o obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 53cb82a7aa5d..1b4bc27d1911 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -528,6 +528,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a774c0_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A774E1 + { + .compatible = "renesas,pfc-r8a774e1", + .data = &r8a774e1_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7778 { .compatible = "renesas,pfc-r8a7778", diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77951.c b/drivers/pinctrl/sh-pfc/pfc-r8a77951.c index f922aa46dba4..c2d0269417ea 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77951.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77951.c @@ -4160,357 +4160,365 @@ static const unsigned int vin5_clk_mux[] = { VI5_CLK_MARK, }; -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(audio_clk_a_a), - SH_PFC_PIN_GROUP(audio_clk_a_b), - SH_PFC_PIN_GROUP(audio_clk_a_c), - SH_PFC_PIN_GROUP(audio_clk_b_a), - SH_PFC_PIN_GROUP(audio_clk_b_b), - SH_PFC_PIN_GROUP(audio_clk_c_a), - SH_PFC_PIN_GROUP(audio_clk_c_b), - SH_PFC_PIN_GROUP(audio_clkout_a), - SH_PFC_PIN_GROUP(audio_clkout_b), - SH_PFC_PIN_GROUP(audio_clkout_c), - SH_PFC_PIN_GROUP(audio_clkout_d), - SH_PFC_PIN_GROUP(audio_clkout1_a), - SH_PFC_PIN_GROUP(audio_clkout1_b), - SH_PFC_PIN_GROUP(audio_clkout2_a), - SH_PFC_PIN_GROUP(audio_clkout2_b), - SH_PFC_PIN_GROUP(audio_clkout3_a), - SH_PFC_PIN_GROUP(audio_clkout3_b), - SH_PFC_PIN_GROUP(avb_link), - SH_PFC_PIN_GROUP(avb_magic), - SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ - SH_PFC_PIN_GROUP(avb_mdio), - SH_PFC_PIN_GROUP(avb_mii), - SH_PFC_PIN_GROUP(avb_avtp_pps), - SH_PFC_PIN_GROUP(avb_avtp_match_a), - SH_PFC_PIN_GROUP(avb_avtp_capture_a), - SH_PFC_PIN_GROUP(avb_avtp_match_b), - SH_PFC_PIN_GROUP(avb_avtp_capture_b), - SH_PFC_PIN_GROUP(can0_data_a), - SH_PFC_PIN_GROUP(can0_data_b), - SH_PFC_PIN_GROUP(can1_data), - SH_PFC_PIN_GROUP(can_clk), - SH_PFC_PIN_GROUP(canfd0_data_a), - SH_PFC_PIN_GROUP(canfd0_data_b), - SH_PFC_PIN_GROUP(canfd1_data), - SH_PFC_PIN_GROUP(drif0_ctrl_a), - SH_PFC_PIN_GROUP(drif0_data0_a), - SH_PFC_PIN_GROUP(drif0_data1_a), - SH_PFC_PIN_GROUP(drif0_ctrl_b), - SH_PFC_PIN_GROUP(drif0_data0_b), - SH_PFC_PIN_GROUP(drif0_data1_b), - SH_PFC_PIN_GROUP(drif0_ctrl_c), - SH_PFC_PIN_GROUP(drif0_data0_c), - SH_PFC_PIN_GROUP(drif0_data1_c), - SH_PFC_PIN_GROUP(drif1_ctrl_a), - SH_PFC_PIN_GROUP(drif1_data0_a), - SH_PFC_PIN_GROUP(drif1_data1_a), - SH_PFC_PIN_GROUP(drif1_ctrl_b), - SH_PFC_PIN_GROUP(drif1_data0_b), - SH_PFC_PIN_GROUP(drif1_data1_b), - SH_PFC_PIN_GROUP(drif1_ctrl_c), - SH_PFC_PIN_GROUP(drif1_data0_c), - SH_PFC_PIN_GROUP(drif1_data1_c), - SH_PFC_PIN_GROUP(drif2_ctrl_a), - SH_PFC_PIN_GROUP(drif2_data0_a), - SH_PFC_PIN_GROUP(drif2_data1_a), - SH_PFC_PIN_GROUP(drif2_ctrl_b), - SH_PFC_PIN_GROUP(drif2_data0_b), - SH_PFC_PIN_GROUP(drif2_data1_b), - SH_PFC_PIN_GROUP(drif3_ctrl_a), - SH_PFC_PIN_GROUP(drif3_data0_a), - SH_PFC_PIN_GROUP(drif3_data1_a), - SH_PFC_PIN_GROUP(drif3_ctrl_b), - SH_PFC_PIN_GROUP(drif3_data0_b), - SH_PFC_PIN_GROUP(drif3_data1_b), - SH_PFC_PIN_GROUP(du_rgb666), - SH_PFC_PIN_GROUP(du_rgb888), - SH_PFC_PIN_GROUP(du_clk_out_0), - SH_PFC_PIN_GROUP(du_clk_out_1), - SH_PFC_PIN_GROUP(du_sync), - SH_PFC_PIN_GROUP(du_oddf), - SH_PFC_PIN_GROUP(du_cde), - SH_PFC_PIN_GROUP(du_disp), - SH_PFC_PIN_GROUP(hscif0_data), - SH_PFC_PIN_GROUP(hscif0_clk), - SH_PFC_PIN_GROUP(hscif0_ctrl), - SH_PFC_PIN_GROUP(hscif1_data_a), - SH_PFC_PIN_GROUP(hscif1_clk_a), - SH_PFC_PIN_GROUP(hscif1_ctrl_a), - SH_PFC_PIN_GROUP(hscif1_data_b), - SH_PFC_PIN_GROUP(hscif1_clk_b), - SH_PFC_PIN_GROUP(hscif1_ctrl_b), - SH_PFC_PIN_GROUP(hscif2_data_a), - SH_PFC_PIN_GROUP(hscif2_clk_a), - SH_PFC_PIN_GROUP(hscif2_ctrl_a), - SH_PFC_PIN_GROUP(hscif2_data_b), - SH_PFC_PIN_GROUP(hscif2_clk_b), - SH_PFC_PIN_GROUP(hscif2_ctrl_b), - SH_PFC_PIN_GROUP(hscif2_data_c), - SH_PFC_PIN_GROUP(hscif2_clk_c), - SH_PFC_PIN_GROUP(hscif2_ctrl_c), - SH_PFC_PIN_GROUP(hscif3_data_a), - SH_PFC_PIN_GROUP(hscif3_clk), - SH_PFC_PIN_GROUP(hscif3_ctrl), - SH_PFC_PIN_GROUP(hscif3_data_b), - SH_PFC_PIN_GROUP(hscif3_data_c), - SH_PFC_PIN_GROUP(hscif3_data_d), - SH_PFC_PIN_GROUP(hscif4_data_a), - SH_PFC_PIN_GROUP(hscif4_clk), - SH_PFC_PIN_GROUP(hscif4_ctrl), - SH_PFC_PIN_GROUP(hscif4_data_b), - SH_PFC_PIN_GROUP(i2c0), - SH_PFC_PIN_GROUP(i2c1_a), - SH_PFC_PIN_GROUP(i2c1_b), - SH_PFC_PIN_GROUP(i2c2_a), - SH_PFC_PIN_GROUP(i2c2_b), - SH_PFC_PIN_GROUP(i2c3), - SH_PFC_PIN_GROUP(i2c5), - SH_PFC_PIN_GROUP(i2c6_a), - SH_PFC_PIN_GROUP(i2c6_b), - SH_PFC_PIN_GROUP(i2c6_c), - SH_PFC_PIN_GROUP(intc_ex_irq0), - SH_PFC_PIN_GROUP(intc_ex_irq1), - SH_PFC_PIN_GROUP(intc_ex_irq2), - SH_PFC_PIN_GROUP(intc_ex_irq3), - SH_PFC_PIN_GROUP(intc_ex_irq4), - SH_PFC_PIN_GROUP(intc_ex_irq5), - SH_PFC_PIN_GROUP(msiof0_clk), - SH_PFC_PIN_GROUP(msiof0_sync), - SH_PFC_PIN_GROUP(msiof0_ss1), - SH_PFC_PIN_GROUP(msiof0_ss2), - SH_PFC_PIN_GROUP(msiof0_txd), - SH_PFC_PIN_GROUP(msiof0_rxd), - SH_PFC_PIN_GROUP(msiof1_clk_a), - SH_PFC_PIN_GROUP(msiof1_sync_a), - SH_PFC_PIN_GROUP(msiof1_ss1_a), - SH_PFC_PIN_GROUP(msiof1_ss2_a), - SH_PFC_PIN_GROUP(msiof1_txd_a), - SH_PFC_PIN_GROUP(msiof1_rxd_a), - SH_PFC_PIN_GROUP(msiof1_clk_b), - SH_PFC_PIN_GROUP(msiof1_sync_b), - SH_PFC_PIN_GROUP(msiof1_ss1_b), - SH_PFC_PIN_GROUP(msiof1_ss2_b), - SH_PFC_PIN_GROUP(msiof1_txd_b), - SH_PFC_PIN_GROUP(msiof1_rxd_b), - SH_PFC_PIN_GROUP(msiof1_clk_c), - SH_PFC_PIN_GROUP(msiof1_sync_c), - SH_PFC_PIN_GROUP(msiof1_ss1_c), - SH_PFC_PIN_GROUP(msiof1_ss2_c), - SH_PFC_PIN_GROUP(msiof1_txd_c), - SH_PFC_PIN_GROUP(msiof1_rxd_c), - SH_PFC_PIN_GROUP(msiof1_clk_d), - SH_PFC_PIN_GROUP(msiof1_sync_d), - SH_PFC_PIN_GROUP(msiof1_ss1_d), - SH_PFC_PIN_GROUP(msiof1_ss2_d), - SH_PFC_PIN_GROUP(msiof1_txd_d), - SH_PFC_PIN_GROUP(msiof1_rxd_d), - SH_PFC_PIN_GROUP(msiof1_clk_e), - SH_PFC_PIN_GROUP(msiof1_sync_e), - SH_PFC_PIN_GROUP(msiof1_ss1_e), - SH_PFC_PIN_GROUP(msiof1_ss2_e), - SH_PFC_PIN_GROUP(msiof1_txd_e), - SH_PFC_PIN_GROUP(msiof1_rxd_e), - SH_PFC_PIN_GROUP(msiof1_clk_f), - SH_PFC_PIN_GROUP(msiof1_sync_f), - SH_PFC_PIN_GROUP(msiof1_ss1_f), - SH_PFC_PIN_GROUP(msiof1_ss2_f), - SH_PFC_PIN_GROUP(msiof1_txd_f), - SH_PFC_PIN_GROUP(msiof1_rxd_f), - SH_PFC_PIN_GROUP(msiof1_clk_g), - SH_PFC_PIN_GROUP(msiof1_sync_g), - SH_PFC_PIN_GROUP(msiof1_ss1_g), - SH_PFC_PIN_GROUP(msiof1_ss2_g), - SH_PFC_PIN_GROUP(msiof1_txd_g), - SH_PFC_PIN_GROUP(msiof1_rxd_g), - SH_PFC_PIN_GROUP(msiof2_clk_a), - SH_PFC_PIN_GROUP(msiof2_sync_a), - SH_PFC_PIN_GROUP(msiof2_ss1_a), - SH_PFC_PIN_GROUP(msiof2_ss2_a), - SH_PFC_PIN_GROUP(msiof2_txd_a), - SH_PFC_PIN_GROUP(msiof2_rxd_a), - SH_PFC_PIN_GROUP(msiof2_clk_b), - SH_PFC_PIN_GROUP(msiof2_sync_b), - SH_PFC_PIN_GROUP(msiof2_ss1_b), - SH_PFC_PIN_GROUP(msiof2_ss2_b), - SH_PFC_PIN_GROUP(msiof2_txd_b), - SH_PFC_PIN_GROUP(msiof2_rxd_b), - SH_PFC_PIN_GROUP(msiof2_clk_c), - SH_PFC_PIN_GROUP(msiof2_sync_c), - SH_PFC_PIN_GROUP(msiof2_ss1_c), - SH_PFC_PIN_GROUP(msiof2_ss2_c), - SH_PFC_PIN_GROUP(msiof2_txd_c), - SH_PFC_PIN_GROUP(msiof2_rxd_c), - SH_PFC_PIN_GROUP(msiof2_clk_d), - SH_PFC_PIN_GROUP(msiof2_sync_d), - SH_PFC_PIN_GROUP(msiof2_ss1_d), - SH_PFC_PIN_GROUP(msiof2_ss2_d), - SH_PFC_PIN_GROUP(msiof2_txd_d), - SH_PFC_PIN_GROUP(msiof2_rxd_d), - SH_PFC_PIN_GROUP(msiof3_clk_a), - SH_PFC_PIN_GROUP(msiof3_sync_a), - SH_PFC_PIN_GROUP(msiof3_ss1_a), - SH_PFC_PIN_GROUP(msiof3_ss2_a), - SH_PFC_PIN_GROUP(msiof3_txd_a), - SH_PFC_PIN_GROUP(msiof3_rxd_a), - SH_PFC_PIN_GROUP(msiof3_clk_b), - SH_PFC_PIN_GROUP(msiof3_sync_b), - SH_PFC_PIN_GROUP(msiof3_ss1_b), - SH_PFC_PIN_GROUP(msiof3_ss2_b), - SH_PFC_PIN_GROUP(msiof3_txd_b), - SH_PFC_PIN_GROUP(msiof3_rxd_b), - SH_PFC_PIN_GROUP(msiof3_clk_c), - SH_PFC_PIN_GROUP(msiof3_sync_c), - SH_PFC_PIN_GROUP(msiof3_txd_c), - SH_PFC_PIN_GROUP(msiof3_rxd_c), - SH_PFC_PIN_GROUP(msiof3_clk_d), - SH_PFC_PIN_GROUP(msiof3_sync_d), - SH_PFC_PIN_GROUP(msiof3_ss1_d), - SH_PFC_PIN_GROUP(msiof3_txd_d), - SH_PFC_PIN_GROUP(msiof3_rxd_d), - SH_PFC_PIN_GROUP(msiof3_clk_e), - SH_PFC_PIN_GROUP(msiof3_sync_e), - SH_PFC_PIN_GROUP(msiof3_ss1_e), - SH_PFC_PIN_GROUP(msiof3_ss2_e), - SH_PFC_PIN_GROUP(msiof3_txd_e), - SH_PFC_PIN_GROUP(msiof3_rxd_e), - SH_PFC_PIN_GROUP(pwm0), - SH_PFC_PIN_GROUP(pwm1_a), - SH_PFC_PIN_GROUP(pwm1_b), - SH_PFC_PIN_GROUP(pwm2_a), - SH_PFC_PIN_GROUP(pwm2_b), - SH_PFC_PIN_GROUP(pwm3_a), - SH_PFC_PIN_GROUP(pwm3_b), - SH_PFC_PIN_GROUP(pwm4_a), - SH_PFC_PIN_GROUP(pwm4_b), - SH_PFC_PIN_GROUP(pwm5_a), - SH_PFC_PIN_GROUP(pwm5_b), - SH_PFC_PIN_GROUP(pwm6_a), - SH_PFC_PIN_GROUP(pwm6_b), - SH_PFC_PIN_GROUP(sata0_devslp_a), - SH_PFC_PIN_GROUP(sata0_devslp_b), - SH_PFC_PIN_GROUP(scif0_data), - SH_PFC_PIN_GROUP(scif0_clk), - SH_PFC_PIN_GROUP(scif0_ctrl), - SH_PFC_PIN_GROUP(scif1_data_a), - SH_PFC_PIN_GROUP(scif1_clk), - SH_PFC_PIN_GROUP(scif1_ctrl), - SH_PFC_PIN_GROUP(scif1_data_b), - SH_PFC_PIN_GROUP(scif2_data_a), - SH_PFC_PIN_GROUP(scif2_clk), - SH_PFC_PIN_GROUP(scif2_data_b), - SH_PFC_PIN_GROUP(scif3_data_a), - SH_PFC_PIN_GROUP(scif3_clk), - SH_PFC_PIN_GROUP(scif3_ctrl), - SH_PFC_PIN_GROUP(scif3_data_b), - SH_PFC_PIN_GROUP(scif4_data_a), - SH_PFC_PIN_GROUP(scif4_clk_a), - SH_PFC_PIN_GROUP(scif4_ctrl_a), - SH_PFC_PIN_GROUP(scif4_data_b), - SH_PFC_PIN_GROUP(scif4_clk_b), - SH_PFC_PIN_GROUP(scif4_ctrl_b), - SH_PFC_PIN_GROUP(scif4_data_c), - SH_PFC_PIN_GROUP(scif4_clk_c), - SH_PFC_PIN_GROUP(scif4_ctrl_c), - SH_PFC_PIN_GROUP(scif5_data_a), - SH_PFC_PIN_GROUP(scif5_clk_a), - SH_PFC_PIN_GROUP(scif5_data_b), - SH_PFC_PIN_GROUP(scif5_clk_b), - SH_PFC_PIN_GROUP(scif_clk_a), - SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi1_cd), - SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(sdhi2_cd_a), - SH_PFC_PIN_GROUP(sdhi2_wp_a), - SH_PFC_PIN_GROUP(sdhi2_cd_b), - SH_PFC_PIN_GROUP(sdhi2_wp_b), - SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), - SH_PFC_PIN_GROUP(sdhi3_ctrl), - SH_PFC_PIN_GROUP(sdhi3_cd), - SH_PFC_PIN_GROUP(sdhi3_wp), - SH_PFC_PIN_GROUP(sdhi3_ds), - SH_PFC_PIN_GROUP(ssi0_data), - SH_PFC_PIN_GROUP(ssi01239_ctrl), - SH_PFC_PIN_GROUP(ssi1_data_a), - SH_PFC_PIN_GROUP(ssi1_data_b), - SH_PFC_PIN_GROUP(ssi1_ctrl_a), - SH_PFC_PIN_GROUP(ssi1_ctrl_b), - SH_PFC_PIN_GROUP(ssi2_data_a), - SH_PFC_PIN_GROUP(ssi2_data_b), - SH_PFC_PIN_GROUP(ssi2_ctrl_a), - SH_PFC_PIN_GROUP(ssi2_ctrl_b), - SH_PFC_PIN_GROUP(ssi3_data), - SH_PFC_PIN_GROUP(ssi349_ctrl), - SH_PFC_PIN_GROUP(ssi4_data), - SH_PFC_PIN_GROUP(ssi4_ctrl), - SH_PFC_PIN_GROUP(ssi5_data), - SH_PFC_PIN_GROUP(ssi5_ctrl), - SH_PFC_PIN_GROUP(ssi6_data), - SH_PFC_PIN_GROUP(ssi6_ctrl), - SH_PFC_PIN_GROUP(ssi7_data), - SH_PFC_PIN_GROUP(ssi78_ctrl), - SH_PFC_PIN_GROUP(ssi8_data), - SH_PFC_PIN_GROUP(ssi9_data_a), - SH_PFC_PIN_GROUP(ssi9_data_b), - SH_PFC_PIN_GROUP(ssi9_ctrl_a), - SH_PFC_PIN_GROUP(ssi9_ctrl_b), - SH_PFC_PIN_GROUP(tmu_tclk1_a), - SH_PFC_PIN_GROUP(tmu_tclk1_b), - SH_PFC_PIN_GROUP(tmu_tclk2_a), - SH_PFC_PIN_GROUP(tmu_tclk2_b), - SH_PFC_PIN_GROUP(tpu_to0), - SH_PFC_PIN_GROUP(tpu_to1), - SH_PFC_PIN_GROUP(tpu_to2), - SH_PFC_PIN_GROUP(tpu_to3), - SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb1), - SH_PFC_PIN_GROUP(usb2), - SH_PFC_PIN_GROUP(usb2_ch3), - SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), - SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), - SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), - SH_PFC_PIN_GROUP(vin4_sync), - SH_PFC_PIN_GROUP(vin4_field), - SH_PFC_PIN_GROUP(vin4_clkenb), - SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 16), - SH_PFC_PIN_GROUP(vin5_sync), - SH_PFC_PIN_GROUP(vin5_field), - SH_PFC_PIN_GROUP(vin5_clkenb), - SH_PFC_PIN_GROUP(vin5_clk), +static const struct { + struct sh_pfc_pin_group common[320]; + struct sh_pfc_pin_group automotive[30]; +} pinmux_groups = { + .common = { + SH_PFC_PIN_GROUP(audio_clk_a_a), + SH_PFC_PIN_GROUP(audio_clk_a_b), + SH_PFC_PIN_GROUP(audio_clk_a_c), + SH_PFC_PIN_GROUP(audio_clk_b_a), + SH_PFC_PIN_GROUP(audio_clk_b_b), + SH_PFC_PIN_GROUP(audio_clk_c_a), + SH_PFC_PIN_GROUP(audio_clk_c_b), + SH_PFC_PIN_GROUP(audio_clkout_a), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout_c), + SH_PFC_PIN_GROUP(audio_clkout_d), + SH_PFC_PIN_GROUP(audio_clkout1_a), + SH_PFC_PIN_GROUP(audio_clkout1_b), + SH_PFC_PIN_GROUP(audio_clkout2_a), + SH_PFC_PIN_GROUP(audio_clkout2_b), + SH_PFC_PIN_GROUP(audio_clkout3_a), + SH_PFC_PIN_GROUP(audio_clkout3_b), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_avtp_pps), + SH_PFC_PIN_GROUP(avb_avtp_match_a), + SH_PFC_PIN_GROUP(avb_avtp_capture_a), + SH_PFC_PIN_GROUP(avb_avtp_match_b), + SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(can0_data_a), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data_a), + SH_PFC_PIN_GROUP(canfd0_data_b), + SH_PFC_PIN_GROUP(canfd1_data), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_sync), + SH_PFC_PIN_GROUP(du_oddf), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_ctrl_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_a), + SH_PFC_PIN_GROUP(hscif2_clk_a), + SH_PFC_PIN_GROUP(hscif2_ctrl_a), + SH_PFC_PIN_GROUP(hscif2_data_b), + SH_PFC_PIN_GROUP(hscif2_clk_b), + SH_PFC_PIN_GROUP(hscif2_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_c), + SH_PFC_PIN_GROUP(hscif2_clk_c), + SH_PFC_PIN_GROUP(hscif2_ctrl_c), + SH_PFC_PIN_GROUP(hscif3_data_a), + SH_PFC_PIN_GROUP(hscif3_clk), + SH_PFC_PIN_GROUP(hscif3_ctrl), + SH_PFC_PIN_GROUP(hscif3_data_b), + SH_PFC_PIN_GROUP(hscif3_data_c), + SH_PFC_PIN_GROUP(hscif3_data_d), + SH_PFC_PIN_GROUP(hscif4_data_a), + SH_PFC_PIN_GROUP(hscif4_clk), + SH_PFC_PIN_GROUP(hscif4_ctrl), + SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c2_a), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c5), + SH_PFC_PIN_GROUP(i2c6_a), + SH_PFC_PIN_GROUP(i2c6_b), + SH_PFC_PIN_GROUP(i2c6_c), + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_rxd), + SH_PFC_PIN_GROUP(msiof1_clk_a), + SH_PFC_PIN_GROUP(msiof1_sync_a), + SH_PFC_PIN_GROUP(msiof1_ss1_a), + SH_PFC_PIN_GROUP(msiof1_ss2_a), + SH_PFC_PIN_GROUP(msiof1_txd_a), + SH_PFC_PIN_GROUP(msiof1_rxd_a), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_sync_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_txd_b), + SH_PFC_PIN_GROUP(msiof1_rxd_b), + SH_PFC_PIN_GROUP(msiof1_clk_c), + SH_PFC_PIN_GROUP(msiof1_sync_c), + SH_PFC_PIN_GROUP(msiof1_ss1_c), + SH_PFC_PIN_GROUP(msiof1_ss2_c), + SH_PFC_PIN_GROUP(msiof1_txd_c), + SH_PFC_PIN_GROUP(msiof1_rxd_c), + SH_PFC_PIN_GROUP(msiof1_clk_d), + SH_PFC_PIN_GROUP(msiof1_sync_d), + SH_PFC_PIN_GROUP(msiof1_ss1_d), + SH_PFC_PIN_GROUP(msiof1_ss2_d), + SH_PFC_PIN_GROUP(msiof1_txd_d), + SH_PFC_PIN_GROUP(msiof1_rxd_d), + SH_PFC_PIN_GROUP(msiof1_clk_e), + SH_PFC_PIN_GROUP(msiof1_sync_e), + SH_PFC_PIN_GROUP(msiof1_ss1_e), + SH_PFC_PIN_GROUP(msiof1_ss2_e), + SH_PFC_PIN_GROUP(msiof1_txd_e), + SH_PFC_PIN_GROUP(msiof1_rxd_e), + SH_PFC_PIN_GROUP(msiof1_clk_f), + SH_PFC_PIN_GROUP(msiof1_sync_f), + SH_PFC_PIN_GROUP(msiof1_ss1_f), + SH_PFC_PIN_GROUP(msiof1_ss2_f), + SH_PFC_PIN_GROUP(msiof1_txd_f), + SH_PFC_PIN_GROUP(msiof1_rxd_f), + SH_PFC_PIN_GROUP(msiof1_clk_g), + SH_PFC_PIN_GROUP(msiof1_sync_g), + SH_PFC_PIN_GROUP(msiof1_ss1_g), + SH_PFC_PIN_GROUP(msiof1_ss2_g), + SH_PFC_PIN_GROUP(msiof1_txd_g), + SH_PFC_PIN_GROUP(msiof1_rxd_g), + SH_PFC_PIN_GROUP(msiof2_clk_a), + SH_PFC_PIN_GROUP(msiof2_sync_a), + SH_PFC_PIN_GROUP(msiof2_ss1_a), + SH_PFC_PIN_GROUP(msiof2_ss2_a), + SH_PFC_PIN_GROUP(msiof2_txd_a), + SH_PFC_PIN_GROUP(msiof2_rxd_a), + SH_PFC_PIN_GROUP(msiof2_clk_b), + SH_PFC_PIN_GROUP(msiof2_sync_b), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_txd_b), + SH_PFC_PIN_GROUP(msiof2_rxd_b), + SH_PFC_PIN_GROUP(msiof2_clk_c), + SH_PFC_PIN_GROUP(msiof2_sync_c), + SH_PFC_PIN_GROUP(msiof2_ss1_c), + SH_PFC_PIN_GROUP(msiof2_ss2_c), + SH_PFC_PIN_GROUP(msiof2_txd_c), + SH_PFC_PIN_GROUP(msiof2_rxd_c), + SH_PFC_PIN_GROUP(msiof2_clk_d), + SH_PFC_PIN_GROUP(msiof2_sync_d), + SH_PFC_PIN_GROUP(msiof2_ss1_d), + SH_PFC_PIN_GROUP(msiof2_ss2_d), + SH_PFC_PIN_GROUP(msiof2_txd_d), + SH_PFC_PIN_GROUP(msiof2_rxd_d), + SH_PFC_PIN_GROUP(msiof3_clk_a), + SH_PFC_PIN_GROUP(msiof3_sync_a), + SH_PFC_PIN_GROUP(msiof3_ss1_a), + SH_PFC_PIN_GROUP(msiof3_ss2_a), + SH_PFC_PIN_GROUP(msiof3_txd_a), + SH_PFC_PIN_GROUP(msiof3_rxd_a), + SH_PFC_PIN_GROUP(msiof3_clk_b), + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_ss1_b), + SH_PFC_PIN_GROUP(msiof3_ss2_b), + SH_PFC_PIN_GROUP(msiof3_txd_b), + SH_PFC_PIN_GROUP(msiof3_rxd_b), + SH_PFC_PIN_GROUP(msiof3_clk_c), + SH_PFC_PIN_GROUP(msiof3_sync_c), + SH_PFC_PIN_GROUP(msiof3_txd_c), + SH_PFC_PIN_GROUP(msiof3_rxd_c), + SH_PFC_PIN_GROUP(msiof3_clk_d), + SH_PFC_PIN_GROUP(msiof3_sync_d), + SH_PFC_PIN_GROUP(msiof3_ss1_d), + SH_PFC_PIN_GROUP(msiof3_txd_d), + SH_PFC_PIN_GROUP(msiof3_rxd_d), + SH_PFC_PIN_GROUP(msiof3_clk_e), + SH_PFC_PIN_GROUP(msiof3_sync_e), + SH_PFC_PIN_GROUP(msiof3_ss1_e), + SH_PFC_PIN_GROUP(msiof3_ss2_e), + SH_PFC_PIN_GROUP(msiof3_txd_e), + SH_PFC_PIN_GROUP(msiof3_rxd_e), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm1_a), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2_a), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm3_a), + SH_PFC_PIN_GROUP(pwm3_b), + SH_PFC_PIN_GROUP(pwm4_a), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(pwm5_a), + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm6_a), + SH_PFC_PIN_GROUP(pwm6_b), + SH_PFC_PIN_GROUP(sata0_devslp_a), + SH_PFC_PIN_GROUP(sata0_devslp_b), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif2_data_a), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif3_data_a), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_ctrl), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif4_data_a), + SH_PFC_PIN_GROUP(scif4_clk_a), + SH_PFC_PIN_GROUP(scif4_ctrl_a), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_clk_b), + SH_PFC_PIN_GROUP(scif4_ctrl_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif4_clk_c), + SH_PFC_PIN_GROUP(scif4_ctrl_c), + SH_PFC_PIN_GROUP(scif5_data_a), + SH_PFC_PIN_GROUP(scif5_clk_a), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scif5_clk_b), + SH_PFC_PIN_GROUP(scif_clk_a), + SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_data8), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd_a), + SH_PFC_PIN_GROUP(sdhi2_wp_a), + SH_PFC_PIN_GROUP(sdhi2_cd_b), + SH_PFC_PIN_GROUP(sdhi2_wp_b), + SH_PFC_PIN_GROUP(sdhi2_ds), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_data8), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(sdhi3_ds), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi01239_ctrl), + SH_PFC_PIN_GROUP(ssi1_data_a), + SH_PFC_PIN_GROUP(ssi1_data_b), + SH_PFC_PIN_GROUP(ssi1_ctrl_a), + SH_PFC_PIN_GROUP(ssi1_ctrl_b), + SH_PFC_PIN_GROUP(ssi2_data_a), + SH_PFC_PIN_GROUP(ssi2_data_b), + SH_PFC_PIN_GROUP(ssi2_ctrl_a), + SH_PFC_PIN_GROUP(ssi2_ctrl_b), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi349_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5_data), + SH_PFC_PIN_GROUP(ssi5_ctrl), + SH_PFC_PIN_GROUP(ssi6_data), + SH_PFC_PIN_GROUP(ssi6_ctrl), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi9_data_a), + SH_PFC_PIN_GROUP(ssi9_data_b), + SH_PFC_PIN_GROUP(ssi9_ctrl_a), + SH_PFC_PIN_GROUP(ssi9_ctrl_b), + SH_PFC_PIN_GROUP(tmu_tclk1_a), + SH_PFC_PIN_GROUP(tmu_tclk1_b), + SH_PFC_PIN_GROUP(tmu_tclk2_a), + SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb2), + SH_PFC_PIN_GROUP(usb2_ch3), + SH_PFC_PIN_GROUP(usb30), + VIN_DATA_PIN_GROUP(vin4_data, 8, _a), + VIN_DATA_PIN_GROUP(vin4_data, 10, _a), + VIN_DATA_PIN_GROUP(vin4_data, 12, _a), + VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + SH_PFC_PIN_GROUP(vin4_data18_a), + VIN_DATA_PIN_GROUP(vin4_data, 20, _a), + VIN_DATA_PIN_GROUP(vin4_data, 24, _a), + VIN_DATA_PIN_GROUP(vin4_data, 8, _b), + VIN_DATA_PIN_GROUP(vin4_data, 10, _b), + VIN_DATA_PIN_GROUP(vin4_data, 12, _b), + VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + SH_PFC_PIN_GROUP(vin4_data18_b), + VIN_DATA_PIN_GROUP(vin4_data, 20, _b), + VIN_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP(vin4_sync), + SH_PFC_PIN_GROUP(vin4_field), + SH_PFC_PIN_GROUP(vin4_clkenb), + SH_PFC_PIN_GROUP(vin4_clk), + VIN_DATA_PIN_GROUP(vin5_data, 8), + VIN_DATA_PIN_GROUP(vin5_data, 10), + VIN_DATA_PIN_GROUP(vin5_data, 12), + VIN_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP(vin5_sync), + SH_PFC_PIN_GROUP(vin5_field), + SH_PFC_PIN_GROUP(vin5_clkenb), + SH_PFC_PIN_GROUP(vin5_clk), + }, + .automotive = { + SH_PFC_PIN_GROUP(drif0_ctrl_a), + SH_PFC_PIN_GROUP(drif0_data0_a), + SH_PFC_PIN_GROUP(drif0_data1_a), + SH_PFC_PIN_GROUP(drif0_ctrl_b), + SH_PFC_PIN_GROUP(drif0_data0_b), + SH_PFC_PIN_GROUP(drif0_data1_b), + SH_PFC_PIN_GROUP(drif0_ctrl_c), + SH_PFC_PIN_GROUP(drif0_data0_c), + SH_PFC_PIN_GROUP(drif0_data1_c), + SH_PFC_PIN_GROUP(drif1_ctrl_a), + SH_PFC_PIN_GROUP(drif1_data0_a), + SH_PFC_PIN_GROUP(drif1_data1_a), + SH_PFC_PIN_GROUP(drif1_ctrl_b), + SH_PFC_PIN_GROUP(drif1_data0_b), + SH_PFC_PIN_GROUP(drif1_data1_b), + SH_PFC_PIN_GROUP(drif1_ctrl_c), + SH_PFC_PIN_GROUP(drif1_data0_c), + SH_PFC_PIN_GROUP(drif1_data1_c), + SH_PFC_PIN_GROUP(drif2_ctrl_a), + SH_PFC_PIN_GROUP(drif2_data0_a), + SH_PFC_PIN_GROUP(drif2_data1_a), + SH_PFC_PIN_GROUP(drif2_ctrl_b), + SH_PFC_PIN_GROUP(drif2_data0_b), + SH_PFC_PIN_GROUP(drif2_data1_b), + SH_PFC_PIN_GROUP(drif3_ctrl_a), + SH_PFC_PIN_GROUP(drif3_data0_a), + SH_PFC_PIN_GROUP(drif3_data1_a), + SH_PFC_PIN_GROUP(drif3_ctrl_b), + SH_PFC_PIN_GROUP(drif3_data0_b), + SH_PFC_PIN_GROUP(drif3_data1_b), + } + }; static const char * const audio_clk_groups[] = { @@ -5034,64 +5042,72 @@ static const char * const vin5_groups[] = { "vin5_clk", }; -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(audio_clk), - SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(can0), - SH_PFC_FUNCTION(can1), - SH_PFC_FUNCTION(can_clk), - SH_PFC_FUNCTION(canfd0), - SH_PFC_FUNCTION(canfd1), - SH_PFC_FUNCTION(drif0), - SH_PFC_FUNCTION(drif1), - SH_PFC_FUNCTION(drif2), - SH_PFC_FUNCTION(drif3), - SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(hscif0), - SH_PFC_FUNCTION(hscif1), - SH_PFC_FUNCTION(hscif2), - SH_PFC_FUNCTION(hscif3), - SH_PFC_FUNCTION(hscif4), - SH_PFC_FUNCTION(i2c0), - SH_PFC_FUNCTION(i2c1), - SH_PFC_FUNCTION(i2c2), - SH_PFC_FUNCTION(i2c3), - SH_PFC_FUNCTION(i2c5), - SH_PFC_FUNCTION(i2c6), - SH_PFC_FUNCTION(intc_ex), - SH_PFC_FUNCTION(msiof0), - SH_PFC_FUNCTION(msiof1), - SH_PFC_FUNCTION(msiof2), - SH_PFC_FUNCTION(msiof3), - SH_PFC_FUNCTION(pwm0), - SH_PFC_FUNCTION(pwm1), - SH_PFC_FUNCTION(pwm2), - SH_PFC_FUNCTION(pwm3), - SH_PFC_FUNCTION(pwm4), - SH_PFC_FUNCTION(pwm5), - SH_PFC_FUNCTION(pwm6), - SH_PFC_FUNCTION(sata0), - SH_PFC_FUNCTION(scif0), - SH_PFC_FUNCTION(scif1), - SH_PFC_FUNCTION(scif2), - SH_PFC_FUNCTION(scif3), - SH_PFC_FUNCTION(scif4), - SH_PFC_FUNCTION(scif5), - SH_PFC_FUNCTION(scif_clk), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(sdhi3), - SH_PFC_FUNCTION(ssi), - SH_PFC_FUNCTION(tmu), - SH_PFC_FUNCTION(tpu), - SH_PFC_FUNCTION(usb0), - SH_PFC_FUNCTION(usb1), - SH_PFC_FUNCTION(usb2), - SH_PFC_FUNCTION(usb2_ch3), - SH_PFC_FUNCTION(usb30), - SH_PFC_FUNCTION(vin4), - SH_PFC_FUNCTION(vin5), +static const struct { + struct sh_pfc_function common[53]; + struct sh_pfc_function automotive[4]; +} pinmux_functions = { + .common = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c5), + SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(intc_ex), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(sata0), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tmu), + SH_PFC_FUNCTION(tpu), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), + SH_PFC_FUNCTION(usb2_ch3), + SH_PFC_FUNCTION(usb30), + SH_PFC_FUNCTION(vin4), + SH_PFC_FUNCTION(vin5), + }, + .automotive = { + SH_PFC_FUNCTION(drif0), + SH_PFC_FUNCTION(drif1), + SH_PFC_FUNCTION(drif2), + SH_PFC_FUNCTION(drif3), + } + }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -5780,7 +5796,9 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { +#ifdef CONFIG_PINCTRL_PFC_R8A77951 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ +#endif { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ { PIN_TMS, 4, 2 }, /* TMS */ @@ -5901,8 +5919,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ - { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */ - { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */ + { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */ + { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */ } }, { }, }; @@ -6223,6 +6241,32 @@ static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { .set_bias = r8a77951_pinmux_set_bias, }; +#ifdef CONFIG_PINCTRL_PFC_R8A774E1 +const struct sh_pfc_soc_info r8a774e1_pinmux_info = { + .name = "r8a774e1_pfc", + .ops = &r8a77951_pinmux_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common), + + .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif + +#ifdef CONFIG_PINCTRL_PFC_R8A77951 const struct sh_pfc_soc_info r8a77951_pinmux_info = { .name = "r8a77951_pfc", .ops = &r8a77951_pinmux_ops, @@ -6232,10 +6276,12 @@ const struct sh_pfc_soc_info r8a77951_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + + ARRAY_SIZE(pinmux_groups.automotive), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + + ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, .drive_regs = pinmux_drive_regs, @@ -6245,3 +6291,4 @@ const struct sh_pfc_soc_info r8a77951_pinmux_info = { .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; +#endif diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index e8e1e1a8a7cf..5342031a8a44 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -313,6 +313,7 @@ extern const struct sh_pfc_soc_info r8a77470_pinmux_info; extern const struct sh_pfc_soc_info r8a774a1_pinmux_info; extern const struct sh_pfc_soc_info r8a774b1_pinmux_info; extern const struct sh_pfc_soc_info r8a774c0_pinmux_info; +extern const struct sh_pfc_soc_info r8a774e1_pinmux_info; extern const struct sh_pfc_soc_info r8a7778_pinmux_info; extern const struct sh_pfc_soc_info r8a7779_pinmux_info; extern const struct sh_pfc_soc_info r8a7790_pinmux_info; From patchwork Fri Aug 21 09:43:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729099 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 69B4517D4 for ; Fri, 21 Aug 2020 10:58:41 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C4DD20656 for ; Fri, 21 Aug 2020 10:58:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="PPlo2NPl" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3C4DD20656 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5200+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id LvvRYY4521763xlTYfgaM8zg; Fri, 21 Aug 2020 03:58:41 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.131167.1598003052343639956 for ; Fri, 21 Aug 2020 02:44:18 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954642" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:44:18 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 7E6484232078; Fri, 21 Aug 2020 18:44:16 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 33/36] arm64: dts: renesas: Initial r8a774e1 SoC device tree Date: Fri, 21 Aug 2020 10:43:09 +0100 Message-Id: <20200821094312.3249-34-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: qbZZFQdWfsSQk9QIy325qS0Ox4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007521; bh=HSopQQNSolBPB5akkN1VzHS+FtQdwpGZRnYI4mlw3jU=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=PPlo2NPlPF096OSOOxvO1rVSQDCAenDS8BxxZ3SnBiV7b+jTbZuqsXyneIv1tuNK8N2 oP4qbaPWLdYd+pbv3dOgRncAjAWcppoxTbT3GnR7bkVLMIC1KJoQlj/nc2TK0N2PYWzMX xL3Zk0lEBP+tBKK/zWHUQR0T1A/HJaMoGAs= From: Marian-Cristian Rotariu Basic support for the RZ/G2H SoC. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594230511-24790-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven (cherry picked from commit 4dd61a524539a42180f2140a4744c6fb82905d0c) Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 652 ++++++++++++++++++++++ 1 file changed, 652 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi new file mode 100644 index 000000000000..eb7226e8e892 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -0,0 +1,652 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a774e1 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 + +/ { + compatible = "renesas,r8a774e1"; + #address-cells = <2>; + #size-cells = <2>; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&a57_0>; + }; + core1 { + cpu = <&a57_1>; + }; + core2 { + cpu = <&a57_2>; + }; + core3 { + cpu = <&a57_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&a53_0>; + }; + core1 { + cpu = <&a53_1>; + }; + core2 { + cpu = <&a53_2>; + }; + core3 { + cpu = <&a53_3>; + }; + }; + }; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + dynamic-power-coefficient = <854>; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a57_2: cpu@2 { + compatible = "arm,cortex-a57"; + reg = <0x2>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a57_3: cpu@3 { + compatible = "arm,cortex-a57"; + reg = <0x3>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a53_0: cpu@100 { + compatible = "arm,cortex-a53"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + #cooling-cells = <2>; + dynamic-power-coefficient = <277>; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + capacity-dmips-mhz = <535>; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + capacity-dmips-mhz = <535>; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + capacity-dmips-mhz = <535>; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + capacity-dmips-mhz = <535>; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A774E1_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A774E1_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + reg = <0 0xe6020000 0 0x0c>; + status = "disabled"; + + /* placeholder */ + }; + + gpio0: gpio@e6050000 { + reg = <0 0xe6050000 0 0x50>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + + /* placeholder */ + }; + + gpio1: gpio@e6051000 { + reg = <0 0xe6051000 0 0x50>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + + /* placeholder */ + }; + + gpio2: gpio@e6052000 { + reg = <0 0xe6052000 0 0x50>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + + /* placeholder */ + }; + + gpio3: gpio@e6053000 { + /* placeholder */ + reg = <0 0xe6053000 0 0x50>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + + /* placeholder */ + }; + + gpio4: gpio@e6054000 { + reg = <0 0xe6054000 0 0x50>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + + /* placeholder */ + }; + + gpio5: gpio@e6055000 { + reg = <0 0xe6055000 0 0x50>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + + /* placeholder */ + }; + + gpio6: gpio@e6055400 { + reg = <0 0xe6055400 0 0x50>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + + /* placeholder */ + }; + + gpio7: gpio@e6055800 { + reg = <0 0xe6055800 0 0x50>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + + /* placeholder */ + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a774e1"; + reg = <0 0xe6060000 0 0x50c>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a774e1-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a774e1-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a774e1-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + i2c2: i2c@e6510000 { + reg = <0 0xe6510000 0 0x40>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + /* placeholder */ + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xe66d8000 0 0x40>; + status = "disabled"; + + /* placeholder */ + }; + + hscif0: serial@e6540000 { + reg = <0 0xe6540000 0 0x60>; + status = "disabled"; + + /* placeholder */ + }; + + hsusb: usb@e6590000 { + reg = <0 0xe6590000 0 0x200>; + status = "disabled"; + + /* placeholder */ + }; + + usb3_phy0: usb-phy@e65ee000 { + reg = <0 0xe65ee000 0 0x90>; + #phy-cells = <0>; + status = "disabled"; + + /* placeholder */ + }; + + avb: ethernet@e6800000 { + reg = <0 0xe6800000 0 0x800>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + /* placeholder */ + }; + + can0: can@e6c30000 { + reg = <0 0xe6c30000 0 0x1000>; + status = "disabled"; + + /* placeholder */ + }; + + can1: can@e6c38000 { + reg = <0 0xe6c38000 0 0x1000>; + status = "disabled"; + + /* placeholder */ + }; + + pwm0: pwm@e6e30000 { + reg = <0 0xe6e30000 0 0x8>; + #pwm-cells = <2>; + status = "disabled"; + + /* placeholder */ + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a774e1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + status = "disabled"; + + /* placeholder */ + + rcar_sound,ssi { + ssi2: ssi-2 { + /* placeholder */ + }; + }; + }; + + xhci0: usb@ee000000 { + reg = <0 0xee000000 0 0xc00>; + status = "disabled"; + + /* placeholder */ + }; + + usb3_peri0: usb@ee020000 { + reg = <0 0xee020000 0 0x400>; + status = "disabled"; + + /* placeholder */ + }; + + ohci0: usb@ee080000 { + reg = <0 0xee080000 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ohci1: usb@ee0a0000 { + reg = <0 0xee0a0000 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ehci0: usb@ee080100 { + reg = <0 0xee080100 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ehci1: usb@ee0a0100 { + reg = <0 0xee0a0100 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + usb2_phy0: usb-phy@ee080200 { + reg = <0 0xee080200 0 0x700>; + status = "disabled"; + + /* placeholder */ + }; + + usb2_phy1: usb-phy@ee0a0200 { + reg = <0 0xee0a0200 0 0x700>; + status = "disabled"; + + /* placeholder */ + }; + + sdhi0: mmc@ee100000 { + reg = <0 0xee100000 0 0x2000>; + status = "disabled"; + + /* placeholder */ + }; + + sdhi2: mmc@ee140000 { + reg = <0 0xee140000 0 0x2000>; + status = "disabled"; + + /* placeholder */ + }; + + sdhi3: mmc@ee160000 { + compatible = "renesas,sdhi-r8a774e1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + pciec0: pcie@fe000000 { + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + /* placeholder */ + }; + + hdmi0: hdmi@fead0000 { + reg = <0 0xfead0000 0 0x10000>; + status = "disabled"; + + /* placeholder */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + }; + }; + + du: display@feb00000 { + reg = <0 0xfeb00000 0 0x80000>; + status = "disabled"; + + /* placeholder */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + }; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clocks - can be overridden by the board */ + usb3s0_clk: usb3s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; +}; From patchwork Fri Aug 21 09:43:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729107 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C7A8B17CF for ; Fri, 21 Aug 2020 10:58:45 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A34002072D for ; Fri, 21 Aug 2020 10:58:45 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Fri, 21 Aug 2020 18:44:18 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 34/36] dt-bindings: arm: renesas: Add HopeRun RZ/G2H boards Date: Fri, 21 Aug 2020 10:43:10 +0100 Message-Id: <20200821094312.3249-35-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: wLCC97lc0tR5XhZ5d1tphMMJx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007525; bh=8R3mntouKZ9SOToC0TQfS6tzPdJ5MceuJXIEBRVhvPE=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=PcXCyBWqbTLsnsA7iDfk4yYon/IzNKIVDmasees+sjMkFbfqTdMUche+KAjhaw3IhE4 BphvdfaTxppA8ubvOmEuQ+4tZB/3PvCzc5gZyn8f5Vl/u1/iOWNjXyZLq1W0Yspz/lElC p+NyJnQNnbp+qB0PlrVGcL55QMGfx3qljUo= From: Marian-Cristian Rotariu commit 6dfb9f369c00fe90f982eaf28032a889a89ee4b8 upstream. This patch adds board HiHope RZ/G2H (the main board, powered by the R8A774E1) and board HiHope RZ/G2 EX (the expansion board that sits on top of the HiHope RZ/G2H). Both boards are made by Jiangsu HopeRun Software Co., Ltd. (a.k.a. HopeRun). Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [biju: Patched text version of bindings file] Signed-off-by: Biju Das --- Documentation/devicetree/bindings/arm/shmobile.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 58a9c5194c36..5da33a737023 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -94,9 +94,12 @@ Boards: - Henninger compatible = "renesas,henninger", "renesas,r8a7791" - HopeRun expansion board for HiHope RZ/G2 platforms - compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1", + compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1", + "hoperun,hihope-rzg2m", "renesas,r8a774a1", "hoperun,hihope-rzg2n", "renesas,r8a774b1", "hoperun,hihope-rzg2-ex" + - HopeRun HiHope RZ/G2H platform + compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1" - HopeRun HiHope RZ/G2M platform compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1" - HopeRun HiHope RZ/G2N platform From patchwork Fri Aug 21 09:43:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729105 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 76BED109B for ; Fri, 21 Aug 2020 10:58:45 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 523192078D for ; Fri, 21 Aug 2020 10:58:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="AzjsOkcz" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 523192078D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5202+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id 7eknYY4521763xP9gZBAaa1r; Fri, 21 Aug 2020 03:58:45 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.131167.1598003052343639956 for ; Fri, 21 Aug 2020 02:44:22 -0700 X-IronPort-AV: E=Sophos;i="5.76,335,1592838000"; d="scan'208";a="54954645" X-Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 21 Aug 2020 18:44:21 +0900 X-Received: from localhost.localdomain (unknown [172.29.52.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 4D9AC4232078; Fri, 21 Aug 2020 18:44:20 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 35/36] arm64: dts: renesas: Add HiHope RZ/G2H main board support Date: Fri, 21 Aug 2020 10:43:11 +0100 Message-Id: <20200821094312.3249-36-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: KITp4vDgnAoxaxYaCCrGIj6Ux4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007525; bh=haEGBky8fc34AzNsj/vOZ4e3fgFGRkcjvO2RtHOWSR4=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=AzjsOkczOKltwmEFHxwcyllFnvfXH27ehQdfu3Uqf1h4IhPyrq2VZcXas1iUgWinFmn +1NSUWcciru1W+AGL/h6ilNtIbfus7XQMnztdl+5KiAVUrL7RBMkiTgi92Wqg9LjsHmfZ zZpePCgk9SjqqWynFip2ehZ297d24l+DXpc= From: Marian-Cristian Rotariu commit deadcd50771bc06ad03a3d09c568a0f66694e053 upstream. Basic support for the HiHope RZ/G2H main board: - Memory, - Main crystal, - Serial console - eMMC Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594230511-24790-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../arm64/boot/dts/renesas/hihope-common.dtsi | 4 +-- arch/arm64/boot/dts/renesas/hihope-rev4.dtsi | 4 +-- .../dts/renesas/r8a774e1-hihope-rzg2h.dts | 26 +++++++++++++++++++ 4 files changed, 31 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index d43027ca5c03..9c2942510ab5 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb \ r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \ r8a774c0-ek874-idk-2121wr.dtb +dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi index 3132c2cc99c4..5091c27a378e 100644 --- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the HiHope RZ/G2[MN] main board - * Rev.[2.0/3.0/4.0] common parts + * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and + * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts * * Copyright (C) 2019 Renesas Electronics Corp. */ diff --git a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi index 9f869187aea6..3046c07a288b 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the HiHope RZ/G2[MN] Rev.3.0/4.0 main board - * common parts + * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and + * HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts * * Copyright (C) 2020 Renesas Electronics Corp. */ diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts new file mode 100644 index 000000000000..cdbe527e9340 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2H main board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774e1.dtsi" +#include "hihope-rev4.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2H main board based on r8a774e1"; + compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@500000000 { + device_type = "memory"; + reg = <0x5 0x00000000 0x0 0x80000000>; + }; +}; From patchwork Fri Aug 21 09:43:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11729115 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B620722 for ; Fri, 21 Aug 2020 10:58:46 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 455FF20656 for ; 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Fri, 21 Aug 2020 18:44:21 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 36/36] arm64: dts: renesas: Add HiHope RZ/G2H sub board support Date: Fri, 21 Aug 2020 10:43:12 +0100 Message-Id: <20200821094312.3249-37-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: iZGMAiwdd2BYmnmnP4wS498yx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598007526; bh=Eob/raF6Hf8nSYmQYH8q25z312JAmO2Lf3L2A36eU8c=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=u0qBo4kYUC74crwuqQt0J7/wPrblyD7dcAExKtjfvdMmGIeZjdnpkq+VuoJijafmVhO z88qqKA7Nx0q4Hc95BG5yQn7vG/TZI8FoLzu7MOzSNkeieF5gWdE4XyAJa+ee2P8ogmEI KR5YLzkogxXsh0wq8Ku9N1WsThRW85U6wTc= From: Marian-Cristian Rotariu commit adbe62e93c1e793ad08d5e913151137b6c24daa4 upstream. The HiHope RZ/G2H sub board sits below the HiHope RZ/G2H main board. These boards are identical with the ones for RZ/G2M[N]. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594230511-24790-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/Makefile | 1 + arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 2 +- .../boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts | 15 +++++++++++++++ 3 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 9c2942510ab5..73cf57a3919b 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb \ dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \ r8a774c0-ek874-idk-2121wr.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb +dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi index acfcfd050a6c..178401a34cbf 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the RZ/G2[MN] HiHope sub board common parts + * Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts * * Copyright (C) 2019 Renesas Electronics Corp. */ diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts new file mode 100644 index 000000000000..265355e0de5f --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2H sub board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a774e1-hihope-rzg2h.dts" +#include "hihope-rzg2-ex.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2H with sub board"; + compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h", + "renesas,r8a774e1"; +};