From patchwork Tue Aug 25 02:03:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 11734705 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2D36E1575 for ; Tue, 25 Aug 2020 02:05:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1567F204EC for ; Tue, 25 Aug 2020 02:05:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="nb+J7c7j" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726882AbgHYCEt (ORCPT ); Mon, 24 Aug 2020 22:04:49 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:56765 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726104AbgHYCEp (ORCPT ); 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Tue, 25 Aug 2020 10:04:33 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Vinod Koul , Andy Gross , Bjorn Andersson , Matthias Brugger , Chunfeng Yun , Rikard Falkeborn , Bharat Gooty , Rayagonda Kokatanur , , , , Subject: [PATCH 1/6] phy: phy-bcm-ns-usb3: convert to readl_poll_timeout_atomic() Date: Tue, 25 Aug 2020 10:03:02 +0800 Message-ID: <1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 X-TM-SNTS-SMTP: 3EA5F72587F0E7679915674B6362ACC1B90384DA174A992330AA4FB1FA65C9752000:8 X-MTK: N Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use readl_poll_timeout_atomic() to simplify code Signed-off-by: Chunfeng Yun --- drivers/phy/broadcom/phy-bcm-ns-usb3.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/phy/broadcom/phy-bcm-ns-usb3.c b/drivers/phy/broadcom/phy-bcm-ns-usb3.c index 14f45bc..47b029f 100644 --- a/drivers/phy/broadcom/phy-bcm-ns-usb3.c +++ b/drivers/phy/broadcom/phy-bcm-ns-usb3.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -258,29 +259,24 @@ static int bcm_ns_usb3_mdio_probe(struct mdio_device *mdiodev) **************************************************/ static int bcm_ns_usb3_wait_reg(struct bcm_ns_usb3 *usb3, void __iomem *addr, - u32 mask, u32 value, unsigned long timeout) + u32 mask, u32 value, int usec) { - unsigned long deadline = jiffies + timeout; u32 val; + int ret; - do { - val = readl(addr); - if ((val & mask) == value) - return 0; - cpu_relax(); - udelay(10); - } while (!time_after_eq(jiffies, deadline)); + ret = readl_poll_timeout_atomic(addr, val, ((val & mask) == value), + 10, usec); + if (ret) + dev_err(usb3->dev, "Timeout waiting for register %p\n", addr); - dev_err(usb3->dev, "Timeout waiting for register %p\n", addr); - - return -EBUSY; + return ret; } static inline int bcm_ns_usb3_mii_mng_wait_idle(struct bcm_ns_usb3 *usb3) { return bcm_ns_usb3_wait_reg(usb3, usb3->ccb_mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, - usecs_to_jiffies(BCM_NS_USB3_MII_MNG_TIMEOUT_US)); + BCM_NS_USB3_MII_MNG_TIMEOUT_US); } static int bcm_ns_usb3_platform_phy_write(struct bcm_ns_usb3 *usb3, u16 reg, From patchwork Tue Aug 25 02:03:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 11734697 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 45E37138A for ; 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X-UUID: f3eda44dd7d9449a9dbac3ed2a327111-20200825 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1259988992; Tue, 25 Aug 2020 10:04:39 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 25 Aug 2020 10:04:36 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 25 Aug 2020 10:04:36 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Vinod Koul , Andy Gross , Bjorn Andersson , Matthias Brugger , Chunfeng Yun , Rikard Falkeborn , Bharat Gooty , Rayagonda Kokatanur , , , , Subject: [PATCH 2/6] phy: phy-bcm-ns2-usbdrd: convert to readl_poll_timeout_atomic() Date: Tue, 25 Aug 2020 10:03:03 +0800 Message-ID: <1598320987-25518-2-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com> References: <1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: EEC3529724919847FA126E25E02BCF7766E0E17551D1EF8D6C698E3376E31CD22000:8 X-MTK: N Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use readl_poll_timeout_atomic() to simplify code Signed-off-by: Chunfeng Yun --- drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c b/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c index 5276259..9630ac1 100644 --- a/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c +++ b/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -87,17 +88,11 @@ struct ns2_phy_data { static inline int pll_lock_stat(u32 usb_reg, int reg_mask, struct ns2_phy_driver *driver) { - int retry = PLL_LOCK_RETRY; u32 val; - do { - udelay(1); - val = readl(driver->icfgdrd_regs + usb_reg); - if (val & reg_mask) - return 0; - } while (--retry > 0); - - return -EBUSY; + return readl_poll_timeout_atomic(driver->icfgdrd_regs + usb_reg, + val, (val & reg_mask), 1, + PLL_LOCK_RETRY); } static int ns2_drd_phy_init(struct phy *phy) From patchwork Tue Aug 25 02:03:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 11734703 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 46B3516B1 for ; Tue, 25 Aug 2020 02:05:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3080F20738 for ; Tue, 25 Aug 2020 02:05:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="H0y3ntQs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727003AbgHYCFI (ORCPT ); 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Tue, 25 Aug 2020 10:04:39 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 25 Aug 2020 10:04:39 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Vinod Koul , Andy Gross , Bjorn Andersson , Matthias Brugger , Chunfeng Yun , Rikard Falkeborn , Bharat Gooty , Rayagonda Kokatanur , , , , Subject: [PATCH 3/6] phy: phy-bcm-sr-usb: convert to readl_poll_timeout_atomic() Date: Tue, 25 Aug 2020 10:03:04 +0800 Message-ID: <1598320987-25518-3-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com> References: <1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 588180CEE0623FA533389B0780B86B46F91CBD423006F5AC70031FD8AFAC5E452000:8 X-MTK: N Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use readl_poll_timeout_atomic() to simplify code Signed-off-by: Chunfeng Yun --- drivers/phy/broadcom/phy-bcm-sr-usb.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/phy/broadcom/phy-bcm-sr-usb.c b/drivers/phy/broadcom/phy-bcm-sr-usb.c index 77c025a..c3e99ad 100644 --- a/drivers/phy/broadcom/phy-bcm-sr-usb.c +++ b/drivers/phy/broadcom/phy-bcm-sr-usb.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -109,19 +110,15 @@ static inline void bcm_usb_reg32_setbits(void __iomem *addr, uint32_t set) static int bcm_usb_pll_lock_check(void __iomem *addr, u32 bit) { - int retry; - u32 rd_data; + u32 data; + int ret; - retry = PLL_LOCK_RETRY_COUNT; - do { - rd_data = readl(addr); - if (rd_data & bit) - return 0; - udelay(1); - } while (--retry > 0); + ret = readl_poll_timeout_atomic(addr, data, (data & bit), 1, + PLL_LOCK_RETRY_COUNT); + if (ret) + pr_err("%s: FAIL\n", __func__); - pr_err("%s: FAIL\n", __func__); - return -ETIMEDOUT; + return ret; } static int bcm_usb_ss_phy_init(struct bcm_usb_phy_cfg *phy_cfg) From patchwork Tue Aug 25 02:03:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 11734707 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 49A1C1575 for ; Tue, 25 Aug 2020 02:05:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 321CE20578 for ; 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Tue, 25 Aug 2020 10:04:42 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 25 Aug 2020 10:04:40 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 25 Aug 2020 10:04:40 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Vinod Koul , Andy Gross , Bjorn Andersson , Matthias Brugger , Chunfeng Yun , Rikard Falkeborn , Bharat Gooty , Rayagonda Kokatanur , , , , Subject: [PATCH 4/6] phy: phy-qcom-apq8064-sata: convert to readl_relaxed_poll_timeout() Date: Tue, 25 Aug 2020 10:03:05 +0800 Message-ID: <1598320987-25518-4-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com> References: <1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: A5EAD1C8FD2955FE87DADAE9B2E41C9C6E073672D0E9B9753269DF5A26EC82042000:8 X-MTK: N Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use readl_relaxed_poll_timeout() to simplify code, rename local function read_poll_timeout() as poll_timeout() to avoid repeated definition Signed-off-by: Chunfeng Yun --- drivers/phy/qualcomm/phy-qcom-apq8064-sata.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c b/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c index febe0ae..ce91ae7 100644 --- a/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c +++ b/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -72,18 +73,12 @@ struct qcom_apq8064_sata_phy { }; /* Helper function to do poll and timeout */ -static int read_poll_timeout(void __iomem *addr, u32 mask) +static int poll_timeout(void __iomem *addr, u32 mask) { - unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS); + u32 val; - do { - if (readl_relaxed(addr) & mask) - return 0; - - usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50); - } while (!time_after(jiffies, timeout)); - - return (readl_relaxed(addr) & mask) ? 0 : -ETIMEDOUT; + return readl_relaxed_poll_timeout(addr, val, (val & mask), + DELAY_INTERVAL_US, TIMEOUT_MS * 1000); } static int qcom_apq8064_sata_phy_init(struct phy *generic_phy) @@ -137,21 +132,21 @@ static int qcom_apq8064_sata_phy_init(struct phy *generic_phy) writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2); /* PLL Lock wait */ - ret = read_poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK); + ret = poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK); if (ret) { dev_err(phy->dev, "poll timeout UNIPHY_PLL_STATUS\n"); return ret; } /* TX Calibration */ - ret = read_poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL); + ret = poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL); if (ret) { dev_err(phy->dev, "poll timeout SATA_PHY_TX_IMCAL_STAT\n"); return ret; } /* RX Calibration */ - ret = read_poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL); + ret = poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL); if (ret) { dev_err(phy->dev, "poll timeout SATA_PHY_RX_IMCAL_STAT\n"); return ret; From patchwork Tue Aug 25 02:03:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 11734699 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 26CBE138A for ; Tue, 25 Aug 2020 02:05:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 098CB204EC for ; Tue, 25 Aug 2020 02:05:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="HYPJ0J6g" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727097AbgHYCFB (ORCPT ); Mon, 24 Aug 2020 22:05:01 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:53690 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727003AbgHYCEw (ORCPT ); Mon, 24 Aug 2020 22:04:52 -0400 X-UUID: 9d8fa058bf2e4100bbae97ab31ee9267-20200825 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Hg3xDnzPmtGQak8Ute3Rvxu6qZDbOpMb8i88ROzC9nY=; b=HYPJ0J6g95mPpceVWsOz8bFxMDCN2wz+ozXNLdpf1q8Nw3tiMCLH/Pd1eyjXUx7xbEhChB9lmIpE2qfH4XwpK/DNhlMMBsOH3pvO2thA87nSm8AIj6hXANOohTxXHo7KYETIugOLmaOAL1uvw7FJgjSQzUyicj97Mwg6rKW80u4=; X-UUID: 9d8fa058bf2e4100bbae97ab31ee9267-20200825 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1183580573; Tue, 25 Aug 2020 10:04:45 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 25 Aug 2020 10:04:41 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 25 Aug 2020 10:04:42 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Vinod Koul , Andy Gross , Bjorn Andersson , Matthias Brugger , Chunfeng Yun , Rikard Falkeborn , Bharat Gooty , Rayagonda Kokatanur , , , , Subject: [PATCH 5/6] phy: phy-pxa-28nm-hsic: convert to readl_poll_timeout() Date: Tue, 25 Aug 2020 10:03:06 +0800 Message-ID: <1598320987-25518-5-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com> References: <1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 28FF1B787476A0B3AF2469E02C492C33A28A47D3B4816BF7035E5B68A61F09612000:8 X-MTK: N Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use readl_poll_timeout() to simplify code Signed-off-by: Chunfeng Yun --- drivers/phy/marvell/phy-pxa-28nm-hsic.c | 40 ++++++++++++++++----------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/phy/marvell/phy-pxa-28nm-hsic.c b/drivers/phy/marvell/phy-pxa-28nm-hsic.c index ae8370a..31b43d2 100644 --- a/drivers/phy/marvell/phy-pxa-28nm-hsic.c +++ b/drivers/phy/marvell/phy-pxa-28nm-hsic.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -44,15 +45,12 @@ struct mv_hsic_phy { struct clk *clk; }; -static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout) +static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms) { - timeout += jiffies; - while (time_is_after_eq_jiffies(timeout)) { - if ((readl(reg) & mask) == mask) - return true; - msleep(1); - } - return false; + u32 val; + + return readl_poll_timeout(reg, val, ((val & mask) == mask), + 1000, 1000 * ms); } static int mv_hsic_phy_init(struct phy *phy) @@ -60,6 +58,7 @@ static int mv_hsic_phy_init(struct phy *phy) struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy); struct platform_device *pdev = mv_phy->pdev; void __iomem *base = mv_phy->base; + int ret; clk_prepare_enable(mv_phy->clk); @@ -75,14 +74,14 @@ static int mv_hsic_phy_init(struct phy *phy) base + PHY_28NM_HSIC_PLL_CTRL2); /* Make sure PHY PLL is locked */ - if (!wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2, - PHY_28NM_HSIC_H2S_PLL_LOCK, HZ / 10)) { + ret = wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2, + PHY_28NM_HSIC_H2S_PLL_LOCK, 100); + if (ret) { dev_err(&pdev->dev, "HSIC PHY PLL not locked after 100mS."); clk_disable_unprepare(mv_phy->clk); - return -ETIMEDOUT; } - return 0; + return ret; } static int mv_hsic_phy_power_on(struct phy *phy) @@ -91,6 +90,7 @@ static int mv_hsic_phy_power_on(struct phy *phy) struct platform_device *pdev = mv_phy->pdev; void __iomem *base = mv_phy->base; u32 reg; + int ret; reg = readl(base + PHY_28NM_HSIC_CTRL); /* Avoid SE0 state when resume for some device will take it as reset */ @@ -108,20 +108,20 @@ static int mv_hsic_phy_power_on(struct phy *phy) */ /* Make sure PHY Calibration is ready */ - if (!wait_for_reg(base + PHY_28NM_HSIC_IMPCAL_CAL, - PHY_28NM_HSIC_H2S_IMPCAL_DONE, HZ / 10)) { + ret = wait_for_reg(base + PHY_28NM_HSIC_IMPCAL_CAL, + PHY_28NM_HSIC_H2S_IMPCAL_DONE, 100); + if (ret) { dev_warn(&pdev->dev, "HSIC PHY READY not set after 100mS."); - return -ETIMEDOUT; + return ret; } /* Waiting for HSIC connect int*/ - if (!wait_for_reg(base + PHY_28NM_HSIC_INT, - PHY_28NM_HSIC_CONNECT_INT, HZ / 5)) { + ret = wait_for_reg(base + PHY_28NM_HSIC_INT, + PHY_28NM_HSIC_CONNECT_INT, 200); + if (ret) dev_warn(&pdev->dev, "HSIC wait for connect interrupt timeout."); - return -ETIMEDOUT; - } - return 0; + return ret; } static int mv_hsic_phy_power_off(struct phy *phy) From patchwork Tue Aug 25 02:03:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 11734701 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AD9771575 for ; Tue, 25 Aug 2020 02:05:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9770B20738 for ; Tue, 25 Aug 2020 02:05:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ChZ+3hCf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726998AbgHYCEu (ORCPT ); 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Tue, 25 Aug 2020 10:04:41 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 25 Aug 2020 10:04:43 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Vinod Koul , Andy Gross , Bjorn Andersson , Matthias Brugger , Chunfeng Yun , Rikard Falkeborn , Bharat Gooty , Rayagonda Kokatanur , , , , Subject: [PATCH 6/6] phy: phy-pxa-28nm-usb2: convert to readl_poll_timeout() Date: Tue, 25 Aug 2020 10:03:07 +0800 Message-ID: <1598320987-25518-6-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com> References: <1598320987-25518-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 4B7CA52755C8D266865A594E4B03F79BCD596B20C172F3EC76907D9CF8D018632000:8 X-MTK: N Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use readl_poll_timeout() to simplify code Signed-off-by: Chunfeng Yun --- drivers/phy/marvell/phy-pxa-28nm-usb2.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/drivers/phy/marvell/phy-pxa-28nm-usb2.c b/drivers/phy/marvell/phy-pxa-28nm-usb2.c index 9fd8817..a175ae9 100644 --- a/drivers/phy/marvell/phy-pxa-28nm-usb2.c +++ b/drivers/phy/marvell/phy-pxa-28nm-usb2.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -138,15 +139,12 @@ struct mv_usb2_phy { struct clk *clk; }; -static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout) +static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms) { - timeout += jiffies; - while (time_is_after_eq_jiffies(timeout)) { - if ((readl(reg) & mask) == mask) - return true; - msleep(1); - } - return false; + u32 val; + + return readl_poll_timeout(reg, val, ((val & mask) == mask), + 1000, 1000 * ms); } static int mv_usb2_phy_28nm_init(struct phy *phy) @@ -208,24 +206,23 @@ static int mv_usb2_phy_28nm_init(struct phy *phy) */ /* Make sure PHY Calibration is ready */ - if (!wait_for_reg(base + PHY_28NM_CAL_REG, - PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE, - HZ / 10)) { + ret = wait_for_reg(base + PHY_28NM_CAL_REG, + PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE, + 100); + if (ret) { dev_warn(&pdev->dev, "USB PHY PLL calibrate not done after 100mS."); - ret = -ETIMEDOUT; goto err_clk; } - if (!wait_for_reg(base + PHY_28NM_RX_REG1, - PHY_28NM_RX_SQCAL_DONE, HZ / 10)) { + ret = wait_for_reg(base + PHY_28NM_RX_REG1, + PHY_28NM_RX_SQCAL_DONE, 100); + if (ret) { dev_warn(&pdev->dev, "USB PHY RX SQ calibrate not done after 100mS."); - ret = -ETIMEDOUT; goto err_clk; } /* Make sure PHY PLL is ready */ - if (!wait_for_reg(base + PHY_28NM_PLL_REG0, - PHY_28NM_PLL_READY, HZ / 10)) { + ret = wait_for_reg(base + PHY_28NM_PLL_REG0, PHY_28NM_PLL_READY, 100); + if (ret) { dev_warn(&pdev->dev, "PLL_READY not set after 100mS."); - ret = -ETIMEDOUT; goto err_clk; }