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Tue, 25 Aug 2020 10:09:03 +0000 From: Wei Chen To: , , CC: , , , , Subject: [PATCH v3 1/2] xen/arm: Missing N1/A76/A75 FP registers in vCPU context switch Date: Tue, 25 Aug 2020 10:08:46 +0000 Message-ID: <20200825100847.27988-2-wei.chen@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200825100847.27988-1-wei.chen@arm.com> References: <20200825100847.27988-1-wei.chen@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 813b3cc1-4f1f-4ce0-35b4-08d848defa22 X-MS-TrafficTypeDiagnostic: AM6PR08MB4327:|DBBPR08MB4363: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:7691;OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 9JsKiqe1qBsHSKO6DCaw4dUvl+Ldn+p3nBBr3WEkpAgyfBH6neaEVpzv7Psg38V7EpAo6HfyZW7eyL5a0zCqTgmrVGYtuumXbTFMhv8z+THwty936/OjJflUL0kFOSrsLGrfUqlUnG7fKRCF5uTmARKBPQfQk3KXS/VNYAUwh0ilQl9UNw4p8wdMFe0A7+JC+S1SpEQOKvdGnajJl75lUuwjGtbfTz78O1PySebDCyJCeOB8lx0UuafbOSp9BMz+W7WKsatZQdMw0MiqVWpBn+hu1A5dHjGyh/3ZxdDF6orTDXNeTwmQrFE3HQy4E+J+8SI261/iSA22CJspcVC42wF0D6/R08StjzTcKMIDwTn7UEUtal+4vcH4ZHJZhHRKHf3hko3f8lRX2utpU6GuPw== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(136003)(376002)(346002)(396003)(39860400002)(46966005)(82740400003)(26005)(44832011)(81166007)(82310400002)(2616005)(47076004)(316002)(426003)(36906005)(8936002)(110136005)(4326008)(5660300002)(54906003)(186003)(478600001)(1076003)(86362001)(6666004)(8676002)(70206006)(36756003)(83380400001)(336012)(2906002)(70586007); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Aug 2020 10:09:38.8391 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 813b3cc1-4f1f-4ce0-35b4-08d848defa22 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT039.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB4363 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Xen has cpu_has_fp/cpu_has_simd to detect whether the CPU supports FP/SIMD or not. But currently, these two MACROs only consider value 0 of ID_AA64PFR0_EL1.FP/SIMD as FP/SIMD features enabled. But for CPUs that support FP/SIMD and half-precision floating-point arithmetic, the ID_AA64PFR0_EL1.FP/SIMD are 1 (see Arm ARM DDI0487F.b, D13.2.64). For these CPUs, xen will treat them as no FP/SIMD support, the vfp_save/restore_state will not take effect. From the TRM documents of Cortex-A75/A76/N1, we know these CPUs support basic Advanced SIMD/FP and half-precision floating-point arithmetic. In this case, on N1/A76/A75 platforms, Xen will always miss the floating pointer registers save/restore. If different vCPUs are running on the same pCPU, the floating pointer registers will be corrupted randomly. This patch fixes Xen on these new cores. Signed-off-by: Wei Chen Reviewed-by: Bertrand Marquis Reviewed-by: Julien Grall --- xen/include/asm-arm/cpufeature.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index 674beb0353..10878ead8a 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -13,8 +13,8 @@ #define cpu_has_el2_64 (boot_cpu_feature64(el2) >= 1) #define cpu_has_el3_32 (boot_cpu_feature64(el3) == 2) #define cpu_has_el3_64 (boot_cpu_feature64(el3) >= 1) -#define cpu_has_fp (boot_cpu_feature64(fp) == 0) -#define cpu_has_simd (boot_cpu_feature64(simd) == 0) +#define cpu_has_fp (boot_cpu_feature64(fp) < 8) +#define cpu_has_simd (boot_cpu_feature64(simd) < 8) #define cpu_has_gicv3 (boot_cpu_feature64(gic) == 1) #endif From patchwork Tue Aug 25 10:08:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Chen X-Patchwork-Id: 11735455 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 140E113A4 for ; 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SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Aug 2020 10:09:28.2537 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ba8c812-c575-4d4d-8746-08d848def3c4 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT063.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0801MB1985 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU FP/SIMD implementations. Currently, we exactly know the meaning of 0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD features presented. If there is a value 0x2 bumped in the future, Xen behaviors for value <= 0x1 can also take effect. But what Xen done for value <= 0x1 may not always cover new value 0x2 required. We throw these messages to break the silence when Xen detected unknown FP/SIMD IDs to notice user to check. Signed-off-by: Wei Chen Reviewed-by: Bertrand Marquis --- xen/arch/arm/setup.c | 12 ++++++++++++ xen/include/asm-arm/cpufeature.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 7968cee47d..ef39ce1ec6 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -133,6 +133,18 @@ static void __init processor_id(void) cpu_has_simd ? " AdvancedSIMD" : "", cpu_has_gicv3 ? " GICv3-SysReg" : ""); + /* Warn user if we find unknown floating-point features */ + if ( cpu_has_unknown_fp ) + printk(XENLOG_WARNING "WARNING: Unknown Floating-point ID:%d, " + "this may result to corruption on the platform\n", + boot_cpu_feature64(fp)); + + /* Warn user if we find unknown AdvancedSIMD features */ + if ( cpu_has_unknown_simd ) + printk(XENLOG_WARNING "WARNING: Unknown AdvancedSIMD ID:%d, " + "this may result to corruption on the platform\n", + boot_cpu_feature64(simd)); + printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n", boot_cpu_data.dbg64.bits[0], boot_cpu_data.dbg64.bits[1]); printk(" Auxiliary Features: %016"PRIx64" %016"PRIx64"\n", diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index 10878ead8a..a32309986e 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -16,6 +16,8 @@ #define cpu_has_fp (boot_cpu_feature64(fp) < 8) #define cpu_has_simd (boot_cpu_feature64(simd) < 8) #define cpu_has_gicv3 (boot_cpu_feature64(gic) == 1) +#define cpu_has_unknown_fp (cpu_has_fp && (boot_cpu_feature64(fp) >= 2)) +#define cpu_has_unknown_simd (cpu_has_simd && (boot_cpu_feature64(simd) >= 2)) #endif #define cpu_feature32(c, feat) ((c)->pfr32.feat)