From patchwork Tue Aug 25 13:21:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11735725 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C0FE11751 for ; Tue, 25 Aug 2020 13:41:59 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 97CD3204EA for ; Tue, 25 Aug 2020 13:41:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="sGxRgM8q" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 97CD3204EA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5241+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id xuJ7YY4521763xjcBKUKXjif; Tue, 25 Aug 2020 06:41:59 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.13479.1598361721660454951 for ; Tue, 25 Aug 2020 06:22:02 -0700 X-IronPort-AV: E=Sophos;i="5.76,352,1592838000"; d="scan'208";a="55486173" X-Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 25 Aug 2020 22:22:01 +0900 X-Received: from localhost.localdomain (unknown [172.29.51.65]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A39E0400517E; Tue, 25 Aug 2020 22:21:59 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 4.19.y-cip 01/10] arm64: dts: renesas: r8a774e1: Add operating points Date: Tue, 25 Aug 2020 14:21:47 +0100 Message-Id: <20200825132156.7839-2-biju.das.jz@bp.renesas.com> In-Reply-To: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> References: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: 5TjzvqP4NIucKQ47ZxlhZvzZx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598362919; bh=7x3HRl+VjDQFSW+lAgzziVw3hc3NwUxULyT+WMBpb4c=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=sGxRgM8qQ2GgAOYTFG3KRJltKQ4AA4t+v7I43XBoJpfi0CAuyAyBzkwk/3I2K7FSWYt 1gDodoNnGbwfotfWgDh9OryT/+zaURIG5mEQd8D/57ZPjd8DdNavBJREN7vwMZIwM1hqP T2Dbc6WjTeJ7RBEN0tI4WH2/FkDS5XBpzJ8= From: Marian-Cristian Rotariu commit d18dbce4e8c02634866dc80c7873e6121fcae970 upstream. The RZ/G2H (r8a774e1) comes with two clusters of processors, similarly to the r8a774a1. The first cluster is made of A57s, the second cluster is made of A53s. The operating points for the cluster with the A57s are: Frequency | Voltage ----------|--------- 500 MHz | 0.82V 1.0 GHz | 0.82V 1.5 GHz | 0.82V The operating points for the cluster with the A53s are: Frequency | Voltage ----------|--------- 800 MHz | 0.82V 1.0 GHz | 0.82V 1.2 GHz | 0.82V This patch adds the definitions for the operating points to the SoC specific DT. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594811350-14066-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 51 +++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index d76aec73aa28..3a3490adc8a0 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -34,6 +34,49 @@ clock-frequency = <0>; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -79,6 +122,7 @@ enable-method = "psci"; dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -91,6 +135,7 @@ next-level-cache = <&L2_CA57>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -103,6 +148,7 @@ next-level-cache = <&L2_CA57>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -115,6 +161,7 @@ next-level-cache = <&L2_CA57>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; #cooling-cells = <2>; }; @@ -129,6 +176,7 @@ #cooling-cells = <2>; dynamic-power-coefficient = <277>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; }; @@ -140,6 +188,7 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; }; @@ -151,6 +200,7 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; }; @@ -162,6 +212,7 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; }; From patchwork Tue Aug 25 13:21:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11735729 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1BA13913 for ; Tue, 25 Aug 2020 13:42:00 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EA076204EA for ; Tue, 25 Aug 2020 13:41:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="QB7DY2K8" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EA076204EA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5242+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id fqWwYY4521763xtbObSxZGKE; Tue, 25 Aug 2020 06:41:59 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web12.13293.1598361720422412146 for ; Tue, 25 Aug 2020 06:22:03 -0700 X-IronPort-AV: E=Sophos;i="5.76,352,1592838000"; d="scan'208";a="55269188" X-Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 25 Aug 2020 22:22:02 +0900 X-Received: from localhost.localdomain (unknown [172.29.51.65]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 7F2A64008C59; Tue, 25 Aug 2020 22:22:01 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 4.19.y-cip 02/10] thermal: rcar_gen3_thermal: Remove temperature bound Date: Tue, 25 Aug 2020 14:21:48 +0100 Message-Id: <20200825132156.7839-3-biju.das.jz@bp.renesas.com> In-Reply-To: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> References: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: t0FL5WX34GogIAP8I5VR3MWOx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598362919; bh=u9DcwjqDdXICmSPGRWWKCpfMl/99Agzt5621JMVqCs8=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=QB7DY2K84G5e5rMIufy3larvKcQNMUNfmnYOQfW2SVy59bxOvYlHWnixvKf/9M2O1a0 OCwrSCKuzqbtdTOw9JWodbc87RyNJPh9GJ4BON+sBWfS+IVardzqQc/7fUrgEbrYs9ABf KqbtKPL2+FU+baxUC+z9Ix+/0EbOJhsWVCc= From: Niklas Söderlund commit 0f510a2457cbbba18a98492bab1bf540be57ebd1 upstream. The hardware manual states that the operation of the sensor is not guaranteed with temperatures above 125°C, not that the readings are invalid. Remove the bound check and try to deliver temperature readings even if we are outside the guaranteed operation range. Signed-off-by: Niklas Söderlund Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200117160554.3812787-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Biju Das --- drivers/thermal/rcar_gen3_thermal.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c index 42ec69d29540..e7a0c7fc9897 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c @@ -182,9 +182,7 @@ static int rcar_gen3_thermal_get_temp(void *devdata, int *temp) tsc->coef.a2); mcelsius = FIXPT_TO_MCELSIUS(val); - /* Make sure we are inside specifications */ - if ((mcelsius < MCELSIUS(-40)) || (mcelsius > MCELSIUS(125))) - return -EIO; + /* Guaranteed operating range is -40C to 125C. */ /* Round value to device granularity setting */ *temp = rcar_gen3_thermal_round(mcelsius); From patchwork Tue Aug 25 13:21:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11735737 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B76BF159A for ; Tue, 25 Aug 2020 13:42:00 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 923AE2075F for ; Tue, 25 Aug 2020 13:42:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="igSlwEsw" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 923AE2075F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5244+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id B86LYY4521763x4KH2cICCKC; Tue, 25 Aug 2020 06:42:00 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.13479.1598361721660454951 for ; Tue, 25 Aug 2020 06:22:07 -0700 X-IronPort-AV: E=Sophos;i="5.76,352,1592838000"; d="scan'208";a="55486197" X-Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 25 Aug 2020 22:22:06 +0900 X-Received: from localhost.localdomain (unknown [172.29.51.65]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 38717400517E; Tue, 25 Aug 2020 22:22:05 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 4.19.y-cip 04/10] thermal/drivers/rcar_gen3: Fix undefined temperature if negative Date: Tue, 25 Aug 2020 14:21:50 +0100 Message-Id: <20200825132156.7839-5-biju.das.jz@bp.renesas.com> In-Reply-To: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> References: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: BaSzsjaPAWQ2TPzGJhqCF1Wax4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598362920; bh=NQqvU35iPrgDgJuitAXFrGMNj2oL8R1y+GOIi9J/Uew=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=igSlwEswWnLh2Q/SotIBFyhysGI1AI9R7yhOEEas/3ptGfhUg4Qxv06xIU1gztBM0yJ p1MVdiaux8mJF8eeIhuk4NlBq0PVEMGa91GkQl1d3EZHi/1JWt5z236BDK7eUjngIflm8 cqf6womtSSF44v8qNxSwDJip9dz5Gb/mWyo= From: Dien Pham commit 5f8f06425a0dcdad7bedbb77e67f5c65ab4dacfc upstream. As description for DIV_ROUND_CLOSEST in file include/linux/kernel.h. "Result is undefined for negative divisors if the dividend variable type is unsigned and for negative dividends if the divisor variable type is unsigned." In current code, the FIXPT_DIV uses DIV_ROUND_CLOSEST but has not checked sign of divisor before using. It makes undefined temperature value in case the value is negative. This patch fixes to satisfy DIV_ROUND_CLOSEST description and fix bug too. Note that the variable name "reg" is not good because it should be the same type as rcar_gen3_thermal_read(). However, it's better to rename the "reg" in a further patch as cleanup. Signed-off-by: Van Do Signed-off-by: Dien Pham [shimoda: minor fixes, add Fixes tag] Fixes: 564e73d283af ("thermal: rcar_gen3_thermal: Add R-Car Gen3 thermal driver") Signed-off-by: Yoshihiro Shimoda Reviewed-by: Niklas Soderlund Tested-by: Niklas Soderlund Reviewed-by: Amit Kucheria Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/1593085099-2057-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Biju Das --- drivers/thermal/rcar_gen3_thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c index 166cadf4bf02..92758445c574 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c @@ -167,7 +167,7 @@ static int rcar_gen3_thermal_get_temp(void *devdata, int *temp) { struct rcar_gen3_thermal_tsc *tsc = devdata; int mcelsius, val; - u32 reg; + int reg; /* Read register and convert to mili Celsius */ reg = rcar_gen3_thermal_read(tsc, REG_GEN3_TEMP) & CTEMP_MASK; From patchwork Tue Aug 25 13:21:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11735723 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E2626913 for ; Tue, 25 Aug 2020 13:41:58 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4C8F620786 for ; Tue, 25 Aug 2020 13:41:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="mgKEnOq3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4C8F620786 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5245+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id MD5GYY4521763x2raSCMuwvy; Tue, 25 Aug 2020 06:41:57 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.13479.1598361721660454951 for ; Tue, 25 Aug 2020 06:22:08 -0700 X-IronPort-AV: E=Sophos;i="5.76,352,1592838000"; d="scan'208";a="55486200" X-Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 25 Aug 2020 22:22:08 +0900 X-Received: from localhost.localdomain (unknown [172.29.51.65]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 0FBB64004950; Tue, 25 Aug 2020 22:22:06 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 4.19.y-cip 05/10] thermal: rcar_gen3_thermal: Add r8a774e1 support Date: Tue, 25 Aug 2020 14:21:51 +0100 Message-Id: <20200825132156.7839-6-biju.das.jz@bp.renesas.com> In-Reply-To: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> References: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: Fc5bzLq7UCUZq5ENKEGU4o5ux4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598362917; bh=kba5NQ3D5Zzl9qf2XK/KYpES7I5cciB67NyYfBSSXbg=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=mgKEnOq3a0iVWsO1M10YbJ0BCPwLMo3QA54g2lJMo0pLEUpjZa1yA34757/GhreH5v5 FCQmOfg2Kn6V7jkzYj1Cpss5eVH5Uy9/b8xeUIJgft9yN4Q3/l1LegtutfdWzz7dCXOnm Kufy6lMvI+Y7TLQeAunY0sgoMz3E7FHasYw= From: Marian-Cristian Rotariu commit 947d85f00c030aa88eef0c065b6f4636547257d7 upstream. Add r8a774e1 specific compatible string. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/1594811350-14066-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Biju Das --- drivers/thermal/rcar_gen3_thermal.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c index 92758445c574..9ebcbb07bbc0 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c @@ -314,6 +314,10 @@ static const struct of_device_id rcar_gen3_thermal_dt_ids[] = { .compatible = "renesas,r8a774b1-thermal", .data = &rcar_gen3_ths_tj_1, }, + { + .compatible = "renesas,r8a774e1-thermal", + .data = &rcar_gen3_ths_tj_1, + }, { .compatible = "renesas,r8a7795-thermal", .data = &rcar_gen3_ths_tj_1, From patchwork Tue Aug 25 13:21:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11735727 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BE7FE159A for ; Tue, 25 Aug 2020 13:41:59 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 988992075F for ; Tue, 25 Aug 2020 13:41:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="NoLYDihR" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 988992075F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5246+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id oJ9SYY4521763xXF4jIosbNA; Tue, 25 Aug 2020 06:41:59 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.13479.1598361721660454951 for ; Tue, 25 Aug 2020 06:22:10 -0700 X-IronPort-AV: E=Sophos;i="5.76,352,1592838000"; d="scan'208";a="55486203" X-Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 25 Aug 2020 22:22:10 +0900 X-Received: from localhost.localdomain (unknown [172.29.51.65]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id DEE1E4004950; Tue, 25 Aug 2020 22:22:08 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 4.19.y-cip 06/10] arm64: dts: renesas: r8a774e1: Add RZ/G2H thermal support Date: Tue, 25 Aug 2020 14:21:52 +0100 Message-Id: <20200825132156.7839-7-biju.das.jz@bp.renesas.com> In-Reply-To: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> References: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: WcTeEW6YBTCpgm7UfaF87bLjx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598362919; bh=jfnbYvaViu0bIA0RQ3KIzACdgdBHtUZCdQoX2cx4KVU=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=NoLYDihR9aPngrIBhkxsfiZiD0u3MqHYAhVxLaHPoyPBWNhojLII5Y949U2NfgA5vs1 an3c7JfdsElKVmBJNt5ylqFQxpp+o9r7e1q1tYCBKdeEDPSaqtXzoyQW7mfHPwC21uH+5 +xFZHgTz4OqYxKcEkLRSQBSoa5ulbIx2/Lw= From: Marian-Cristian Rotariu commit 6dd733679911598354b0445f07a3e6c3141c865c upstream. Add thermal support for R8A774E1 (RZ/G2H) SoC. Based on the work done for r8a774a1 SoC. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594811350-14066-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 81 +++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 3a3490adc8a0..70c5e28e201e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -442,6 +442,20 @@ #power-domain-cells = <1>; }; + tsc: thermal@e6198000 { + compatible = "renesas,r8a774e1-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; #interrupt-cells = <2>; @@ -1003,6 +1017,73 @@ }; }; + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + sustainable-power = <6313>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + sustainable-power = <6313>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + sustainable-power = <6313>; + + trips { + target: trip-point1 { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&a57_0 0 2>; + contribution = <1024>; + }; + + map1 { + trip = <&target>; + cooling-device = <&a53_0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, From patchwork Tue Aug 25 13:21:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11735735 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6DD1217C7 for ; Tue, 25 Aug 2020 13:42:00 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 47723204EA for ; Tue, 25 Aug 2020 13:42:00 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Tue, 25 Aug 2020 22:22:10 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 4.19.y-cip 07/10] arm64: dts: renesas: r8a774e1: Add CMT device nodes Date: Tue, 25 Aug 2020 14:21:53 +0100 Message-Id: <20200825132156.7839-8-biju.das.jz@bp.renesas.com> In-Reply-To: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> References: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: UpMuvpMUUAWFT2fAhWcxi3lVx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598362920; bh=DxZ5anLtXCDaXj403aTuQw9Vwt6EhlhJqEgZqL2szL4=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=JIEvoQU+O11Qal+Q8g79AxGW1cP+XvmkStNnsE26ROC5Sr3SdY8t3LxHFYO02z/o85u pzSYfr5e4K20FULXUUabWFgnrinucA8hX0hExWy4CpKtrLiZnQE8Kkm0evEYqa/QMo/z5 EkodPvvD1ZIEn5KYjHb5EQQnRFX+fRWKS1c= From: Marian-Cristian Rotariu commit c6c4b7defd391da84da0ac640df0da2a13680a9e upstream. This patch adds the CMT[0123] device tree nodes to the r8a774e1 SoC specific DT. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594811350-14066-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 70 +++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 70c5e28e201e..264f3b7e3c11 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -421,6 +421,76 @@ reg = <0 0xe6060000 0 0x50c>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a774e1-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a774e1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a774e1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a774e1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a774e1-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; From patchwork Tue Aug 25 13:21:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11735741 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13CB317CF for ; Tue, 25 Aug 2020 13:42:01 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E23DC204EA for ; Tue, 25 Aug 2020 13:42:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="kVId7nmP" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E23DC204EA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5248+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id BKvJYY4521763x7aDVDR3LFB; Tue, 25 Aug 2020 06:42:00 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.13479.1598361721660454951 for ; Tue, 25 Aug 2020 06:22:14 -0700 X-IronPort-AV: E=Sophos;i="5.76,352,1592838000"; d="scan'208";a="55486209" X-Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 25 Aug 2020 22:22:14 +0900 X-Received: from localhost.localdomain (unknown [172.29.51.65]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A8049400517E; Tue, 25 Aug 2020 22:22:12 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 4.19.y-cip 08/10] arm64: dts: renesas: r8a774e1: Add TMU device nodes Date: Tue, 25 Aug 2020 14:21:54 +0100 Message-Id: <20200825132156.7839-9-biju.das.jz@bp.renesas.com> In-Reply-To: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> References: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: n1KGBjNvy5DwF60glFpPL59dx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598362920; bh=UsGuI2nlqo67BhHIK/YeX5dl1Ge16B0KE1w2x1aIN2g=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=kVId7nmPdtKP93dPc2nnfUGfdyjtZMx1cg5+WaJVWsU28rkNSyArK7A5pMi66Wy1zzg icBqLcJKfvJMXH+T+vjCwMwvl4DyPMRNhtITAN57eTnO3QKyW1hJh/aEtKLC9sKAzWdNG riQeC/nyQT0MfYpI9NIxOf2CP0XE/UHm3UM= From: Marian-Cristian Rotariu commit 58eb575cf0450bab583dc4009a39644bf98754cc upstream. This patch adds TMU[01234] device tree nodes to the r8a774e1 SoC specific DT. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594811350-14066-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 65 +++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 264f3b7e3c11..c4f12544703d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -542,6 +542,71 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + i2c2: i2c@e6510000 { reg = <0 0xe6510000 0 0x40>; #address-cells = <1>; From patchwork Tue Aug 25 13:21:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11735733 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6DD3C17F7 for ; Tue, 25 Aug 2020 13:42:00 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 480782075F for ; Tue, 25 Aug 2020 13:42:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="VVXx6BYj" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 480782075F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5249+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id SXh6YY4521763x7G7vIYp5g0; Tue, 25 Aug 2020 06:42:00 -0700 X-Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web12.13297.1598361736502564135 for ; Tue, 25 Aug 2020 06:22:16 -0700 X-IronPort-AV: E=Sophos;i="5.76,352,1592838000"; d="scan'208";a="55269203" X-Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 25 Aug 2020 22:22:15 +0900 X-Received: from localhost.localdomain (unknown [172.29.51.65]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 854884004950; Tue, 25 Aug 2020 22:22:14 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 4.19.y-cip 09/10] can: rcar_can: Remove unused platform data support Date: Tue, 25 Aug 2020 14:21:55 +0100 Message-Id: <20200825132156.7839-10-biju.das.jz@bp.renesas.com> In-Reply-To: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> References: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: HuESvDATI2HlghQKs3DzcsXKx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598362920; bh=po3yIXxmxASdGNJ4NeGN5m1Z76Zuh+sIcU49JJUcnFs=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=VVXx6BYjNMcrSjPfAn8hMdQRuhISGzG/g/iQ1zFCGMU2JBlgGkRcwTEWIWiKPf/IlxM 6PwL+ssA25EUxCGUH4ZJ9t57Iwqsz20z+GKu6/tc5Z3K4crdAZo0binnLLF+DAhN+3Ne0 c8whFGPWaWpVm0/8uYgqlLFVMV4/Fb1WyOw= From: Geert Uytterhoeven commit 30cc0ed73e3390af7c5573b159826e8162f09fe7 upstream. All R-Car platforms use DT for describing CAN controllers. R-Car CAN platform data support was never used in any upstream kernel. Move the Clock Select Register settings enum into the driver, and remove platform data support and the corresponding header file. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Signed-off-by: Marc Kleine-Budde --- drivers/net/can/rcar/rcar_can.c | 22 +++++++++------------- include/linux/can/platform/rcar_can.h | 18 ------------------ 2 files changed, 9 insertions(+), 31 deletions(-) delete mode 100644 include/linux/can/platform/rcar_can.h diff --git a/drivers/net/can/rcar/rcar_can.c b/drivers/net/can/rcar/rcar_can.c index 771a46083739..bfb674193a21 100644 --- a/drivers/net/can/rcar/rcar_can.c +++ b/drivers/net/can/rcar/rcar_can.c @@ -19,11 +19,17 @@ #include #include #include -#include #include #define RCAR_CAN_DRV_NAME "rcar_can" +/* Clock Select Register settings */ +enum CLKR { + CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */ + CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */ + CLKR_CLKEXT = 3, /* Externally input clock */ +}; + #define RCAR_SUPPORTED_CLOCKS (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \ BIT(CLKR_CLKEXT)) @@ -740,7 +746,6 @@ static const char * const clock_names[] = { static int rcar_can_probe(struct platform_device *pdev) { - struct rcar_can_platform_data *pdata; struct rcar_can_priv *priv; struct net_device *ndev; struct resource *mem; @@ -749,17 +754,8 @@ static int rcar_can_probe(struct platform_device *pdev) int err = -ENODEV; int irq; - if (pdev->dev.of_node) { - of_property_read_u32(pdev->dev.of_node, - "renesas,can-clock-select", &clock_select); - } else { - pdata = dev_get_platdata(&pdev->dev); - if (!pdata) { - dev_err(&pdev->dev, "No platform data provided!\n"); - goto fail; - } - clock_select = pdata->clock_select; - } + of_property_read_u32(pdev->dev.of_node, "renesas,can-clock-select", + &clock_select); irq = platform_get_irq(pdev, 0); if (irq < 0) { diff --git a/include/linux/can/platform/rcar_can.h b/include/linux/can/platform/rcar_can.h deleted file mode 100644 index a43dcd0cf79e..000000000000 --- a/include/linux/can/platform/rcar_can.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CAN_PLATFORM_RCAR_CAN_H_ -#define _CAN_PLATFORM_RCAR_CAN_H_ - -#include - -/* Clock Select Register settings */ -enum CLKR { - CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */ - CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */ - CLKR_CLKEXT = 3 /* Externally input clock */ -}; - -struct rcar_can_platform_data { - enum CLKR clock_select; /* Clock source select */ -}; - -#endif /* !_CAN_PLATFORM_RCAR_CAN_H_ */ From patchwork Tue Aug 25 13:21:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11735739 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B86E51751 for ; Tue, 25 Aug 2020 13:42:00 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 91E20204EA for ; Tue, 25 Aug 2020 13:42:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="rkqOJJHC" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 91E20204EA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5250+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id eQ7WYY4521763xZmMXdfNMM5; Tue, 25 Aug 2020 06:42:00 -0700 X-Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com []) by mx.groups.io with SMTP id smtpd.web10.13479.1598361721660454951 for ; Tue, 25 Aug 2020 06:22:18 -0700 X-IronPort-AV: E=Sophos;i="5.76,352,1592838000"; d="scan'208";a="55486213" X-Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 25 Aug 2020 22:22:17 +0900 X-Received: from localhost.localdomain (unknown [172.29.51.65]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 6120B400517E; Tue, 25 Aug 2020 22:22:16 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [cip-dev] [PATCH 4.19.y-cip 10/10] arm64: dts: renesas: r8a774e1: Add CAN[FD] support Date: Tue, 25 Aug 2020 14:21:56 +0100 Message-Id: <20200825132156.7839-11-biju.das.jz@bp.renesas.com> In-Reply-To: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> References: <20200825132156.7839-1-biju.das.jz@bp.renesas.com> Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: MgbT6OzJbhWC9euaK72jRPCux4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1598362920; bh=yvE1+WOuX0/tKdTnAtra9JLsWXFwEFONALnTPSvdgaw=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=rkqOJJHCso8+/LqqoEfGaiXR4HknBSY3aK7kvoXXmOZVpHY/RprxIYCS8LUtu+e0cZM LVw+hShACu3yT2tQ/lH/mJLMRgo5fLautlbPUCUGuRu3IkSkJkAIgcxcV1+4ECAhWBefd 6R3ZITZs8+aTG7SKtXYJ5j4x5HcDhY+Lmdw= From: Lad Prabhakar commit 8e340e7560d1d4db3b7ed5c010d3460de8ff0c1e upstream. Add CAN[01] and CANFD support to RZ/G2H (R8A774E1) SoC specific dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1594811350-14066-21-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 56 +++++++++++++++++++++-- 1 file changed, 53 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index c4f12544703d..af090cd90f5d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -34,6 +34,13 @@ clock-frequency = <0>; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + cluster0_opp: opp_table0 { compatible = "operating-points-v2"; opp-shared; @@ -941,17 +948,60 @@ }; can0: can@e6c30000 { + compatible = "renesas,can-r8a774e1", + "renesas,rcar-gen3-can"; reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; - - /* placeholder */ }; can1: can@e6c38000 { + compatible = "renesas,can-r8a774e1", + "renesas,rcar-gen3-can"; reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; + }; - /* placeholder */ + canfd: can@e66c0000 { + compatible = "renesas,r8a774e1-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; }; pwm0: pwm@e6e30000 {