From patchwork Wed Aug 26 13:01:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 11738341 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9094F13B1 for ; Wed, 26 Aug 2020 13:02:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 69A5620738 for ; Wed, 26 Aug 2020 13:02:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="jwUfxZB/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730099AbgHZNCd (ORCPT ); Wed, 26 Aug 2020 09:02:33 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:12555 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1730158AbgHZNCI (ORCPT ); Wed, 26 Aug 2020 09:02:08 -0400 X-UUID: 4841d7c73c73427abf164f97f122eeae-20200826 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=q+YqZIg/PDK9Io6p3eN7H4lQSTi+FeEESntXUiBV/o8=; b=jwUfxZB/TXvTh36YPSmZHmeheITFTvdLka6igL/3qMwASlnQobZUtwv9BJ70Tq/BUcnvTlcfwsUMlIY2QOCjrc6ZdM1JWwtF8Pf6XonigHwDLDUxux4RuT1MY0hqpXutTRdHhzPV3s8ZqxlDwDB+be8FD9Xf+DOoawNbWEsn1B0=; X-UUID: 4841d7c73c73427abf164f97f122eeae-20200826 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 743984469; Wed, 26 Aug 2020 21:02:02 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 26 Aug 2020 21:01:57 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 26 Aug 2020 21:01:57 +0800 From: Hector Yuan To: , , , , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Catalin Marinas , Will Deacon , Matthias Brugger , Bjorn Andersson , Shawn Guo , Li Yang , Vinod Koul , Arnd Bergmann , Anson Huang , Geert Uytterhoeven , Olof Johansson CC: , Subject: [PATCH v3 1/2] cpufreq: mediatek-hw: Add support for Mediatek cpufreq HW driver Date: Wed, 26 Aug 2020 21:01:52 +0800 Message-ID: <1598446913-24325-2-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1598446913-24325-1-git-send-email-hector.yuan@mediatek.com> References: <1598446913-24325-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: "Hector.Yuan" Add MT6779 cpufreq HW support. Signed-off-by: Hector.Yuan --- drivers/cpufreq/Kconfig.arm | 12 ++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/mediatek-cpufreq-hw.c | 305 +++++++++++++++++++++++++++++++++ 3 files changed, 318 insertions(+) create mode 100644 drivers/cpufreq/mediatek-cpufreq-hw.c diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index c6cbfc8..8e58c12 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -121,6 +121,18 @@ config ARM_MEDIATEK_CPUFREQ help This adds the CPUFreq driver support for MediaTek SoCs. +config ARM_MEDIATEK_CPUFREQ_HW + tristate "MediaTek CPUFreq HW driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + default m + help + Support for the CPUFreq HW driver. + Some MediaTek chipsets have a HW engine to offload the steps + necessary for changing the frequency of the CPUs. Firmware loaded + in this engine exposes a programming interface to the OS. + The driver implements the cpufreq interface for this HW engine. + Say Y if you want to support CPUFreq HW. + config ARM_OMAP2PLUS_CPUFREQ bool "TI OMAP2+" depends on ARCH_OMAP2PLUS diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index f6670c4..dc1f371 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o obj-$(CONFIG_ARM_IMX_CPUFREQ_DT) += imx-cpufreq-dt.o obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o +obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ_HW) += mediatek-cpufreq-hw.o obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediatek-cpufreq-hw.c new file mode 100644 index 0000000..86ce7f0 --- /dev/null +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LUT_MAX_ENTRIES 32U +#define LUT_FREQ GENMASK(11, 0) +#define LUT_VOLT GENMASK(28, 12) +#define LUT_ROW_SIZE 0x4 + +enum { + REG_LUT_TABLE, + REG_ENABLE, + REG_PERF_STATE, + + REG_ARRAY_SIZE, +}; + +struct cpufreq_mtk { + struct cpufreq_frequency_table *table; + void __iomem *reg_bases[REG_ARRAY_SIZE]; + cpumask_t related_cpus; +}; + +static const u16 cpufreq_mtk_offsets[REG_ARRAY_SIZE] = { + [REG_LUT_TABLE] = 0x0, + [REG_ENABLE] = 0x84, + [REG_PERF_STATE] = 0x88, +}; + +static struct cpufreq_mtk *mtk_freq_domain_map[NR_CPUS]; + +static int mtk_cpufreq_hw_target_index(struct cpufreq_policy *policy, + unsigned int index) +{ + struct cpufreq_mtk *c = policy->driver_data; + + writel_relaxed(index, c->reg_bases[REG_PERF_STATE]); + arch_set_freq_scale(policy->related_cpus, + policy->freq_table[index].frequency, + policy->cpuinfo.max_freq); + + return 0; +} + +static unsigned int mtk_cpufreq_hw_get(unsigned int cpu) +{ + struct cpufreq_mtk *c; + struct cpufreq_policy *policy; + unsigned int index; + + policy = cpufreq_cpu_get_raw(cpu); + if (!policy) + return 0; + + c = policy->driver_data; + + index = readl_relaxed(c->reg_bases[REG_PERF_STATE]); + index = min(index, LUT_MAX_ENTRIES - 1); + + return policy->freq_table[index].frequency; +} + +static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) +{ + struct cpufreq_mtk *c; + struct device *cpu_dev; + int ret; + + cpu_dev = get_cpu_device(policy->cpu); + if (!cpu_dev) { + pr_err("%s: failed to get cpu%d device\n", __func__, + policy->cpu); + return -ENODEV; + } + + c = mtk_freq_domain_map[policy->cpu]; + if (!c) { + pr_err("No scaling support for CPU%d\n", policy->cpu); + return -ENODEV; + } + + cpumask_copy(policy->cpus, &c->related_cpus); + + ret = dev_pm_opp_get_opp_count(cpu_dev); + if (ret <= 0) + dev_err(cpu_dev, "OPP table is not ready\n"); + + policy->freq_table = c->table; + policy->driver_data = c; + + /* HW should be in enabled state to proceed now */ + writel_relaxed(0x1, c->reg_bases[REG_ENABLE]); + + return 0; +} + +static struct freq_attr *mtk_cpufreq_hw_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL +}; + +static struct cpufreq_driver cpufreq_mtk_hw_driver = { + .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK | + CPUFREQ_HAVE_GOVERNOR_PER_POLICY, + .verify = cpufreq_generic_frequency_table_verify, + .target_index = mtk_cpufreq_hw_target_index, + .get = mtk_cpufreq_hw_get, + .init = mtk_cpufreq_hw_cpu_init, + .name = "mtk-cpufreq-hw", + .attr = mtk_cpufreq_hw_attr, +}; + +static int mtk_cpufreq_hw_opp_create(struct platform_device *pdev, + struct cpufreq_mtk *c) +{ + struct device *dev = &pdev->dev; + void __iomem *base_table; + u32 data, i, freq, volt, prev_freq = 0; + unsigned long cpu; + + c->table = devm_kcalloc(dev, LUT_MAX_ENTRIES + 1, + sizeof(*c->table), GFP_KERNEL); + if (!c->table) + return -ENOMEM; + + base_table = c->reg_bases[REG_LUT_TABLE]; + + for (i = 0; i < LUT_MAX_ENTRIES; i++) { + data = readl_relaxed(base_table + (i * LUT_ROW_SIZE)); + freq = FIELD_GET(LUT_FREQ, data) * 1000; + volt = FIELD_GET(LUT_VOLT, data) * 10; + c->table[i].frequency = freq; + + dev_dbg(dev, "index=%d freq=%d\n", + i, c->table[i].frequency); + + if (freq == prev_freq) + break; + + prev_freq = freq; + + for_each_cpu(cpu, &c->related_cpus) + dev_pm_opp_add(get_cpu_device(cpu), freq, volt); + } + + c->table[i].frequency = CPUFREQ_TABLE_END; + + return 0; +} + +static int mtk_get_related_cpus(int index, struct cpumask *m) +{ + struct device_node *cpu_np; + struct of_phandle_args args; + int cpu, ret; + + for_each_possible_cpu(cpu) { + cpu_np = of_cpu_device_node_get(cpu); + if (!cpu_np) + continue; + + ret = of_parse_phandle_with_args(cpu_np, "mtk-freq-domain", + "#freq-domain-cells", 0, + &args); + of_node_put(cpu_np); + if (ret < 0) + continue; + + if (index == args.args[0]) + cpumask_set_cpu(cpu, m); + } + + return 0; +} + +static int mtk_cpu_resources_init(struct platform_device *pdev, + unsigned int cpu, int index) +{ + struct cpufreq_mtk *c; + struct resource *res; + struct device *dev = &pdev->dev; + const u16 *offsets; + int ret, i, cpu_r; + void __iomem *base; + + if (mtk_freq_domain_map[cpu]) + return 0; + + c = devm_kzalloc(dev, sizeof(*c), GFP_KERNEL); + if (!c) + return -ENOMEM; + + offsets = of_device_get_match_data(&pdev->dev); + if (!offsets) + return -EINVAL; + + res = platform_get_resource(pdev, IORESOURCE_MEM, index); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + for (i = REG_LUT_TABLE; i < REG_ARRAY_SIZE; i++) + c->reg_bases[i] = base + offsets[i]; + + ret = mtk_get_related_cpus(index, &c->related_cpus); + if (ret) { + dev_err(dev, "Domain-%d failed to get related CPUs\n", index); + return ret; + } + + ret = mtk_cpufreq_hw_opp_create(pdev, c); + if (ret) { + dev_err(dev, "Domain-%d failed to create OPP\n", index); + return ret; + } + + for_each_cpu(cpu_r, &c->related_cpus) + mtk_freq_domain_map[cpu_r] = c; + + return 0; +} + +static int mtk_resources_init(struct platform_device *pdev) +{ + struct device_node *cpu_np; + struct of_phandle_args args; + unsigned int cpu; + int ret; + + for_each_possible_cpu(cpu) { + cpu_np = of_cpu_device_node_get(cpu); + if (!cpu_np) { + dev_dbg(&pdev->dev, "Failed to get cpu %d device\n", + cpu); + continue; + } + + ret = of_parse_phandle_with_args(cpu_np, "mtk-freq-domain", + "#freq-domain-cells", 0, &args); + if (ret < 0) + return ret; + + ret = mtk_cpu_resources_init(pdev, cpu, args.args[0]); + if (ret) + return ret; + } + + return 0; +} + +static int mtk_cpufreq_hw_driver_probe(struct platform_device *pdev) +{ + int ret; + + /* Get the bases of cpufreq for domains */ + ret = mtk_resources_init(pdev); + if (ret) { + dev_err(&pdev->dev, "CPUFreq resource init failed\n"); + return ret; + } + + ret = cpufreq_register_driver(&cpufreq_mtk_hw_driver); + if (ret) { + dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); + return ret; + } + + dev_dbg(&pdev->dev, "Mediatek CPUFreq HW driver initialized\n"); + of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + + return 0; +} + +static const struct of_device_id mtk_cpufreq_hw_match[] = { + { .compatible = "mediatek,cpufreq-hw", .data = &cpufreq_mtk_offsets }, + {} +}; + +static struct platform_driver mtk_cpufreq_hw_driver = { + .probe = mtk_cpufreq_hw_driver_probe, + .driver = { + .name = "mtk-cpufreq-hw", + .of_match_table = mtk_cpufreq_hw_match, + }, +}; + +static int __init mtk_cpufreq_hw_init(void) +{ + return platform_driver_register(&mtk_cpufreq_hw_driver); +} +subsys_initcall(mtk_cpufreq_hw_init); + +MODULE_DESCRIPTION("mtk CPUFREQ HW Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Aug 26 13:01:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 11738339 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4AEC014F6 for ; Wed, 26 Aug 2020 13:02:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 281D620B1F for ; Wed, 26 Aug 2020 13:02:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="rD/I6SIH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730161AbgHZNCS (ORCPT ); Wed, 26 Aug 2020 09:02:18 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:8470 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1730099AbgHZNCI (ORCPT ); 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Wed, 26 Aug 2020 21:01:59 +0800 From: Hector Yuan To: , , , , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Catalin Marinas , Will Deacon , Matthias Brugger , Bjorn Andersson , Shawn Guo , Li Yang , Vinod Koul , Arnd Bergmann , Anson Huang , Geert Uytterhoeven , Olof Johansson CC: , Subject: [PATCH v3 2/2] dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW Date: Wed, 26 Aug 2020 21:01:53 +0800 Message-ID: <1598446913-24325-3-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1598446913-24325-1-git-send-email-hector.yuan@mediatek.com> References: <1598446913-24325-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: "Hector.Yuan" Add devicetree bindings for MediaTek HW driver. Signed-off-by: Hector.Yuan --- .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 141 ++++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml new file mode 100644 index 0000000..5be5867 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek's CPUFREQ Bindings + +maintainers: + - Hector Yuan + +description: + CPUFREQ HW is a hardware engine used by MediaTek + SoCs to manage frequency in hardware. It is capable of controlling frequency + for multiple clusters. + +properties: + compatible: + const: mediatek,cpufreq-hw + + reg: + minItems: 1 + maxItems: 2 + description: | + Addresses and sizes for the memory of the HW bases in each frequency domain. + + reg-names: + items: + - const: "freq-domain0" + - const: "freq-domain1" + description: | + Frequency domain name. i.e. + "freq-domain0", "freq-domain1". + + "#freq-domain-cells": + const: 1 + description: | + Number of cells in a freqency domain specifier. + + mtk-freq-domain: + maxItems: 1 + description: | + Define this cpu belongs to which frequency domain. i.e. + cpu0-3 belong to frequency domain0, + cpu4-6 belong to frequency domain1. + +required: + - compatible + - reg + - reg-names + - "#freq-domain-cells" + +examples: + - | + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 0>; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 0>; + reg = <0x100>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 0>; + reg = <0x200>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 0>; + reg = <0x300>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 1>; + reg = <0x400>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 1>; + reg = <0x500>; + }; + + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 1>; + reg = <0x600>; + }; + + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + mtk-freq-domain = <&cpufreq_hw 1>; + reg = <0x700>; + }; + }; + + /* ... */ + + soc { + #address-cells = <2>; + #size-cells = <2>; + + cpufreq_hw: cpufreq@11bc00 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x11bc10 0 0x8c>, + <0 0x11bca0 0 0x8c>; + reg-names = "freq-domain0", "freq-domain1"; + #freq-domain-cells = <1>; + }; + }; + + + +