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Fri, 28 Aug 2020 02:34:12 +0000 From: Wei Chen To: , , CC: , , , , Subject: [PATCH v5 1/2] xen/arm: Missing N1/A76/A75 FP registers in vCPU context switch Date: Fri, 28 Aug 2020 02:34:03 +0000 Message-ID: <20200828023404.28638-2-wei.chen@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200828023404.28638-1-wei.chen@arm.com> References: <20200828023404.28638-1-wei.chen@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: aef9998c-2f75-4bbd-aaeb-08d84afae00e X-MS-TrafficTypeDiagnostic: DBAPR08MB5767:|DB6PR0801MB2023: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:7691;OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: fVDdI1NKyWuQ8PexL9jUMWjcvkF/v7nz7Yi1u8YcQGDYK8o/vASXUTRt6lBwh50w0AYVAw2tl5ybntP43cAEbqNbh0ZQNrpafA+JEASs6d4euiOrq2q5QhAwSnKcRLKaAxl2OUYE3Il3j4a7kFPLuvWSRDNgUa1zgYn/kfc7GX7DY9fcbNg/WULMuCqpefxKlBxGrVZu+NzYJ+XgfF+DL2efHNZFQd6vC2UrAxLm06Z7W2j3W6Jci4LmpLOrVgZvClxKHeNFlkpjeDqxsFgJ5bFWr/ZxQABUlUpnIBlCr9mXbxwn8LdUDrTvGXVm1titKyLKMg0fYzSDuSirFERFmV9C3mUVXFG5oNgJr/2HeDPJ4vvtlEPLCSMiNLUGaRjANr3mEttLAa658uRM4S7ltw== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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But currently, these two MACROs only consider value 0 of ID_AA64PFR0_EL1.FP/SIMD as FP/SIMD features enabled. But for CPUs that support FP/SIMD and half-precision floating-point arithmetic, the ID_AA64PFR0_EL1.FP/SIMD are 1 (see Arm ARM DDI0487F.b, D13.2.64). For these CPUs, xen will treat them as no FP/SIMD support, the vfp_save/restore_state will not take effect. From the TRM documents of Cortex-A75/A76/N1, we know these CPUs support basic Advanced SIMD/FP and half-precision floating-point arithmetic. In this case, on N1/A76/A75 platforms, Xen will always miss the floating pointer registers save/restore. If different vCPUs are running on the same pCPU, the floating pointer registers will be corrupted randomly. This patch fixes Xen on these new cores. Signed-off-by: Wei Chen Reviewed-by: Bertrand Marquis Reviewed-by: Julien Grall --- xen/include/asm-arm/cpufeature.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index 674beb0353..10878ead8a 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -13,8 +13,8 @@ #define cpu_has_el2_64 (boot_cpu_feature64(el2) >= 1) #define cpu_has_el3_32 (boot_cpu_feature64(el3) == 2) #define cpu_has_el3_64 (boot_cpu_feature64(el3) >= 1) -#define cpu_has_fp (boot_cpu_feature64(fp) == 0) -#define cpu_has_simd (boot_cpu_feature64(simd) == 0) +#define cpu_has_fp (boot_cpu_feature64(fp) < 8) +#define cpu_has_simd (boot_cpu_feature64(simd) < 8) #define cpu_has_gicv3 (boot_cpu_feature64(gic) == 1) #endif From patchwork Fri Aug 28 02:34:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Chen X-Patchwork-Id: 11742081 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AA2EE13B6 for ; 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Fri, 28 Aug 2020 02:34:15 +0000 From: Wei Chen To: , , CC: , , , , Subject: [PATCH v5 2/2] xen/arm: Throw messages for unknown FP/SIMD implement ID Date: Fri, 28 Aug 2020 02:34:04 +0000 Message-ID: <20200828023404.28638-3-wei.chen@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200828023404.28638-1-wei.chen@arm.com> References: <20200828023404.28638-1-wei.chen@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 88674923-cb4c-4611-279c-08d84afae358 X-MS-TrafficTypeDiagnostic: AM6PR08MB5142:|VE1PR08MB5149: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:8882;OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 5vzVdR71D5tjK4wFllD2LHC9mGtnvzOjZcplPY0t2S0JE+myzjI8JkDznqjwm2ZThg95FTzUGTfRBhYEMREJLFqDBr6jUgvXdOZwZFEZXCjFE/NGD3YB5dC0IDLMmb03Jq+M8l3o2QHrHw9bDppv2gSbQWkEFU1PX45Kex98/s77WOAV/4HQlcdmTCCkSSg1BogEbzqg820HKxrCoqW2XT8/J7H10oCTEWO/UmGQ62N3kILTjvGm2smtnVWIHXd4YyCl31t0vxUszz5c3cZvGmIY546bfCZz+jE1ji2qi6dgu0JfYrMRhvBrlKg7GXV3OGGoF409X5gbVzheELIm+dJw26LZJyk+VRfJdezsw9VCdtD9zQJyHcaTMErYVDP/d7d2r4f4tw/WSHjb16+q/A== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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Currently, we exactly know the meaning of 0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD features presented. If there is a value 0x2 bumped in the future, Xen behaviors for value <= 0x1 can also take effect. But what Xen done for value <= 0x1 may not always cover new value 0x2 required. We throw these messages to break the silence when Xen detected unknown FP/SIMD IDs to notice user to check. Signed-off-by: Wei Chen Reviewed-by: Bertrand Marquis Acked-by: Julien Grall --- xen/arch/arm/setup.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 7968cee47d..f16b33fa87 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -133,6 +133,18 @@ static void __init processor_id(void) cpu_has_simd ? " AdvancedSIMD" : "", cpu_has_gicv3 ? " GICv3-SysReg" : ""); + /* Warn user if we find unknown floating-point features */ + if ( cpu_has_fp && (boot_cpu_feature64(fp) >= 2) ) + printk(XENLOG_WARNING "WARNING: Unknown Floating-point ID:%d, " + "this may result in corruption on the platform\n", + boot_cpu_feature64(fp)); + + /* Warn user if we find unknown AdvancedSIMD features */ + if ( cpu_has_simd && (boot_cpu_feature64(simd) >= 2) ) + printk(XENLOG_WARNING "WARNING: Unknown AdvancedSIMD ID:%d, " + "this may result in corruption on the platform\n", + boot_cpu_feature64(simd)); + printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n", boot_cpu_data.dbg64.bits[0], boot_cpu_data.dbg64.bits[1]); printk(" Auxiliary Features: %016"PRIx64" %016"PRIx64"\n",