From patchwork Tue Sep 1 16:46:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 11749261 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 274C113B6 for ; Tue, 1 Sep 2020 16:49:38 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F2FA02067C for ; Tue, 1 Sep 2020 16:49:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Xn9jVnus"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="o0HjAU+e" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F2FA02067C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=wJplq4U23ljZPDDISiLrcirH9WIooITS2Lo16vxBZVA=; b=Xn9jVnusE0+EEJyx3D4EyOw6I 9kJc8GBsz3V9U9p5fHH5z5oBKRxeNbwvckJud6pjAUy+o6Q5RWaRYbPA0HTv8lER7CkzWZmGqhvE9 qb3ytv9QK7615WOkWpNSE6vPDayncVrxsRT9k3DGHCn5aDEYHNK+gQj2vsFucRlHsbw4U+la3yNzY T9ZGnWNntMXXzlfMbWKRDZqAl+WwqfyDpv7lMiLFgX/zEwYzfIOofqkuymiSatqqL4LiuCoXaX4BV UJYQpMYmhLcv8hTh65xdW6VI1023GaZNaCSscmsc7wxAwxd4xP9ZynXq91Fy5BSS2T1hsVXQkFfh5 Hz+GIElKw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9R9-0005L7-FT; Tue, 01 Sep 2020 16:47:11 +0000 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9R6-0005Ju-Sr for linux-arm-kernel@lists.infradead.org; Tue, 01 Sep 2020 16:47:09 +0000 Received: by mail-pj1-x1044.google.com with SMTP id np15so873510pjb.0 for ; Tue, 01 Sep 2020 09:47:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2FYkuDdKfZnq0C2m032hzkvhRzd15B2Kmt9oLbZcU5c=; b=o0HjAU+eO0eVEW69ynSmkWf0X28KnBPwmaRZJNBxYK2FEwYPSfbXtrDRKMWcPYxJ8x z9/ceSjNKIk+9TMYg4tdnV5uE80khfkGQpxt4TXLf7+jywEoZKkbdUcDn98xWEAq5oZx xHbRFRzuM4ttZOAx4WwnL7+brWiaLq8WTd0SmFO8/ey2Hp2fyi2cGgmyp6lOtFxkb13c qNic/o+FL5IF9rYTAjBb62NQ11vRZTzoMYBMNYmAgK6lq8j81VGgj+yaO7RWZwmL99QZ ws5tpHaiuawCLWD0uk5Garqc1CcmVxEcO4rrvh0/ubax51wtSEdZVWk/oNufULl4ATbt qjFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2FYkuDdKfZnq0C2m032hzkvhRzd15B2Kmt9oLbZcU5c=; b=KQ0BYavC1EmULoCCeHEpSlttcy3RjzFVGvJSSJPVfpGjfrlOtDIwF9/hEGHxR65aav ANdi8FO7ZIrEGKoHhyoAG4QoyWiuJSjiqDZvBsLzxf8gyMq+nFrv/JAfWCFJezKv8HUg LWVqmwj7aWAgM6UlvIj81VjQ22pg7724R358Tmu5UAGiYUKV7JPDnp1pAvoG/cP8cltP EnbrxbvDvFiEkxc+ckRpBbRZUH1Looo9MEe0IDKMPm7bd8Z/pTeibmF4+2v0fl6im2Q6 1tNbSk8A9BgaCGvdgU8AGyjyGyOTqx8LnWzukcoOllLZ86iGlXCdtnlhuWTb5MEOSXas QOKw== X-Gm-Message-State: AOAM531YhkHf1fgyqvXhxBeud+WwVqH69X+1rhHYveyjEIdrrCbzLjrN rVpiNe8Lu7mgaS0WidxH+Sk= X-Google-Smtp-Source: ABdhPJyZrrMMvdwtDYnjzNN0ZavE7E4JxesijLNi3COZopUMe83ivyVwsBJpkaFA/L4BrcggzGwCYQ== X-Received: by 2002:a17:90b:384d:: with SMTP id nl13mr2412923pjb.227.1598978826758; Tue, 01 Sep 2020 09:47:06 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id bx18sm2062725pjb.6.2020.09.01.09.47.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2020 09:47:05 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Will Deacon , Robin Murphy Subject: [PATCH v16 12/20] iommu/arm-smmu: Pass io-pgtable config to implementation specific function Date: Tue, 1 Sep 2020 09:46:29 -0700 Message-Id: <20200901164707.2645413-13-robdclark@gmail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200901164707.2645413-1-robdclark@gmail.com> References: <20200901164707.2645413-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200901_124708_938949_95238181 X-CRM114-Status: GOOD ( 18.22 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1044 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [robdclark[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , open list , Greg Kroah-Hartman , Joerg Roedel , Akhil P Oommen , Stephen Boyd , Jordan Crouse , Thierry Reding , Sibi Sankar , Vivek Gautam , Bjorn Andersson , Hanna Hawa , "moderated list:ARM SMMU DRIVERS" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Jordan Crouse Construct the io-pgtable config before calling the implementation specific init_context function and pass it so the implementation specific function can get a chance to change it before the io-pgtable is created. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson --- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 ++- drivers/iommu/arm/arm-smmu/arm-smmu.c | 11 ++++++----- drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 ++- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c index f4ff124a1967..a9861dcd0884 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c @@ -68,7 +68,8 @@ static int cavium_cfg_probe(struct arm_smmu_device *smmu) return 0; } -static int cavium_init_context(struct arm_smmu_domain *smmu_domain) +static int cavium_init_context(struct arm_smmu_domain *smmu_domain, + struct io_pgtable_cfg *pgtbl_cfg) { struct cavium_smmu *cs = container_of(smmu_domain->smmu, struct cavium_smmu, smmu); diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 09c42af9f31e..37d8d49299b4 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -795,11 +795,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, cfg->asid = cfg->cbndx; smmu_domain->smmu = smmu; - if (smmu->impl && smmu->impl->init_context) { - ret = smmu->impl->init_context(smmu_domain); - if (ret) - goto out_unlock; - } pgtbl_cfg = (struct io_pgtable_cfg) { .pgsize_bitmap = smmu->pgsize_bitmap, @@ -810,6 +805,12 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, .iommu_dev = smmu->dev, }; + if (smmu->impl && smmu->impl->init_context) { + ret = smmu->impl->init_context(smmu_domain, &pgtbl_cfg); + if (ret) + goto out_clear_smmu; + } + if (smmu_domain->non_strict) pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index d890a4a968e8..83294516ac08 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -386,7 +386,8 @@ struct arm_smmu_impl { u64 val); int (*cfg_probe)(struct arm_smmu_device *smmu); int (*reset)(struct arm_smmu_device *smmu); - int (*init_context)(struct arm_smmu_domain *smmu_domain); + int (*init_context)(struct arm_smmu_domain *smmu_domain, + struct io_pgtable_cfg *cfg); void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync, int status); int (*def_domain_type)(struct device *dev); From patchwork Tue Sep 1 16:46:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 11749249 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B5132109A for ; Tue, 1 Sep 2020 16:48:58 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8DB602067C for ; Tue, 1 Sep 2020 16:48:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="oRg+5NLG"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Fc9Tcsza" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8DB602067C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=R/FUc6Svpl310mPJmS+BzUqp4Xgr57sVon3pM8epHZE=; b=oRg+5NLG2/hIiysfUGkeYqM+O +vfAsSSO/Ed7iF9zow5dBP2H9j7xZXRIQx0oQNFuywGHCJ3fRComcczL3IsVlWAbfGwqlVWdoRl8z BUew8coSILQY2qo/ASnAKRfBXtylYF9G6X7WPw36t5cvz70+yyoiRkH0cP7cyf3icd9E4FYddL87o vkY8IgwiOXuTNizTbAa5xcD0r9Rfkj9TSeso7FCt/Dtd+9NWpaPlXuAOiEiR6qeCBnA5zkrFztH6b d0VhR/urxpZICqHfLzxAYGg2XFnxJOhMqyC+NTyqkf+ULjycMpZ/RSYzcaNdUg8mvS8IOEf90BYi2 Xu79cd8Dg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9RE-0005NL-Qa; Tue, 01 Sep 2020 16:47:16 +0000 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9RB-0005La-7b for linux-arm-kernel@lists.infradead.org; Tue, 01 Sep 2020 16:47:15 +0000 Received: by mail-pj1-x1044.google.com with SMTP id mw10so888447pjb.2 for ; Tue, 01 Sep 2020 09:47:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e9NL/zqQnmkXSTv+zE5CjT9WgTIhkDu67eIbOBI/UcM=; b=Fc9Tcszai4/bLCcetlVEqYPAQ1RbvGCHa9RLG2Ilfq2hnHpUlH+Lr12DMYNrZdmIvd J1gYJyFz3ZiOX/nGK3nQjczz2tSYqUxBCxDgHFvewsnmXEHL6YOWDr9VUQUCbibQwnBk M2fdYx4wzwvAtVk13Zqj6hCdsFIiwdWeSQqGbgziZxiUH0VphzSLWp5ZUvWWJx2MOn2h gL54vp6ySx99JC7MH/gq8RjevHdiaiSvvXOrCHWy1sXa2yjK+ruue6B+w7cWMPWFR1Kr KJThp6mg237V6t+C9r4SBa1hX1xsy3I8Iy0oDK9sQUzCB9sS59nACFzmNK8ZkkNkBuT8 rW/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e9NL/zqQnmkXSTv+zE5CjT9WgTIhkDu67eIbOBI/UcM=; b=Ou4b4EpCINWv2vuYXoNPb/flLfWR1hVykVK1t3dHQ1TBwPhMSfGfoFI6PVjjS/TVDS HAElbucUOKG5Hr/t/uy9EvyXXnM9kuocgnr1aAAsxLA5G3wxmOGmPCIMIvT3/DxEMjVM M5OtUw23amqUtTjTP1GgNg3i23h91w9T2OfBjrqU0FZEu3v/tMnA01pCRSsG82Cnavbi bQRgu7izqTHFLhw04OkAVAWQzbb5P5ceow1OERYYb4vWFG1Voj1w96YjnUXASlGhMh2I zOwSsHSjzj1Vz9PTEX/k+4D5ORbIJX2vv661vJUjkESaTGodecLvCRaHxt+ZwWX7bc04 VwAw== X-Gm-Message-State: AOAM532UI3/Sw4Ru6vYkVdgOxhGE5EsqGgvC0rqnu0KZhpNjpG7I5HpE kK3j7igujcHVFwMAPPdouh8= X-Google-Smtp-Source: ABdhPJz0lqmiiFmT7Ipagca1YExexKrcu3kTt6dMEXbM6hlOjXoTtuz3jq+P6Mh0ozaDUeXYEjzlPQ== X-Received: by 2002:a17:902:a60f:: with SMTP id u15mr2120473plq.239.1598978831367; Tue, 01 Sep 2020 09:47:11 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id b64sm2430699pfa.200.2020.09.01.09.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2020 09:47:10 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Will Deacon , Robin Murphy Subject: [PATCH v16 13/20] iommu/arm-smmu: Add support for split pagetables Date: Tue, 1 Sep 2020 09:46:30 -0700 Message-Id: <20200901164707.2645413-14-robdclark@gmail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200901164707.2645413-1-robdclark@gmail.com> References: <20200901164707.2645413-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200901_124713_321999_549AFAD4 X-CRM114-Status: GOOD ( 19.44 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1044 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [robdclark[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Thierry Reding , open list , Greg Kroah-Hartman , Joerg Roedel , Akhil P Oommen , Stephen Boyd , Jordan Crouse , Sibi Sankar , Vivek Gautam , Bjorn Andersson , "moderated list:ARM SMMU DRIVERS" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Jordan Crouse Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected by the io-pgtable configuration. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 19 +++++++++++++++---- drivers/iommu/arm/arm-smmu/arm-smmu.h | 25 +++++++++++++++++++------ 2 files changed, 34 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 37d8d49299b4..8e884e58f208 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -552,11 +552,15 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; cb->ttbr[1] = 0; } else { - cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; - cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, - cfg->asid); + cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, + cfg->asid); cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cfg->asid); + + if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) + cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; + else + cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; } } else { cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; @@ -822,7 +826,14 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, /* Update the domain's page sizes to reflect the page table format */ domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; - domain->geometry.aperture_end = (1UL << ias) - 1; + + if (pgtbl_cfg.quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) { + domain->geometry.aperture_start = ~0UL << ias; + domain->geometry.aperture_end = ~0UL; + } else { + domain->geometry.aperture_end = (1UL << ias) - 1; + } + domain->geometry.force_aperture = true; /* Initialise the context bank with our page table cfg */ diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 83294516ac08..f3e456893f28 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -169,10 +169,12 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_CB_TCR 0x30 #define ARM_SMMU_TCR_EAE BIT(31) #define ARM_SMMU_TCR_EPD1 BIT(23) +#define ARM_SMMU_TCR_A1 BIT(22) #define ARM_SMMU_TCR_TG0 GENMASK(15, 14) #define ARM_SMMU_TCR_SH0 GENMASK(13, 12) #define ARM_SMMU_TCR_ORGN0 GENMASK(11, 10) #define ARM_SMMU_TCR_IRGN0 GENMASK(9, 8) +#define ARM_SMMU_TCR_EPD0 BIT(7) #define ARM_SMMU_TCR_T0SZ GENMASK(5, 0) #define ARM_SMMU_VTCR_RES1 BIT(31) @@ -350,12 +352,23 @@ struct arm_smmu_domain { static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg) { - return ARM_SMMU_TCR_EPD1 | - FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | - FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) | - FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) | - FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) | - FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz); + u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | + FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) | + FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) | + FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) | + FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz); + + /* + * When TTBR1 is selected shift the TCR fields by 16 bits and disable + * translation in TTBR0 + */ + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) { + tcr = (tcr << 16) & ~ARM_SMMU_TCR_A1; + tcr |= ARM_SMMU_TCR_EPD0; + } else + tcr |= ARM_SMMU_TCR_EPD1; + + return tcr; } static inline u32 arm_smmu_lpae_tcr2(struct io_pgtable_cfg *cfg) From patchwork Tue Sep 1 16:46:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 11749267 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AE9B613B6 for ; Tue, 1 Sep 2020 16:50:07 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 74E5D20767 for ; Tue, 1 Sep 2020 16:50:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="G4qSKztu"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KF6VyTYt" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 74E5D20767 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BCCrLK2vpFIqRc+nosEkGhtUtPhiOU0ykCwNtuxoC6o=; b=G4qSKztus+aI0iTevLqyHGTH4 HxV3atgE/mGF53O8jV+qd/pLpRhme5CpvB1d1HoSM/jHFE8+fBcDTExOIgWeuaFY6TVZn0ua7z5FT 9YZJQPc8ZXAKzeY6juqr0TDu8tfzDg2EZObhHadsO3aZE3kkzAzNCuBw8OyFwW3+6YVhnplZatMjV IPT7S8uLXTZ92SoQJefPkBI9hgYSpTpcgMiyvzz5eI9aM6uU3oQg29TonX5ylr1hjZktmHWbMcRIU RHQB7OFKyCyFdWW3xZRjmuSEyYq31OqtYGHRvr8soI2eGP9OsibnTWPypgkaOxCbiAZ2Unf4rTiJu iEK0r+NIA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9RL-0005Q3-4h; Tue, 01 Sep 2020 16:47:23 +0000 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9RH-0005Ny-UD for linux-arm-kernel@lists.infradead.org; Tue, 01 Sep 2020 16:47:20 +0000 Received: by mail-pf1-x443.google.com with SMTP id o68so1126803pfg.2 for ; Tue, 01 Sep 2020 09:47:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Tpvqka10jtiI4Fakhi4yppkwdviTd0raegoqIiBhtwU=; b=KF6VyTYt6S062StiB0OxYqSvtKJfg/6p3HU1eaLAbRElNS9WMsgiYnXoKtXDQwz2be 8bK4W+jC1LGCMYypglcXVIi3eKSctvWFUOs9NQn09hq+aHaA8bVKPjuzwTW3RejLa17a 2zqMdbS6xOmM6sUfitkIj2b+07pzpMl7qRcbYGhR5ZCcoHjgidIgd+JFukx32lrB9854 ujfK2cl/QZ0v7IdgesPG+xZU/EdopZFT8iUapTNFVDz7YvMRMxSd7Q1oPez3mvdcCUnd hSH15MIwmg+z4HvJv/cgyGBHwnzoQZ37oRsLB1qfz00CcW9SeBqD2z9e/9Z8MkXckDfX 2jFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Tpvqka10jtiI4Fakhi4yppkwdviTd0raegoqIiBhtwU=; b=L/O9A3QHSZYqRDYRkD1yXpRYZ8BaXRlkg9dfYu9yLyyLowaf2SHq0Sk4kK+hc565lH 8VUd91ccUYWgyJLmfgyBX8C4fqvF/1+iqFIrv60etnIUo6ooAEjRcl+uZNOWJkPeBa0/ keSPp9UmBcL2P5nVHXFZX4PiWVvoG/7axu/UvN4SvDAl89pMGCl7+9c/rHJfBODxnHS3 K18anD3RaYJ7MAjiNux8P7hq8ixNUqU9pa8jmXgJwfDOy//zcFn3A6uzgTTzAfi/6Dob 61ekIcfB4I25o4gDdSKZjl1auy+uuGuP1Z05WFmDaWrypexDSXhrh8PSteYSw+/uwBgF 54Mg== X-Gm-Message-State: AOAM533nSFGjZdZoU5ZZiubiTAD/Ge7RO3vEoyBnn73Y6xyxICuK1oPm exLUyFwEQdxQaI0MjV+lP+g= X-Google-Smtp-Source: ABdhPJwvaRmqhf9pjuHxTFHp3b/76glw/kTFHmxDQt+rc+mvX/FMJejx+ANCfD7XgzLokQHWRZatVg== X-Received: by 2002:a63:4e52:: with SMTP id o18mr2196521pgl.171.1598978837732; Tue, 01 Sep 2020 09:47:17 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id k5sm2773406pgk.78.2020.09.01.09.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2020 09:47:15 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Will Deacon , Robin Murphy Subject: [PATCH v16 14/20] iommu/arm-smmu: Prepare for the adreno-smmu implementation Date: Tue, 1 Sep 2020 09:46:31 -0700 Message-Id: <20200901164707.2645413-15-robdclark@gmail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200901164707.2645413-1-robdclark@gmail.com> References: <20200901164707.2645413-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200901_124719_979753_D7E761C7 X-CRM114-Status: GOOD ( 24.80 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:443 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [robdclark[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , open list , Jonathan Marek , Greg Kroah-Hartman , Joerg Roedel , Akhil P Oommen , Stephen Boyd , Jordan Crouse , Sibi Sankar , Vivek Gautam , Bjorn Andersson , Hanna Hawa , "moderated list:ARM SMMU DRIVERS" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Jordan Crouse Do a bit of prep work to add the upcoming adreno-smmu implementation. Add an hook to allow the implementation to choose which context banks to allocate. Move some of the common structs to arm-smmu.h in anticipation of them being used by the implementations and update some of the existing hooks to pass more information that the implementation will need. These modifications will be used by the upcoming Adreno SMMU implementation to identify the GPU device and properly configure it for pagetable switching. Co-developed-by: Rob Clark Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson --- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +- drivers/iommu/arm/arm-smmu/arm-smmu.c | 69 ++++++---------------- drivers/iommu/arm/arm-smmu/arm-smmu.h | 51 +++++++++++++++- 3 files changed, 68 insertions(+), 54 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c index a9861dcd0884..88f17cc33023 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c @@ -69,7 +69,7 @@ static int cavium_cfg_probe(struct arm_smmu_device *smmu) } static int cavium_init_context(struct arm_smmu_domain *smmu_domain, - struct io_pgtable_cfg *pgtbl_cfg) + struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { struct cavium_smmu *cs = container_of(smmu_domain->smmu, struct cavium_smmu, smmu); diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 8e884e58f208..68b7b9e6140e 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -65,41 +65,10 @@ module_param(disable_bypass, bool, S_IRUGO); MODULE_PARM_DESC(disable_bypass, "Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU."); -struct arm_smmu_s2cr { - struct iommu_group *group; - int count; - enum arm_smmu_s2cr_type type; - enum arm_smmu_s2cr_privcfg privcfg; - u8 cbndx; -}; - #define s2cr_init_val (struct arm_smmu_s2cr){ \ .type = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS, \ } -struct arm_smmu_smr { - u16 mask; - u16 id; - bool valid; -}; - -struct arm_smmu_cb { - u64 ttbr[2]; - u32 tcr[2]; - u32 mair[2]; - struct arm_smmu_cfg *cfg; -}; - -struct arm_smmu_master_cfg { - struct arm_smmu_device *smmu; - s16 smendx[]; -}; -#define INVALID_SMENDX -1 -#define cfg_smendx(cfg, fw, i) \ - (i >= fw->num_ids ? INVALID_SMENDX : cfg->smendx[i]) -#define for_each_cfg_sme(cfg, fw, i, idx) \ - for (i = 0; idx = cfg_smendx(cfg, fw, i), i < fw->num_ids; ++i) - static bool using_legacy_binding, using_generic_binding; static inline int arm_smmu_rpm_get(struct arm_smmu_device *smmu) @@ -234,19 +203,6 @@ static int arm_smmu_register_legacy_master(struct device *dev, } #endif /* CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS */ -static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) -{ - int idx; - - do { - idx = find_next_zero_bit(map, end, start); - if (idx == end) - return -ENOSPC; - } while (test_and_set_bit(idx, map)); - - return idx; -} - static void __arm_smmu_free_bitmap(unsigned long *map, int idx) { clear_bit(idx, map); @@ -578,7 +534,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, } } -static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) +void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) { u32 reg; bool stage1; @@ -665,7 +621,8 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) } static int arm_smmu_init_domain_context(struct iommu_domain *domain, - struct arm_smmu_device *smmu) + struct arm_smmu_device *smmu, + struct device *dev) { int irq, start, ret = 0; unsigned long ias, oas; @@ -780,10 +737,20 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, ret = -EINVAL; goto out_unlock; } - ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, + + smmu_domain->smmu = smmu; + + if (smmu->impl && smmu->impl->alloc_context_bank) + ret = smmu->impl->alloc_context_bank(smmu_domain, dev, + start, smmu->num_context_banks); + else + ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); - if (ret < 0) + + if (ret < 0) { + smmu_domain->smmu = NULL; goto out_unlock; + } cfg->cbndx = ret; if (smmu->version < ARM_SMMU_V2) { @@ -798,8 +765,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, else cfg->asid = cfg->cbndx; - smmu_domain->smmu = smmu; - pgtbl_cfg = (struct io_pgtable_cfg) { .pgsize_bitmap = smmu->pgsize_bitmap, .ias = ias, @@ -810,7 +775,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, }; if (smmu->impl && smmu->impl->init_context) { - ret = smmu->impl->init_context(smmu_domain, &pgtbl_cfg); + ret = smmu->impl->init_context(smmu_domain, &pgtbl_cfg, dev); if (ret) goto out_clear_smmu; } @@ -1194,7 +1159,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) return ret; /* Ensure that the domain is finalised */ - ret = arm_smmu_init_domain_context(domain, smmu); + ret = arm_smmu_init_domain_context(domain, smmu, dev); if (ret < 0) goto rpm_put; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index f3e456893f28..59ff3fc5c6c8 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -256,6 +256,21 @@ enum arm_smmu_implementation { QCOM_SMMUV2, }; +struct arm_smmu_s2cr { + struct iommu_group *group; + int count; + enum arm_smmu_s2cr_type type; + enum arm_smmu_s2cr_privcfg privcfg; + u8 cbndx; +}; + +struct arm_smmu_smr { + u16 mask; + u16 id; + bool valid; + bool pinned; +}; + struct arm_smmu_device { struct device *dev; @@ -331,6 +346,13 @@ struct arm_smmu_cfg { }; #define ARM_SMMU_INVALID_IRPTNDX 0xff +struct arm_smmu_cb { + u64 ttbr[2]; + u32 tcr[2]; + u32 mair[2]; + struct arm_smmu_cfg *cfg; +}; + enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 = 0, ARM_SMMU_DOMAIN_S2, @@ -350,6 +372,11 @@ struct arm_smmu_domain { struct iommu_domain domain; }; +struct arm_smmu_master_cfg { + struct arm_smmu_device *smmu; + s16 smendx[]; +}; + static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg) { u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | @@ -400,14 +427,35 @@ struct arm_smmu_impl { int (*cfg_probe)(struct arm_smmu_device *smmu); int (*reset)(struct arm_smmu_device *smmu); int (*init_context)(struct arm_smmu_domain *smmu_domain, - struct io_pgtable_cfg *cfg); + struct io_pgtable_cfg *cfg, struct device *dev); void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync, int status); int (*def_domain_type)(struct device *dev); irqreturn_t (*global_fault)(int irq, void *dev); irqreturn_t (*context_fault)(int irq, void *dev); + int (*alloc_context_bank)(struct arm_smmu_domain *smmu_domain, + struct device *dev, int start, int max); }; +#define INVALID_SMENDX -1 +#define cfg_smendx(cfg, fw, i) \ + (i >= fw->num_ids ? INVALID_SMENDX : cfg->smendx[i]) +#define for_each_cfg_sme(cfg, fw, i, idx) \ + for (i = 0; idx = cfg_smendx(cfg, fw, i), i < fw->num_ids; ++i) + +static inline int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) +{ + int idx; + + do { + idx = find_next_zero_bit(map, end, start); + if (idx == end) + return -ENOSPC; + } while (test_and_set_bit(idx, map)); + + return idx; +} + static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n) { return smmu->base + (n << smmu->pgshift); @@ -472,6 +520,7 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu); struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu); struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); +void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx); int arm_mmu500_reset(struct arm_smmu_device *smmu); #endif /* _ARM_SMMU_H */ From patchwork Tue Sep 1 16:46:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 11749263 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E60BF109A for ; Tue, 1 Sep 2020 16:49:47 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BA9912067C for ; Tue, 1 Sep 2020 16:49:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="SRBpLckb"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="J04apcnc" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BA9912067C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=L6pF5JFe0OvXYtflWbHZbIGY6iqvmGdrl/YsGKMH1PE=; b=SRBpLckbrqEq42wFcCh2y/OLa C3Rr6Ycjv7dMLVskYhTwczc/zksc0y+aVOPcoJwzKOrZ69kXlV5Ffsyt5Si8I7lVlXpECp1oygxjt L2RJfyMWd+zhlfW1wA2OgNyRzTDnV0PHW5CJPyABYgCsGj0Rkwd5p692eWkH3xDqak22WFH1aGhmn sPQdzt+9E52M/fU4BC3yJ9sUjCIO67K5D97rUwtOy/58dcLAdwD4k+IYG8ArXwh2zYs36e9dXfrTF UUaHg5K8yhLVdNL/w2SxU82NBO4O5nr6dMlFB4JRpRWpSHMYp3TxkFgOxZHak7bQivHw9soooHQ2M 6CL7xEpAg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9RP-0005SZ-Rt; Tue, 01 Sep 2020 16:47:27 +0000 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9RL-0005Pm-Sv for linux-arm-kernel@lists.infradead.org; Tue, 01 Sep 2020 16:47:24 +0000 Received: by mail-pl1-x642.google.com with SMTP id t11so821556plr.5 for ; Tue, 01 Sep 2020 09:47:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TkWyTxARTuQIVpZ4nA1zGbs/CkLTaav5w1kzBb9PxHE=; b=J04apcnc9yNiayNZvi3RYs6LgZ8DqVcJmH8Wr7KTsf3utcG6+8ceh5GGe5HDRit6bk MdnphK+NGv+I+f/0sk1/MaAHJmh7Ktms/5w3cL3HrJf3mZ0W5ysTqzr+uVCGsNi54rdD rbMoWwFeCig9zC+wiWq9md/RLsMrviLGxPOZZN0NOe+0xEB+j0laN7Xo5Owln6TF29+P eh6M6tnKd8cTmhDBIPYHE863ookRQ6I8lmDX0mV5Uhc8sLnydbYSbjJvwbMYCh4oJk0n Nqh1wBWRypBsmGZYuXraOizi28hKZ/p3WEGvqXA1NuPh18aROFbAVr8B1Uj4YI8vwNGK jMvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TkWyTxARTuQIVpZ4nA1zGbs/CkLTaav5w1kzBb9PxHE=; b=GNkK1IjqhBKq0qWgpCFqElf1OIfJMjwV9aW7jWi3hScGfp3WmSZ47T/hCQBFuZWCiM ggNEvN5/SkDidfq46IBu7u1I+gZebbp2V6lCCsnyN0kY2vz91WsIqY+HcKoubSTQnb7x ZmC9HhgSKnVK7QGpdfX+ta8QrbKHfavMyXc5QuC8Jl/zVcd93QkDr3ZtL0JiQA/MsKOG agn0z5VLCNQeXtAq5Xy8IvDruMwEp1urBZAoihU7rJNZ9E8xivlePj0iu538Wg+AUMw+ mD/NEHnkFl+GrccTeQ6XsCr40rsh3SIWhTf7Iiy7UyCr1zfJ68BWHxsXC79p0ynin9m5 RVQQ== X-Gm-Message-State: AOAM532qe9HirQXN4/A0Sn6HrawSsUCL6ab7wKM4SMT0YBsR27IHt25H s4AixQCAcuaTIzKCCaTpKik= X-Google-Smtp-Source: ABdhPJzPwgooR5I07lG6agi4o+XJIiUnZtxaG2d2E6PYRW6u09VjILA4cchEz56ubddK4K9nWje7yw== X-Received: by 2002:a17:902:407:: with SMTP id 7mr2182544ple.167.1598978841446; Tue, 01 Sep 2020 09:47:21 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id u2sm2036508pjj.57.2020.09.01.09.47.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2020 09:47:20 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Will Deacon , Robin Murphy Subject: [PATCH v16 15/20] iommu/arm-smmu: Constify some helpers Date: Tue, 1 Sep 2020 09:46:32 -0700 Message-Id: <20200901164707.2645413-16-robdclark@gmail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200901164707.2645413-1-robdclark@gmail.com> References: <20200901164707.2645413-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200901_124723_954830_806C3F5D X-CRM114-Status: GOOD ( 12.33 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:642 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [robdclark[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , open list , Joerg Roedel , Akhil P Oommen , Stephen Boyd , Jordan Crouse , Sibi Sankar , Vivek Gautam , Bjorn Andersson , "moderated list:ARM SMMU DRIVERS" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Rob Clark Sprinkle a few `const`s where helpers don't need write access. Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson --- drivers/iommu/arm/arm-smmu/arm-smmu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 59ff3fc5c6c8..27c83333fc50 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -377,7 +377,7 @@ struct arm_smmu_master_cfg { s16 smendx[]; }; -static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg) +static inline u32 arm_smmu_lpae_tcr(const struct io_pgtable_cfg *cfg) { u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) | @@ -398,13 +398,13 @@ static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg) return tcr; } -static inline u32 arm_smmu_lpae_tcr2(struct io_pgtable_cfg *cfg) +static inline u32 arm_smmu_lpae_tcr2(const struct io_pgtable_cfg *cfg) { return FIELD_PREP(ARM_SMMU_TCR2_PASIZE, cfg->arm_lpae_s1_cfg.tcr.ips) | FIELD_PREP(ARM_SMMU_TCR2_SEP, ARM_SMMU_TCR2_SEP_UPSTREAM); } -static inline u32 arm_smmu_lpae_vtcr(struct io_pgtable_cfg *cfg) +static inline u32 arm_smmu_lpae_vtcr(const struct io_pgtable_cfg *cfg) { return ARM_SMMU_VTCR_RES1 | FIELD_PREP(ARM_SMMU_VTCR_PS, cfg->arm_lpae_s2_cfg.vtcr.ps) | From patchwork Tue Sep 1 16:46:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 11749265 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 224F713B6 for ; Tue, 1 Sep 2020 16:49:55 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E2C0220767 for ; Tue, 1 Sep 2020 16:49:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="HtMOHU4Y"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Vvt4z6NY" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E2C0220767 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/t7iv1nlZr50aS6/INgJVRe3pL9UNjjE0kiMR/QYtF8=; b=HtMOHU4Y9ARBgKUBYQmhoorRv bMINffmFnGf6PUhASV0hkeHBZiwYBCvBUuBU+zTZaTx/4FAkOyTuvFcc2xFeVHi7BM3rGDO51j4Hf I0Hr58G2PXuL8lQAzwcd1OXtX+PjThxm5ulfGpbh7nBYKdlMuAYsNpz1a5W66IfAZ0SzUd/EAG2O8 MNRNf63nan8gnqVivL6sWaXvBeM9fDqC4tpnYwId/iRh9sqHsa3A0YPB3Sb9AQdeu3MBWiN03QOw1 ioHeBBFssVCDerjTWFJIKYeVSYI/na44qZDJM0P32mxdgtBLv8hiRH4LiDLTdw8EU8WliA3MVa9Bv jAcdCj3HQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9RV-0005Ux-HZ; Tue, 01 Sep 2020 16:47:33 +0000 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9RS-0005TM-Kw for linux-arm-kernel@lists.infradead.org; Tue, 01 Sep 2020 16:47:31 +0000 Received: by mail-pl1-x644.google.com with SMTP id z15so814972plo.7 for ; Tue, 01 Sep 2020 09:47:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HHQe8hd0SNUst71ZNXeL5chYz56GGcoaTg6ES2ptaYQ=; b=Vvt4z6NYCla4GP+vjbTyAMlKrVVgcHmpCYZH5Z5TjYwOUTKsymhis7Ay1mZnAPameZ MneTXP8iZFk4BUdv5V6yeY8O04TY9zDM+oMhEzCStH8zZGerYpnGlwQSNVuGaDYpL2Oc Y8HETyj7gC0dcdzGKKTYx2D5uLm4fqZyJBf6ItlCOiBYHwJFoevanLVLBXLq90BfqJQF wjQrk4FGPHIzoo2647pbgAOQZXScG5vltEDKyvqz+DxRL29DvJoMg5AT9JGM+OF9wP3Z O4d6I4Ycjd3yqoto4uk59y1G4FQMxA6qtyRkiQzvv597aLu+pJfh62F7uDArGJFcMKhH 2N0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HHQe8hd0SNUst71ZNXeL5chYz56GGcoaTg6ES2ptaYQ=; b=KpfCKKraHICpTDYvXwaDJts5gc9c6KvdYqJK3NrYTuQHfupRcwzlVgXFcBXHSq2Pt2 DsW3m9CZ8ZD6nBl2CL7tTYF8p6y++2EFbT9AfNb5kKHcfO3iTlgZvZ998IDBFQNTrLZC lCDIrjuCXjVVSwnJhdlXv55A2dViQzDpF5Rg29f5vB717487/EZuhsCHHE1Velgix5pw Op4/NlK55vV2CkETfEHCU6bNWsqf6RCYsW52zrbddkL2s7Jkgt5CDSxL74rCTM+oyNAU aXLGiCWLEman+I74aQmePWVNijV6QcLMHNOMU2VKc0gd1vOFzJv+cOMEe3kvM6ZCfQeh 04VA== X-Gm-Message-State: AOAM533WtVtSfoTCDmOyDrRf/u9JKn5XMkN7/D4tCSSlnkVLASCOQ5sb 3KSGjeAvRA31miUKAnf/F94= X-Google-Smtp-Source: ABdhPJwrz7fA6ioJ6DgxUvLVHDoIaOlNAA5IhAzEfNhey3L+TN5atixeGGeG3X40lEuWD68FTalp5w== X-Received: by 2002:a17:90a:f682:: with SMTP id cl2mr2492580pjb.158.1598978848095; Tue, 01 Sep 2020 09:47:28 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id b18sm2607960pgk.36.2020.09.01.09.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2020 09:47:27 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Will Deacon , Robin Murphy Subject: [PATCH v16 16/20] iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU Date: Tue, 1 Sep 2020 09:46:33 -0700 Message-Id: <20200901164707.2645413-17-robdclark@gmail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200901164707.2645413-1-robdclark@gmail.com> References: <20200901164707.2645413-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200901_124730_711816_A4DE5074 X-CRM114-Status: GOOD ( 26.80 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:644 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [robdclark[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , open list , Joerg Roedel , Akhil P Oommen , Stephen Boyd , Jordan Crouse , Sibi Sankar , Vivek Gautam , Bjorn Andersson , Hanna Hawa , "moderated list:ARM SMMU DRIVERS" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Jordan Crouse Add a special implementation for the SMMU attached to most Adreno GPU target triggered from the qcom,adreno-smmu compatible string. The new Adreno SMMU implementation will enable split pagetables (TTBR1) for the domain attached to the GPU device (SID 0) and hard code it context bank 0 so the GPU hardware can implement per-instance pagetables. Co-developed-by: Rob Clark Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson --- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 + drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 149 ++++++++++++++++++++- drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + 3 files changed, 151 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c index 88f17cc33023..d199b4bff15d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c @@ -223,6 +223,9 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) of_device_is_compatible(np, "qcom,sm8250-smmu-500")) return qcom_smmu_impl_init(smmu); + if (of_device_is_compatible(smmu->dev->of_node, "qcom,adreno-smmu")) + return qcom_adreno_smmu_impl_init(smmu); + if (of_device_is_compatible(np, "marvell,ap806-smmu-500")) smmu->impl = &mrvl_mmu500_impl; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index be4318044f96..5640d9960610 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -3,6 +3,7 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ +#include #include #include @@ -12,6 +13,132 @@ struct qcom_smmu { struct arm_smmu_device smmu; }; +#define QCOM_ADRENO_SMMU_GPU_SID 0 + +static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + int i; + + /* + * The GPU will always use SID 0 so that is a handy way to uniquely + * identify it and configure it for per-instance pagetables + */ + for (i = 0; i < fwspec->num_ids; i++) { + u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); + + if (sid == QCOM_ADRENO_SMMU_GPU_SID) + return true; + } + + return false; +} + +static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg( + const void *cookie) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct io_pgtable *pgtable = + io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); + return &pgtable->cfg; +} + +/* + * Local implementation to configure TTBR0 with the specified pagetable config. + * The GPU driver will call this to enable TTBR0 when per-instance pagetables + * are active + */ + +static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, + const struct io_pgtable_cfg *pgtbl_cfg) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; + + /* The domain must have split pagetables already enabled */ + if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) + return -EINVAL; + + /* If the pagetable config is NULL, disable TTBR0 */ + if (!pgtbl_cfg) { + /* Do nothing if it is already disabled */ + if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) + return -EINVAL; + + /* Set TCR to the original configuration */ + cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); + cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); + } else { + u32 tcr = cb->tcr[0]; + + /* Don't call this again if TTBR0 is already enabled */ + if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) + return -EINVAL; + + tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); + tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); + + cb->tcr[0] = tcr; + cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; + cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); + } + + arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); + + return 0; +} + +static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, + struct device *dev, int start, int count) +{ + struct arm_smmu_device *smmu = smmu_domain->smmu; + + /* + * Assign context bank 0 to the GPU device so the GPU hardware can + * switch pagetables + */ + if (qcom_adreno_smmu_is_gpu_device(dev)) { + start = 0; + count = 1; + } else { + start = 1; + } + + return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); +} + +static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, + struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) +{ + struct adreno_smmu_priv *priv; + + /* Only enable split pagetables for the GPU device (SID 0) */ + if (!qcom_adreno_smmu_is_gpu_device(dev)) + return 0; + + /* + * All targets that use the qcom,adreno-smmu compatible string *should* + * be AARCH64 stage 1 but double check because the arm-smmu code assumes + * that is the case when the TTBR1 quirk is enabled + */ + if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && + (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) + pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; + + /* + * Initialize private interface with GPU: + */ + + priv = dev_get_drvdata(dev); + priv->cookie = smmu_domain; + priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; + priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; + + return 0; +} + static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { .compatible = "qcom,adreno" }, { .compatible = "qcom,mdp4" }, @@ -65,7 +192,15 @@ static const struct arm_smmu_impl qcom_smmu_impl = { .reset = qcom_smmu500_reset, }; -struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) +static const struct arm_smmu_impl qcom_adreno_smmu_impl = { + .init_context = qcom_adreno_smmu_init_context, + .def_domain_type = qcom_smmu_def_domain_type, + .reset = qcom_smmu500_reset, + .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, +}; + +static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, + const struct arm_smmu_impl *impl) { struct qcom_smmu *qsmmu; @@ -75,8 +210,18 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) qsmmu->smmu = *smmu; - qsmmu->smmu.impl = &qcom_smmu_impl; + qsmmu->smmu.impl = impl; devm_kfree(smmu->dev, smmu); return &qsmmu->smmu; } + +struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) +{ + return qcom_smmu_create(smmu, &qcom_smmu_impl); +} + +struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu) +{ + return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); +} diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 27c83333fc50..cd75a33967bb 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -519,6 +519,7 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page, struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu); struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu); struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); +struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu); void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx); int arm_mmu500_reset(struct arm_smmu_device *smmu); From patchwork Tue Sep 1 16:46:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 11749233 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 40559109A for ; Tue, 1 Sep 2020 16:48:05 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 186B12067C for ; Tue, 1 Sep 2020 16:48:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="EuL/Pboe"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="I7UCJIze" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 186B12067C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=TTxuWLhH5kAIYSV4EFvzPIVKL/rXMIMtzFfB1ncL494=; b=EuL/PboeR9xf8g1YOXc0PCjLI lMl/5uTVSHiZmZYnAx2vtjx/rEYPfFN2kDCxj9ywqsx+4wcF45Fsjd8Mz6kEkm3Im0P2c7NPa8lJq X3CXmFFE6894sP1EM7bVgA2xSY0otuWCKkZeRfxrYSjJq05NmQpPObFvz+k6eGDOtGyt6h7qyorbW z/ev7i8KO5iKJ476wKlwua5sSThvXIAq1lHe83e24o+n3uFdGXCN1EaHmQoTMI+A8KszCFb/iVyNo z9bJJGxAsOnLzvgW+QY4iiaANb7jqlAe03DiKMZZP7EKwqy9w0Gdx7zyUvVQ+whQcp42RW4Xwf234 +FhCW7wZg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9Rk-0005cF-RI; Tue, 01 Sep 2020 16:47:49 +0000 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9RZ-0005X1-KR for linux-arm-kernel@lists.infradead.org; Tue, 01 Sep 2020 16:47:39 +0000 Received: by mail-pg1-x541.google.com with SMTP id h12so976599pgm.7 for ; Tue, 01 Sep 2020 09:47:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6bArpQOenZ1r4IwzKVpzZ3sdPjqYb3Z5T6BZu8MLRy0=; b=I7UCJIzeBAAOgAsNsgzoZK0Uza7dH630S1MxfkMHiactiF7JQraMk9MJUguKgnYv2q veR/pLP1tvmFgw31DChdsSWvzB082tn5HdPs6QStgad0OAEqSQVtxxzoz1a4U6Q1BSl1 f36D17v3JLTqEsrDLWUw3jvM5fOpOIM9QRY+99292MfG+ajAbggm1TZAo4GktMprZHXx aKdKGCwrN+fcInF0B1thh9V3FrL9xReZb8qF35PSwTxaz3jTDfLdTpGX+6mEkBzUC1LO AWzae63KE8yDM8KCr/56g4Ryiom6ATcPCuMoQOhO4mHakiv0tm5ZTM7YKiiSoOF9P0sE 4WcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6bArpQOenZ1r4IwzKVpzZ3sdPjqYb3Z5T6BZu8MLRy0=; b=MsfhIvCRlQz/87MiiK0psuGrJ98hrVJLE6J3PTlmWk11tFspShQFdGR2vCHFaagUfL kQQZicvBpY4uv93iR1OuCEX5uUg4+6wvvL9V05LXak/auwoU4SXXnR1Xt/G4CS+oRrH8 dOCRzeMfHd50cYBgqK1e9tnj0dHqarog+51PC9k9eyi1MNzwnVgjs5VprdBKQPR2xXMp KpJNQqHkOzBsFxLSKyLbi8A7fswIu9cPvnOglUUda+l+AzR9VgKqZR30nBTf7WPoWoK/ boaGnT9RWFTf+uA11o80ZlmS+JkcK+LHFtEXD/PdI1r6FG777ME0Fl7+Zfx7WxvEo4wb xvZQ== X-Gm-Message-State: AOAM533nsG9vLaZjxHKB9dDJ3ri3yz7DoKIw3UNPC5ZRyu0wEZ2MqLwY MLlxvpQ8c5k0sWz5d1wUraQ= X-Google-Smtp-Source: ABdhPJxP2Btj8c5sNN2AEoBDA2X8SJkq9iwTq3L2XoqeeqMxQ9sgaHXP7ArHd4K3sOypPhsMrGtq/Q== X-Received: by 2002:a63:62c7:: with SMTP id w190mr2280107pgb.25.1598978854996; Tue, 01 Sep 2020 09:47:34 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id k6sm1998873pju.2.2020.09.01.09.47.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2020 09:47:33 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Will Deacon , Robin Murphy Subject: [PATCH v16 17/20] iommu/arm-smmu: Add a way for implementations to influence SCTLR Date: Tue, 1 Sep 2020 09:46:34 -0700 Message-Id: <20200901164707.2645413-18-robdclark@gmail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200901164707.2645413-1-robdclark@gmail.com> References: <20200901164707.2645413-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200901_124738_104131_A826CBD7 X-CRM114-Status: GOOD ( 15.91 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:541 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [robdclark[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , Thierry Reding , open list , Greg Kroah-Hartman , Joerg Roedel , Akhil P Oommen , Stephen Boyd , Jordan Crouse , Sibi Sankar , Vivek Gautam , Bjorn Andersson , "moderated list:ARM SMMU DRIVERS" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Rob Clark For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that pending translations are not terminated on iova fault. Otherwise a terminated CP read could hang the GPU by returning invalid command-stream data. Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++++++ drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++ 3 files changed, 12 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 5640d9960610..2aa6249050ff 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -127,6 +127,12 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; + /* + * On the GPU device we want to process subsequent transactions after a + * fault to keep the GPU from hanging + */ + smmu_domain->cfg.sctlr_set |= ARM_SMMU_SCTLR_HUPCF; + /* * Initialize private interface with GPU: */ diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 68b7b9e6140e..1773f54a7464 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -617,6 +617,9 @@ void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) reg |= ARM_SMMU_SCTLR_E; + reg |= cfg->sctlr_set; + reg &= ~cfg->sctlr_clr; + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index cd75a33967bb..2df3a70a8a41 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -144,6 +144,7 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_CB_SCTLR 0x0 #define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12) #define ARM_SMMU_SCTLR_CFCFG BIT(7) +#define ARM_SMMU_SCTLR_HUPCF BIT(8) #define ARM_SMMU_SCTLR_CFIE BIT(6) #define ARM_SMMU_SCTLR_CFRE BIT(5) #define ARM_SMMU_SCTLR_E BIT(4) @@ -341,6 +342,8 @@ struct arm_smmu_cfg { u16 asid; u16 vmid; }; + u32 sctlr_set; /* extra bits to set in SCTLR */ + u32 sctlr_clr; /* bits to mask in SCTLR */ enum arm_smmu_cbar_type cbar; enum arm_smmu_context_fmt fmt; }; From patchwork Tue Sep 1 16:46:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 11749235 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C23B5109A for ; Tue, 1 Sep 2020 16:48:12 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 991E72078B for ; Tue, 1 Sep 2020 16:48:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="nblOm33d"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iK/gWhvX" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 991E72078B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=07A8eaz6PTpBpq4LmedOSFNlwA0SYrP02jLpH/AwhaA=; b=nblOm33dVz3D4qYor1ET7YygB V0jolFT+HbLyL0JJQ9a9j7NSMdXlm6s8IL1oP3S3pMGlFR70XRau8C4t76uwCtWdm5Pijj+CXeDZY mNU5AXlDbO+fEdhY91tVSx+XnA47Zulrk8YX9OabzO+0/1Gy7/GShEBSIi4F8AGfeG/EpHwHM3BF2 wI5hAxEHQcQlJir7pmn3EHnM8z6xggqiSt2Ogy0dlTTBc+ZObVAWw/GJgz17UkCGTtYIOQV2BHrXA 8ovcD2OlKEuvL3OZdPkdS9khVlnXrUELY3FDPCP6nBsPOVTEruO1BUWJQ9YeVA88TboEyUG5/4ulM VhrxVwtTw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9Ru-0005l7-Ru; Tue, 01 Sep 2020 16:47:58 +0000 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kD9Rc-0005Yi-3I for linux-arm-kernel@lists.infradead.org; Tue, 01 Sep 2020 16:47:44 +0000 Received: by mail-pg1-x542.google.com with SMTP id d19so969796pgl.10 for ; Tue, 01 Sep 2020 09:47:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RI73hAm8taFHglKyL+fRjHiZ9E+te2SePrFdWbpImkA=; b=iK/gWhvX43nTVceqadIhYvSqK91IRCJCr5an4KZFK1DTvINxVcTZMuQyegyN/355Bw JZQ7Y2NxnEyNgHakr4ZD9u87n6KRWb0TKstSl2SZ3PzPV7YLJVSPcDu6euUaGOQkNRud h/4COkh5TdixQZkT8bM/oxcl04nzVQ3WdlDCo9PGw+fVjnSiUbbujl8LFIUnDWnDJ2Xd Kxrsomm8Prr7eCxcP7aZHzasUFTLyJ4ODxcdLAuEMq9dv/FyYghppWV3sNUAyRmMhpzB UUeqqU/WJ87+Ydrrx0WdNSh8807h1sbE0add+3495kD6sIYWodJy28OaQcodE2eH8PRw XMCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RI73hAm8taFHglKyL+fRjHiZ9E+te2SePrFdWbpImkA=; b=g319y4Sw40N3tpB5DIZ5w4avaiGV8ahyYM1IYhvc/FA1+O5U+F2p8AeMV6HhhLYudt QFm3Qe2jWHalKpa7YtBcKmHQBZSUUHXtfK8X1PVstGq203CwlagzzBhjyJW9kJYb2uBO Ziv4OEsYCrG8w09Y2KMXqLBlgntzMu5u7w7ZoTfF2p9uBptLOtVrt+WZUebM5QFZGgO4 WdcagP/D5wB/ew/U9XP7CmMiOXKR2pvQ5jql3SjCtv3SxpSECooC+6fRe8azbFLKa4vZ el2+DcPdLXW4VpuR5wpR+cmrIu/cp+cd0FhYJ79vAWFFmH08F3iJz5o6XTFksmx2+0QT MGug== X-Gm-Message-State: AOAM532nRRu8mBANCcRynoyq6tdNvMI1qUlcJs+GN8/pnIq6fbyiG4QG yB4/aZLijp6ll2EueE3gPFU= X-Google-Smtp-Source: ABdhPJxqESFlReg5RGOlUO1KFXl0W8xH0asJAzoRAGy9j2bDD2ncGLx0thhLxLusFeJPcxyqh3MDbA== X-Received: by 2002:a63:6d4c:: with SMTP id i73mr2312150pgc.63.1598978857690; Tue, 01 Sep 2020 09:47:37 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id i1sm2497656pfo.212.2020.09.01.09.47.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2020 09:47:36 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Will Deacon , Robin Murphy Subject: [PATCH v16 18/20] dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU Date: Tue, 1 Sep 2020 09:46:35 -0700 Message-Id: <20200901164707.2645413-19-robdclark@gmail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200901164707.2645413-1-robdclark@gmail.com> References: <20200901164707.2645413-1-robdclark@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200901_124740_211389_4DB737D8 X-CRM114-Status: GOOD ( 11.63 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:542 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [robdclark[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list , Joerg Roedel , Akhil P Oommen , Stephen Boyd , Jordan Crouse , Rob Herring , Sibi Sankar , Vivek Gautam , Bjorn Andersson , "moderated list:ARM SMMU DRIVERS" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Jordan Crouse Every Qcom Adreno GPU has an embedded SMMU for its own use. These devices depend on unique features such as split pagetables, different stall/halt requirements and other settings. Identify them with a compatible string so that they can be identified in the arm-smmu implementation specific code. Signed-off-by: Jordan Crouse Reviewed-by: Rob Herring Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 503160a7b9a0..3b63f2ae24db 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -28,8 +28,6 @@ properties: - enum: - qcom,msm8996-smmu-v2 - qcom,msm8998-smmu-v2 - - qcom,sc7180-smmu-v2 - - qcom,sdm845-smmu-v2 - const: qcom,smmu-v2 - description: Qcom SoCs implementing "arm,mmu-500" @@ -40,6 +38,13 @@ properties: - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - const: arm,mmu-500 + - description: Qcom Adreno GPUs implementing "arm,smmu-v2" + items: + - enum: + - qcom,sc7180-smmu-v2 + - qcom,sdm845-smmu-v2 + - const: qcom,adreno-smmu + - const: qcom,smmu-v2 - description: Marvell SoCs implementing "arm,mmu-500" items: - const: marvell,ap806-smmu-500