From patchwork Thu Sep 3 15:04:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satya Priya X-Patchwork-Id: 11753973 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C18301575 for ; Thu, 3 Sep 2020 15:07:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A7C3C2072A for ; Thu, 3 Sep 2020 15:07:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729024AbgICPH2 (ORCPT ); Thu, 3 Sep 2020 11:07:28 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:10653 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729469AbgICPFi (ORCPT ); Thu, 3 Sep 2020 11:05:38 -0400 Received: from ironmsg07-lv.qualcomm.com (HELO ironmsg07-lv.qulacomm.com) ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 03 Sep 2020 08:05:31 -0700 Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qulacomm.com with ESMTP/TLS/AES256-SHA; 03 Sep 2020 08:05:29 -0700 Received: from c-skakit-linux.ap.qualcomm.com (HELO c-skakit-linux.qualcomm.com) ([10.242.51.242]) by ironmsg02-blr.qualcomm.com with ESMTP; 03 Sep 2020 20:35:05 +0530 Received: by c-skakit-linux.qualcomm.com (Postfix, from userid 2344709) id 9D197D83; Thu, 3 Sep 2020 20:35:04 +0530 (IST) From: satya priya To: Bjorn Andersson Cc: Matthias Kaehlcke , gregkh@linuxfoundation.org, Andy Gross , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, akashast@codeaurora.org, rojay@codeaurora.org, msavaliy@qti.qualcomm.com, satya priya Subject: [PATCH V4 1/4] arm64: dts: sc7180: Add wakeup support over UART RX Date: Thu, 3 Sep 2020 20:34:55 +0530 Message-Id: <1599145498-20707-2-git-send-email-skakit@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599145498-20707-1-git-send-email-skakit@codeaurora.org> References: <1599145498-20707-1-git-send-email-skakit@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the necessary pinctrl and interrupts to make UART wakeup capable. If QUP function is selected in sleep state, UART RTS/RFR is pulled high during suspend and BT SoC not able to send wakeup bytes. So, configure GPIO mode in sleep state to keep it low during suspend. Signed-off-by: satya priya Reviewed-by: Akash Asthana --- Changes in V2: - As per Matthias's comment added wakeup support for all the UARTs of SC7180. Changes in V3: - No change. Changes in V4: - As per Matthias's comment, added the reason for configuring GPIO mode for sleep state in commit text. arch/arm64/boot/dts/qcom/sc7180.dtsi | 98 ++++++++++++++++++++++++++++++------ 1 file changed, 84 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index d46b383..855b13e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -793,9 +793,11 @@ reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&qup_uart0_default>; - interrupts = ; + pinctrl-1 = <&qup_uart0_sleep>; + interrupts-extended = <&intc GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 37 IRQ_TYPE_EDGE_FALLING>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, @@ -845,9 +847,11 @@ reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&qup_uart1_default>; - interrupts = ; + pinctrl-1 = <&qup_uart1_sleep>; + interrupts-extended = <&intc GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 3 IRQ_TYPE_EDGE_FALLING>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, @@ -931,9 +935,11 @@ reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&qup_uart3_default>; - interrupts = ; + pinctrl-1 = <&qup_uart3_sleep>; + interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, @@ -1017,9 +1023,11 @@ reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&qup_uart5_default>; - interrupts = ; + pinctrl-1 = <&qup_uart5_sleep>; + interrupts-extended = <&intc GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 28 IRQ_TYPE_EDGE_FALLING>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>, @@ -1084,9 +1092,11 @@ reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&qup_uart6_default>; - interrupts = ; + pinctrl-1 = <&qup_uart6_sleep>; + interrupts-extended = <&intc GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 62 IRQ_TYPE_EDGE_FALLING>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, @@ -1256,9 +1266,11 @@ reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&qup_uart10_default>; - interrupts = ; + pinctrl-1 = <&qup_uart10_sleep>; + interrupts-extended = <&intc GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 89 IRQ_TYPE_EDGE_FALLING>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, @@ -1308,9 +1320,11 @@ reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&qup_uart11_default>; - interrupts = ; + pinctrl-1 = <&qup_uart11_sleep>; + interrupts-extended = <&intc GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 56 IRQ_TYPE_EDGE_FALLING>; power-domains = <&rpmhpd SC7180_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>, @@ -1638,6 +1652,14 @@ }; }; + qup_uart0_sleep: qup-uart0-sleep { + pinmux { + pins = "gpio34", "gpio35", + "gpio36", "gpio37"; + function = "gpio"; + }; + }; + qup_uart1_default: qup-uart1-default { pinmux { pins = "gpio0", "gpio1", @@ -1646,6 +1668,14 @@ }; }; + qup_uart1_sleep: qup-uart1-sleep { + pinmux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + }; + qup_uart2_default: qup-uart2-default { pinmux { pins = "gpio15", "gpio16"; @@ -1661,6 +1691,14 @@ }; }; + qup_uart3_sleep: qup-uart3-sleep { + pinmux { + pins = "gpio38", "gpio39", + "gpio40", "gpio41"; + function = "gpio"; + }; + }; + qup_uart4_default: qup-uart4-default { pinmux { pins = "gpio115", "gpio116"; @@ -1676,6 +1714,14 @@ }; }; + qup_uart5_sleep: qup-uart5-sleep { + pinmux { + pins = "gpio25", "gpio26", + "gpio27", "gpio28"; + function = "gpio"; + }; + }; + qup_uart6_default: qup-uart6-default { pinmux { pins = "gpio59", "gpio60", @@ -1684,6 +1730,14 @@ }; }; + qup_uart6_sleep: qup-uart6-sleep { + pinmux { + pins = "gpio59", "gpio60", + "gpio61", "gpio62"; + function = "gpio"; + }; + }; + qup_uart7_default: qup-uart7-default { pinmux { pins = "gpio6", "gpio7"; @@ -1713,6 +1767,14 @@ }; }; + qup_uart10_sleep: qup-uart10-sleep { + pinmux { + pins = "gpio86", "gpio87", + "gpio88", "gpio89"; + function = "gpio"; + }; + }; + qup_uart11_default: qup-uart11-default { pinmux { pins = "gpio53", "gpio54", @@ -1721,6 +1783,14 @@ }; }; + qup_uart11_sleep: qup-uart11-sleep { + pinmux { + pins = "gpio53", "gpio54", + "gpio55", "gpio56"; + function = "gpio"; + }; + }; + sdc1_on: sdc1-on { pinconf-clk { pins = "sdc1_clk"; From patchwork Thu Sep 3 15:04:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satya Priya X-Patchwork-Id: 11753977 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 16E04618 for ; Thu, 3 Sep 2020 15:08:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 03F4E20716 for ; Thu, 3 Sep 2020 15:08:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729046AbgICPHa (ORCPT ); Thu, 3 Sep 2020 11:07:30 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:22454 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729495AbgICPFi (ORCPT ); Thu, 3 Sep 2020 11:05:38 -0400 Received: from ironmsg07-lv.qualcomm.com (HELO ironmsg07-lv.qulacomm.com) ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 03 Sep 2020 08:05:32 -0700 Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qulacomm.com with ESMTP/TLS/AES256-SHA; 03 Sep 2020 08:05:31 -0700 Received: from c-skakit-linux.ap.qualcomm.com (HELO c-skakit-linux.qualcomm.com) ([10.242.51.242]) by ironmsg02-blr.qualcomm.com with ESMTP; 03 Sep 2020 20:35:05 +0530 Received: by c-skakit-linux.qualcomm.com (Postfix, from userid 2344709) id B0B154435; Thu, 3 Sep 2020 20:35:04 +0530 (IST) From: satya priya To: Bjorn Andersson Cc: Matthias Kaehlcke , gregkh@linuxfoundation.org, Andy Gross , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, akashast@codeaurora.org, rojay@codeaurora.org, msavaliy@qti.qualcomm.com, satya priya Subject: [PATCH V4 2/4] arm64: dts: qcom: sc7180: Improve the pin config settings for CTS and TX Date: Thu, 3 Sep 2020 20:34:56 +0530 Message-Id: <1599145498-20707-3-git-send-email-skakit@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599145498-20707-1-git-send-email-skakit@codeaurora.org> References: <1599145498-20707-1-git-send-email-skakit@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Configure no-pull for CTS, as this is driven by BT do not specify any pull in order to not conflict with BT pulls. Remove output-high from CTS and TX as this is not really required. During bringup to fix transfer failures this was added to match with console uart settings. Probably some boot loader config was missing then. As it is working fine now, remove it. Signed-off-by: satya priya Reviewed-by: Akash Asthana Reviewed-by: Matthias Kaehlcke --- Changes in V4: - This is newly added in V4 to separate the improvements in pin settings and wakeup related changes. arch/arm64/boot/dts/qcom/sc7180-idp.dts | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index d8b5507..cecac3e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -474,32 +474,30 @@ &qup_uart3_default { pinconf-cts { /* - * Configure a pull-down on 38 (CTS) to match the pull of - * the Bluetooth module. + * Configure no-pull on CTS. As this is driven by BT, do not + * specify any pull in order to not conflict with BT pulls. */ pins = "gpio38"; - bias-pull-down; - output-high; + bias-disable; }; pinconf-rts { - /* We'll drive 39 (RTS), so no pull */ + /* We'll drive RTS, so no pull */ pins = "gpio39"; drive-strength = <2>; bias-disable; }; pinconf-tx { - /* We'll drive 40 (TX), so no pull */ + /* We'll drive TX, so no pull */ pins = "gpio40"; drive-strength = <2>; bias-disable; - output-high; }; pinconf-rx { /* - * Configure a pull-up on 41 (RX). This is needed to avoid + * Configure a pull-up on RX. This is needed to avoid * garbage data when the TX pin of the Bluetooth module is * in tri-state (module powered off or not driving the * signal yet). From patchwork Thu Sep 3 15:04:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satya Priya X-Patchwork-Id: 11753975 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E39FD1575 for ; Thu, 3 Sep 2020 15:08:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D18C12072A for ; Thu, 3 Sep 2020 15:08:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729049AbgICPHb (ORCPT ); Thu, 3 Sep 2020 11:07:31 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:45300 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729499AbgICPFi (ORCPT ); Thu, 3 Sep 2020 11:05:38 -0400 Received: from ironmsg07-lv.qualcomm.com (HELO ironmsg07-lv.qulacomm.com) ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 03 Sep 2020 08:05:34 -0700 Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qulacomm.com with ESMTP/TLS/AES256-SHA; 03 Sep 2020 08:05:32 -0700 Received: from c-skakit-linux.ap.qualcomm.com (HELO c-skakit-linux.qualcomm.com) ([10.242.51.242]) by ironmsg02-blr.qualcomm.com with ESMTP; 03 Sep 2020 20:35:05 +0530 Received: by c-skakit-linux.qualcomm.com (Postfix, from userid 2344709) id CE84C44AA; Thu, 3 Sep 2020 20:35:04 +0530 (IST) From: satya priya To: Bjorn Andersson Cc: Matthias Kaehlcke , gregkh@linuxfoundation.org, Andy Gross , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, akashast@codeaurora.org, rojay@codeaurora.org, msavaliy@qti.qualcomm.com, satya priya Subject: [PATCH V4 3/4] arm64: dts: qcom: sc7180: Add sleep state for BT UART Date: Thu, 3 Sep 2020 20:34:57 +0530 Message-Id: <1599145498-20707-4-git-send-email-skakit@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599145498-20707-1-git-send-email-skakit@codeaurora.org> References: <1599145498-20707-1-git-send-email-skakit@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add sleep state for BT uart to support the wakeup feature. Signed-off-by: satya priya Reviewed-by: Akash Asthana Reviewed-by: Matthias Kaehlcke --- Changes in V2: - This patch adds sleep state for BT UART. Newly added in V2. Changes in V3: - Remove "output-high" for TX from both sleep and default states as it is not required. Configure pull-up for TX in sleep state. Changes in V4: - As per Matthias's comment, removed drive-strength for sleep state and fixed nit-pick. arch/arm64/boot/dts/qcom/sc7180-idp.dts | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index cecac3e..77e3523 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -507,6 +507,43 @@ }; }; +&qup_uart3_sleep { + pinconf-cts { + /* + * Configure no-pull on CTS. As this is driven by BT, do not + * specify any pull in order to not conflict with BT pulls. + */ + pins = "gpio38"; + bias-disable; + }; + + pinconf-rts { + /* + * Configure pull-down on RTS to make sure that the BT SoC can + * wake up the system by sending wakeup bytes during suspend. + */ + pins = "gpio39"; + bias-pull-down; + }; + + pinconf-tx { + /* Configure pull-up on TX when it isn't actively driven */ + pins = "gpio40"; + bias-pull-up; + }; + + pinconf-rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + pins = "gpio41"; + bias-pull-up; + }; +}; + &qup_uart8_default { pinconf-tx { pins = "gpio44"; From patchwork Thu Sep 3 15:04:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satya Priya X-Patchwork-Id: 11753971 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AE6781575 for ; Thu, 3 Sep 2020 15:07:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A0E6C20722 for ; Thu, 3 Sep 2020 15:07:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729514AbgICPFu (ORCPT ); Thu, 3 Sep 2020 11:05:50 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:45300 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729357AbgICPFt (ORCPT ); Thu, 3 Sep 2020 11:05:49 -0400 Received: from ironmsg07-lv.qualcomm.com (HELO ironmsg07-lv.qulacomm.com) ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 03 Sep 2020 08:05:36 -0700 Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg07-lv.qulacomm.com with ESMTP/TLS/AES256-SHA; 03 Sep 2020 08:05:34 -0700 Received: from c-skakit-linux.ap.qualcomm.com (HELO c-skakit-linux.qualcomm.com) ([10.242.51.242]) by ironmsg02-blr.qualcomm.com with ESMTP; 03 Sep 2020 20:35:05 +0530 Received: by c-skakit-linux.qualcomm.com (Postfix, from userid 2344709) id E50A244AB; Thu, 3 Sep 2020 20:35:04 +0530 (IST) From: satya priya To: Bjorn Andersson Cc: Matthias Kaehlcke , gregkh@linuxfoundation.org, Andy Gross , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, akashast@codeaurora.org, rojay@codeaurora.org, msavaliy@qti.qualcomm.com, satya priya Subject: [PATCH V4 4/4] tty: serial: qcom_geni_serial: Fix the UART wakeup issue Date: Thu, 3 Sep 2020 20:34:58 +0530 Message-Id: <1599145498-20707-5-git-send-email-skakit@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599145498-20707-1-git-send-email-skakit@codeaurora.org> References: <1599145498-20707-1-git-send-email-skakit@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As a part of system suspend uart_port_suspend is called from the Serial driver, which calls set_mctrl passing mctrl as NULL. This makes RFR high(NOT_READY) during suspend. Due to this BT SoC is not able to send wakeup bytes to UART during suspend. Include if check for non-suspend case to keep RFR low during suspend. Signed-off-by: satya priya Acked-by: Greg Kroah-Hartman Reviewed-by: Akash Asthana --- Changes in V2: - This patch fixes the UART flow control issue during suspend. Newly added in V2. Changes in V3: - As per Matthias's comment removed the extra parentheses. Changes in V4: - No change. drivers/tty/serial/qcom_geni_serial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 07b7b6b..2aad9d7 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -242,7 +242,7 @@ static void qcom_geni_serial_set_mctrl(struct uart_port *uport, if (mctrl & TIOCM_LOOP) port->loopback = RX_TX_CTS_RTS_SORTED; - if (!(mctrl & TIOCM_RTS)) + if (!(mctrl & TIOCM_RTS) && !uport->suspended) uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); }