From patchwork Fri Sep 4 07:44:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhangqing X-Patchwork-Id: 11756165 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 40A1F1599 for ; Fri, 4 Sep 2020 07:44:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 294762074D for ; Fri, 4 Sep 2020 07:44:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726171AbgIDHo2 (ORCPT ); Fri, 4 Sep 2020 03:44:28 -0400 Received: from lucky1.263xmail.com ([211.157.147.135]:44000 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728205AbgIDHoR (ORCPT ); Fri, 4 Sep 2020 03:44:17 -0400 Received: from localhost (unknown [192.168.167.223]) by lucky1.263xmail.com (Postfix) with ESMTP id 39744A28D4; Fri, 4 Sep 2020 15:44:10 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P15471T140656136742656S1599205448140075_; Fri, 04 Sep 2020 15:44:10 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <8b926b330aefa52891ba72ba4efc267b> X-RL-SENDER: zhangqing@rock-chips.com X-SENDER: zhangqing@rock-chips.com X-LOGIN-NAME: zhangqing@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Elaine Zhang To: heiko@sntech.de Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com, kever.yang@rock-chips.com, Elaine Zhang Subject: [PATCH v3 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls Date: Fri, 4 Sep 2020 15:44:00 +0800 Message-Id: <20200904074405.24439-2-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200904074405.24439-1-zhangqing@rock-chips.com> References: <20200904074405.24439-1-zhangqing@rock-chips.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org clk_hw_register_composite it's already exported. Preparation for compilation of rK common clock drivers into modules. Signed-off-by: Elaine Zhang Reported-by: kernel test robot Reviewed-by: Kever Yang Reviewed-by: Heiko Stuebner --- drivers/clk/rockchip/clk-half-divider.c | 18 ++++---- drivers/clk/rockchip/clk.c | 61 ++++++++++++------------- 2 files changed, 40 insertions(+), 39 deletions(-) diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c index b333fc28c94b..e97fd3dfbae7 100644 --- a/drivers/clk/rockchip/clk-half-divider.c +++ b/drivers/clk/rockchip/clk-half-divider.c @@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name, unsigned long flags, spinlock_t *lock) { - struct clk *clk; + struct clk_hw *hw; struct clk_mux *mux = NULL; struct clk_gate *gate = NULL; struct clk_divider *div = NULL; @@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char *name, div_ops = &clk_half_divider_ops; } - clk = clk_register_composite(NULL, name, parent_names, num_parents, - mux ? &mux->hw : NULL, mux_ops, - div ? &div->hw : NULL, div_ops, - gate ? &gate->hw : NULL, gate_ops, - flags); + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, + mux ? &mux->hw : NULL, mux_ops, + div ? &div->hw : NULL, div_ops, + gate ? &gate->hw : NULL, gate_ops, + flags); + if (IS_ERR(hw)) + goto err_div; - return clk; + return hw->clk; err_div: kfree(gate); err_gate: kfree(mux); - return ERR_PTR(-ENOMEM); + return ERR_CAST(hw); } diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 546e810c3560..46409972983e 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) { - struct clk *clk; + struct clk_hw *hw; struct clk_mux *mux = NULL; struct clk_gate *gate = NULL; struct clk_divider *div = NULL; @@ -100,20 +100,18 @@ static struct clk *rockchip_clk_register_branch(const char *name, : &clk_divider_ops; } - clk = clk_register_composite(NULL, name, parent_names, num_parents, - mux ? &mux->hw : NULL, mux_ops, - div ? &div->hw : NULL, div_ops, - gate ? &gate->hw : NULL, gate_ops, - flags); - - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - goto err_composite; + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, + mux ? &mux->hw : NULL, mux_ops, + div ? &div->hw : NULL, div_ops, + gate ? &gate->hw : NULL, gate_ops, + flags); + if (IS_ERR(hw)) { + kfree(div); + kfree(gate); + return ERR_CAST(hw); } - return clk; -err_composite: - kfree(div); + return hw->clk; err_div: kfree(gate); err_gate: @@ -214,8 +212,8 @@ static struct clk *rockchip_clk_register_frac_branch( unsigned long flags, struct rockchip_clk_branch *child, spinlock_t *lock) { + struct clk_hw *hw; struct rockchip_clk_frac *frac; - struct clk *clk; struct clk_gate *gate = NULL; struct clk_fractional_divider *div = NULL; const struct clk_ops *div_ops = NULL, *gate_ops = NULL; @@ -255,14 +253,14 @@ static struct clk *rockchip_clk_register_frac_branch( div->approximation = rockchip_fractional_approximation; div_ops = &clk_fractional_divider_ops; - clk = clk_register_composite(NULL, name, parent_names, num_parents, - NULL, NULL, - &div->hw, div_ops, - gate ? &gate->hw : NULL, gate_ops, - flags | CLK_SET_RATE_UNGATE); - if (IS_ERR(clk)) { + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, + NULL, NULL, + &div->hw, div_ops, + gate ? &gate->hw : NULL, gate_ops, + flags | CLK_SET_RATE_UNGATE); + if (IS_ERR(hw)) { kfree(frac); - return clk; + return ERR_CAST(hw); } if (child) { @@ -292,7 +290,7 @@ static struct clk *rockchip_clk_register_frac_branch( mux_clk = clk_register(NULL, &frac_mux->hw); if (IS_ERR(mux_clk)) { kfree(frac); - return clk; + return mux_clk; } rockchip_clk_add_lookup(ctx, mux_clk, child->id); @@ -301,7 +299,7 @@ static struct clk *rockchip_clk_register_frac_branch( if (frac->mux_frac_idx >= 0) { pr_debug("%s: found fractional parent in mux at pos %d\n", __func__, frac->mux_frac_idx); - ret = clk_notifier_register(clk, &frac->clk_nb); + ret = clk_notifier_register(hw->clk, &frac->clk_nb); if (ret) pr_err("%s: failed to register clock notifier for %s\n", __func__, name); @@ -311,7 +309,7 @@ static struct clk *rockchip_clk_register_frac_branch( } } - return clk; + return hw->clk; } static struct clk *rockchip_clk_register_factor_branch(const char *name, @@ -320,7 +318,7 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) { - struct clk *clk; + struct clk_hw *hw; struct clk_gate *gate = NULL; struct clk_fixed_factor *fix = NULL; @@ -349,16 +347,17 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name, fix->mult = mult; fix->div = div; - clk = clk_register_composite(NULL, name, parent_names, num_parents, - NULL, NULL, - &fix->hw, &clk_fixed_factor_ops, - &gate->hw, &clk_gate_ops, flags); - if (IS_ERR(clk)) { + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, + NULL, NULL, + &fix->hw, &clk_fixed_factor_ops, + &gate->hw, &clk_gate_ops, flags); + if (IS_ERR(hw)) { kfree(fix); kfree(gate); + return ERR_CAST(hw); } - return clk; + return hw->clk; } struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np, From patchwork Fri Sep 4 07:44:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhangqing X-Patchwork-Id: 11756157 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2097614F9 for ; Fri, 4 Sep 2020 07:44:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 066BB206A5 for ; Fri, 4 Sep 2020 07:44:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728248AbgIDHoP (ORCPT ); Fri, 4 Sep 2020 03:44:15 -0400 Received: from lucky1.263xmail.com ([211.157.147.131]:48578 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728170AbgIDHoP (ORCPT ); Fri, 4 Sep 2020 03:44:15 -0400 Received: from localhost (unknown [192.168.167.223]) by lucky1.263xmail.com (Postfix) with ESMTP id 4E516B21EC; Fri, 4 Sep 2020 15:44:11 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P15471T140656136742656S1599205448140075_; Fri, 04 Sep 2020 15:44:10 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <4dac87a665b377536b15cc5cfbba7e94> X-RL-SENDER: zhangqing@rock-chips.com X-SENDER: zhangqing@rock-chips.com X-LOGIN-NAME: zhangqing@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Elaine Zhang To: heiko@sntech.de Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com, kever.yang@rock-chips.com, Elaine Zhang Subject: [PATCH v3 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk() Date: Fri, 4 Sep 2020 15:44:01 +0800 Message-Id: <20200904074405.24439-3-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200904074405.24439-1-zhangqing@rock-chips.com> References: <20200904074405.24439-1-zhangqing@rock-chips.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module.. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk-ddr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c index 9273bce4d7b6..282b6f22eb22 100644 --- a/drivers/clk/rockchip/clk-ddr.c +++ b/drivers/clk/rockchip/clk-ddr.c @@ -136,3 +136,4 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, return clk; } +EXPORT_SYMBOL(rockchip_clk_register_ddrclk); From patchwork Fri Sep 4 07:44:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhangqing X-Patchwork-Id: 11756175 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF91A138E for ; Fri, 4 Sep 2020 07:44:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B37F5206A5 for ; Fri, 4 Sep 2020 07:44:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729744AbgIDHoj (ORCPT ); Fri, 4 Sep 2020 03:44:39 -0400 Received: from lucky1.263xmail.com ([211.157.147.131]:48588 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728112AbgIDHoQ (ORCPT ); Fri, 4 Sep 2020 03:44:16 -0400 Received: from localhost (unknown [192.168.167.223]) by lucky1.263xmail.com (Postfix) with ESMTP id EE542B2236; Fri, 4 Sep 2020 15:44:11 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P15471T140656136742656S1599205448140075_; Fri, 04 Sep 2020 15:44:11 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <9a7e37fcb4d78403b256b4ee0b674a65> X-RL-SENDER: zhangqing@rock-chips.com X-SENDER: zhangqing@rock-chips.com X-LOGIN-NAME: zhangqing@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Elaine Zhang To: heiko@sntech.de Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com, kever.yang@rock-chips.com, Elaine Zhang Subject: [PATCH v3 3/6] clk: rockchip: Export rockchip_register_softrst() Date: Fri, 4 Sep 2020 15:44:02 +0800 Message-Id: <20200904074405.24439-4-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200904074405.24439-1-zhangqing@rock-chips.com> References: <20200904074405.24439-1-zhangqing@rock-chips.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module.. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- drivers/clk/rockchip/softrst.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c index 5f1ff5e47c4f..caba9055090b 100644 --- a/drivers/clk/rockchip/softrst.c +++ b/drivers/clk/rockchip/softrst.c @@ -77,9 +77,9 @@ static const struct reset_control_ops rockchip_softrst_ops = { .deassert = rockchip_softrst_deassert, }; -void __init rockchip_register_softrst(struct device_node *np, - unsigned int num_regs, - void __iomem *base, u8 flags) +void rockchip_register_softrst(struct device_node *np, + unsigned int num_regs, + void __iomem *base, u8 flags) { struct rockchip_softrst *softrst; int ret; @@ -107,3 +107,4 @@ void __init rockchip_register_softrst(struct device_node *np, kfree(softrst); } }; +EXPORT_SYMBOL(rockchip_register_softrst); From patchwork Fri Sep 4 07:44:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhangqing X-Patchwork-Id: 11756173 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7DA97138E for ; Fri, 4 Sep 2020 07:44:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6CF4A20748 for ; Fri, 4 Sep 2020 07:44:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728205AbgIDHoe (ORCPT ); Fri, 4 Sep 2020 03:44:34 -0400 Received: from lucky1.263xmail.com ([211.157.147.134]:42756 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726089AbgIDHoR (ORCPT ); Fri, 4 Sep 2020 03:44:17 -0400 Received: from localhost (unknown [192.168.167.223]) by lucky1.263xmail.com (Postfix) with ESMTP id BAC9EC1739; Fri, 4 Sep 2020 15:44:11 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P15471T140656136742656S1599205448140075_; Fri, 04 Sep 2020 15:44:12 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: zhangqing@rock-chips.com X-SENDER: zhangqing@rock-chips.com X-LOGIN-NAME: zhangqing@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Elaine Zhang To: heiko@sntech.de Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com, kever.yang@rock-chips.com, Elaine Zhang Subject: [PATCH v3 4/6] clk: rockchip: Export some clock common APIs for module drivers Date: Fri, 4 Sep 2020 15:44:03 +0800 Message-Id: <20200904074405.24439-5-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200904074405.24439-1-zhangqing@rock-chips.com> References: <20200904074405.24439-1-zhangqing@rock-chips.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk.c | 52 ++++++++++++++++++++++---------------- 1 file changed, 30 insertions(+), 22 deletions(-) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 46409972983e..fd3aff2a599d 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -360,8 +360,9 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name, return hw->clk; } -struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np, - void __iomem *base, unsigned long nr_clks) +struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, + void __iomem *base, + unsigned long nr_clks) { struct rockchip_clk_provider *ctx; struct clk **clk_table; @@ -393,14 +394,16 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np, kfree(ctx); return ERR_PTR(-ENOMEM); } +EXPORT_SYMBOL(rockchip_clk_init); -void __init rockchip_clk_of_add_provider(struct device_node *np, - struct rockchip_clk_provider *ctx) +void rockchip_clk_of_add_provider(struct device_node *np, + struct rockchip_clk_provider *ctx) { if (of_clk_add_provider(np, of_clk_src_onecell_get, &ctx->clk_data)) pr_err("%s: could not register clk provider\n", __func__); } +EXPORT_SYMBOL(rockchip_clk_of_add_provider); void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, struct clk *clk, unsigned int id) @@ -408,8 +411,9 @@ void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, if (ctx->clk_data.clks && id) ctx->clk_data.clks[id] = clk; } +EXPORT_SYMBOL(rockchip_clk_add_lookup); -void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, +void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, struct rockchip_pll_clock *list, unsigned int nr_pll, int grf_lock_offset) { @@ -432,11 +436,11 @@ void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, rockchip_clk_add_lookup(ctx, clk, list->id); } } +EXPORT_SYMBOL(rockchip_clk_register_plls); -void __init rockchip_clk_register_branches( - struct rockchip_clk_provider *ctx, - struct rockchip_clk_branch *list, - unsigned int nr_clk) +void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *list, + unsigned int nr_clk) { struct clk *clk = NULL; unsigned int idx; @@ -565,14 +569,15 @@ void __init rockchip_clk_register_branches( rockchip_clk_add_lookup(ctx, clk, list->id); } } - -void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, - unsigned int lookup_id, - const char *name, const char *const *parent_names, - u8 num_parents, - const struct rockchip_cpuclk_reg_data *reg_data, - const struct rockchip_cpuclk_rate_table *rates, - int nrates) +EXPORT_SYMBOL(rockchip_clk_register_branches); + +void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, + unsigned int lookup_id, + const char *name, const char *const *parent_names, + u8 num_parents, + const struct rockchip_cpuclk_reg_data *reg_data, + const struct rockchip_cpuclk_rate_table *rates, + int nrates) { struct clk *clk; @@ -587,9 +592,10 @@ void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, rockchip_clk_add_lookup(ctx, clk, lookup_id); } +EXPORT_SYMBOL(rockchip_clk_register_armclk); -void __init rockchip_clk_protect_critical(const char *const clocks[], - int nclocks) +void rockchip_clk_protect_critical(const char *const clocks[], + int nclocks) { int i; @@ -601,6 +607,7 @@ void __init rockchip_clk_protect_critical(const char *const clocks[], clk_prepare_enable(clk); } } +EXPORT_SYMBOL(rockchip_clk_protect_critical); static void __iomem *rst_base; static unsigned int reg_restart; @@ -620,10 +627,10 @@ static struct notifier_block rockchip_restart_handler = { .priority = 128, }; -void __init +void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, - unsigned int reg, - void (*cb)(void)) + unsigned int reg, + void (*cb)(void)) { int ret; @@ -635,3 +642,4 @@ rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, pr_err("%s: cannot register restart handler, %d\n", __func__, ret); } +EXPORT_SYMBOL(rockchip_register_restart_notifier); From patchwork Fri Sep 4 07:44:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhangqing X-Patchwork-Id: 11756177 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 811D714F9 for ; Fri, 4 Sep 2020 07:44:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6AAB6206A5 for ; Fri, 4 Sep 2020 07:44:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728248AbgIDHo5 (ORCPT ); Fri, 4 Sep 2020 03:44:57 -0400 Received: from lucky1.263xmail.com ([211.157.147.130]:55334 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728112AbgIDHo4 (ORCPT ); Fri, 4 Sep 2020 03:44:56 -0400 Received: from localhost (unknown [192.168.167.209]) by lucky1.263xmail.com (Postfix) with ESMTP id D8819CC444; Fri, 4 Sep 2020 15:44:53 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P26185T140085639354112S1599205492456414_; Fri, 04 Sep 2020 15:44:53 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: zhangqing@rock-chips.com X-SENDER: zhangqing@rock-chips.com X-LOGIN-NAME: zhangqing@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Elaine Zhang To: heiko@sntech.de Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com, kever.yang@rock-chips.com, Elaine Zhang Subject: [PATCH v3 5/6] clk: rockchip: fix the clk config to support module build Date: Fri, 4 Sep 2020 15:44:48 +0800 Message-Id: <20200904074448.24753-1-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200904074405.24439-1-zhangqing@rock-chips.com> References: <20200904074405.24439-1-zhangqing@rock-chips.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers. use CONFIG_CLK_RKXX for Rk soc clk driver. Mark configuration to "tristate", to support building Rk SoCs clock driver as module. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- drivers/clk/Kconfig | 1 + drivers/clk/rockchip/Kconfig | 78 +++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/Makefile | 42 ++++++++++--------- 3 files changed, 101 insertions(+), 20 deletions(-) create mode 100644 drivers/clk/rockchip/Kconfig diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 4026fac9fac3..b41aaed9bd51 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -373,6 +373,7 @@ source "drivers/clk/meson/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/renesas/Kconfig" +source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" source "drivers/clk/sifive/Kconfig" source "drivers/clk/sprd/Kconfig" diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig new file mode 100644 index 000000000000..53a44396bc35 --- /dev/null +++ b/drivers/clk/rockchip/Kconfig @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0 +# common clock support for ROCKCHIP SoC family. + +config COMMON_CLK_ROCKCHIP + tristate "Rockchip clock controller common support" + depends on ARCH_ROCKCHIP + default ARCH_ROCKCHIP + help + Say y here to enable common clock controller. + +if COMMON_CLK_ROCKCHIP +config CLK_PX30 + tristate "Rockchip Px30 clock controller support" + default y + help + Build the driver for Px30 Clock Driver. + +config CLK_RV110X + tristate "Rockchip Rv110x clock controller support" + default y + help + Build the driver for Rv110x Clock Driver. + +config CLK_RK3036 + tristate "Rockchip Rk3036 clock controller support" + default y + help + Build the driver for Rk3036 Clock Driver. + +config CLK_RK312X + tristate "Rockchip Rk312x clock controller support" + default y + help + Build the driver for Rk312x Clock Driver. + +config CLK_RK3188 + tristate "Rockchip Rk3188 clock controller support" + default y + help + Build the driver for Rk3188 Clock Driver. + +config CLK_RK322X + tristate "Rockchip Rk322x clock controller support" + default y + help + Build the driver for Rk322x Clock Driver. + +config CLK_RK3288 + tristate "Rockchip Rk3288 clock controller support" + depends on ARM + default y + help + Build the driver for Rk3288 Clock Driver. + +config CLK_RK3308 + tristate "Rockchip Rk3308 clock controller support" + default y + help + Build the driver for Rk3308 Clock Driver. + +config CLK_RK3328 + tristate "Rockchip Rk3328 clock controller support" + default y + help + Build the driver for Rk3328 Clock Driver. + +config CLK_RK3368 + tristate "Rockchip Rk3368 clock controller support" + default y + help + Build the driver for Rk3368 Clock Driver. + +config CLK_RK3399 + tristate "Rockchip Rk3399 clock controller support" + default y + help + Build the driver for Rk3399 Clock Driver. +endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 7c5b5813a87c..a99e4d9bbae1 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -3,24 +3,26 @@ # Rockchip Clock specific Makefile # -obj-y += clk.o -obj-y += clk-pll.o -obj-y += clk-cpu.o -obj-y += clk-half-divider.o -obj-y += clk-inverter.o -obj-y += clk-mmc-phase.o -obj-y += clk-muxgrf.o -obj-y += clk-ddr.o -obj-$(CONFIG_RESET_CONTROLLER) += softrst.o +obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o -obj-y += clk-px30.o -obj-y += clk-rv1108.o -obj-y += clk-rk3036.o -obj-y += clk-rk3128.o -obj-y += clk-rk3188.o -obj-y += clk-rk3228.o -obj-y += clk-rk3288.o -obj-y += clk-rk3308.o -obj-y += clk-rk3328.o -obj-y += clk-rk3368.o -obj-y += clk-rk3399.o +clk-rockchip-y += clk.o +clk-rockchip-y += clk-pll.o +clk-rockchip-y += clk-cpu.o +clk-rockchip-y += clk-half-divider.o +clk-rockchip-y += clk-inverter.o +clk-rockchip-y += clk-mmc-phase.o +clk-rockchip-y += clk-muxgrf.o +clk-rockchip-y += clk-ddr.o +clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o + +obj-$(CONFIG_CLK_PX30) += clk-px30.o +obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o +obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o +obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o +obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o +obj-$(CONFIG_CLK_RK322X) += clk-rk3228.o +obj-$(CONFIG_CLK_RK3288) += clk-rk3288.o +obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o +obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o +obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o +obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o From patchwork Fri Sep 4 07:45:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhangqing X-Patchwork-Id: 11756181 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 451F5138C for ; Fri, 4 Sep 2020 07:45:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 329A32084D for ; Fri, 4 Sep 2020 07:45:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726171AbgIDHpM (ORCPT ); Fri, 4 Sep 2020 03:45:12 -0400 Received: from lucky1.263xmail.com ([211.157.147.135]:44866 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728112AbgIDHpM (ORCPT ); Fri, 4 Sep 2020 03:45:12 -0400 Received: from localhost (unknown [192.168.167.13]) by lucky1.263xmail.com (Postfix) with ESMTP id 70F55A2980; Fri, 4 Sep 2020 15:45:08 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P29633T140716038665984S1599205507913558_; Fri, 04 Sep 2020 15:45:09 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <39d007cf5bc0dc25bd91df7362a9d001> X-RL-SENDER: zhangqing@rock-chips.com X-SENDER: zhangqing@rock-chips.com X-LOGIN-NAME: zhangqing@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Elaine Zhang To: heiko@sntech.de Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com, kever.yang@rock-chips.com, Elaine Zhang Subject: [PATCH v3 6/6] clk: rockchip: rk3399: Support module build Date: Fri, 4 Sep 2020 15:45:05 +0800 Message-Id: <20200904074505.24917-1-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200904074405.24439-1-zhangqing@rock-chips.com> References: <20200904074405.24439-1-zhangqing@rock-chips.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org support CLK_OF_DECLARE and builtin_platform_driver_probe double clk init method. add module author, description and license to support building Soc Rk3399 clock driver as module. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk-rk3399.c | 55 +++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index ce1d2446f142..40ff17aee5b6 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -5,9 +5,11 @@ */ #include +#include #include #include #include +#include #include #include #include @@ -1600,3 +1602,56 @@ static void __init rk3399_pmu_clk_init(struct device_node *np) rockchip_clk_of_add_provider(np, ctx); } CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init); + +struct clk_rk3399_inits { + void (*inits)(struct device_node *np); +}; + +static const struct clk_rk3399_inits clk_rk3399_pmucru_init = { + .inits = rk3399_pmu_clk_init, +}; + +static const struct clk_rk3399_inits clk_rk3399_cru_init = { + .inits = rk3399_clk_init, +}; + +static const struct of_device_id clk_rk3399_match_table[] = { + { + .compatible = "rockchip,rk3399-cru", + .data = &clk_rk3399_cru_init, + }, { + .compatible = "rockchip,rk3399-pmucru", + .data = &clk_rk3399_pmucru_init, + }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_rk3399_match_table); + +static int __init clk_rk3399_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; + const struct clk_rk3399_inits *init_data; + + match = of_match_device(clk_rk3399_match_table, &pdev->dev); + if (!match || !match->data) + return -EINVAL; + + init_data = match->data; + if (init_data->inits) + init_data->inits(np); + + return 0; +} + +static struct platform_driver clk_rk3399_driver = { + .driver = { + .name = "clk-rk3399", + .of_match_table = clk_rk3399_match_table, + }, +}; +builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe); + +MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:clk-rk3399");