From patchwork Fri Sep 4 09:51:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sia Jee Heng X-Patchwork-Id: 11756493 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E938D15AB for ; Fri, 4 Sep 2020 10:07:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D68D220791 for ; Fri, 4 Sep 2020 10:07:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729659AbgIDKHT (ORCPT ); Fri, 4 Sep 2020 06:07:19 -0400 Received: from mga09.intel.com ([134.134.136.24]:2059 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728588AbgIDKHT (ORCPT ); Fri, 4 Sep 2020 06:07:19 -0400 IronPort-SDR: Am4iksJNJ5X4+y+himIwoKNBH6sLEfQzXRHZruxnn5eGbfn+yU/ZHqLLAKL0ucweUEYK6vJnic VRWXuwlmFcLQ== X-IronPort-AV: E=McAfee;i="6000,8403,9733"; a="158697567" X-IronPort-AV: E=Sophos;i="5.76,389,1592895600"; d="scan'208";a="158697567" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Sep 2020 03:07:19 -0700 IronPort-SDR: ErUYyIF96cmzSGS0342ga5RrNy7szxygguMC2SRnwgf1ErTRanMwJr1g2sCEx4eyUs8azwRaZy g2NADgFHcUrQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,389,1592895600"; d="scan'208";a="342143647" Received: from unknown (HELO jsia-HP-Z620-Workstation.png.intel.com) ([10.221.118.135]) by orsmga007.jf.intel.com with ESMTP; 04 Sep 2020 03:07:16 -0700 From: Sia Jee Heng To: Cc: , , , Subject: [PATCH 1/4] dt-bindings: dma: Add YAML schemas for dw-axi-dmac Date: Fri, 4 Sep 2020 17:51:31 +0800 Message-Id: <1599213094-30144-2-git-send-email-jee.heng.sia@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1599213094-30144-1-git-send-email-jee.heng.sia@intel.com> References: <1599213094-30144-1-git-send-email-jee.heng.sia@intel.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org YAML schemas Device Tree (DT) binding is the new format for DT to replace the old format. Introduce YAML schemas DT binding for dw-axi-dmac and remove the old version. Signed-off-by: Sia Jee Heng --- .../devicetree/bindings/dma/snps,dw-axi-dmac.txt | 39 ------- .../devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 124 +++++++++++++++++++++ 2 files changed, 124 insertions(+), 39 deletions(-) delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt deleted file mode 100644 index dbe1604..0000000 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt +++ /dev/null @@ -1,39 +0,0 @@ -Synopsys DesignWare AXI DMA Controller - -Required properties: -- compatible: "snps,axi-dma-1.01a" -- reg: Address range of the DMAC registers. This should include - all of the per-channel registers. -- interrupt: Should contain the DMAC interrupt number. -- dma-channels: Number of channels supported by hardware. -- snps,dma-masters: Number of AXI masters supported by the hardware. -- snps,data-width: Maximum AXI data width supported by hardware. - (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits) -- snps,priority: Priority of channel. Array size is equal to the number of - dma-channels. Priority value must be programmed within [0:dma-channels-1] - range. (0 - minimum priority) -- snps,block-size: Maximum block size supported by the controller channel. - Array size is equal to the number of dma-channels. - -Optional properties: -- snps,axi-max-burst-len: Restrict master AXI burst length by value specified - in this property. If this property is missing the maximum AXI burst length - supported by DMAC is used. [1:256] - -Example: - -dmac: dma-controller@80000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x80000 0x400>; - clocks = <&core_clk>, <&cfgr_clk>; - clock-names = "core-clk", "cfgr-clk"; - interrupt-parent = <&intc>; - interrupts = <27>; - - dma-channels = <4>; - snps,dma-masters = <2>; - snps,data-width = <3>; - snps,block-size = <4096 4096 4096 4096>; - snps,priority = <0 1 2 3>; - snps,axi-max-burst-len = <16>; -}; diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml new file mode 100644 index 0000000..e688d25 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare AXI DMA Controller + +maintainers: + - Eugeniy Paltsev + #include + /* example with snps,dw-axi-dmac */ + dmac: dma-controller@80000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x80000 0x400>; + clocks = <&core_clk>, <&cfgr_clk>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = <27>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <2>; + snps,data-width = <3>; + snps,block-size = <4096 4096 4096 4096>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; + }; From patchwork Fri Sep 4 09:51:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sia Jee Heng X-Patchwork-Id: 11756495 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AF01A91F for ; Fri, 4 Sep 2020 10:07:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 95EF720791 for ; Fri, 4 Sep 2020 10:07:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729877AbgIDKHZ (ORCPT ); Fri, 4 Sep 2020 06:07:25 -0400 Received: from mga09.intel.com ([134.134.136.24]:2059 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728588AbgIDKHX (ORCPT ); Fri, 4 Sep 2020 06:07:23 -0400 IronPort-SDR: t2DmOyNPRjnokLqbUzsgWwt10BA+84BJCwTDhyqgzoreaFUN0+LUEfC3bimA6IAWG0K2onWqeS RuCcBjqa/1GA== X-IronPort-AV: E=McAfee;i="6000,8403,9733"; a="158697572" X-IronPort-AV: E=Sophos;i="5.76,389,1592895600"; d="scan'208";a="158697572" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Sep 2020 03:07:21 -0700 IronPort-SDR: rFowHYvt0A+Ja/XHtzMtfrd2b27DixFDjnsVUe9iydKQ9nuf1QTNuRl+QUiwx1P95+rppNaLwk j5Pm3efkfrSw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,389,1592895600"; d="scan'208";a="342143657" Received: from unknown (HELO jsia-HP-Z620-Workstation.png.intel.com) ([10.221.118.135]) by orsmga007.jf.intel.com with ESMTP; 04 Sep 2020 03:07:19 -0700 From: Sia Jee Heng To: Cc: , , , Subject: [PATCH 2/4] dmaengine: dw-axi-dmac: simplify descriptor management Date: Fri, 4 Sep 2020 17:51:32 +0800 Message-Id: <1599213094-30144-3-git-send-email-jee.heng.sia@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1599213094-30144-1-git-send-email-jee.heng.sia@intel.com> References: <1599213094-30144-1-git-send-email-jee.heng.sia@intel.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Simplify and refactor the descriptor management by removing the redundant Linked List Item (LLI) queue control logic from the AxiDMA driver. The descriptor is split into virtual descriptor and hardware LLI so that only hardware LLI memories are allocated from the DMA memory pool. Up to 64 descriptors can be allocated within a PAGE_SIZE compare to 16 descriptors in previous version. This solves the problem where an ALSA driver expects more than 16 DMA descriptors to run. Signed-off-by: Sia Jee Heng Reviewed-by: Shevchenko, Andriy --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 164 ++++++++++++++----------- drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 9 +- 2 files changed, 102 insertions(+), 71 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index 14c1ac2..8cfd645 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include "dw-axi-dmac.h" @@ -195,43 +196,58 @@ static inline const char *axi_chan_name(struct axi_dma_chan *chan) return dma_chan_name(&chan->vc.chan); } -static struct axi_dma_desc *axi_desc_get(struct axi_dma_chan *chan) +static struct axi_dma_desc *axi_desc_alloc(u32 num) { - struct dw_axi_dma *dw = chan->chip->dw; struct axi_dma_desc *desc; + + desc = kzalloc(sizeof(*desc), GFP_NOWAIT); + if (!desc) + return NULL; + + desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT); + if (!desc->hw_desc) { + kfree(desc); + return NULL; + } + + return desc; +} + +static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan, + dma_addr_t *addr) +{ + struct dw_axi_dma *dw = chan->chip->dw; + struct axi_dma_lli *lli; dma_addr_t phys; - desc = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, &phys); - if (unlikely(!desc)) { + lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, &phys); + if (unlikely(!lli)) { dev_err(chan2dev(chan), "%s: not enough descriptors available\n", axi_chan_name(chan)); return NULL; } atomic_inc(&chan->descs_allocated); - INIT_LIST_HEAD(&desc->xfer_list); - desc->vd.tx.phys = phys; - desc->chan = chan; + *addr = phys; - return desc; + return lli; } static void axi_desc_put(struct axi_dma_desc *desc) { struct axi_dma_chan *chan = desc->chan; struct dw_axi_dma *dw = chan->chip->dw; - struct axi_dma_desc *child, *_next; - unsigned int descs_put = 0; + int count = atomic_read(&chan->descs_allocated); + struct axi_dma_hw_desc *hw_desc; + int descs_put; - list_for_each_entry_safe(child, _next, &desc->xfer_list, xfer_list) { - list_del(&child->xfer_list); - dma_pool_free(dw->desc_pool, child, child->vd.tx.phys); - descs_put++; + for (descs_put = 0; descs_put < count; descs_put++) { + hw_desc = &desc->hw_desc[descs_put]; + dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp); } - dma_pool_free(dw->desc_pool, desc, desc->vd.tx.phys); - descs_put++; - + kfree(desc->hw_desc); + kfree(desc); atomic_sub(descs_put, &chan->descs_allocated); dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n", axi_chan_name(chan), descs_put, @@ -258,9 +274,9 @@ static void vchan_desc_put(struct virt_dma_desc *vdesc) return ret; } -static void write_desc_llp(struct axi_dma_desc *desc, dma_addr_t adr) +static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr) { - desc->lli.llp = cpu_to_le64(adr); + desc->lli->llp = cpu_to_le64(adr); } static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr) @@ -295,7 +311,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan *chan, DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS); axi_chan_iowrite32(chan, CH_CFG_H, reg); - write_chan_llp(chan, first->vd.tx.phys | lms); + write_chan_llp(chan, first->hw_desc[0].llp | lms); irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR; axi_chan_irq_sig_set(chan, irq_mask); @@ -378,67 +394,78 @@ static void dma_chan_free_chan_resources(struct dma_chan *dchan) * transfer and completes the DMA transfer operation at the end of current * block transfer. */ -static void set_desc_last(struct axi_dma_desc *desc) +static void set_desc_last(struct axi_dma_hw_desc *desc) { u32 val; - val = le32_to_cpu(desc->lli.ctl_hi); + val = le32_to_cpu(desc->lli->ctl_hi); val |= CH_CTL_H_LLI_LAST; - desc->lli.ctl_hi = cpu_to_le32(val); + desc->lli->ctl_hi = cpu_to_le32(val); } -static void write_desc_sar(struct axi_dma_desc *desc, dma_addr_t adr) +static void write_desc_sar(struct axi_dma_hw_desc *desc, dma_addr_t adr) { - desc->lli.sar = cpu_to_le64(adr); + desc->lli->sar = cpu_to_le64(adr); } -static void write_desc_dar(struct axi_dma_desc *desc, dma_addr_t adr) +static void write_desc_dar(struct axi_dma_hw_desc *desc, dma_addr_t adr) { - desc->lli.dar = cpu_to_le64(adr); + desc->lli->dar = cpu_to_le64(adr); } -static void set_desc_src_master(struct axi_dma_desc *desc) +static void set_desc_src_master(struct axi_dma_hw_desc *desc) { u32 val; /* Select AXI0 for source master */ - val = le32_to_cpu(desc->lli.ctl_lo); + val = le32_to_cpu(desc->lli->ctl_lo); val &= ~CH_CTL_L_SRC_MAST; - desc->lli.ctl_lo = cpu_to_le32(val); + desc->lli->ctl_lo = cpu_to_le32(val); } -static void set_desc_dest_master(struct axi_dma_desc *desc) +static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc, + struct axi_dma_desc *desc) { u32 val; /* Select AXI1 for source master if available */ - val = le32_to_cpu(desc->lli.ctl_lo); + val = le32_to_cpu(hw_desc->lli->ctl_lo); if (desc->chan->chip->dw->hdata->nr_masters > 1) val |= CH_CTL_L_DST_MAST; else val &= ~CH_CTL_L_DST_MAST; - desc->lli.ctl_lo = cpu_to_le32(val); + hw_desc->lli->ctl_lo = cpu_to_le32(val); } static struct dma_async_tx_descriptor * dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr, dma_addr_t src_adr, size_t len, unsigned long flags) { - struct axi_dma_desc *first = NULL, *desc = NULL, *prev = NULL; struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); size_t block_ts, max_block_ts, xfer_len; - u32 xfer_width, reg; + struct axi_dma_hw_desc *hw_desc = NULL; + struct axi_dma_desc *desc = NULL; + u32 xfer_width, reg, num; + u64 llp = 0; u8 lms = 0; /* Select AXI0 master for LLI fetching */ dev_dbg(chan2dev(chan), "%s: memcpy: src: %pad dst: %pad length: %zd flags: %#lx", axi_chan_name(chan), &src_adr, &dst_adr, len, flags); max_block_ts = chan->chip->dw->hdata->block_size[chan->id]; + xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, len); + num = DIV_ROUND_UP(len, max_block_ts << xfer_width); + desc = axi_desc_alloc(num); + if (unlikely(!desc)) + goto err_desc_get; + desc->chan = chan; + num = 0; while (len) { xfer_len = len; + hw_desc = &desc->hw_desc[num]; /* * Take care for the alignment. * Actually source and destination widths can be different, but @@ -457,13 +484,13 @@ static void set_desc_dest_master(struct axi_dma_desc *desc) xfer_len = max_block_ts << xfer_width; } - desc = axi_desc_get(chan); - if (unlikely(!desc)) + hw_desc->lli = axi_desc_get(chan, &hw_desc->llp); + if (unlikely(!hw_desc->lli)) goto err_desc_get; - write_desc_sar(desc, src_adr); - write_desc_dar(desc, dst_adr); - desc->lli.block_ts_lo = cpu_to_le32(block_ts - 1); + write_desc_sar(hw_desc, src_adr); + write_desc_dar(hw_desc, dst_adr); + hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); reg = CH_CTL_H_LLI_VALID; if (chan->chip->dw->hdata->restrict_axi_burst_len) { @@ -474,7 +501,7 @@ static void set_desc_dest_master(struct axi_dma_desc *desc) CH_CTL_H_AWLEN_EN | burst_len << CH_CTL_H_AWLEN_POS); } - desc->lli.ctl_hi = cpu_to_le32(reg); + hw_desc->lli->ctl_hi = cpu_to_le32(reg); reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS | @@ -482,62 +509,61 @@ static void set_desc_dest_master(struct axi_dma_desc *desc) xfer_width << CH_CTL_L_SRC_WIDTH_POS | DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS); - desc->lli.ctl_lo = cpu_to_le32(reg); + hw_desc->lli->ctl_lo = cpu_to_le32(reg); - set_desc_src_master(desc); - set_desc_dest_master(desc); + set_desc_src_master(hw_desc); + set_desc_dest_master(hw_desc, desc); - /* Manage transfer list (xfer_list) */ - if (!first) { - first = desc; - } else { - list_add_tail(&desc->xfer_list, &first->xfer_list); - write_desc_llp(prev, desc->vd.tx.phys | lms); - } - prev = desc; /* update the length and addresses for the next loop cycle */ len -= xfer_len; dst_adr += xfer_len; src_adr += xfer_len; + num++; } /* Total len of src/dest sg == 0, so no descriptor were allocated */ - if (unlikely(!first)) + if (unlikely(!desc)) return NULL; /* Set end-of-link to the last link descriptor of list */ - set_desc_last(desc); + set_desc_last(&desc->hw_desc[num - 1]); + /* Managed transfer list */ + do { + hw_desc = &desc->hw_desc[--num]; + write_desc_llp(hw_desc, llp | lms); + llp = hw_desc->llp; + } while (num); - return vchan_tx_prep(&chan->vc, &first->vd, flags); + return vchan_tx_prep(&chan->vc, &desc->vd, flags); err_desc_get: - if (first) - axi_desc_put(first); + if (desc) + axi_desc_put(desc); return NULL; } static void axi_chan_dump_lli(struct axi_dma_chan *chan, - struct axi_dma_desc *desc) + struct axi_dma_hw_desc *desc) { dev_err(dchan2dev(&chan->vc.chan), "SAR: 0x%llx DAR: 0x%llx LLP: 0x%llx BTS 0x%x CTL: 0x%x:%08x", - le64_to_cpu(desc->lli.sar), - le64_to_cpu(desc->lli.dar), - le64_to_cpu(desc->lli.llp), - le32_to_cpu(desc->lli.block_ts_lo), - le32_to_cpu(desc->lli.ctl_hi), - le32_to_cpu(desc->lli.ctl_lo)); + le64_to_cpu(desc->lli->sar), + le64_to_cpu(desc->lli->dar), + le64_to_cpu(desc->lli->llp), + le32_to_cpu(desc->lli->block_ts_lo), + le32_to_cpu(desc->lli->ctl_hi), + le32_to_cpu(desc->lli->ctl_lo)); } static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, struct axi_dma_desc *desc_head) { - struct axi_dma_desc *desc; + int count = atomic_read(&chan->descs_allocated); + int i; - axi_chan_dump_lli(chan, desc_head); - list_for_each_entry(desc, &desc_head->xfer_list, xfer_list) - axi_chan_dump_lli(chan, desc); + for (i = 0; i < count; i++) + axi_chan_dump_lli(chan, &desc_head->hw_desc[i]); } static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status) @@ -872,7 +898,7 @@ static int dw_probe(struct platform_device *pdev) /* Lli address must be aligned to a 64-byte boundary */ dw->desc_pool = dmam_pool_create(KBUILD_MODNAME, chip->dev, - sizeof(struct axi_dma_desc), 64, 0); + sizeof(struct axi_dma_lli), 64, 0); if (!dw->desc_pool) { dev_err(chip->dev, "No memory for descriptors dma pool\n"); return -ENOMEM; diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h index 18b6014..41e775e 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h @@ -41,6 +41,7 @@ struct axi_dma_chan { struct virt_dma_chan vc; + struct axi_dma_desc *desc; /* these other elements are all protected by vc.lock */ bool is_paused; }; @@ -80,12 +81,16 @@ struct __packed axi_dma_lli { __le32 reserved_hi; }; +struct axi_dma_hw_desc { + struct axi_dma_lli *lli; + dma_addr_t llp; +}; + struct axi_dma_desc { - struct axi_dma_lli lli; + struct axi_dma_hw_desc *hw_desc; struct virt_dma_desc vd; struct axi_dma_chan *chan; - struct list_head xfer_list; }; static inline struct device *dchan2dev(struct dma_chan *dchan) From patchwork Fri Sep 4 09:51:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sia Jee Heng X-Patchwork-Id: 11756497 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 38888618 for ; Fri, 4 Sep 2020 10:07:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2A878207EA for ; Fri, 4 Sep 2020 10:07:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729883AbgIDKH1 (ORCPT ); Fri, 4 Sep 2020 06:07:27 -0400 Received: from mga09.intel.com ([134.134.136.24]:2059 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728588AbgIDKH0 (ORCPT ); Fri, 4 Sep 2020 06:07:26 -0400 IronPort-SDR: Y7q5KaWfayvJjG61D7tZvLiMdS3wJeYIElQTNTPqJ7E89mJIwwzyEsEwT2ZX7ijjzvfmlvOe4P /84L9bwmySCw== X-IronPort-AV: E=McAfee;i="6000,8403,9733"; a="158697577" X-IronPort-AV: E=Sophos;i="5.76,389,1592895600"; d="scan'208";a="158697577" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Sep 2020 03:07:26 -0700 IronPort-SDR: KnAzlR9mPhkMehLOUz3l6m0BcGZeqLbGjTTuYGzmmVGCmw0d7LmjhbhChpKcP0ynuSNQeNDHgo 2bkvnx20jQVg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,389,1592895600"; d="scan'208";a="342143672" Received: from unknown (HELO jsia-HP-Z620-Workstation.png.intel.com) ([10.221.118.135]) by orsmga007.jf.intel.com with ESMTP; 04 Sep 2020 03:07:22 -0700 From: Sia Jee Heng To: Cc: , , , Subject: [PATCH 3/4] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() Date: Fri, 4 Sep 2020 17:51:33 +0800 Message-Id: <1599213094-30144-4-git-send-email-jee.heng.sia@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1599213094-30144-1-git-send-email-jee.heng.sia@intel.com> References: <1599213094-30144-1-git-send-email-jee.heng.sia@intel.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The DMA memory block is created at driver load time and exist for device lifetime. Move the dma_pool_create() to the ->chan_resource() callback function allowing the DMA memory blocks to be created as needed and destroyed when the channel is freed. Signed-off-by: Sia Jee Heng Reviewed-by: Shevchenko, Andriy --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 24 +++++++++++++----------- drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index 8cfd645..46e2ba9 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -216,11 +216,10 @@ static struct axi_dma_desc *axi_desc_alloc(u32 num) static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan, dma_addr_t *addr) { - struct dw_axi_dma *dw = chan->chip->dw; struct axi_dma_lli *lli; dma_addr_t phys; - lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, &phys); + lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys); if (unlikely(!lli)) { dev_err(chan2dev(chan), "%s: not enough descriptors available\n", axi_chan_name(chan)); @@ -236,14 +235,13 @@ static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan, static void axi_desc_put(struct axi_dma_desc *desc) { struct axi_dma_chan *chan = desc->chan; - struct dw_axi_dma *dw = chan->chip->dw; int count = atomic_read(&chan->descs_allocated); struct axi_dma_hw_desc *hw_desc; int descs_put; for (descs_put = 0; descs_put < count; descs_put++) { hw_desc = &desc->hw_desc[descs_put]; - dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp); + dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp); } kfree(desc->hw_desc); @@ -360,6 +358,15 @@ static int dma_chan_alloc_chan_resources(struct dma_chan *dchan) return -EBUSY; } + /* LLI address must be aligned to a 64-byte boundary */ + chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)), + chan->chip->dev, + sizeof(struct axi_dma_lli), + 64, 0); + if (!chan->desc_pool) { + dev_err(chan2dev(chan), "No memory for descriptors\n"); + return -ENOMEM; + } dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan)); pm_runtime_get(chan->chip->dev); @@ -381,6 +388,8 @@ static void dma_chan_free_chan_resources(struct dma_chan *dchan) vchan_free_chan_resources(&chan->vc); + dma_pool_destroy(chan->desc_pool); + chan->desc_pool = NULL; dev_vdbg(dchan2dev(dchan), "%s: free resources, descriptor still allocated: %u\n", axi_chan_name(chan), atomic_read(&chan->descs_allocated)); @@ -896,13 +905,6 @@ static int dw_probe(struct platform_device *pdev) if (ret) return ret; - /* Lli address must be aligned to a 64-byte boundary */ - dw->desc_pool = dmam_pool_create(KBUILD_MODNAME, chip->dev, - sizeof(struct axi_dma_lli), 64, 0); - if (!dw->desc_pool) { - dev_err(chip->dev, "No memory for descriptors dma pool\n"); - return -ENOMEM; - } INIT_LIST_HEAD(&dw->dma.channels); for (i = 0; i < hdata->nr_channels; i++) { diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h index 41e775e..f886b2b 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h @@ -39,6 +39,7 @@ struct axi_dma_chan { u8 id; atomic_t descs_allocated; + struct dma_pool *desc_pool; struct virt_dma_chan vc; struct axi_dma_desc *desc; @@ -49,7 +50,6 @@ struct axi_dma_chan { struct dw_axi_dma { struct dma_device dma; struct dw_axi_dma_hcfg *hdata; - struct dma_pool *desc_pool; /* channels */ struct axi_dma_chan *chan; From patchwork Fri Sep 4 09:51:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sia Jee Heng X-Patchwork-Id: 11756499 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9F87F15AB for ; Fri, 4 Sep 2020 10:07:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8896020791 for ; Fri, 4 Sep 2020 10:07:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728588AbgIDKH2 (ORCPT ); Fri, 4 Sep 2020 06:07:28 -0400 Received: from mga09.intel.com ([134.134.136.24]:2059 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729942AbgIDKH1 (ORCPT ); Fri, 4 Sep 2020 06:07:27 -0400 IronPort-SDR: bu3x2HJpP34LYGDk/SwwCvBycSafQJjc7EQHo3TyfDEUKBzlVXOQ9by+bnLBC+MMetu+ISxWKB FCPaC9YXikLQ== X-IronPort-AV: E=McAfee;i="6000,8403,9733"; a="158697582" X-IronPort-AV: E=Sophos;i="5.76,389,1592895600"; d="scan'208";a="158697582" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Sep 2020 03:07:27 -0700 IronPort-SDR: W41n90XDb6WLbwcMU+CW4y7G7kO9wGKw259qQCx0SBxoi2ExT90gT16hc6oEvGzpQbo40T9mv8 Lun26Ww+G+RA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,389,1592895600"; d="scan'208";a="342143679" Received: from unknown (HELO jsia-HP-Z620-Workstation.png.intel.com) ([10.221.118.135]) by orsmga007.jf.intel.com with ESMTP; 04 Sep 2020 03:07:25 -0700 From: Sia Jee Heng To: Cc: , , , Subject: [PATCH 4/4] dmaengine: dw-axi-dmac: Add device_synchronize() callback Date: Fri, 4 Sep 2020 17:51:34 +0800 Message-Id: <1599213094-30144-5-git-send-email-jee.heng.sia@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1599213094-30144-1-git-send-email-jee.heng.sia@intel.com> References: <1599213094-30144-1-git-send-email-jee.heng.sia@intel.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add support for device_synchronize() callback function to sync with dmaengine_terminate_sync(). Signed-off-by: Sia Jee Heng Reviewed-by: Shevchenko, Andriy --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index 46e2ba9..56b2132 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -347,6 +347,13 @@ static void dma_chan_issue_pending(struct dma_chan *dchan) spin_unlock_irqrestore(&chan->vc.lock, flags); } +static void dw_axi_dma_synchronize(struct dma_chan *dchan) +{ + struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); + + vchan_synchronize(&chan->vc); +} + static int dma_chan_alloc_chan_resources(struct dma_chan *dchan) { struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); @@ -940,6 +947,7 @@ static int dw_probe(struct platform_device *pdev) dw->dma.device_free_chan_resources = dma_chan_free_chan_resources; dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy; + dw->dma.device_synchronize = dw_axi_dma_synchronize; platform_set_drvdata(pdev, chip);