From patchwork Tue Sep 8 07:57:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 11762911 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BC6B416C0 for ; Tue, 8 Sep 2020 08:05:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 92B9521D6C for ; Tue, 8 Sep 2020 08:05:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="q0syyZEH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729789AbgIHIF3 (ORCPT ); Tue, 8 Sep 2020 04:05:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729778AbgIHH5f (ORCPT ); Tue, 8 Sep 2020 03:57:35 -0400 Received: from mail-pj1-x1043.google.com (mail-pj1-x1043.google.com [IPv6:2607:f8b0:4864:20::1043]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D3FAC061755 for ; Tue, 8 Sep 2020 00:57:35 -0700 (PDT) Received: by mail-pj1-x1043.google.com with SMTP id mm21so7870190pjb.4 for ; Tue, 08 Sep 2020 00:57:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jp1JbuEONyh0D3c15mdIEQg1E4rtcuX67btWSgzEVZ0=; b=q0syyZEHC6UJrwegi0WqqL8cvZWfYs02KO3ti/PWcyksi9BW0jaJbDN6ApeYHBSjDv mOeziD6tiK1Xbu3Hnybyo3dlcmP+1cVCyZKh/pj5kWXZMEeV3CwfkhuYVFAA7cE1utQ5 /vCcD4Sk3/BmKlFk8tyf6Kga/Wb42ORnQXm0zNctna93YZKwGX7vb+b9HSWbJatO+XUY sMor/KOYzLcUfeVq3q03J1iFdKxOE665GPxtFlBmHJuGQuCn42XgO8m6J2cruiI1HLhs KAwCBh+a9fqyntz4TOp8iPC82h+tL9jE1s8WsJOECElZs5qL9aNsMs6Anxo0CrByE4f/ u5ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jp1JbuEONyh0D3c15mdIEQg1E4rtcuX67btWSgzEVZ0=; b=p1v7Q9hO1TsId8E6BWKsVZEhGYI7qQ0tf38DDtqkoblKmfXgprR/w4qZZ6e3YJaWgs CbR5xpRV7RxJHZ18eC6YB1OD9zFthzMsOjcbP/OTyE72t6LS9enf+w8pSTUWXupidkpm 4/UVkNebPCwR485UmydTv2F4QwnVlMzpGtTq2NYdZ/FOCahiqjMcQP7nNbW7ODghXOio PvB3jXitAJPqcp8mH6J5M79hW5xR+AlGCkVoAq1kCo8qEFP7s9Zi40u3K2ezfXTfrJtV D9piO+7RTF6vXhNtLwyQ5GnmcTirRbtsc9x4JIk2PhvxUY3NCEgkfPflKcwn6c+41epI aWow== X-Gm-Message-State: AOAM533GDSaajCRBR/P+jwxk1hpFAH0RraXlG3xHjUE6wYUxUaVgnr4I cycb/RXW9uWcoBd4rvqxw9Ty X-Google-Smtp-Source: ABdhPJxKmEuz+uZ0bUmp4YnY8M63J+6oLAHi4IgbNQqubssEsG00n14g7ib0k0+hUHZoOE0Ou6oSpA== X-Received: by 2002:a17:90a:f992:: with SMTP id cq18mr2899411pjb.136.1599551854565; Tue, 08 Sep 2020 00:57:34 -0700 (PDT) Received: from localhost.localdomain ([103.59.133.81]) by smtp.googlemail.com with ESMTPSA id m21sm7560154pfo.13.2020.09.08.00.57.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 00:57:34 -0700 (PDT) From: Manivannan Sadhasivam To: rjw@rjwysocki.net, viresh.kumar@linaro.org, robh+dt@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: amitk@kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dmitry.baryshkov@linaro.org, tdas@codeaurora.org, Manivannan Sadhasivam Subject: [PATCH 1/7] dt-bindings: cpufreq: cpufreq-qcom-hw: Document SM8250 compatible Date: Tue, 8 Sep 2020 13:27:10 +0530 Message-Id: <20200908075716.30357-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> References: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Document the SM8250 SoC specific compatible for Qualcomm Cpufreq HW. The hardware block which carries out CPUFreq operations on SM8250 SoC is called EPSS. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Amit Kucheria Reviewed-by: Bjorn Andersson Acked-by: Rob Herring --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt index 33856947c561..aea4ddb2b9e8 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt @@ -8,7 +8,7 @@ Properties: - compatible Usage: required Value type: - Definition: must be "qcom,cpufreq-hw". + Definition: must be "qcom,cpufreq-hw" or "qcom,sm8250-epss". - clocks Usage: required From patchwork Tue Sep 8 07:57:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 11762831 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7313059D for ; Tue, 8 Sep 2020 07:58:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 58B1021D20 for ; Tue, 8 Sep 2020 07:58:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="mvoXEciH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729953AbgIHH5z (ORCPT ); Tue, 8 Sep 2020 03:57:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729922AbgIHH5s (ORCPT ); Tue, 8 Sep 2020 03:57:48 -0400 Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F84EC061795 for ; Tue, 8 Sep 2020 00:57:40 -0700 (PDT) Received: by mail-pg1-x544.google.com with SMTP id 34so58935pgo.13 for ; Tue, 08 Sep 2020 00:57:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dVSf2eOrndrAFT6QUUuIacL06FJeCrpQS/XjWnR+m+g=; b=mvoXEciH3g8cWyPFw9lkTqVILJbvJy/xomNt+JSdkBHHQNF2MlRH3EQjTsB8fq73HL 2OZCi1DOBNI99po5o1KJh8+/J1arFAi5xBt0YYPBLBFwx9NqCcwg5QyVZt+CFyU4APy4 yc7mNeeXusKRsmrPx3hq6my8gSLdit/IQwU3NM0Q8MlimrqEOp8DNDuQ5G99nQ860Yh3 GnlwLFicuh0PSeLacjzMz5W0R+65KY9RJ2tj4FsCgn2cYAQ4WTwPQAukCbnzwIrP5ylZ kwStDaBvKbOHy67PH4dMpLliQneKVF9eTGavJE0tB+kI1GaRpozoAnjlCxcB4yjo1L4y nEsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dVSf2eOrndrAFT6QUUuIacL06FJeCrpQS/XjWnR+m+g=; b=R+UpWOf0hN3fPS65+c00UNRBPaz5JKq7F+27cNT0e0U0bOoa3x4J0NY4aGK8Tsew4Z dRljswLWe/ZzYGixbH616XCMCokBVkKGJOtix4GtgWyKOrcgYNPxSF2TfIUVPXdMX5KI mlstXAHPAlaI/QLJkEIbXjFfkSBUc9QWEmj77I2nv3dy06VHm1H19NASUmwBcOiDBhk6 gl/y+IZ0vMejik5E9a3d00/zLae2PMgeOwzECoPxZp5sWXWf3j0dRp1Tg+87QebcTVGH e0KOjG+078CUzsg6ps3+rtiR7XQEO8BSWCl4IOdtrZk7pGLpvR1hOm1vgrZ1SBx4Yys0 r0mQ== X-Gm-Message-State: AOAM531IiBd2p2yvnjE+7MpaIIBmYko+MwhKkLyhauH9sNdUEPptaxqp 3BGcX8vYJJjhVEY9TPffZ323 X-Google-Smtp-Source: ABdhPJz/6SYkXXQgE0eri63Ih9i/RSuXmfp61Yk7DuB2kZHEvH+aPSAfVL87BCXdO2+di1y4Y24kkQ== X-Received: by 2002:a63:2055:: with SMTP id r21mr6448504pgm.118.1599551858556; Tue, 08 Sep 2020 00:57:38 -0700 (PDT) Received: from localhost.localdomain ([103.59.133.81]) by smtp.googlemail.com with ESMTPSA id m21sm7560154pfo.13.2020.09.08.00.57.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 00:57:38 -0700 (PDT) From: Manivannan Sadhasivam To: rjw@rjwysocki.net, viresh.kumar@linaro.org, robh+dt@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: amitk@kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dmitry.baryshkov@linaro.org, tdas@codeaurora.org, Manivannan Sadhasivam Subject: [PATCH 2/7] arm64: dts: qcom: sm8250: Add cpufreq hw node Date: Tue, 8 Sep 2020 13:27:11 +0530 Message-Id: <20200908075716.30357-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> References: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Bjorn Andersson Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores on SM8250 SoCs. Signed-off-by: Bjorn Andersson Signed-off-by: Manivannan Sadhasivam Acked-by: Viresh Kumar Reviewed-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index e7d139e1a6ce..aafb46a26a9c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -87,6 +87,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -102,6 +103,7 @@ reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -114,6 +116,7 @@ reg = <0x0 0x200>; enable-method = "psci"; next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -126,6 +129,7 @@ reg = <0x0 0x300>; enable-method = "psci"; next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -138,6 +142,7 @@ reg = <0x0 0x400>; enable-method = "psci"; next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -150,6 +155,7 @@ reg = <0x0 0x500>; enable-method = "psci"; next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -163,6 +169,7 @@ reg = <0x0 0x600>; enable-method = "psci"; next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -175,6 +182,7 @@ reg = <0x0 0x700>; enable-method = "psci"; next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -2076,6 +2084,20 @@ }; }; }; + + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,sm8250-epss"; + reg = <0 0x18591000 0 0x1000>, + <0 0x18592000 0 0x1000>, + <0 0x18593000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1", + "freq-domain2"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; timer { From patchwork Tue Sep 8 07:57:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 11762833 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 21FD5746 for ; Tue, 8 Sep 2020 07:58:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 06B2221D20 for ; Tue, 8 Sep 2020 07:58:04 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Tue, 08 Sep 2020 00:57:42 -0700 (PDT) From: Manivannan Sadhasivam To: rjw@rjwysocki.net, viresh.kumar@linaro.org, robh+dt@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: amitk@kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dmitry.baryshkov@linaro.org, tdas@codeaurora.org, Manivannan Sadhasivam Subject: [PATCH 3/7] cpufreq: qcom-hw: Make use of cpufreq driver_data for passing pdev Date: Tue, 8 Sep 2020 13:27:12 +0530 Message-Id: <20200908075716.30357-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> References: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Get rid of global_pdev pointer and make use of cpufreq driver_data for passing the reference of pdev. This aligns with what other cpufreq drivers are doing. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index 3fb044b907a8..ccea34f61152 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -30,7 +30,6 @@ #define REG_PERF_STATE 0x920 static unsigned long cpu_hw_rate, xo_rate; -static struct platform_device *global_pdev; static bool icc_scaling_enabled; static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy, @@ -240,7 +239,8 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) { - struct device *dev = &global_pdev->dev; + struct platform_device *pdev = cpufreq_get_driver_data(); + struct device *dev = &pdev->dev; struct of_phandle_args args; struct device_node *cpu_np; struct device *cpu_dev; @@ -267,7 +267,7 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) index = args.args[0]; - res = platform_get_resource(global_pdev, IORESOURCE_MEM, index); + res = platform_get_resource(pdev, IORESOURCE_MEM, index); if (!res) return -ENODEV; @@ -316,11 +316,12 @@ static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) { struct device *cpu_dev = get_cpu_device(policy->cpu); void __iomem *base = policy->driver_data - REG_PERF_STATE; + struct platform_device *pdev = cpufreq_get_driver_data(); dev_pm_opp_remove_all_dynamic(cpu_dev); dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); kfree(policy->freq_table); - devm_iounmap(&global_pdev->dev, base); + devm_iounmap(&pdev->dev, base); return 0; } @@ -365,7 +366,7 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV; clk_put(clk); - global_pdev = pdev; + cpufreq_qcom_hw_driver.driver_data = pdev; /* Check for optional interconnect paths on CPU0 */ cpu_dev = get_cpu_device(0); From patchwork Tue Sep 8 07:57:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 11762905 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 63C81746 for ; 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Tue, 08 Sep 2020 00:57:46 -0700 (PDT) Received: from localhost.localdomain ([103.59.133.81]) by smtp.googlemail.com with ESMTPSA id m21sm7560154pfo.13.2020.09.08.00.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 00:57:46 -0700 (PDT) From: Manivannan Sadhasivam To: rjw@rjwysocki.net, viresh.kumar@linaro.org, robh+dt@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: amitk@kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dmitry.baryshkov@linaro.org, tdas@codeaurora.org, Manivannan Sadhasivam Subject: [PATCH 4/7] cpufreq: qcom-hw: Make use of of_match data for offsets and row size Date: Tue, 8 Sep 2020 13:27:13 +0530 Message-Id: <20200908075716.30357-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> References: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org For preparing the driver to handle further SoC revisions, let's use the of_match data for getting the device specific offsets and row size instead of defining them globally. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 96 +++++++++++++++++++++---------- 1 file changed, 66 insertions(+), 30 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index ccea34f61152..41853db7c9b8 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -19,15 +19,21 @@ #define LUT_L_VAL GENMASK(7, 0) #define LUT_CORE_COUNT GENMASK(18, 16) #define LUT_VOLT GENMASK(11, 0) -#define LUT_ROW_SIZE 32 #define CLK_HW_DIV 2 #define LUT_TURBO_IND 1 -/* Register offsets */ -#define REG_ENABLE 0x0 -#define REG_FREQ_LUT 0x110 -#define REG_VOLT_LUT 0x114 -#define REG_PERF_STATE 0x920 +struct qcom_cpufreq_soc_data { + u32 reg_enable; + u32 reg_freq_lut; + u32 reg_volt_lut; + u32 reg_perf_state; + u8 lut_row_size; +}; + +struct qcom_cpufreq_data { + void __iomem *base; + const struct qcom_cpufreq_soc_data *soc_data; +}; static unsigned long cpu_hw_rate, xo_rate; static bool icc_scaling_enabled; @@ -76,10 +82,11 @@ static int qcom_cpufreq_update_opp(struct device *cpu_dev, static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) { - void __iomem *perf_state_reg = policy->driver_data; + struct qcom_cpufreq_data *data = policy->driver_data; + const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; unsigned long freq = policy->freq_table[index].frequency; - writel_relaxed(index, perf_state_reg); + writel_relaxed(index, data->base + soc_data->reg_perf_state); if (icc_scaling_enabled) qcom_cpufreq_set_bw(policy, freq); @@ -91,7 +98,8 @@ static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) { - void __iomem *perf_state_reg; + struct qcom_cpufreq_data *data; + const struct qcom_cpufreq_soc_data *soc_data; struct cpufreq_policy *policy; unsigned int index; @@ -99,9 +107,10 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) if (!policy) return 0; - perf_state_reg = policy->driver_data; + data = policy->driver_data; + soc_data = data->soc_data; - index = readl_relaxed(perf_state_reg); + index = readl_relaxed(data->base + soc_data->reg_perf_state); index = min(index, LUT_MAX_ENTRIES - 1); return policy->freq_table[index].frequency; @@ -110,12 +119,13 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, unsigned int target_freq) { - void __iomem *perf_state_reg = policy->driver_data; + struct qcom_cpufreq_data *data = policy->driver_data; + const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; unsigned int index; unsigned long freq; index = policy->cached_resolved_idx; - writel_relaxed(index, perf_state_reg); + writel_relaxed(index, data->base + soc_data->reg_perf_state); freq = policy->freq_table[index].frequency; arch_set_freq_scale(policy->related_cpus, freq, @@ -125,8 +135,7 @@ static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, } static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, - struct cpufreq_policy *policy, - void __iomem *base) + struct cpufreq_policy *policy) { u32 data, src, lval, i, core_count, prev_freq = 0, freq; u32 volt; @@ -134,6 +143,8 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, struct dev_pm_opp *opp; unsigned long rate; int ret; + struct qcom_cpufreq_data *drv_data = policy->driver_data; + const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data; table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); if (!table) @@ -160,14 +171,14 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, } for (i = 0; i < LUT_MAX_ENTRIES; i++) { - data = readl_relaxed(base + REG_FREQ_LUT + - i * LUT_ROW_SIZE); + data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut + + i * soc_data->lut_row_size); src = FIELD_GET(LUT_SRC, data); lval = FIELD_GET(LUT_L_VAL, data); core_count = FIELD_GET(LUT_CORE_COUNT, data); - data = readl_relaxed(base + REG_VOLT_LUT + - i * LUT_ROW_SIZE); + data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut + + i * soc_data->lut_row_size); volt = FIELD_GET(LUT_VOLT, data) * 1000; if (src) @@ -237,6 +248,20 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) } } +static const struct qcom_cpufreq_soc_data qcom_soc_data = { + .reg_enable = 0x0, + .reg_freq_lut = 0x110, + .reg_volt_lut = 0x114, + .reg_perf_state = 0x920, + .lut_row_size = 32, +}; + +static const struct of_device_id qcom_cpufreq_hw_match[] = { + { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, + {} +}; +MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); + static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) { struct platform_device *pdev = cpufreq_get_driver_data(); @@ -246,6 +271,8 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) struct device *cpu_dev; struct resource *res; void __iomem *base; + struct qcom_cpufreq_data *data; + const struct of_device_id *match; int ret, index; cpu_dev = get_cpu_device(policy->cpu); @@ -275,8 +302,23 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) if (!base) return -ENOMEM; + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) { + ret = -ENOMEM; + goto error; + } + + match = of_match_device(qcom_cpufreq_hw_match, &pdev->dev); + if (!match) { + ret = -ENODEV; + goto error; + } + + data->soc_data = match->data; + data->base = base; + /* HW should be in enabled state to proceed */ - if (!(readl_relaxed(base + REG_ENABLE) & 0x1)) { + if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) { dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); ret = -ENODEV; goto error; @@ -289,9 +331,9 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) goto error; } - policy->driver_data = base + REG_PERF_STATE; + policy->driver_data = data; - ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy, base); + ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy); if (ret) { dev_err(dev, "Domain-%d failed to read LUT\n", index); goto error; @@ -315,13 +357,13 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) { struct device *cpu_dev = get_cpu_device(policy->cpu); - void __iomem *base = policy->driver_data - REG_PERF_STATE; + struct qcom_cpufreq_data *data = policy->driver_data; struct platform_device *pdev = cpufreq_get_driver_data(); dev_pm_opp_remove_all_dynamic(cpu_dev); dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); kfree(policy->freq_table); - devm_iounmap(&pdev->dev, base); + devm_iounmap(&pdev->dev, data->base); return 0; } @@ -391,12 +433,6 @@ static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev) return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver); } -static const struct of_device_id qcom_cpufreq_hw_match[] = { - { .compatible = "qcom,cpufreq-hw" }, - {} -}; -MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); - static struct platform_driver qcom_cpufreq_hw_driver = { .probe = qcom_cpufreq_hw_driver_probe, .remove = qcom_cpufreq_hw_driver_remove, From patchwork Tue Sep 8 07:57:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 11762901 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 717AF746 for ; Tue, 8 Sep 2020 08:05:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5169121D47 for ; Tue, 8 Sep 2020 08:05:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="QQYLtPYQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729643AbgIHIE4 (ORCPT ); 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Tue, 08 Sep 2020 00:57:50 -0700 (PDT) From: Manivannan Sadhasivam To: rjw@rjwysocki.net, viresh.kumar@linaro.org, robh+dt@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: amitk@kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dmitry.baryshkov@linaro.org, tdas@codeaurora.org, Manivannan Sadhasivam Subject: [PATCH 5/7] cpufreq: qcom-hw: Use regmap for accessing hardware registers Date: Tue, 8 Sep 2020 13:27:14 +0530 Message-Id: <20200908075716.30357-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> References: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Use regmap for accessing cpufreq registers in hardware. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 55 ++++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 8 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index 41853db7c9b8..de816bcafd33 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #define LUT_MAX_ENTRIES 40U @@ -32,6 +33,7 @@ struct qcom_cpufreq_soc_data { struct qcom_cpufreq_data { void __iomem *base; + struct regmap *regmap; const struct qcom_cpufreq_soc_data *soc_data; }; @@ -85,8 +87,11 @@ static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, struct qcom_cpufreq_data *data = policy->driver_data; const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; unsigned long freq = policy->freq_table[index].frequency; + int ret; - writel_relaxed(index, data->base + soc_data->reg_perf_state); + ret = regmap_write(data->regmap, soc_data->reg_perf_state, index); + if (ret) + return ret; if (icc_scaling_enabled) qcom_cpufreq_set_bw(policy, freq); @@ -102,6 +107,7 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) const struct qcom_cpufreq_soc_data *soc_data; struct cpufreq_policy *policy; unsigned int index; + int ret; policy = cpufreq_cpu_get_raw(cpu); if (!policy) @@ -110,7 +116,10 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cpu) data = policy->driver_data; soc_data = data->soc_data; - index = readl_relaxed(data->base + soc_data->reg_perf_state); + ret = regmap_read(data->regmap, soc_data->reg_perf_state, &index); + if (ret) + return 0; + index = min(index, LUT_MAX_ENTRIES - 1); return policy->freq_table[index].frequency; @@ -123,9 +132,12 @@ static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy, const struct qcom_cpufreq_soc_data *soc_data = data->soc_data; unsigned int index; unsigned long freq; + int ret; index = policy->cached_resolved_idx; - writel_relaxed(index, data->base + soc_data->reg_perf_state); + ret = regmap_write(data->regmap, soc_data->reg_perf_state, index); + if (ret) + return 0; freq = policy->freq_table[index].frequency; arch_set_freq_scale(policy->related_cpus, freq, @@ -171,14 +183,24 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, } for (i = 0; i < LUT_MAX_ENTRIES; i++) { - data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut + - i * soc_data->lut_row_size); + ret = regmap_read(drv_data->regmap, soc_data->reg_freq_lut + + i * soc_data->lut_row_size, &data); + if (ret) { + kfree(table); + return ret; + } + src = FIELD_GET(LUT_SRC, data); lval = FIELD_GET(LUT_L_VAL, data); core_count = FIELD_GET(LUT_CORE_COUNT, data); - data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut + - i * soc_data->lut_row_size); + ret = regmap_read(drv_data->regmap, soc_data->reg_volt_lut + + i * soc_data->lut_row_size, &data); + if (ret) { + kfree(table); + return ret; + } + volt = FIELD_GET(LUT_VOLT, data) * 1000; if (src) @@ -248,6 +270,13 @@ static void qcom_get_related_cpus(int index, struct cpumask *m) } } +static struct regmap_config qcom_cpufreq_regmap = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + static const struct qcom_cpufreq_soc_data qcom_soc_data = { .reg_enable = 0x0, .reg_freq_lut = 0x110, @@ -274,6 +303,7 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) struct qcom_cpufreq_data *data; const struct of_device_id *match; int ret, index; + u32 val; cpu_dev = get_cpu_device(policy->cpu); if (!cpu_dev) { @@ -316,9 +346,18 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) data->soc_data = match->data; data->base = base; + data->regmap = devm_regmap_init_mmio(dev, base, &qcom_cpufreq_regmap); + if (IS_ERR(data->regmap)) { + ret = PTR_ERR(data->regmap); + goto error; + } /* HW should be in enabled state to proceed */ - if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) { + ret = regmap_read(data->regmap, data->soc_data->reg_enable, &val); + if (ret) + goto error; + + if (!(val & 0x1)) { dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); ret = -ENODEV; goto error; From patchwork Tue Sep 8 07:57:15 2020 Content-Type: text/plain; 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Hence, add support for it in the driver with relevant of_match data. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Amit Kucheria Reviewed-by: Bjorn Andersson --- drivers/cpufreq/qcom-cpufreq-hw.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index de816bcafd33..c3c397cc3dc6 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -285,8 +285,17 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = { .lut_row_size = 32, }; +static const struct qcom_cpufreq_soc_data sm8250_soc_data = { + .reg_enable = 0x0, + .reg_freq_lut = 0x100, + .reg_volt_lut = 0x200, + .reg_perf_state = 0x320, + .lut_row_size = 4, +}; + static const struct of_device_id qcom_cpufreq_hw_match[] = { { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, + { .compatible = "qcom,sm8250-epss", .data = &sm8250_soc_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); From patchwork Tue Sep 8 07:57:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 11762859 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7F45659D for ; Tue, 8 Sep 2020 07:59:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 63BE621D47 for ; Tue, 8 Sep 2020 07:59:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="YQou9t73" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729986AbgIHH6b (ORCPT ); Tue, 8 Sep 2020 03:58:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729685AbgIHH57 (ORCPT ); Tue, 8 Sep 2020 03:57:59 -0400 Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 354EDC061796 for ; Tue, 8 Sep 2020 00:57:59 -0700 (PDT) Received: by mail-pf1-x443.google.com with SMTP id o68so10303300pfg.2 for ; Tue, 08 Sep 2020 00:57:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=p4U6DywWAGG7hqWgno8xA4KNHg7T7GRWqkUHfcQvB3k=; b=YQou9t73q5qKqw0WsgZMOwsCEXbHt8zLCXbEiq5x9ImKUtCw6ZGOQasYp8i6qPO6q8 MoY4rFNcbXHaH/VVnkF+I/EV8/Xefc6LmJetEQ7Jo+jQhbpad5ca92o+uQTmT+QmPRfB miD/PCeXTgw9JjnidrITEqCFnTmMiqveWEvcLy8gFl4sbyW2dWZv9e+ntbOTPEDKyg7O jYBlXLUjy4xJ9qRsnzG/BrB89taE/tVr8drt9rN35c2EsGVXFRfs4D1HkNmKNuVrdtgG yLlfHFsXKBsPF0n5CbmAHxcfw405bEE7X84CBsTR5maDfD3GJs1CXAb1wJh1Ao7HWp2b 98Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=p4U6DywWAGG7hqWgno8xA4KNHg7T7GRWqkUHfcQvB3k=; b=LFleZFw2VA2QsiRcZsqvG8Gg5UvRCaD4JmqwLDzFDHvROBPJYqPvpY08JidcjIe5l1 qXehjI1WG8MeDqvQriPgWsLuAJ4kzKdpRRURqj+mmOBrP50CEX0D+i6QEWpbu6IR3hkq YcbB1ec+s0M21SakAFiBFXhCyKhSv1wrqQUy3Ne5lnel3U1/lhbaQI9YCk9SuJ2ZzeGW XuvBA4S6/YL1HgCsnWX6h7s9ZJudU4T9LB0se7mrD7A26tpaVd2Tfvb7WRifUpa9Jxn6 Eig3YYvOz0jHbBywfPqkgzlHGV+NowWNzKVdxvNRNICO9wslmTpYK2XbUbGsEQ+tOTqP +Yqg== X-Gm-Message-State: AOAM530iRR5hi/1pMp7vLTNOkY8DaFYAa0lYeOPvBm7c7+dTFdJckOL8 uwoheOoMJdva9SpUc1ZyiebU X-Google-Smtp-Source: ABdhPJwRUgI36ssfNhxpK77UGbBRO6qF4+xSHVU9GHpnJGzrN/z7Eow2VJb49MTdxfIMJK78Zg4mjw== X-Received: by 2002:a17:902:8f8a:b029:d0:cc02:8541 with SMTP id z10-20020a1709028f8ab02900d0cc028541mr29499plo.32.1599551878673; Tue, 08 Sep 2020 00:57:58 -0700 (PDT) Received: from localhost.localdomain ([103.59.133.81]) by smtp.googlemail.com with ESMTPSA id m21sm7560154pfo.13.2020.09.08.00.57.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 00:57:58 -0700 (PDT) From: Manivannan Sadhasivam To: rjw@rjwysocki.net, viresh.kumar@linaro.org, robh+dt@kernel.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: amitk@kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dmitry.baryshkov@linaro.org, tdas@codeaurora.org, Manivannan Sadhasivam Subject: [PATCH 7/7] cpufreq: qcom-hw: Use devm_platform_ioremap_resource() to simplify code Date: Tue, 8 Sep 2020 13:27:16 +0530 Message-Id: <20200908075716.30357-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> References: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org devm_platform_ioremap_resource() is the combination of platform_get_resource() and devm_ioremap_resource(). Hence, use it to simplify the code a bit. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Amit Kucheria Reviewed-by: Bjorn Andersson --- drivers/cpufreq/qcom-cpufreq-hw.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index c3c397cc3dc6..6eeeb2bd4dfa 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -307,7 +307,6 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) struct of_phandle_args args; struct device_node *cpu_np; struct device *cpu_dev; - struct resource *res; void __iomem *base; struct qcom_cpufreq_data *data; const struct of_device_id *match; @@ -333,13 +332,9 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) index = args.args[0]; - res = platform_get_resource(pdev, IORESOURCE_MEM, index); - if (!res) - return -ENODEV; - - base = devm_ioremap(dev, res->start, resource_size(res)); - if (!base) - return -ENOMEM; + base = devm_platform_ioremap_resource(pdev, index); + if (IS_ERR(base)) + return PTR_ERR(base); data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) {