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Tue, 8 Sep 2020 09:21:16 +0000 From: peng.fan@nxp.com To: sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, abel.vesa@nxp.com Cc: kernel@pengutronix.de, linux-imx@nxp.com, Anson.Huang@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, aisheng.dong@nxp.com, Peng Fan Subject: [PATCH] clk: imx: lpcg-scu: SW workaround for errata (e10858) Date: Tue, 8 Sep 2020 17:14:47 +0800 Message-Id: <1599556487-31364-1-git-send-email-peng.fan@nxp.com> X-Mailer: git-send-email 2.7.4 X-ClientProxiedBy: SG2PR02CA0003.apcprd02.prod.outlook.com (2603:1096:3:17::15) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from 10.192.242.69 (119.31.174.66) by SG2PR02CA0003.apcprd02.prod.outlook.com (2603:1096:3:17::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3348.15 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: p7jEZWPUxybH5aOvBeLrIQD4rjLQ4qUAoazdRy81D7EGOiaLuDToFt90DTuit4eACs49nAvC9xGa7qBbaENVVtgKUZWX/VOBFKptGz02S26L4Kq4eKH4V2dQ01bUU1U7xCB4qMcntsn+i1gAKW5Qi1at5snOxAdl8hVseTUK8z+GICvDZlTKmfuJ+3QsAEyi6VVjnE4V/a0Ts3v3UNT1tgLeVYYcb3KHHo+8LRjWAmuGyX0NSDBui0uIM8XUilUNcCKr/8ltKR3P8OT54VCTzUGDZrpQTbAAL0ptYSxqOlcqWwG3vF9OgSGlhPxXTV89RHNYv+Xc5agK++qHl2QzrTHbrrjxmJC8mviFg07JDrlSYrcsFUYVlKlE762gKSA1eB0EssGsNAWf0Wl8U5MhapIxzYmnrO5xVAjHSx/BWHGFaPR0lYwwpXCziLqcitPrxFJOhGXcyt1teT3dESyrAQoOdxohw5y3qs3/YIK0boUC6YmPk5BeJU5hJFBYN9jv+Lk5FFKHFe46hAXPjlgSAkXkB6ce5j+ULG5SVM2Kp2sURjUThlhPvOVGLFZMsSmKgO6D6PN3oUuxTmSGeo5qjs7oh8PaboaoVxv3jiMDjJyn0gzLZ+veQeCUyISZCaL37pcSzWsRThOoU8pxNpvhbw== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: fe998cae-0d69-49f9-a8ac-08d853d88967 X-MS-Exchange-CrossTenant-AuthSource: DB6PR0402MB2760.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2020 09:21:15.9726 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Hd+NMvzmdMmk1TR48p2GhGIsrGuyGK9yQWbskAq+W86OeaaaY4Z93tmT9EfRTmpwXWgustiJt2USu2Pm3T66Vg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB4937 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Peng Fan Back-to-back LPCG writes can be ignored by the LPCG register due to a HW bug. The writes need to be separated by at least 4 cycles of the gated clock. The workaround is implemented as follows: 1. For clocks running greater than or equal to 24MHz, a read followed by the write will provide sufficient delay. 2. For clocks running below 24MHz, add a delay of 4 clock cylces after the write to the LPCG register. Signed-off-by: Peng Fan Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-lpcg-scu.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c index 1f0e44f921ae..6ee9d2caedf2 100644 --- a/drivers/clk/imx/clk-lpcg-scu.c +++ b/drivers/clk/imx/clk-lpcg-scu.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -38,6 +39,31 @@ struct clk_lpcg_scu { #define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw) +/* e10858 -LPCG clock gating register synchronization errata */ +static void do_lpcg_workaround(u32 rate, void __iomem *reg, u32 val) +{ + writel(val, reg); + + if (rate >= 24000000 || rate == 0) { + u32 reg1; + + /* + * The time taken to access the LPCG registers from the AP core + * through the interconnect is longer than the minimum delay + * of 4 clock cycles required by the errata. + * Adding a readl will provide sufficient delay to prevent + * back-to-back writes. + */ + reg1 = readl(reg); + } else { + /* + * For clocks running below 24MHz, wait a minimum of + * 4 clock cycles. + */ + ndelay(4 * (DIV_ROUND_UP(1000000000, rate))); + } +} + static int clk_lpcg_scu_enable(struct clk_hw *hw) { struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); @@ -54,7 +80,8 @@ static int clk_lpcg_scu_enable(struct clk_hw *hw) val |= CLK_GATE_SCU_LPCG_HW_SEL; reg |= val << clk->bit_idx; - writel(reg, clk->reg); + + do_lpcg_workaround(clk_hw_get_rate(hw), clk->reg, reg); spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); @@ -71,7 +98,7 @@ static void clk_lpcg_scu_disable(struct clk_hw *hw) reg = readl_relaxed(clk->reg); reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); - writel(reg, clk->reg); + do_lpcg_workaround(clk_hw_get_rate(hw), clk->reg, reg); spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); }