From patchwork Wed Sep 9 04:42:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11764849 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3C0B7138E for ; Wed, 9 Sep 2020 04:44:46 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9645021D40 for ; Wed, 9 Sep 2020 04:44:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="fAjFnsP1" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9645021D40 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5423+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id lkHKYY4521763x9NM8WVyoj2; Tue, 08 Sep 2020 21:44:43 -0700 X-Received: from wens.tw (wens.tw [140.112.194.72]) by mx.groups.io with SMTP id smtpd.web12.6683.1599626681623362607 for ; Tue, 08 Sep 2020 21:44:42 -0700 X-Received: by wens.tw (Postfix, from userid 1000) id CCD095FD01; Wed, 9 Sep 2020 12:44:32 +0800 (CST) From: "Chen-Yu Tsai (Moxa)" To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, JohnsonCH.Chen@moxa.com, victor.yu@moxa.com, wens@csie.org Subject: [cip-dev] [PATCH 4.4.y-cip 01/11] PM / OPP: Parse clock-latency and voltage-tolerance for v1 bindings Date: Wed, 9 Sep 2020 12:42:23 +0800 Message-Id: <20200909044233.4115-2-wens@csie.org> In-Reply-To: <20200909044233.4115-1-wens@csie.org> References: <20200909044233.4115-1-wens@csie.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: RAg5uwxxetJgvO2PkaE4op5Tx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1599626683; bh=l/+k92WlbJyNaZbhnGReewQq9CXqMjsV5o3UPVia9D8=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=fAjFnsP1/Q6EH3OYpoXW5n6ANtUHtW7GzcZ14745JaMc5hDP2HCfvh+c6Ox95pMWXLY 452pm2qpxCSniRAcGoL4jxIO85mh9t+YbLkpJI5TZIF6N1O5LUJPSGpnepqRYfUYMulG/ KSHezVcxZBSqGv7Tiben5qHyZuX+IpfJZ3w= From: Viresh Kumar V2 bindings have better support for clock-latency and voltage-tolerance and doesn't need special care. To use callbacks, like dev_pm_opp_get_max_{transition|volt}_latency(), irrespective of the bindings, the core needs to know clock-latency/voltage-tolerance for the earlier bindings. This patch reads clock-latency/voltage-tolerance from the device node, irrespective of the bindings (to keep it simple) and use them only for V1 bindings. Signed-off-by: Viresh Kumar Reviewed-by: Stephen Boyd Signed-off-by: Rafael J. Wysocki Signed-off-by: Chen-Yu Tsai (Moxa) --- This patch is needed because the OPPv2 table does not include clock-latency-ns properties, but instead uses the clock-latency property from OPPv1. --- drivers/base/power/opp/core.c | 20 ++++++++++++++++++++ drivers/base/power/opp/opp.h | 6 ++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/base/power/opp/core.c b/drivers/base/power/opp/core.c index 1e0a2ddf73323..f983d5d30fa94 100644 --- a/drivers/base/power/opp/core.c +++ b/drivers/base/power/opp/core.c @@ -505,6 +505,7 @@ static struct device_opp *_add_device_opp(struct device *dev) { struct device_opp *dev_opp; struct device_list_opp *list_dev; + struct device_node *np; /* Check for existing list for 'dev' first */ dev_opp = _find_device_opp(dev); @@ -527,6 +528,21 @@ static struct device_opp *_add_device_opp(struct device *dev) return NULL; } + /* + * Only required for backward compatibility with v1 bindings, but isn't + * harmful for other cases. And so we do it unconditionally. + */ + np = of_node_get(dev->of_node); + if (np) { + u32 val; + + if (!of_property_read_u32(np, "clock-latency", &val)) + dev_opp->clock_latency_ns_max = val; + of_property_read_u32(np, "voltage-tolerance", + &dev_opp->voltage_tolerance_v1); + of_node_put(np); + } + srcu_init_notifier_head(&dev_opp->srcu_head); INIT_LIST_HEAD(&dev_opp->opp_list); @@ -759,6 +775,7 @@ static int _opp_add_v1(struct device *dev, unsigned long freq, long u_volt, { struct device_opp *dev_opp; struct dev_pm_opp *new_opp; + unsigned long tol; int ret; /* Hold our list modification lock here */ @@ -772,7 +789,10 @@ static int _opp_add_v1(struct device *dev, unsigned long freq, long u_volt, /* populate the opp table */ new_opp->rate = freq; + tol = u_volt * dev_opp->voltage_tolerance_v1 / 100; new_opp->u_volt = u_volt; + new_opp->u_volt_min = u_volt - tol; + new_opp->u_volt_max = u_volt + tol; new_opp->available = true; new_opp->dynamic = dynamic; diff --git a/drivers/base/power/opp/opp.h b/drivers/base/power/opp/opp.h index 690638ef36ee5..7f0d7c8bfef00 100644 --- a/drivers/base/power/opp/opp.h +++ b/drivers/base/power/opp/opp.h @@ -135,6 +135,8 @@ struct device_list_opp { * @dentry: debugfs dentry pointer of the real device directory (not links). * @dentry_name: Name of the real dentry. * + * @voltage_tolerance_v1: In percentage, for v1 bindings only. + * * This is an internal data structure maintaining the link to opps attached to * a device. This structure is not meant to be shared to users as it is * meant for book keeping and private to OPP library. @@ -153,6 +155,10 @@ struct device_opp { struct device_node *np; unsigned long clock_latency_ns_max; + + /* For backward compatibility with v1 bindings */ + unsigned int voltage_tolerance_v1; + bool shared_opp; struct dev_pm_opp *suspend_opp; From patchwork Wed Sep 9 04:42:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11764853 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 47B7A112E for ; Wed, 9 Sep 2020 04:44:47 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6A90221D40 for ; Wed, 9 Sep 2020 04:44:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="i8y1K8KC" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6A90221D40 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5420+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id 7bXvYY4521763xHfBT6byiis; Tue, 08 Sep 2020 21:44:46 -0700 X-Received: from wens.tw (wens.tw [140.112.194.72]) by mx.groups.io with SMTP id smtpd.web10.6632.1599626681622662730 for ; Tue, 08 Sep 2020 21:44:42 -0700 X-Received: by wens.tw (Postfix, from userid 1000) id B94085FA80; Wed, 9 Sep 2020 12:44:32 +0800 (CST) From: "Chen-Yu Tsai (Moxa)" To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, JohnsonCH.Chen@moxa.com, victor.yu@moxa.com, wens@csie.org Subject: [cip-dev] [PATCH 4.4.y-cip 02/11] PM / OPP: Expose _of_get_opp_desc_node as dev_pm_opp API Date: Wed, 9 Sep 2020 12:42:24 +0800 Message-Id: <20200909044233.4115-3-wens@csie.org> In-Reply-To: <20200909044233.4115-1-wens@csie.org> References: <20200909044233.4115-1-wens@csie.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: rWNqTl3J1sX0kpKiIWntNiKGx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1599626686; bh=gY+frXwhrvwBdGN+3a2F7/fGFVwaQiS3b/n2wYJAlVE=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=i8y1K8KCC+8gpqBDZsf2YeeU8VteH5+GWw+H19pmcd8b6ihl0PwT1qwmXF2NxpuQw+D zOznqfzwCSQbXk7EruAaqifG2ZSfBKUoYbqju6hTbvsI1gfFn83MBywskiDkpehVgP7Hh qq8abMCifMKv+iqYm6W/4rW4FXrj9ShfE7M= From: Dave Gerlach commit 0764c604c8128f17fd740ff8b1701d0a1301eb7e upstream. Rename _of_get_opp_desc_node to dev_pm_opp_of_get_opp_desc_node and add it to include/linux/pm_opp.h to allow other drivers, such as platform OPP and cpufreq drivers, to make use of it. Acked-by: Viresh Kumar Signed-off-by: Dave Gerlach Signed-off-by: Rafael J. Wysocki [wens@csie.org: backported to pre-OF-move files] Signed-off-by: Chen-Yu Tsai (Moxa) --- drivers/base/power/opp/core.c | 5 +++-- drivers/base/power/opp/cpu.c | 4 ++-- include/linux/pm_opp.h | 6 ++++++ 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/base/power/opp/core.c b/drivers/base/power/opp/core.c index f983d5d30fa94..c41bf5f1a038d 100644 --- a/drivers/base/power/opp/core.c +++ b/drivers/base/power/opp/core.c @@ -1488,7 +1488,7 @@ unlock: EXPORT_SYMBOL_GPL(dev_pm_opp_of_remove_table); /* Returns opp descriptor node for a device, caller must do of_node_put() */ -struct device_node *_of_get_opp_desc_node(struct device *dev) +struct device_node *dev_pm_opp_of_get_opp_desc_node(struct device *dev) { /* * TODO: Support for multiple OPP tables. @@ -1499,6 +1499,7 @@ struct device_node *_of_get_opp_desc_node(struct device *dev) return of_parse_phandle(dev->of_node, "operating-points-v2", 0); } +EXPORT_SYMBOL_GPL(dev_pm_opp_of_get_opp_desc_node); /* Initializes OPP tables based on new bindings */ static int _of_add_opp_table_v2(struct device *dev, struct device_node *opp_np) @@ -1627,7 +1628,7 @@ int dev_pm_opp_of_add_table(struct device *dev) * OPPs have two version of bindings now. The older one is deprecated, * try for the new binding first. */ - opp_np = _of_get_opp_desc_node(dev); + opp_np = dev_pm_opp_of_get_opp_desc_node(dev); if (!opp_np) { /* * Try old-deprecated bindings for backward compatibility with diff --git a/drivers/base/power/opp/cpu.c b/drivers/base/power/opp/cpu.c index a0db8b3575f38..29c5b42eff346 100644 --- a/drivers/base/power/opp/cpu.c +++ b/drivers/base/power/opp/cpu.c @@ -227,7 +227,7 @@ int dev_pm_opp_of_get_sharing_cpus(struct device *cpu_dev, cpumask_var_t cpumask int cpu, ret = 0; /* Get OPP descriptor node */ - np = _of_get_opp_desc_node(cpu_dev); + np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); if (!np) { dev_dbg(cpu_dev, "%s: Couldn't find cpu_dev node.\n", __func__); return -ENOENT; @@ -252,7 +252,7 @@ int dev_pm_opp_of_get_sharing_cpus(struct device *cpu_dev, cpumask_var_t cpumask } /* Get OPP descriptor node */ - tmp_np = _of_get_opp_desc_node(tcpu_dev); + tmp_np = dev_pm_opp_of_get_opp_desc_node(tcpu_dev); if (!tmp_np) { dev_err(tcpu_dev, "%s: Couldn't find tcpu_dev node.\n", __func__); diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index 95403d2ccaf56..4a8f5b33d7023 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -160,6 +160,7 @@ int dev_pm_opp_of_cpumask_add_table(cpumask_var_t cpumask); void dev_pm_opp_of_cpumask_remove_table(cpumask_var_t cpumask); int dev_pm_opp_of_get_sharing_cpus(struct device *cpu_dev, cpumask_var_t cpumask); int dev_pm_opp_set_sharing_cpus(struct device *cpu_dev, cpumask_var_t cpumask); +struct device_node *dev_pm_opp_of_get_opp_desc_node(struct device *dev); #else static inline int dev_pm_opp_of_add_table(struct device *dev) { @@ -188,6 +189,11 @@ static inline int dev_pm_opp_set_sharing_cpus(struct device *cpu_dev, cpumask_va { return -ENOSYS; } + +static inline struct device_node *dev_pm_opp_of_get_opp_desc_node(struct device *dev) +{ + return NULL; +} #endif #endif /* __LINUX_OPP_H__ */ From patchwork Wed Sep 9 04:42:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11764855 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4E88113B1 for ; Wed, 9 Sep 2020 04:44:47 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 13DBE21D47 for ; Wed, 9 Sep 2020 04:44:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="FbRy1Hao" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 13DBE21D47 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5419+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id UXEXYY4521763x41L9kI5SgL; Tue, 08 Sep 2020 21:44:46 -0700 X-Received: from wens.tw (wens.tw [140.112.194.72]) by mx.groups.io with SMTP id smtpd.web12.6685.1599626681625135068 for ; Tue, 08 Sep 2020 21:44:42 -0700 X-Received: by wens.tw (Postfix, from userid 1000) id DBE145FCD0; Wed, 9 Sep 2020 12:44:32 +0800 (CST) From: "Chen-Yu Tsai (Moxa)" To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, JohnsonCH.Chen@moxa.com, victor.yu@moxa.com, wens@csie.org Subject: [cip-dev] [PATCH 4.4.y-cip 03/11] Documentation: dt: add bindings for ti-cpufreq Date: Wed, 9 Sep 2020 12:42:25 +0800 Message-Id: <20200909044233.4115-4-wens@csie.org> In-Reply-To: <20200909044233.4115-1-wens@csie.org> References: <20200909044233.4115-1-wens@csie.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: gMQ7BXupjjwhfCXNAKSkIFi2x4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1599626686; bh=/myZRKQhhGKsMWn85Xj2EQB8NSh7w3no1pQSED+4m4g=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=FbRy1HaojsroJhsPZwqf0gYulRIBInQ1FdCGP+7yXaE54ir9dX0cS4dLeZ38+BZRD9D E3othjTx7aCppP4MR5cJgW+g0Jm6+bSWsljgf/RtSrVOTT/HmCrMpIZ88j0fvE9Y9r6rI ed+qk/fGuSGHTAX+64W2ze/z/EIMwNgi7To= From: Dave Gerlach commit 953a0f18337406ab041252ce5a62db5d173bee5f upstream. Add the device tree bindings document for the TI CPUFreq/OPP driver on AM33xx, AM43xx, DRA7xx, and AM57xx SoCs. The operating-points-v2 binding allows us to provide an opp-supported-hw property for each OPP to define when it is available. This driver is responsible for reading and parsing registers to determine which OPPs can be selectively enabled based on the specific SoC in use by matching against the opp-supported-hw data. Acked-by: Viresh Kumar Signed-off-by: Dave Gerlach Acked-by: Rob Herring Signed-off-by: Rafael J. Wysocki Signed-off-by: Chen-Yu Tsai (Moxa) --- .../bindings/cpufreq/ti-cpufreq.txt | 128 ++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt diff --git a/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt new file mode 100644 index 0000000000000..ba0e15ad5bd9d --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt @@ -0,0 +1,128 @@ +TI CPUFreq and OPP bindings +================================ + +Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx +families support different OPPs depending on the silicon variant in use. +The ti-cpufreq driver can use revision and an efuse value from the SoC to +provide the OPP framework with supported hardware information. This is +used to determine which OPPs from the operating-points-v2 table get enabled +when it is parsed by the OPP framework. + +Required properties: +-------------------- +In 'cpus' nodes: +- operating-points-v2: Phandle to the operating-points-v2 table to use. + +In 'operating-points-v2' table: +- compatible: Should be + - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx SoCs +- syscon: A phandle pointing to a syscon node representing the control module + register space of the SoC. + +Optional properties: +-------------------- +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: Two bitfields indicating: + 1. Which revision of the SoC the OPP is supported by + 2. Which eFuse bits indicate this OPP is available + + A bitwise AND is performed against these values and if any bit + matches, the OPP gets enabled. + +Example: +-------- + +/* From arch/arm/boot/dts/am33xx.dtsi */ +cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "arm,cortex-a8"; + device_type = "cpu"; + reg = <0>; + + operating-points-v2 = <&cpu0_opp_table>; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + }; +}; + +/* + * cpu0 has different OPPs depending on SoC revision and some on revisions + * 0x2 and 0x4 have eFuse bits that indicate if they are available or not + */ +cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_conf>; + + /* + * The three following nodes are marked with opp-suspend + * because they can not be enabled simultaneously on a + * single SoC. + */ + opp50@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0x06 0x0010>; + opp-suspend; + }; + + opp100@275000000 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0x00FF>; + opp-suspend; + }; + + opp100@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0020>; + opp-suspend; + }; + + opp100@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp100@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0040>; + }; + + opp120@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp120@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x06 0x0080>; + }; + + oppturbo@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + oppturbo@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x06 0x0100>; + }; + + oppnitro@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000 1298500 1351500>; + opp-supported-hw = <0x04 0x0200>; + }; +}; From patchwork Wed Sep 9 04:42:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11764851 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C8E9112E for ; Wed, 9 Sep 2020 04:44:46 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9842521D46 for ; Wed, 9 Sep 2020 04:44:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="Nqpt8whN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9842521D46 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5421+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id 0ctxYY4521763xelGBwOSvmR; Tue, 08 Sep 2020 21:44:43 -0700 X-Received: from wens.tw (wens.tw [140.112.194.72]) by mx.groups.io with SMTP id smtpd.web12.6684.1599626681625055740 for ; Tue, 08 Sep 2020 21:44:42 -0700 X-Received: by wens.tw (Postfix, from userid 1000) id E63B75FD2B; Wed, 9 Sep 2020 12:44:32 +0800 (CST) From: "Chen-Yu Tsai (Moxa)" To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, JohnsonCH.Chen@moxa.com, victor.yu@moxa.com, wens@csie.org Subject: [cip-dev] [PATCH 4.4.y-cip 04/11] cpufreq: ti: Add cpufreq driver to determine available OPPs at runtime Date: Wed, 9 Sep 2020 12:42:26 +0800 Message-Id: <20200909044233.4115-5-wens@csie.org> In-Reply-To: <20200909044233.4115-1-wens@csie.org> References: <20200909044233.4115-1-wens@csie.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: pMBGOMMtWFt233CqECbq5A1Lx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1599626683; bh=p/bS1YA0RVwO+H3I8Jl/IAznt9SMPm9zIrbKsfrWZEg=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Nqpt8whNNMNEax9QxI8zrtvkaH/OxhfeYl3N1Px+aAwiEmZB4SsHUh0D4EgVkXkV4OF 7XRqQMBSEYHdp7FXVzuPIIVlMER5ztAM41mBfQJJvWDfYThXPjbeZ4UfocEmq9CFBZFrM 2xiCY9r+l5vZF3qYaD83t0VHZEkr5aBLFfg= From: Dave Gerlach commit e13cf046cd70894393a1085ca39da7ef751353fb upstream. Some TI SoCs, like those in the AM335x, AM437x, DRA7x, and AM57x families, have different OPPs available for the MPU depending on which specific variant of the SoC is in use. This can be determined through use of the revision and an eFuse register present in the silicon. Introduce a ti-cpufreq driver that can read the aformentioned values and provide them as version matching data to the opp framework. Through this the opp-supported-hw dt binding that is part of the operating-points-v2 table can be used to indicate availability of OPPs for each device. This driver also creates the "cpufreq-dt" platform_device after passing the version matching data to the OPP framework so that the cpufreq-dt handles the actual cpufreq implementation. Even without the necessary data to pass the version matching data the driver will still create this device to maintain backwards compatibility with operating-points v1 tables. Acked-by: Viresh Kumar Signed-off-by: Dave Gerlach Signed-off-by: Rafael J. Wysocki Signed-off-by: Chen-Yu Tsai (Moxa) --- drivers/cpufreq/Kconfig.arm | 11 ++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/ti-cpufreq.c | 272 +++++++++++++++++++++++++++++++++++ 3 files changed, 284 insertions(+) create mode 100644 drivers/cpufreq/ti-cpufreq.c diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index eed1e073d96d7..6b834112d857b 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -231,6 +231,17 @@ config ARM_TEGRA124_CPUFREQ help This adds the CPUFreq driver support for Tegra124 SOCs. +config ARM_TI_CPUFREQ + bool "Texas Instruments CPUFreq support" + depends on ARCH_OMAP2PLUS + help + This driver enables valid OPPs on the running platform based on + values contained within the SoC in use. Enable this in order to + use the cpufreq-dt driver on all Texas Instruments platforms that + provide dt based operating-points-v2 tables with opp-supported-hw + data provided. Required for cpufreq support on AM335x, AM437x, + DRA7x, and AM57x platforms. + config ARM_PXA2xx_CPUFREQ tristate "Intel PXA2xx CPUfreq driver" depends on PXA27x || PXA25x diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index c0af1a1281c89..6e889596d9a12 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -75,6 +75,7 @@ obj-$(CONFIG_ARM_SCPI_CPUFREQ) += scpi-cpufreq.o obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o +obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-cpufreq.o obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c new file mode 100644 index 0000000000000..7ff7ae3c3911c --- /dev/null +++ b/drivers/cpufreq/ti-cpufreq.c @@ -0,0 +1,272 @@ +/* + * TI CPUFreq/OPP hw-supported driver + * + * Copyright (C) 2016-2017 Texas Instruments, Inc. + * Dave Gerlach + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define REVISION_MASK 0xF +#define REVISION_SHIFT 28 + +#define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F +#define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA + +#define DRA7_EFUSE_HAS_OD_MPU_OPP 11 +#define DRA7_EFUSE_HAS_HIGH_MPU_OPP 15 +#define DRA7_EFUSE_HAS_ALL_MPU_OPP 23 + +#define DRA7_EFUSE_NOM_MPU_OPP BIT(0) +#define DRA7_EFUSE_OD_MPU_OPP BIT(1) +#define DRA7_EFUSE_HIGH_MPU_OPP BIT(2) + +#define VERSION_COUNT 2 + +struct ti_cpufreq_data; + +struct ti_cpufreq_soc_data { + unsigned long (*efuse_xlate)(struct ti_cpufreq_data *opp_data, + unsigned long efuse); + unsigned long efuse_fallback; + unsigned long efuse_offset; + unsigned long efuse_mask; + unsigned long efuse_shift; + unsigned long rev_offset; +}; + +struct ti_cpufreq_data { + struct device *cpu_dev; + struct device_node *opp_node; + struct regmap *syscon; + const struct ti_cpufreq_soc_data *soc_data; +}; + +static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data, + unsigned long efuse) +{ + if (!efuse) + efuse = opp_data->soc_data->efuse_fallback; + /* AM335x and AM437x use "OPP disable" bits, so invert */ + return ~efuse; +} + +static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data, + unsigned long efuse) +{ + unsigned long calculated_efuse = DRA7_EFUSE_NOM_MPU_OPP; + + /* + * The efuse on dra7 and am57 parts contains a specific + * value indicating the highest available OPP. + */ + + switch (efuse) { + case DRA7_EFUSE_HAS_ALL_MPU_OPP: + case DRA7_EFUSE_HAS_HIGH_MPU_OPP: + calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP; + case DRA7_EFUSE_HAS_OD_MPU_OPP: + calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP; + } + + return calculated_efuse; +} + +static struct ti_cpufreq_soc_data am3x_soc_data = { + .efuse_xlate = amx3_efuse_xlate, + .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ, + .efuse_offset = 0x07fc, + .efuse_mask = 0x1fff, + .rev_offset = 0x600, +}; + +static struct ti_cpufreq_soc_data am4x_soc_data = { + .efuse_xlate = amx3_efuse_xlate, + .efuse_fallback = AM43XX_600M_ARM_MPU_MAX_FREQ, + .efuse_offset = 0x0610, + .efuse_mask = 0x3f, + .rev_offset = 0x600, +}; + +static struct ti_cpufreq_soc_data dra7_soc_data = { + .efuse_xlate = dra7_efuse_xlate, + .efuse_offset = 0x020c, + .efuse_mask = 0xf80000, + .efuse_shift = 19, + .rev_offset = 0x204, +}; + +/** + * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC + * @opp_data: pointer to ti_cpufreq_data context + * @efuse_value: Set to the value parsed from efuse + * + * Returns error code if efuse not read properly. + */ +static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data, + u32 *efuse_value) +{ + struct device *dev = opp_data->cpu_dev; + u32 efuse; + int ret; + + ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, + &efuse); + if (ret) { + dev_err(dev, + "Failed to read the efuse value from syscon: %d\n", + ret); + return ret; + } + + efuse = (efuse & opp_data->soc_data->efuse_mask); + efuse >>= opp_data->soc_data->efuse_shift; + + *efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse); + + return 0; +} + +/** + * ti_cpufreq_get_rev() - Parse and return rev value present on SoC + * @opp_data: pointer to ti_cpufreq_data context + * @revision_value: Set to the value parsed from revision register + * + * Returns error code if revision not read properly. + */ +static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data, + u32 *revision_value) +{ + struct device *dev = opp_data->cpu_dev; + u32 revision; + int ret; + + ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset, + &revision); + if (ret) { + dev_err(dev, + "Failed to read the revision number from syscon: %d\n", + ret); + return ret; + } + + *revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK); + + return 0; +} + +static int ti_cpufreq_setup_syscon_register(struct ti_cpufreq_data *opp_data) +{ + struct device *dev = opp_data->cpu_dev; + struct device_node *np = opp_data->opp_node; + + opp_data->syscon = syscon_regmap_lookup_by_phandle(np, + "syscon"); + if (IS_ERR(opp_data->syscon)) { + dev_err(dev, + "\"syscon\" is missing, cannot use OPPv2 table.\n"); + return PTR_ERR(opp_data->syscon); + } + + return 0; +} + +static const struct of_device_id ti_cpufreq_of_match[] = { + { .compatible = "ti,am33xx", .data = &am3x_soc_data, }, + { .compatible = "ti,am4372", .data = &am4x_soc_data, }, + { .compatible = "ti,dra7", .data = &dra7_soc_data }, + {}, +}; + +static int ti_cpufreq_init(void) +{ + u32 version[VERSION_COUNT]; + struct device_node *np; + const struct of_device_id *match; + struct ti_cpufreq_data *opp_data; + int ret; + + np = of_find_node_by_path("/"); + match = of_match_node(ti_cpufreq_of_match, np); + if (!match) + return -ENODEV; + + opp_data = kzalloc(sizeof(*opp_data), GFP_KERNEL); + if (!opp_data) + return -ENOMEM; + + opp_data->soc_data = match->data; + + opp_data->cpu_dev = get_cpu_device(0); + if (!opp_data->cpu_dev) { + pr_err("%s: Failed to get device for CPU0\n", __func__); + return -ENODEV; + } + + opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev); + if (!opp_data->opp_node) { + dev_info(opp_data->cpu_dev, + "OPP-v2 not supported, cpufreq-dt will attempt to use legacy tables.\n"); + goto register_cpufreq_dt; + } + + ret = ti_cpufreq_setup_syscon_register(opp_data); + if (ret) + goto fail_put_node; + + /* + * OPPs determine whether or not they are supported based on + * two metrics: + * 0 - SoC Revision + * 1 - eFuse value + */ + ret = ti_cpufreq_get_rev(opp_data, &version[0]); + if (ret) + goto fail_put_node; + + ret = ti_cpufreq_get_efuse(opp_data, &version[1]); + if (ret) + goto fail_put_node; + + of_node_put(opp_data->opp_node); + + ret = PTR_ERR_OR_ZERO(dev_pm_opp_set_supported_hw(opp_data->cpu_dev, + version, VERSION_COUNT)); + if (ret) { + dev_err(opp_data->cpu_dev, + "Failed to set supported hardware\n"); + goto fail_put_node; + } + +register_cpufreq_dt: + platform_device_register_simple("cpufreq-dt", -1, NULL, 0); + + return 0; + +fail_put_node: + of_node_put(opp_data->opp_node); + + return ret; +} +module_init(ti_cpufreq_init); + +MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver"); +MODULE_AUTHOR("Dave Gerlach "); +MODULE_LICENSE("GPL v2"); From patchwork Wed Sep 9 04:42:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11764865 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7795613B1 for ; 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Wed, 9 Sep 2020 12:44:32 +0800 (CST) From: "Chen-Yu Tsai (Moxa)" To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, JohnsonCH.Chen@moxa.com, victor.yu@moxa.com, wens@csie.org Subject: [cip-dev] [PATCH 4.4.y-cip 05/11] cpufreq: ti: Fix 'of_node_put' being called twice in error handling path Date: Wed, 9 Sep 2020 12:42:27 +0800 Message-Id: <20200909044233.4115-6-wens@csie.org> In-Reply-To: <20200909044233.4115-1-wens@csie.org> References: <20200909044233.4115-1-wens@csie.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: KVeCvGF0su6RdLQlLCZQ1rZVx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1599626688; bh=Cb6gezkkgO7V+HrfaxkDctH3hJm6PNtVqGKrCf22z1o=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=JCF02axc/+gPbQB/Go2BwwUsa4lKQq98FnHnlfaMtz+gp8Zn7ob6aMLIDdrlCEZzGt2 R0X0RpDVBSXukZKyHyEXiBE0QnxG3AJY5ZRXYZQkPtfIeLuxzBib1GTQ+Z9WMyVxxltAt Ma8D1lCDptPmg00Ivm20RrCYz09B6ikCMoI= From: Christophe Jaillet commit 9a6e91d08e7707baa2f824257342ca7efcb199bc upstream. If 'dev_pm_opp_set_supported_hw()' fails, 'opp_data->opp_node' refcount will be decremented 2 times. One, just a few lines above, and another one in the error handling path. Fix it by simply moving the 'of_node_put' call of the normal path. Signed-off-by: Christophe JAILLET Acked-by: Viresh Kumar Signed-off-by: Rafael J. Wysocki Signed-off-by: Chen-Yu Tsai (Moxa) --- drivers/cpufreq/ti-cpufreq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index 7ff7ae3c3911c..1c63e96cba1f2 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -245,8 +245,6 @@ static int ti_cpufreq_init(void) if (ret) goto fail_put_node; - of_node_put(opp_data->opp_node); - ret = PTR_ERR_OR_ZERO(dev_pm_opp_set_supported_hw(opp_data->cpu_dev, version, VERSION_COUNT)); if (ret) { @@ -255,6 +253,8 @@ static int ti_cpufreq_init(void) goto fail_put_node; } + of_node_put(opp_data->opp_node); + register_cpufreq_dt: platform_device_register_simple("cpufreq-dt", -1, NULL, 0); From patchwork Wed Sep 9 04:42:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11764869 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D6ECC112E for ; Wed, 9 Sep 2020 04:44:48 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A90FD21D43 for ; Wed, 9 Sep 2020 04:44:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="UiVidrqv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A90FD21D43 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5430+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id NMzAYY4521763xEtL34lHfzh; Tue, 08 Sep 2020 21:44:48 -0700 X-Received: from wens.tw (wens.tw [140.112.194.72]) by mx.groups.io with SMTP id smtpd.web11.6578.1599626683840206784 for ; Tue, 08 Sep 2020 21:44:44 -0700 X-Received: by wens.tw (Postfix, from userid 1000) id 0201B5FDD7; Wed, 9 Sep 2020 12:44:32 +0800 (CST) From: "Chen-Yu Tsai (Moxa)" To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, JohnsonCH.Chen@moxa.com, victor.yu@moxa.com, wens@csie.org Subject: [cip-dev] [PATCH 4.4.y-cip 06/11] cpufreq: ti-cpufreq: kfree opp_data when failure Date: Wed, 9 Sep 2020 12:42:28 +0800 Message-Id: <20200909044233.4115-7-wens@csie.org> In-Reply-To: <20200909044233.4115-1-wens@csie.org> References: <20200909044233.4115-1-wens@csie.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: S4BK8CzOjY6US34jv9eSgS2ux4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1599626688; bh=IaNbhZeuLabP+6E5pL6K8ZmxZfbK4H2VBzuvU19oits=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=UiVidrqv+2hRwwT8kMz+D7a+MlImIWfspnx5vfLq21NPESVrN14KzueuQHYLm74SI2n ZS4CACaDin5VzJkBhXjQbyjMZnCU95mRCNanLRGHkU8gEYVQTwNikn5isAvEF4ymXvpty pGk+M6SpsFf6NdfYnSa/Lb1MUudFe4HnHkc= From: Zumeng Chen commit 05829d9431df1bf6de98679fbcfbad282c1c55a4 upstream. memory leakage was found by kmemleak. opp_data needs to be freed when failure, including fail_put_node. unreferenced object 0xccdd4c40 (size 64): comm "swapper", pid 1, jiffies 4294938465 (age 888.520s) hex dump (first 32 bytes): 00 7c 00 c1 98 69 d8 ce 00 24 03 ce 00 24 03 ce .|...i...$...$.. 20 35 23 c1 00 00 00 00 00 00 00 00 00 00 00 00 5#............. backtrace: [] kmem_cache_alloc_trace+0x2c4/0x3cc [] ti_cpufreq_probe+0x6c/0x334 [] platform_drv_probe+0x60/0xc0 [] driver_probe_device+0x218/0x2c4 [] __device_attach_driver+0xa8/0xdc [] bus_for_each_drv+0x70/0xa4 [] __device_attach+0xc0/0x124 [] device_initial_probe+0x1c/0x20 [] bus_probe_device+0x94/0x9c [] device_add+0x404/0x590 [] platform_device_add+0x11c/0x230 [] platform_device_register_full+0x10c/0x128 [] ti_cpufreq_init+0x44/0x50 [] do_one_initcall+0x54/0x180 [] kernel_init_freeable+0x270/0x33c [] kernel_init+0x18/0x124 Signed-off-by: Zumeng Chen Acked-by: Viresh Kumar Signed-off-by: Rafael J. Wysocki Signed-off-by: Chen-Yu Tsai (Moxa) --- drivers/cpufreq/ti-cpufreq.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index 1c63e96cba1f2..36627b2b256f8 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -217,7 +217,8 @@ static int ti_cpufreq_init(void) opp_data->cpu_dev = get_cpu_device(0); if (!opp_data->cpu_dev) { pr_err("%s: Failed to get device for CPU0\n", __func__); - return -ENODEV; + ret = ENODEV; + goto free_opp_data; } opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev); @@ -262,6 +263,8 @@ register_cpufreq_dt: fail_put_node: of_node_put(opp_data->opp_node); +free_opp_data: + kfree(opp_data); return ret; } From patchwork Wed Sep 9 04:42:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11764857 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AD4FD138E for ; Wed, 9 Sep 2020 04:44:47 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7BCFF21D46 for ; Wed, 9 Sep 2020 04:44:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="cwbBCH5b" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7BCFF21D46 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5424+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id HcetYY4521763xwoQLlYw01z; Tue, 08 Sep 2020 21:44:47 -0700 X-Received: from wens.tw (wens.tw [140.112.194.72]) by mx.groups.io with SMTP id smtpd.web10.6633.1599626683531375698 for ; Tue, 08 Sep 2020 21:44:43 -0700 X-Received: by wens.tw (Postfix, from userid 1000) id 0ACC560161; Wed, 9 Sep 2020 12:44:33 +0800 (CST) From: "Chen-Yu Tsai (Moxa)" To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, JohnsonCH.Chen@moxa.com, victor.yu@moxa.com, wens@csie.org Subject: [cip-dev] [PATCH 4.4.y-cip 07/11] cpufreq: ti-cpufreq: add missing of_node_put() Date: Wed, 9 Sep 2020 12:42:29 +0800 Message-Id: <20200909044233.4115-8-wens@csie.org> In-Reply-To: <20200909044233.4115-1-wens@csie.org> References: <20200909044233.4115-1-wens@csie.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: 3kOEjIz1dfByGi7zFP7CzyWmx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1599626687; bh=rtqkzAsg9ZvPmnMNeeT49PqLFmDndByAZEgn4reRhwM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=cwbBCH5bcZib27IwgMtEnFeHuLLmm+9DynC/1WsniWGlXywAQjNs84xPbD+FoRpTiQy f0wwonBkF1IkYErL9vzGGzyhTahEyvfccd+aTSpIsYiUMqwzUw3oaJAt1Da8C4MAOUwuy CJ3SUkR2tRS+ZhcgR92Bith13A65a1qKNk4= From: Zumeng Chen commit 248aefdcc3a7e0cfbd014946b4dead63e750e71b upstream. call of_node_put to release the refcount of np. Signed-off-by: Zumeng Chen Acked-by: Viresh Kumar Signed-off-by: Rafael J. Wysocki Signed-off-by: Chen-Yu Tsai (Moxa) --- drivers/cpufreq/ti-cpufreq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index 36627b2b256f8..afbe9db29992d 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -205,6 +205,7 @@ static int ti_cpufreq_init(void) np = of_find_node_by_path("/"); match = of_match_node(ti_cpufreq_of_match, np); + of_node_put(np); if (!match) return -ENODEV; From patchwork Wed Sep 9 04:42:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11764867 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7AF741709 for ; Wed, 9 Sep 2020 04:44:48 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4C0BB21D43 for ; Wed, 9 Sep 2020 04:44:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="xZW4iJNM" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4C0BB21D43 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5426+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id By99YY4521763xaypRGA2lSL; Tue, 08 Sep 2020 21:44:48 -0700 X-Received: from wens.tw (wens.tw [140.112.194.72]) by mx.groups.io with SMTP id smtpd.web12.6688.1599626683683137977 for ; Tue, 08 Sep 2020 21:44:44 -0700 X-Received: by wens.tw (Postfix, from userid 1000) id 103C760193; Wed, 9 Sep 2020 12:44:33 +0800 (CST) From: "Chen-Yu Tsai (Moxa)" To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, JohnsonCH.Chen@moxa.com, victor.yu@moxa.com, wens@csie.org Subject: [cip-dev] [PATCH 4.4.y-cip 08/11] cpufreq: ti-cpufreq: Fix an incorrect error return value Date: Wed, 9 Sep 2020 12:42:30 +0800 Message-Id: <20200909044233.4115-9-wens@csie.org> In-Reply-To: <20200909044233.4115-1-wens@csie.org> References: <20200909044233.4115-1-wens@csie.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: 1MPxpp39j9iPLY0jLWsSM762x4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1599626688; bh=LjOilCexA+B55n/YFVHg9hjs4pQwPyXRRb6wQYKBz7c=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=xZW4iJNMfnMo/Ihjqdv/FU7yXrDowMWICjMKmwLKBgZfCIXvLTv2e25/gvcxmD+VwO8 ppONWMnI2U9w+TxL9kSWpfxYNcjJXqlK/P7jG+GSb7mJaZ7BpbWXI+Oj5vyxUUvUu8pPB fNMCSGzO5XyIF64MiODSByjAdYk8zmx3+IM= From: Suman Anna commit e5d295b06d69a1924665a16a4987be475addd00f upstream. Commit 05829d9431df ("cpufreq: ti-cpufreq: kfree opp_data when failure") has fixed a memory leak in the failure path, however the patch returned a positive value on get_cpu_device() failure instead of the previous negative value. Fix this incorrect error return value properly. Fixes: 05829d9431df ("cpufreq: ti-cpufreq: kfree opp_data when failure") Cc: 4.14+ # v4.14+ Signed-off-by: Suman Anna Acked-by: Viresh Kumar Signed-off-by: Rafael J. Wysocki [wens@csie.org: Fix commit reference format in commit log] Signed-off-by: Chen-Yu Tsai (Moxa) --- drivers/cpufreq/ti-cpufreq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index afbe9db29992d..59777685114d9 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -218,7 +218,7 @@ static int ti_cpufreq_init(void) opp_data->cpu_dev = get_cpu_device(0); if (!opp_data->cpu_dev) { pr_err("%s: Failed to get device for CPU0\n", __func__); - ret = ENODEV; + ret = -ENODEV; goto free_opp_data; } From patchwork Wed Sep 9 04:42:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11764863 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 210C515AB for ; Wed, 9 Sep 2020 04:44:48 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E90E221D47 for ; Wed, 9 Sep 2020 04:44:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="ilftdNAx" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E90E221D47 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5428+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id 0zgVYY4521763xgNKS69xW82; Tue, 08 Sep 2020 21:44:47 -0700 X-Received: from wens.tw (wens.tw [140.112.194.72]) by mx.groups.io with SMTP id smtpd.web11.6576.1599626683742757130 for ; Tue, 08 Sep 2020 21:44:44 -0700 X-Received: by wens.tw (Postfix, from userid 1000) id 18CAA601BD; Wed, 9 Sep 2020 12:44:33 +0800 (CST) From: "Chen-Yu Tsai (Moxa)" To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, JohnsonCH.Chen@moxa.com, victor.yu@moxa.com, wens@csie.org Subject: [cip-dev] [PATCH 4.4.y-cip 09/11] cpufreq: dt: Don't use generic platdev driver for ti-cpufreq platforms Date: Wed, 9 Sep 2020 12:42:31 +0800 Message-Id: <20200909044233.4115-10-wens@csie.org> In-Reply-To: <20200909044233.4115-1-wens@csie.org> References: <20200909044233.4115-1-wens@csie.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: ozbFve1tA6eK7Eq8gDW3Ifb8x4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1599626687; bh=v+Rn5Eq28V6vtwisKa+6zJ4u158SowSIwJOaFOXt+xc=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=ilftdNAxpLjBwnvGqxdl69RuFcoexvf6aodk19Y0q46mfrPLI0D0E61eGAW4pt1JDbA ZpjhGCQH0+QqsXGdmM9B3wE8PPUji3I9jn1bLSI4AdkE9ImIH+ZVSOZK3LuFgpeG2tCEc 7VLfR0K0O3/jMvxvT0ftL2c9/4LJY/RizUo= From: Dave Gerlach commit 051bd84bb45bc994b7d762467f60b3bd0c7aa6bc upstream. Some TI platforms, specifically those in the am33xx, am43xx, dra7xx, and am57xx families of SoCs can make use of the ti-cpufreq driver to selectively enable OPPs based on the exact configuration in use. The ti-cpufreq is given the responsibility of creating the cpufreq-dt platform device when the driver is in use so drop am33xx and dra7xx from the cpufreq-dt-platdev driver so it is not created twice. Acked-by: Viresh Kumar Signed-off-by: Dave Gerlach Signed-off-by: Rafael J. Wysocki [wens@csie.org: Backport to pre generic platdev driver] Signed-off-by: Chen-Yu Tsai (Moxa) --- I kept the original patch subject to make it easier for scripts to match against upstream patches. --- arch/arm/mach-omap2/pm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 3d876bde8c859..88cb34c608ab8 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -281,6 +281,9 @@ static inline void omap_init_cpufreq(void) if (!of_have_populated_dt()) devinfo.name = "omap-cpufreq"; + else if (of_machine_is_compatible("ti,am33xx") || + of_machine_is_compatible("ti,dra7")) + return; else devinfo.name = "cpufreq-dt"; platform_device_register_full(&devinfo); From patchwork Wed Sep 9 04:42:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11764871 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DC89F15AB for ; Wed, 9 Sep 2020 04:44:48 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A3FF921D40 for ; Wed, 9 Sep 2020 04:44:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="b2+ztwEO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A3FF921D40 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5429+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id lww1YY4521763xNJ5jI46xY8; Tue, 08 Sep 2020 21:44:48 -0700 X-Received: from wens.tw (wens.tw [140.112.194.72]) by mx.groups.io with SMTP id smtpd.web11.6577.1599626683757804090 for ; Tue, 08 Sep 2020 21:44:44 -0700 X-Received: by wens.tw (Postfix, from userid 1000) id 24AB5601E8; Wed, 9 Sep 2020 12:44:33 +0800 (CST) From: "Chen-Yu Tsai (Moxa)" To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, JohnsonCH.Chen@moxa.com, victor.yu@moxa.com, wens@csie.org Subject: [cip-dev] [PATCH 4.4.y-cip 10/11] ARM: omap2plus_defconfig: Enable support for ti-cpufreq Date: Wed, 9 Sep 2020 12:42:32 +0800 Message-Id: <20200909044233.4115-11-wens@csie.org> In-Reply-To: <20200909044233.4115-1-wens@csie.org> References: <20200909044233.4115-1-wens@csie.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: hKRUC5y3YWHXrlNqfby7JXbCx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1599626688; bh=4NypLmMB4N8+Mh361JsMRXka65zvPqlQzJJ9ODG+Jk0=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=b2+ztwEOqds3vMf7CeUSsNC22ypv5Fj6BAt7wDUATo84G47qRzPqFDoBtFkldrWhJj1 9SivtApZTdsKCooEybCqqGHyzMHKHNrFBZSC/7Xwofcp9Ju6rW5vX+eTC16u2j4kwzuHf v/4B4IyDxCnAzt2WBrVO8NKmpg31nDjEWlE= From: Dave Gerlach commit 69c8ab148006a2ec7ac1a1f08945e95febc1c132 upstream. AM335x, AM437x, DRA7xx, and AM57xx platforms all now depend on ti-cpufreq driver to enable proper OPPs for use with cpufreq, so enable the same. Signed-off-by: Dave Gerlach Reviewed-by: Lukasz Majewski Signed-off-by: Tony Lindgren Signed-off-by: Chen-Yu Tsai (Moxa) --- arch/arm/configs/omap2plus_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 09ebd37e01e02..c6eec207dcbd8 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -69,6 +69,7 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPUFREQ_DT=y +CONFIG_ARM_TI_CPUFREQ=y # CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set CONFIG_CPU_IDLE=y CONFIG_BINFMT_MISC=y From patchwork Wed Sep 9 04:42:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11764861 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1E65C112E for ; Wed, 9 Sep 2020 04:44:48 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D92C021D46 for ; Wed, 9 Sep 2020 04:44:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="mGWrunUI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D92C021D46 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+5425+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id zgQHYY4521763xyUcG0f7QMu; Tue, 08 Sep 2020 21:44:47 -0700 X-Received: from wens.tw (wens.tw [140.112.194.72]) by mx.groups.io with SMTP id smtpd.web12.6687.1599626683570857026 for ; Tue, 08 Sep 2020 21:44:43 -0700 X-Received: by wens.tw (Postfix, from userid 1000) id 336AF5FEF3; Wed, 9 Sep 2020 12:44:33 +0800 (CST) From: "Chen-Yu Tsai (Moxa)" To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, JohnsonCH.Chen@moxa.com, victor.yu@moxa.com, wens@csie.org Subject: [cip-dev] [PATCH 4.4.y-cip 11/11] ARM: dts: am33xx: Add updated operating-points-v2 table for cpu Date: Wed, 9 Sep 2020 12:42:33 +0800 Message-Id: <20200909044233.4115-12-wens@csie.org> In-Reply-To: <20200909044233.4115-1-wens@csie.org> References: <20200909044233.4115-1-wens@csie.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: 9ivtWBP70TEDiMDcve5N5r8Zx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1599626687; bh=rvrzrAf9jqksUmKXPCbPoNYYCCPb3KsPrhvfG46RkgY=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=mGWrunUINOLqERGq/85MpN/cduCOyzGlWq/Q2VMW0/PfaN1S678kTxCyMZZXKok5hEn e+k9JPKiH1oofdTSxEUmJM+sFd4ECX5/mZDLv2fJ3uudxFtt+PWWk4Bmb+8KeTd5ETtY2 jXv+cH2N1kn0HYS6kHBMYlJkOvy4nTQAXbM= From: Dave Gerlach commit 72ac40fcb164a3d8fbd1ff13647abe67df26ced5 upstream. After the ti-cpufreq driver has been added, we can now drop the operating-points table present in am33xx.dtsi for the cpu and add an operating-points-v2 table with all OPPs available for all silicon revisions. Also add necessary data for use by ti-cpufreq to selectively enable the appropriate OPPs at runtime as part of the operating-points table. Information from AM335x Data Manual, SPRS717i, Revised December 2015, Table 5-7. Signed-off-by: Dave Gerlach Reviewed-by: Lukasz Majewski Acked-by: Viresh Kumar Signed-off-by: Tony Lindgren Signed-off-by: Chen-Yu Tsai (Moxa) --- arch/arm/boot/dts/am33xx.dtsi | 87 +++++++++++++++++++++++++++++------ 1 file changed, 74 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 4b40e6d401a03..c256718d75801 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -45,19 +45,7 @@ device_type = "cpu"; reg = <0>; - /* - * To consider voltage drop between PMIC and SoC, - * tolerance value is reduced to 2% from 4% and - * voltage value is increased as a precaution. - */ - operating-points = < - /* kHz uV */ - 720000 1285000 - 600000 1225000 - 500000 1125000 - 275000 1125000 - >; - voltage-tolerance = <2>; /* 2 percentage */ + operating-points-v2 = <&cpu0_opp_table>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -66,6 +54,79 @@ }; }; + cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_conf>; + + /* + * The three following nodes are marked with opp-suspend + * because the can not be enabled simultaneously on a + * single SoC. + */ + opp50@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0x06 0x0010>; + opp-suspend; + }; + + opp100@275000000 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0x00FF>; + opp-suspend; + }; + + opp100@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0020>; + opp-suspend; + }; + + opp100@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp100@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0040>; + }; + + opp120@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp120@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x06 0x0080>; + }; + + oppturbo@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + oppturbo@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x06 0x0100>; + }; + + oppnitro@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000 1298500 1351500>; + opp-supported-hw = <0x04 0x0200>; + }; + }; + pmu { compatible = "arm,cortex-a8-pmu"; interrupts = <3>;