From patchwork Thu Sep 10 02:22:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krish Sadhukhan X-Patchwork-Id: 11766383 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 723A1746 for ; Thu, 10 Sep 2020 02:24:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 52C5B21D7E for ; Thu, 10 Sep 2020 02:24:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=oracle.com header.i=@oracle.com header.b="oGy20AHZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730878AbgIJCYr (ORCPT ); Wed, 9 Sep 2020 22:24:47 -0400 Received: from userp2120.oracle.com ([156.151.31.85]:34574 "EHLO userp2120.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730794AbgIJCWg (ORCPT ); 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Thu, 10 Sep 2020 02:22:30 GMT Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by aserp3020.oracle.com with ESMTP id 33cmk88wee-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 10 Sep 2020 02:22:30 +0000 Received: from abhmp0013.oracle.com (abhmp0013.oracle.com [141.146.116.19]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id 08A2MTDe012667; Thu, 10 Sep 2020 02:22:29 GMT Received: from nsvm-sadhukhan-1.osdevelopmeniad.oraclevcn.com (/100.100.230.216) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Wed, 09 Sep 2020 19:22:29 -0700 From: Krish Sadhukhan To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, jmattson@google.com, thomas.lendacky@amd.com Subject: [PATCH 1/3 v2] KVM: SVM: Replace numeric value for SME CPUID leaf with a #define Date: Thu, 10 Sep 2020 02:22:09 +0000 Message-Id: <20200910022211.5417-2-krish.sadhukhan@oracle.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200910022211.5417-1-krish.sadhukhan@oracle.com> References: <20200910022211.5417-1-krish.sadhukhan@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9739 signatures=668679 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 malwarescore=0 phishscore=0 mlxlogscore=936 bulkscore=0 adultscore=0 mlxscore=0 suspectscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009100020 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9739 signatures=668679 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=951 suspectscore=1 adultscore=0 mlxscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009100020 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Krish Sadhukhan --- arch/x86/boot/compressed/mem_encrypt.S | 5 +++-- arch/x86/include/asm/cpufeatures.h | 5 +++++ arch/x86/kernel/cpu/amd.c | 2 +- arch/x86/kernel/cpu/scattered.c | 4 ++-- arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/svm/svm.c | 4 ++-- arch/x86/mm/mem_encrypt_identity.c | 4 ++-- 7 files changed, 16 insertions(+), 10 deletions(-) diff --git a/arch/x86/boot/compressed/mem_encrypt.S b/arch/x86/boot/compressed/mem_encrypt.S index dd07e7b41b11..22e30b0c0d19 100644 --- a/arch/x86/boot/compressed/mem_encrypt.S +++ b/arch/x86/boot/compressed/mem_encrypt.S @@ -12,6 +12,7 @@ #include #include #include +#include .text .code32 @@ -31,7 +32,7 @@ SYM_FUNC_START(get_sev_encryption_bit) movl $0x80000000, %eax /* CPUID to check the highest leaf */ cpuid - cmpl $0x8000001f, %eax /* See if 0x8000001f is available */ + cmpl $CPUID_AMD_SME, %eax /* See if 0x8000001f is available */ jb .Lno_sev /* @@ -40,7 +41,7 @@ SYM_FUNC_START(get_sev_encryption_bit) * CPUID Fn8000_001F[EBX] - Bits 5:0 * Pagetable bit position used to indicate encryption */ - movl $0x8000001f, %eax + movl $CPUID_AMD_SME, %eax cpuid bt $1, %eax /* Check if SEV is available */ jnc .Lno_sev diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 2901d5df4366..81335e6fe47d 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -10,6 +10,11 @@ #include #endif +/* + * AMD CPUID functions + */ +#define CPUID_AMD_SME 0x8000001f /* Secure Memory Encryption */ + /* * Defines x86 CPU feature bits */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index dcc3d943c68f..4507ededb978 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -630,7 +630,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) * will be a value above 32-bits this is still done for * CONFIG_X86_32 so that accurate values are reported. */ - c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; + c->x86_phys_bits -= (cpuid_ebx(CPUID_AMD_SME) >> 6) & 0x3f; if (IS_ENABLED(CONFIG_X86_32)) goto clear_all; diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 62b137c3c97a..033c112e03fc 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -39,8 +39,8 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, - { X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 }, - { X86_FEATURE_SEV, CPUID_EAX, 1, 0x8000001f, 0 }, + { X86_FEATURE_SME, CPUID_EAX, 0, CPUID_AMD_SME, 0 }, + { X86_FEATURE_SEV, CPUID_EAX, 1, CPUID_AMD_SME, 0 }, { 0, 0, 0, 0, 0 } }; diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 3fd6eec202d7..95863e767d3d 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -756,7 +756,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) entry->edx = 0; break; case 0x80000000: - entry->eax = min(entry->eax, 0x8000001f); + entry->eax = min(entry->eax, CPUID_AMD_SME); break; case 0x80000001: cpuid_entry_override(entry, CPUID_8000_0001_EDX); diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 0194336b64a4..a4e92ae399b4 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -749,7 +749,7 @@ static __init void svm_adjust_mmio_mask(void) u64 msr, mask; /* If there is no memory encryption support, use existing mask */ - if (cpuid_eax(0x80000000) < 0x8000001f) + if (cpuid_eax(0x80000000) < CPUID_AMD_SME) return; /* If memory encryption is not enabled, use existing mask */ @@ -757,7 +757,7 @@ static __init void svm_adjust_mmio_mask(void) if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) return; - enc_bit = cpuid_ebx(0x8000001f) & 0x3f; + enc_bit = cpuid_ebx(CPUID_AMD_SME) & 0x3f; mask_bit = boot_cpu_data.x86_phys_bits; /* Increment the mask bit if it is the same as the encryption bit */ diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_identity.c index e2b0e2ac07bb..cbe600dd357b 100644 --- a/arch/x86/mm/mem_encrypt_identity.c +++ b/arch/x86/mm/mem_encrypt_identity.c @@ -498,7 +498,7 @@ void __init sme_enable(struct boot_params *bp) eax = 0x80000000; ecx = 0; native_cpuid(&eax, &ebx, &ecx, &edx); - if (eax < 0x8000001f) + if (eax < CPUID_AMD_SME) return; #define AMD_SME_BIT BIT(0) @@ -520,7 +520,7 @@ void __init sme_enable(struct boot_params *bp) * CPUID Fn8000_001F[EBX] * - Bits 5:0 - Pagetable bit position used to indicate encryption */ - eax = 0x8000001f; + eax = CPUID_AMD_SME; ecx = 0; native_cpuid(&eax, &ebx, &ecx, &edx); if (!(eax & feature_mask)) From patchwork Thu Sep 10 02:22:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krish Sadhukhan X-Patchwork-Id: 11766405 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9E66E746 for ; Thu, 10 Sep 2020 02:35:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8325821D7E for ; Thu, 10 Sep 2020 02:35:29 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Thu, 10 Sep 2020 02:22:31 +0000 Received: from pps.filterd (aserp3020.oracle.com [127.0.0.1]) by aserp3020.oracle.com (8.16.0.42/8.16.0.42) with SMTP id 08A2L6Sj022985; Thu, 10 Sep 2020 02:22:30 GMT Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by aserp3020.oracle.com with ESMTP id 33cmk88weu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 10 Sep 2020 02:22:30 +0000 Received: from abhmp0013.oracle.com (abhmp0013.oracle.com [141.146.116.19]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id 08A2MUf2012670; Thu, 10 Sep 2020 02:22:30 GMT Received: from nsvm-sadhukhan-1.osdevelopmeniad.oraclevcn.com (/100.100.230.216) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Wed, 09 Sep 2020 19:22:29 -0700 From: Krish Sadhukhan To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, jmattson@google.com, thomas.lendacky@amd.com Subject: [PATCH 2/3 v2] KVM: SVM: Add hardware-enforced cache coherency as a CPUID feature Date: Thu, 10 Sep 2020 02:22:10 +0000 Message-Id: <20200910022211.5417-3-krish.sadhukhan@oracle.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200910022211.5417-1-krish.sadhukhan@oracle.com> References: <20200910022211.5417-1-krish.sadhukhan@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9739 signatures=668679 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 mlxscore=0 suspectscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009100020 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9739 signatures=668679 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=1 adultscore=0 mlxscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009100020 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Some AMD hardware platforms enforce cache coherency across encryption domains. Add this hardware feature as a CPUID feature to the kernel. Signed-off-by: Krish Sadhukhan --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/amd.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 81335e6fe47d..0e5b27ee5931 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -293,6 +293,7 @@ #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */ #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */ #define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */ +#define X86_FEATURE_HW_CACHE_COHERENCY (11*32+ 7) /* AMD hardware-enforced cache coherency */ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 4507ededb978..698884812989 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -632,6 +632,9 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) */ c->x86_phys_bits -= (cpuid_ebx(CPUID_AMD_SME) >> 6) & 0x3f; + if (cpuid_eax(CPUID_AMD_SME) & 0x400) + set_cpu_cap(c, X86_FEATURE_HW_CACHE_COHERENCY); + if (IS_ENABLED(CONFIG_X86_32)) goto clear_all; From patchwork Thu Sep 10 02:22:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krish Sadhukhan X-Patchwork-Id: 11766403 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9CB50746 for ; Thu, 10 Sep 2020 02:35:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 836B02087C for ; Thu, 10 Sep 2020 02:35:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=oracle.com header.i=@oracle.com header.b="aZW0G9Aj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730478AbgIJCfM (ORCPT ); Wed, 9 Sep 2020 22:35:12 -0400 Received: from userp2130.oracle.com ([156.151.31.86]:54860 "EHLO userp2130.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730810AbgIJCWk (ORCPT ); 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Thu, 10 Sep 2020 02:22:30 GMT Received: from aserv0121.oracle.com (aserv0121.oracle.com [141.146.126.235]) by aserp3030.oracle.com with ESMTP id 33dacme99k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 10 Sep 2020 02:22:30 +0000 Received: from abhmp0013.oracle.com (abhmp0013.oracle.com [141.146.116.19]) by aserv0121.oracle.com (8.14.4/8.13.8) with ESMTP id 08A2MURI002058; Thu, 10 Sep 2020 02:22:30 GMT Received: from nsvm-sadhukhan-1.osdevelopmeniad.oraclevcn.com (/100.100.230.216) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Wed, 09 Sep 2020 19:22:30 -0700 From: Krish Sadhukhan To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, jmattson@google.com, thomas.lendacky@amd.com Subject: [PATCH 3/3 v2] KVM: SVM: Don't flush cache of encrypted pages if hardware enforces cache coherenc Date: Thu, 10 Sep 2020 02:22:11 +0000 Message-Id: <20200910022211.5417-4-krish.sadhukhan@oracle.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200910022211.5417-1-krish.sadhukhan@oracle.com> References: <20200910022211.5417-1-krish.sadhukhan@oracle.com> X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9739 signatures=668679 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxlogscore=999 malwarescore=0 bulkscore=0 phishscore=0 adultscore=0 suspectscore=1 spamscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009100020 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9739 signatures=668679 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 priorityscore=1501 mlxlogscore=999 mlxscore=0 bulkscore=0 suspectscore=1 spamscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009100020 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Some hardware implementations may enforce cache coherency across encryption domains. In such cases, it's not required to flush encrypted pages off cache lines. Signed-off-by: Krish Sadhukhan --- arch/x86/kvm/svm/sev.c | 3 ++- arch/x86/mm/pat/set_memory.c | 6 ++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 402dc4234e39..8aa2209f2637 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -384,7 +384,8 @@ static void sev_clflush_pages(struct page *pages[], unsigned long npages) uint8_t *page_virtual; unsigned long i; - if (npages == 0 || pages == NULL) + if (this_cpu_has(X86_FEATURE_HW_CACHE_COHERENCY) || npages == 0 || + pages == NULL) return; for (i = 0; i < npages; i++) { diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index d1b2a889f035..5e2c618cbe84 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -1999,7 +1999,8 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) /* * Before changing the encryption attribute, we need to flush caches. */ - cpa_flush(&cpa, 1); + if (!this_cpu_has(X86_FEATURE_HW_CACHE_COHERENCY)) + cpa_flush(&cpa, 1); ret = __change_page_attr_set_clr(&cpa, 1); @@ -2010,7 +2011,8 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) * flushing gets optimized in the cpa_flush() path use the same logic * as above. */ - cpa_flush(&cpa, 0); + if (!this_cpu_has(X86_FEATURE_HW_CACHE_COHERENCY)) + cpa_flush(&cpa, 0); return ret; }