From patchwork Thu Sep 10 13:01:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Bailon X-Patchwork-Id: 11769495 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D846139F for ; Thu, 10 Sep 2020 21:56:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 00CF8208E4 for ; Thu, 10 Sep 2020 21:56:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="e1BCbpsX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728500AbgIJVmc (ORCPT ); Thu, 10 Sep 2020 17:42:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730644AbgIJNBo (ORCPT ); Thu, 10 Sep 2020 09:01:44 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A13FC061786 for ; Thu, 10 Sep 2020 06:01:40 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id t10so6631290wrv.1 for ; Thu, 10 Sep 2020 06:01:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pRs7Uzub0zJIby8weUidtFyGgxBuDRRReFxv1hE4uO8=; b=e1BCbpsXv9QwCCYq522KpmcV/gk6T8ibKbGXusxUOfAfP2F3CYIxea926Q3rOONKiI Rzl8B7GGIANojnTkvRGBr2uu72MpTHHDCNtHhD4yyD+b7SSDXbAYdCN+ImfUBrfmPAWg EnOxs50Im1TZFZVUxvBrJYQTIGujYBUAw6TypR8XcDTWN8Gvaq503Urh22FAiPblCx1k PS3Zc0optxM7KKJMz86JCliv8SH1QyDsfCON0rUiTTChG5yW+3AomEktH6Lxa7h1xT+3 sbl6e6D5fbYtDpWmLKX7lyqsY2U970qtVw/X5OfLyjWjVVyvSgRQj0O1XdCwuFCNVIhb RWDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pRs7Uzub0zJIby8weUidtFyGgxBuDRRReFxv1hE4uO8=; b=TWGj88eXkydPCKZUQeHNDIxXaQnzWdlDAww7swdPSI/ufmAyZ1928vu1/1PSXc+ajv fpNQzs08twihU/GODS/9yLnnoxHCNBWgd+SsS4mJqQfm9j0jdwdMDlocZfbmG6kMhDTy Q/Ap+s0dHWccWJ0+5AtPVBeWAi03FAqWF0wQZ6Ymn/2D2+rS7Q5gdrihNW5MK2WkdQW5 l2t2lkWyKczQDw2VwlkTTFcLgDO1bn4wWZ9GeS6wdgkGsVKUgMzs8AzOyCtOp6bLjGT4 dJcHPP6fBRXKoW8oNH6FJEa4sPJl9XLbxQLtGH3w0TzqGQAA+TIqCZep/wisuGNV1Sjd HoMQ== X-Gm-Message-State: AOAM531RLjMIG1AQZhJfoyVnL4FawKWP3x2mq4KPYSIXhyShjQqt8Xa6 zuBWe0duH7kNlqt6rxYSQIwvZQ== X-Google-Smtp-Source: ABdhPJx4KLaMhKr7HdhOjKyG9sCQC8O62DGqMbs3kGQb1cIb++035zPL1Wso7SB/gY7s9bimrlrhXA== X-Received: by 2002:adf:e6cf:: with SMTP id y15mr8886654wrm.346.1599742898647; Thu, 10 Sep 2020 06:01:38 -0700 (PDT) Received: from alex-xps13.baylibre.local (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id y1sm9488269wru.87.2020.09.10.06.01.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 06:01:37 -0700 (PDT) From: Alexandre Bailon To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, matthias.bgg@gmail.com, mathieu.poirier@linaro.org Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, stephane.leprovost@mediatek.com, gpain@baylibre.com, Alexandre Bailon Subject: [PATCH v2 1/4] dt bindings: remoteproc: Add bindings for MT8183 APU Date: Thu, 10 Sep 2020 15:01:45 +0200 Message-Id: <20200910130148.8734-2-abailon@baylibre.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200910130148.8734-1-abailon@baylibre.com> References: <20200910130148.8734-1-abailon@baylibre.com> MIME-Version: 1.0 Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org This adds dt bindings for the APU present in the MT8183. Signed-off-by: Alexandre Bailon Reviewed-by: Rob Herring --- .../bindings/remoteproc/mtk,apu.yaml | 107 ++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/mtk,apu.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,apu.yaml b/Documentation/devicetree/bindings/remoteproc/mtk,apu.yaml new file mode 100644 index 000000000000..7a71d2f5c4e6 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/mtk,apu.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 + +--- +$id: "http://devicetree.org/schemas/remoteproc/mtk,apu.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MT8183 AI Processor Unit (APU) a.k.a. Vision Processor Unit (VPU) + +description: + This document defines the binding for the APU, a co-processor that could + offload the CPU for machine learning and neural network. + +maintainers: + - Alexandre Bailon + +properties: + compatible: + const: mediatek,mt8183-apu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + description: + Three clocks are expected for AXI, IPU and JTAG. + The JTAG clock seems to be required to run the DSP, + even when JTAG is not in use." + maxItems: 3 + + clock-names: + items: + - const: axi + - const: ipu + - const: jtag + + iommus: + maxItems: 3 + + memory-region: + maxItems: 1 + + power-domains: + maxItems: 1 + + pinctrl: + description: pinctrl handles, required to configure pins for JTAG. + + pinctrl-names: + items: + - const: jtag + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - iommus + - memory-region + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apu_ram: apu_ram@0x60000000 { + compatible = "shared-dma-pool"; + reg = <0x60000000 0x040000000>; + no-map; + linux,cma-default; + }; + }; + + apu0: apu@19100000 { + compatible = "mediatek,mt8183-apu"; + reg = <0x19180000 0x14000>; + interrupts = ; + + iommus = <&iommu M4U_PORT_IMG_IPUO>, + <&iommu M4U_PORT_IMG_IPU3O>, + <&iommu M4U_PORT_IMG_IPUI>; + + clocks = <&ipu_core0 CLK_IPU_CORE0_AXI>, + <&ipu_core0 CLK_IPU_CORE0_IPU>, + <&ipu_core0 CLK_IPU_CORE0_JTAG>; + + clock-names = "axi", "ipu", "jtag"; + + power-domains = <&scpsys MT8183_POWER_DOMAIN_VPU_CORE0>; + memory-region = <&apu_ram>; + }; +... From patchwork Thu Sep 10 13:01:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Bailon X-Patchwork-Id: 11769491 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 82063746 for ; Thu, 10 Sep 2020 21:56:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5AB7C2076C for ; Thu, 10 Sep 2020 21:56:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="Y9TXfiHQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728508AbgIJVmf (ORCPT ); Thu, 10 Sep 2020 17:42:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730294AbgIJNBo (ORCPT ); Thu, 10 Sep 2020 09:01:44 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55A3BC061796 for ; Thu, 10 Sep 2020 06:01:41 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id g4so6616361wrs.5 for ; Thu, 10 Sep 2020 06:01:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5HHGxURno6iN1uVHk5NKvm0AlOWlESWAaBP5TWi1j9Q=; b=Y9TXfiHQZx3NUNHPR/bCE9bYFmeAK/ISE5p9c76yDDOB0dGTTMd1Yhq3Rjjs14qoNL seji/cl2Jka8j9V8pcxCquiZfXsa/bhNMAtG+i17fyt2JjLhRwasM8/1dgkwogexBRBp TUKdUO/CLw0rWiGqEL+mjhAOYl7yeNm7mr8c4aXn0ogF6GhrrZKuZ5ABo2D9zgihws9V Tj/ptrOnMWKSawy6hgs42Dhn0dnD6BXax+3xcaO5ou62t/cmAOEssjjKkqk2wleBcmAh A3BaNeosrggrjxcvj3EbggAKrEH7aLzZu9nk7BZypZnnciKIpNK1gcw6ks+ccodUvLA9 TYdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5HHGxURno6iN1uVHk5NKvm0AlOWlESWAaBP5TWi1j9Q=; b=TD9GcBbNtCKxnn1YNSnMMP5fFCcQXmyVlK7Tg7r3T3vR5AH6iMm6anVU170uDMwJHd swR2z/kzZ0IwzHqmbZgpdEdtmp1T671NXX9+jTL/RV2kynX7cVl+kAfB1nYbwz8ALLE0 ZnI3Q4WNKJhXxi1N8xqziTV1e2u064EuWGLRS87Hw4rebzmX4YHCUNHXK8kByvPjpmWX GGbAeKszbSGXaSzruDxjxpPntKPGYHaQvFeT6d0JtJMW2Lu6DvsZkWBp+7g8G85C578d 6n8YvPQ48sGvLzjh62jscbWTe+Rzq5s512qJLmwUlS04rMmQo1e8crQogpc+Pyi/dsMm vUcQ== X-Gm-Message-State: AOAM530iedJzhK0JzJEh8S/YxnvDw6vtOqsiJYbfi9M/zHqzo1CKl3+q NUoHo/OYpzj4i0eRq/JOKNiBGQ== X-Google-Smtp-Source: ABdhPJy3hp3TtnwGTU8nthyleVzgDo1/0iy7lMI82XoEB9qrM4O6P3IehN6bt+Xzpw7Q/vqA0RS5FQ== X-Received: by 2002:a5d:6886:: with SMTP id h6mr9179469wru.374.1599742900003; Thu, 10 Sep 2020 06:01:40 -0700 (PDT) Received: from alex-xps13.baylibre.local (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id y1sm9488269wru.87.2020.09.10.06.01.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 06:01:39 -0700 (PDT) From: Alexandre Bailon To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, matthias.bgg@gmail.com, mathieu.poirier@linaro.org Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, stephane.leprovost@mediatek.com, gpain@baylibre.com, Alexandre Bailon Subject: [PATCH v2 2/4] remoteproc: Add a remoteproc driver for the MT8183's APU Date: Thu, 10 Sep 2020 15:01:46 +0200 Message-Id: <20200910130148.8734-3-abailon@baylibre.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200910130148.8734-1-abailon@baylibre.com> References: <20200910130148.8734-1-abailon@baylibre.com> MIME-Version: 1.0 Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org This adds a driver to control the APU present in the MT8183. This loads the firmware and start the DSP. Signed-off-by: Alexandre Bailon --- drivers/remoteproc/Kconfig | 10 ++ drivers/remoteproc/Makefile | 1 + drivers/remoteproc/mtk_apu.c | 288 +++++++++++++++++++++++++++++++++++ 3 files changed, 299 insertions(+) create mode 100644 drivers/remoteproc/mtk_apu.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index c6659dfea7c7..4ebea57bf4c8 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -51,6 +51,16 @@ config MTK_SCP It's safe to say N here. +config MTK_APU + tristate "Mediatek APU remoteproc support" + depends on ARCH_MEDIATEK + depends on MTK_IOMMU + help + Say y to support the Mediatek's Accelerated Processing Unit (APU) via + the remote processor framework. + + It's safe to say N here. + config OMAP_REMOTEPROC tristate "OMAP remoteproc support" depends on ARCH_OMAP4 || SOC_OMAP5 || SOC_DRA7XX diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 3dfa28e6c701..174644f38fda 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_REMOTEPROC_CDEV) += remoteproc_cdev.o obj-$(CONFIG_IMX_REMOTEPROC) += imx_rproc.o obj-$(CONFIG_INGENIC_VPU_RPROC) += ingenic_rproc.o obj-$(CONFIG_MTK_SCP) += mtk_scp.o mtk_scp_ipi.o +obj-$(CONFIG_MTK_APU) += mtk_apu.o obj-$(CONFIG_OMAP_REMOTEPROC) += omap_remoteproc.o obj-$(CONFIG_WKUP_M3_RPROC) += wkup_m3_rproc.o obj-$(CONFIG_DA8XX_REMOTEPROC) += da8xx_remoteproc.o diff --git a/drivers/remoteproc/mtk_apu.c b/drivers/remoteproc/mtk_apu.c new file mode 100644 index 000000000000..6d2f577cfde5 --- /dev/null +++ b/drivers/remoteproc/mtk_apu.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 BayLibre SAS + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "remoteproc_internal.h" + +/* From MT8183 4.5 Vision Processor Unit (VPU).pdf datasheet */ +#define SW_RST (0x0000000C) +#define SW_RST_OCD_HALT_ON_RST BIT(12) +#define SW_RST_IPU_D_RST BIT(8) +#define SW_RST_IPU_B_RST BIT(4) +#define CORE_CTRL (0x00000110) +#define CORE_CTRL_PDEBUG_ENABLE BIT(31) +#define CORE_CTRL_SRAM_64K_iMEM (0x00 << 27) +#define CORE_CTRL_SRAM_96K_iMEM (0x01 << 27) +#define CORE_CTRL_SRAM_128K_iMEM (0x02 << 27) +#define CORE_CTRL_SRAM_192K_iMEM (0x03 << 27) +#define CORE_CTRL_SRAM_256K_iMEM (0x04 << 27) +#define CORE_CTRL_PBCLK_ENABLE BIT(26) +#define CORE_CTRL_RUN_STALL BIT(23) +#define CORE_CTRL_STATE_VECTOR_SELECT BIT(19) +#define CORE_CTRL_PIF_GATED BIT(17) +#define CORE_CTRL_NMI BIT(0) +#define CORE_XTENSA_INT (0x00000114) +#define CORE_CTL_XTENSA_INT (0x00000118) +#define CORE_DEFAULT0 (0x0000013C) +#define CORE_DEFAULT0_QOS_SWAP_0 (0x00 << 28) +#define CORE_DEFAULT0_QOS_SWAP_1 (0x01 << 28) +#define CORE_DEFAULT0_QOS_SWAP_2 (0x02 << 28) +#define CORE_DEFAULT0_QOS_SWAP_3 (0x03 << 28) +#define CORE_DEFAULT0_ARUSER_USE_IOMMU (0x10 << 23) +#define CORE_DEFAULT0_AWUSER_USE_IOMMU (0x10 << 18) +#define CORE_DEFAULT1 (0x00000140) +#define CORE_DEFAULT0_ARUSER_IDMA_USE_IOMMU (0x10 << 0) +#define CORE_DEFAULT0_AWUSER_IDMA_USE_IOMMU (0x10 << 5) +#define CORE_XTENSA_ALTRESETVEC (0x000001F8) + +struct mtk_apu_rproc { + struct device *dev; + struct rproc *rproc; + + void __iomem *base; + int irq; + struct clk_bulk_data clks[3]; +}; + +static int mtk_apu_rproc_prepare(struct rproc *rproc) +{ + struct mtk_apu_rproc *apu_rproc = rproc->priv; + int ret; + + ret = clk_bulk_prepare_enable(ARRAY_SIZE(apu_rproc->clks), + apu_rproc->clks); + if (ret) + dev_err(apu_rproc->dev, "Failed to enable clocks\n"); + + return ret; +} + +static int mtk_apu_rproc_unprepare(struct rproc *rproc) +{ + struct mtk_apu_rproc *apu_rproc = rproc->priv; + + clk_bulk_disable_unprepare(ARRAY_SIZE(apu_rproc->clks), + apu_rproc->clks); + + return 0; +} + +static int mtk_apu_rproc_start(struct rproc *rproc) +{ + struct mtk_apu_rproc *apu_rproc = rproc->priv; + u32 core_ctrl; + + /* Set reset vector of APU firmware boot address */ + writel(rproc->bootaddr, apu_rproc->base + CORE_XTENSA_ALTRESETVEC); + + /* Turn on the clocks and stall the APU */ + core_ctrl = readl(apu_rproc->base + CORE_CTRL); + core_ctrl |= CORE_CTRL_PDEBUG_ENABLE | CORE_CTRL_PBCLK_ENABLE | + CORE_CTRL_STATE_VECTOR_SELECT | CORE_CTRL_RUN_STALL | + CORE_CTRL_PIF_GATED; + writel(core_ctrl, apu_rproc->base + CORE_CTRL); + + /* Reset the APU */ + writel(SW_RST_OCD_HALT_ON_RST | SW_RST_IPU_B_RST | SW_RST_IPU_D_RST, + apu_rproc->base + SW_RST); + ndelay(27); + writel(0, apu_rproc->base + SW_RST); + + core_ctrl &= ~CORE_CTRL_PIF_GATED; + writel(core_ctrl, apu_rproc->base + CORE_CTRL); + + /* Configure memory accesses to go through the IOMMU */ + writel(CORE_DEFAULT0_AWUSER_USE_IOMMU | CORE_DEFAULT0_ARUSER_USE_IOMMU | + CORE_DEFAULT0_QOS_SWAP_1, apu_rproc->base + CORE_DEFAULT0); + writel(CORE_DEFAULT0_AWUSER_IDMA_USE_IOMMU | + CORE_DEFAULT0_ARUSER_IDMA_USE_IOMMU, + apu_rproc->base + CORE_DEFAULT1); + + /* Release the APU */ + core_ctrl &= ~CORE_CTRL_RUN_STALL; + writel(core_ctrl, apu_rproc->base + CORE_CTRL); + + return 0; +} + +static int mtk_apu_rproc_stop(struct rproc *rproc) +{ + struct mtk_apu_rproc *apu_rproc = rproc->priv; + u32 core_ctrl; + + core_ctrl = readl(apu_rproc->base + CORE_CTRL); + writel(core_ctrl | CORE_CTRL_RUN_STALL, apu_rproc->base + CORE_CTRL); + + return 0; +} + +static void mtk_apu_rproc_kick(struct rproc *rproc, int vqid) +{ + struct mtk_apu_rproc *apu_rproc = rproc->priv; + + writel(1 << vqid, apu_rproc->base + CORE_CTL_XTENSA_INT); +} + +static const struct rproc_ops mtk_apu_rproc_ops = { + .prepare = mtk_apu_rproc_prepare, + .unprepare = mtk_apu_rproc_unprepare, + .start = mtk_apu_rproc_start, + .stop = mtk_apu_rproc_stop, + .kick = mtk_apu_rproc_kick, +}; + +static irqreturn_t mtk_apu_rproc_callback(int irq, void *data) +{ + struct rproc *rproc = data; + struct mtk_apu_rproc *apu_rproc = (struct mtk_apu_rproc *)rproc->priv; + + writel(1, apu_rproc->base + CORE_XTENSA_INT); + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t handle_event(int irq, void *data) +{ + struct rproc *rproc = data; + + rproc_vq_interrupt(rproc, 0); + rproc_vq_interrupt(rproc, 1); + + return IRQ_HANDLED; +} + +static int mtk_apu_rproc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_apu_rproc *apu_rproc; + struct rproc *rproc; + struct resource *res; + int ret; + + rproc = rproc_alloc(dev, dev_name(dev), &mtk_apu_rproc_ops, NULL, + sizeof(*apu_rproc)); + if (!rproc) + return -ENOMEM; + + rproc->recovery_disabled = true; + rproc->has_iommu = false; + + apu_rproc = rproc->priv; + apu_rproc->rproc = rproc; + apu_rproc->dev = dev; + + platform_set_drvdata(pdev, rproc); + + rproc->domain = iommu_get_domain_for_dev(dev); + if (!rproc->domain) { + dev_err(dev, "Failed to get the IOMMU domain\n"); + ret = -EINVAL; + goto free_rproc; + } + + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + apu_rproc->base = devm_ioremap_resource(dev, res); + if (IS_ERR(apu_rproc->base)) { + dev_err(dev, "Failed to map mmio\n"); + ret = PTR_ERR(apu_rproc->base); + goto free_rproc; + } + + apu_rproc->irq = platform_get_irq(pdev, 0); + if (apu_rproc->irq < 0) { + ret = apu_rproc->irq; + goto free_rproc; + } + + ret = devm_request_threaded_irq(dev, apu_rproc->irq, + mtk_apu_rproc_callback, handle_event, + IRQF_SHARED | IRQF_ONESHOT, + NULL, rproc); + if (ret) { + dev_err(dev, "devm_request_threaded_irq error: %d\n", ret); + goto free_rproc; + } + + apu_rproc->clks[0].id = "ipu"; + apu_rproc->clks[1].id = "axi"; + apu_rproc->clks[1].id = "jtag"; + + ret = devm_clk_bulk_get(dev, ARRAY_SIZE(apu_rproc->clks), + apu_rproc->clks); + if (ret) { + dev_err(dev, "Failed to get clocks\n"); + goto free_rproc; + } + + ret = of_reserved_mem_device_init(dev); + if (ret) { + dev_err(dev, "device does not have specific CMA pool\n"); + goto free_rproc; + } + + ret = rproc_add(rproc); + if (ret) { + dev_err(dev, "rproc_add failed: %d\n", ret); + goto free_mem; + } + + return 0; + +free_mem: + of_reserved_mem_device_release(dev); +free_rproc: + rproc_free(rproc); + + return ret; +} + +static int mtk_apu_rproc_remove(struct platform_device *pdev) +{ + struct rproc *rproc = platform_get_drvdata(pdev); + struct mtk_apu_rproc *apu_rproc = (struct mtk_apu_rproc *)rproc->priv; + struct device *dev = &pdev->dev; + + disable_irq(apu_rproc->irq); + + rproc_del(rproc); + of_reserved_mem_device_release(dev); + rproc_free(rproc); + + return 0; +} + +static const struct of_device_id mtk_apu_rproc_of_match[] = { + { .compatible = "mediatek,mt8183-apu", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, mtk_apu_rproc_of_match); + +static struct platform_driver mtk_apu_rproc_driver = { + .probe = mtk_apu_rproc_probe, + .remove = mtk_apu_rproc_remove, + .driver = { + .name = "mtk_apu-rproc", + .of_match_table = of_match_ptr(mtk_apu_rproc_of_match), + }, +}; +module_platform_driver(mtk_apu_rproc_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Alexandre Bailon"); +MODULE_DESCRIPTION("MTK APU Remote Processor control driver"); From patchwork Thu Sep 10 13:01:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Bailon X-Patchwork-Id: 11769445 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C20B313B1 for ; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id y1sm9488269wru.87.2020.09.10.06.01.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 06:01:40 -0700 (PDT) From: Alexandre Bailon To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, matthias.bgg@gmail.com, mathieu.poirier@linaro.org Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, stephane.leprovost@mediatek.com, gpain@baylibre.com, Alexandre Bailon Subject: [PATCH v2 3/4] remoteproc: mtk_vpu_rproc: Add support of JTAG Date: Thu, 10 Sep 2020 15:01:47 +0200 Message-Id: <20200910130148.8734-4-abailon@baylibre.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200910130148.8734-1-abailon@baylibre.com> References: <20200910130148.8734-1-abailon@baylibre.com> MIME-Version: 1.0 Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org The DSP could be debugged using JTAG. The support of JTAG could enabled at build time and it could be enabled using debugfs. Signed-off-by: Alexandre Bailon --- drivers/remoteproc/Kconfig | 9 +++ drivers/remoteproc/mtk_apu.c | 151 ++++++++++++++++++++++++++++++++++- 2 files changed, 159 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 4ebea57bf4c8..310462346bd8 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -61,6 +61,15 @@ config MTK_APU It's safe to say N here. +config MTK_APU_JTAG + bool "Enable support of JTAG" + depends on MTK_APU + help + Say y to enable support of JTAG. + By default, JTAG will remain disabled until it is enabled using + debugfs: remoteproc/remoteproc0/jtag. Write 1 to enable it and + 0 to disable it. + config OMAP_REMOTEPROC tristate "OMAP remoteproc support" depends on ARCH_OMAP4 || SOC_OMAP5 || SOC_DRA7XX diff --git a/drivers/remoteproc/mtk_apu.c b/drivers/remoteproc/mtk_apu.c index 6d2f577cfde5..07157fdc24ba 100644 --- a/drivers/remoteproc/mtk_apu.c +++ b/drivers/remoteproc/mtk_apu.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -14,6 +15,7 @@ #include #include #include +#include #include #include @@ -48,6 +50,11 @@ #define CORE_DEFAULT1 (0x00000140) #define CORE_DEFAULT0_ARUSER_IDMA_USE_IOMMU (0x10 << 0) #define CORE_DEFAULT0_AWUSER_IDMA_USE_IOMMU (0x10 << 5) +#define CORE_DEFAULT2 (0x00000144) +#define CORE_DEFAULT2_DBG_EN BIT(3) +#define CORE_DEFAULT2_NIDEN BIT(2) +#define CORE_DEFAULT2_SPNIDEN BIT(1) +#define CORE_DEFAULT2_SPIDEN BIT(0) #define CORE_XTENSA_ALTRESETVEC (0x000001F8) struct mtk_apu_rproc { @@ -57,6 +64,13 @@ struct mtk_apu_rproc { void __iomem *base; int irq; struct clk_bulk_data clks[3]; + +#ifdef CONFIG_MTK_APU_JTAG + struct pinctrl *pinctrl; + struct pinctrl_state *pinctrl_jtag; + bool jtag_enabled; + struct mutex jtag_mutex; +#endif }; static int mtk_apu_rproc_prepare(struct rproc *rproc) @@ -166,6 +180,137 @@ static irqreturn_t handle_event(int irq, void *data) return IRQ_HANDLED; } +#ifdef CONFIG_MTK_APU_JTAG + +static int apu_enable_jtag(struct mtk_apu_rproc *apu_rproc) +{ + int ret = 0; + + mutex_lock(&apu_rproc->jtag_mutex); + if (apu_rproc->jtag_enabled) { + ret = -EINVAL; + goto err_mutex_unlock; + } + + writel(CORE_DEFAULT2_SPNIDEN | CORE_DEFAULT2_SPIDEN | + CORE_DEFAULT2_NIDEN | CORE_DEFAULT2_DBG_EN, + apu_rproc->base + CORE_DEFAULT2); + + apu_rproc->jtag_enabled = 1; + +err_mutex_unlock: + mutex_unlock(&apu_rproc->jtag_mutex); + + return ret; +} + +static int apu_disable_jtag(struct mtk_apu_rproc *apu_rproc) +{ + int ret = 0; + + mutex_lock(&apu_rproc->jtag_mutex); + if (!apu_rproc->jtag_enabled) { + ret = -EINVAL; + goto err_mutex_unlock; + } + + writel(0, apu_rproc->base + CORE_DEFAULT2); + + apu_rproc->jtag_enabled = 0; + +err_mutex_unlock: + mutex_unlock(&apu_rproc->jtag_mutex); + + return ret; +} + +static ssize_t rproc_jtag_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct rproc *rproc = filp->private_data; + struct mtk_apu_rproc *apu_rproc = (struct mtk_apu_rproc *)rproc->priv; + char *buf = apu_rproc->jtag_enabled ? "enabled\n" : "disabled\n"; + + return simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); +} + +static ssize_t rproc_jtag_write(struct file *filp, const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct rproc *rproc = filp->private_data; + struct mtk_apu_rproc *apu_rproc = (struct mtk_apu_rproc *)rproc->priv; + char buf[10]; + int ret; + + if (count < 1 || count > sizeof(buf)) + return -EINVAL; + + ret = copy_from_user(buf, user_buf, count); + if (ret) + return -EFAULT; + + /* remove end of line */ + if (buf[count - 1] == '\n') + buf[count - 1] = '\0'; + + if (!strncmp(buf, "enabled", count)) + ret = apu_enable_jtag(apu_rproc); + else if (!strncmp(buf, "disabled", count)) + ret = apu_disable_jtag(apu_rproc); + else + return -EINVAL; + + return ret ? ret : count; +} + +static const struct file_operations rproc_jtag_ops = { + .read = rproc_jtag_read, + .write = rproc_jtag_write, + .open = simple_open, +}; + +static int apu_jtag_probe(struct mtk_apu_rproc *apu_rproc) +{ + int ret; + + if (!apu_rproc->rproc->dbg_dir) + return -ENODEV; + + apu_rproc->pinctrl = devm_pinctrl_get(apu_rproc->dev); + if (IS_ERR(apu_rproc->pinctrl)) { + dev_warn(apu_rproc->dev, "Failed to find JTAG pinctrl\n"); + return PTR_ERR(apu_rproc->pinctrl); + } + + apu_rproc->pinctrl_jtag = pinctrl_lookup_state(apu_rproc->pinctrl, + "jtag"); + if (IS_ERR(apu_rproc->pinctrl_jtag)) + return PTR_ERR(apu_rproc->pinctrl_jtag); + + ret = pinctrl_select_state(apu_rproc->pinctrl, + apu_rproc->pinctrl_jtag); + if (ret < 0) + return ret; + + mutex_init(&apu_rproc->jtag_mutex); + + debugfs_create_file("jtag", 0600, apu_rproc->rproc->dbg_dir, + apu_rproc->rproc, &rproc_jtag_ops); + + return 0; +} +#else +static int apu_jtag_probe(struct mtk_apu_rproc *apu_rproc) +{ + return 0; +} + +static int apu_disable_jtag(struct mtk_apu_rproc *apu_rproc) +{ + return 0; +} +#endif /* CONFIG_MTK_APU_JTAG */ + static int mtk_apu_rproc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -242,6 +387,10 @@ static int mtk_apu_rproc_probe(struct platform_device *pdev) goto free_mem; } + ret = apu_jtag_probe(apu_rproc); + if (ret) + dev_warn(dev, "Failed to configure jtag\n"); + return 0; free_mem: @@ -259,7 +408,7 @@ static int mtk_apu_rproc_remove(struct platform_device *pdev) struct device *dev = &pdev->dev; disable_irq(apu_rproc->irq); - + apu_disable_jtag(apu_rproc); rproc_del(rproc); of_reserved_mem_device_release(dev); rproc_free(rproc); From patchwork Thu Sep 10 13:01:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Bailon X-Patchwork-Id: 11769485 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 19EF1139F for ; Thu, 10 Sep 2020 21:55:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F142F20719 for ; Thu, 10 Sep 2020 21:55:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="KTLKPAFf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728365AbgIJVmo (ORCPT ); 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id y1sm9488269wru.87.2020.09.10.06.01.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 06:01:41 -0700 (PDT) From: Alexandre Bailon To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, matthias.bgg@gmail.com, mathieu.poirier@linaro.org Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, stephane.leprovost@mediatek.com, gpain@baylibre.com, Alexandre Bailon Subject: [PATCH v2 4/4] ARM64: mt8183: Add support of APU to mt8183 Date: Thu, 10 Sep 2020 15:01:48 +0200 Message-Id: <20200910130148.8734-5-abailon@baylibre.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200910130148.8734-1-abailon@baylibre.com> References: <20200910130148.8734-1-abailon@baylibre.com> MIME-Version: 1.0 Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org This adds the support of APU to mt8183. Signed-off-by: Alexandre Bailon Reported-by: kernel test robot --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 39 ++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index e215f1eb3eb2..28f75452961c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -967,12 +967,51 @@ ipu_adl: syscon@19010000 { #clock-cells = <1>; }; + apu0: apu@0x19100000 { + compatible = "mediatek,mt8183-apu"; + reg = <0 0x19180000 0 0x14000>; + interrupts = ; + + iommus = <&iommu M4U_PORT_IMG_IPUO>, + <&iommu M4U_PORT_IMG_IPU3O>, + <&iommu M4U_PORT_IMG_IPUI>; + + clocks = <&ipu_core0 CLK_IPU_CORE0_AXI>, + <&ipu_core0 CLK_IPU_CORE0_IPU>, + <&ipu_core0 CLK_IPU_CORE0_JTAG>; + + clock-names = "axi", "ipu", "jtag"; + + power-domains = <&scpsys MT8183_POWER_DOMAIN_VPU_CORE0>; + status = "disabled"; + }; + ipu_core0: syscon@19180000 { compatible = "mediatek,mt8183-ipu_core0", "syscon"; reg = <0 0x19180000 0 0x1000>; #clock-cells = <1>; }; + apu1: apu@19200000 { + compatible = "mediatek,mt8183-apu"; + reg = <0 0x19280000 0 0x14000>; + interrupts = ; + + iommus = <&iommu M4U_PORT_CAM_IPUO>, + <&iommu M4U_PORT_CAM_IPU2O>, + <&iommu M4U_PORT_CAM_IPU3O>, + <&iommu M4U_PORT_CAM_IPUI>, + <&iommu M4U_PORT_CAM_IPU2I>; + + clocks = <&ipu_core0 CLK_IPU_CORE1_AXI>, + <&ipu_core0 CLK_IPU_CORE1_IPU>, + <&ipu_core0 CLK_IPU_CORE1_JTAG>; + + clock-names = "axi", "ipu", "jtag"; + + power-domains = <&scpsys MT8183_POWER_DOMAIN_VPU_CORE1>; + }; + ipu_core1: syscon@19280000 { compatible = "mediatek,mt8183-ipu_core1", "syscon"; reg = <0 0x19280000 0 0x1000>;