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Fri, 11 Sep 2020 03:45:29 -0400 (EDT) From: Andrew Jeffery To: linux-mmc@vger.kernel.org Subject: [PATCH v2 1/3] dt: bindings: mmc: Add phase control properties for the Aspeed SDHCI Date: Fri, 11 Sep 2020 17:14:50 +0930 Message-Id: <20200911074452.3148259-2-andrew@aj.id.au> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200911074452.3148259-1-andrew@aj.id.au> References: <20200911074452.3148259-1-andrew@aj.id.au> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200911_034534_485688_51FE95C7 X-CRM114-Status: UNSURE ( 9.88 ) X-CRM114-Notice: Please train this message. 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Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml b/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml index 987b287f3bff..d7b605968c8a 100644 --- a/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml @@ -61,6 +61,14 @@ patternProperties: sdhci,auto-cmd12: type: boolean description: Specifies that controller should use auto CMD12 + "aspeed,input-phase": + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + The input phase delay value. + "aspeed,output-phase": + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + The output phase delay value. required: - compatible - reg From patchwork Fri Sep 11 07:44:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 11769885 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 61877698 for ; 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Fri, 11 Sep 2020 03:45:32 -0400 (EDT) From: Andrew Jeffery To: linux-mmc@vger.kernel.org Subject: [PATCH v2 2/3] mmc: sdhci-of-aspeed: Expose phase delay tuning Date: Fri, 11 Sep 2020 17:14:51 +0930 Message-Id: <20200911074452.3148259-3-andrew@aj.id.au> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200911074452.3148259-1-andrew@aj.id.au> References: <20200911074452.3148259-1-andrew@aj.id.au> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200911_034537_229660_5E1CC215 X-CRM114-Status: GOOD ( 21.39 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [64.147.123.19 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [64.147.123.19 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ulf.hansson@linaro.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, adrian.hunter@intel.com, joel@jms.id.au, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The Aspeed SD/eMMC controllers feature up to two SDHCIs alongside a a set of "global" configuration registers. The global configuration registers house controller-specific settings that aren't exposed by the SDHCI, one example being a register for phase tuning. The phase tuning feature is new in the AST2600 design. It's exposed as a single register in the global register set and controls both the input and output phase adjustment for each slot. As the settings are slot-specific, the values to program are extracted from properties in the SDHCI devicetree nodes. Signed-off-by: Andrew Jeffery --- In v2: * Rework devicetree parsing to minimise state disruption * Switch some log statements from dev_info() to dev_dbg() --- drivers/mmc/host/sdhci-of-aspeed.c | 126 +++++++++++++++++++++++++++-- 1 file changed, 121 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c index 4f008ba3280e..c61eb42e1ebb 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -16,9 +16,19 @@ #include "sdhci-pltfm.h" -#define ASPEED_SDC_INFO 0x00 -#define ASPEED_SDC_S1MMC8 BIT(25) -#define ASPEED_SDC_S0MMC8 BIT(24) +#define ASPEED_SDC_INFO 0x00 +#define ASPEED_SDC_S1_MMC8 BIT(25) +#define ASPEED_SDC_S0_MMC8 BIT(24) +#define ASPEED_SDC_PHASE 0xf4 +#define ASPEED_SDC_S1_PHASE_IN GENMASK(25, 21) +#define ASPEED_SDC_S0_PHASE_IN GENMASK(20, 16) +#define ASPEED_SDC_S1_PHASE_OUT GENMASK(15, 11) +#define ASPEED_SDC_S1_PHASE_IN_EN BIT(10) +#define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8) +#define ASPEED_SDC_S0_PHASE_OUT GENMASK(7, 3) +#define ASPEED_SDC_S0_PHASE_IN_EN BIT(2) +#define ASPEED_SDC_S0_PHASE_OUT_EN GENMASK(1, 0) +#define ASPEED_SDC_PHASE_MAX 31 struct aspeed_sdc { struct clk *clk; @@ -28,9 +38,21 @@ struct aspeed_sdc { void __iomem *regs; }; +struct aspeed_sdhci_phase_desc { + u32 value_mask; + u32 enable_mask; + u8 enable_value; +}; + +struct aspeed_sdhci_phase { + struct aspeed_sdhci_phase_desc in; + struct aspeed_sdhci_phase_desc out; +}; + struct aspeed_sdhci { struct aspeed_sdc *parent; u32 width_mask; + const struct aspeed_sdhci_phase *phase; }; static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc, @@ -50,6 +72,22 @@ static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc, spin_unlock(&sdc->lock); } +static void +aspeed_sdc_configure_phase(struct aspeed_sdc *sdc, + const struct aspeed_sdhci_phase_desc *phase, + uint8_t value) +{ + u32 reg; + + spin_lock(&sdc->lock); + reg = readl(sdc->regs + ASPEED_SDC_PHASE); + reg &= ~(phase->enable_mask | phase->value_mask); + reg |= value << __ffs(phase->value_mask); + reg |= phase->enable_value << __ffs(phase->enable_mask); + writel(reg, sdc->regs + ASPEED_SDC_PHASE); + spin_unlock(&sdc->lock); +} + static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host; @@ -155,8 +193,49 @@ static inline int aspeed_sdhci_calculate_slot(struct aspeed_sdhci *dev, return (delta / 0x100) - 1; } +static int aspeed_sdhci_configure_of(struct platform_device *pdev, + struct aspeed_sdhci *sdhci) +{ + struct device_node *np; + struct device *dev; + u32 phase; + + if (!sdhci->phase) + return 0; + + dev = &pdev->dev; + np = dev->of_node; + + if (!of_property_read_u32(np, "aspeed,input-phase", &phase)) { + if (phase <= ASPEED_SDC_PHASE_MAX) { + aspeed_sdc_configure_phase(sdhci->parent, + &sdhci->phase->in, + phase); + dev_dbg(dev, "Input phase adjustment: %u", phase); + } else { + dev_err(dev, "Invalid input phase value: %u", phase); + return -EINVAL; + } + } + + if (!of_property_read_u32(np, "aspeed,output-phase", &phase)) { + if (phase <= ASPEED_SDC_PHASE_MAX) { + aspeed_sdc_configure_phase(sdhci->parent, + &sdhci->phase->out, + phase); + dev_dbg(dev, "Output phase adjustment: %u", phase); + } else { + dev_err(dev, "Invalid output phase value: %u", phase); + return -EINVAL; + } + } + + return 0; +} + static int aspeed_sdhci_probe(struct platform_device *pdev) { + const struct aspeed_sdhci_phase *phase; struct sdhci_pltfm_host *pltfm_host; struct aspeed_sdhci *dev; struct sdhci_host *host; @@ -181,7 +260,10 @@ static int aspeed_sdhci_probe(struct platform_device *pdev) return -EINVAL; dev_info(&pdev->dev, "Configuring for slot %d\n", slot); - dev->width_mask = !slot ? ASPEED_SDC_S0MMC8 : ASPEED_SDC_S1MMC8; + dev->width_mask = !slot ? ASPEED_SDC_S0_MMC8 : ASPEED_SDC_S1_MMC8; + phase = of_device_get_match_data(&pdev->dev); + if (phase) + dev->phase = &phase[slot]; sdhci_get_of_property(pdev); @@ -195,6 +277,10 @@ static int aspeed_sdhci_probe(struct platform_device *pdev) goto err_pltfm_free; } + ret = aspeed_sdhci_configure_of(pdev, dev); + if (ret) + goto err_sdhci_add; + ret = mmc_of_parse(host->mmc); if (ret) goto err_sdhci_add; @@ -230,10 +316,40 @@ static int aspeed_sdhci_remove(struct platform_device *pdev) return 0; } +static const struct aspeed_sdhci_phase ast2600_sdhci_phase[] = { + /* SDHCI/Slot 0 */ + [0] = { + .in = { + .value_mask = ASPEED_SDC_S0_PHASE_IN, + .enable_mask = ASPEED_SDC_S0_PHASE_IN_EN, + .enable_value = 1, + }, + .out = { + .value_mask = ASPEED_SDC_S0_PHASE_OUT, + .enable_mask = ASPEED_SDC_S0_PHASE_OUT_EN, + .enable_value = 3, + }, + }, + /* SDHCI/Slot 1 */ + [1] = { + .in = { + .value_mask = ASPEED_SDC_S1_PHASE_IN, + .enable_mask = ASPEED_SDC_S1_PHASE_IN_EN, + .enable_value = 1, + }, + .out = { + .value_mask = ASPEED_SDC_S1_PHASE_OUT, + .enable_mask = ASPEED_SDC_S1_PHASE_OUT_EN, + .enable_value = 3, + }, + }, +}; + +/* If supported, phase adjustment fields are stored in the data pointer */ static const struct of_device_id aspeed_sdhci_of_match[] = { { .compatible = "aspeed,ast2400-sdhci", }, { .compatible = "aspeed,ast2500-sdhci", }, - { .compatible = "aspeed,ast2600-sdhci", }, + { .compatible = "aspeed,ast2600-sdhci", .data = ast2600_sdhci_phase }, { } }; From patchwork Fri Sep 11 07:44:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 11769891 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 205B692C for ; Fri, 11 Sep 2020 07:47:18 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DA6972076C for ; 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Fri, 11 Sep 2020 03:45:35 -0400 (EDT) From: Andrew Jeffery To: linux-mmc@vger.kernel.org Subject: [PATCH v2 3/3] ARM: dts: tacoma: Add phase delay for eMMC Date: Fri, 11 Sep 2020 17:14:52 +0930 Message-Id: <20200911074452.3148259-4-andrew@aj.id.au> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200911074452.3148259-1-andrew@aj.id.au> References: <20200911074452.3148259-1-andrew@aj.id.au> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200911_034540_580746_F348590F X-CRM114-Status: GOOD ( 11.43 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [64.147.123.19 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [64.147.123.19 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ulf.hansson@linaro.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, adrian.hunter@intel.com, joel@jms.id.au, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Adjust the phase delay to avoid data timeout splats like the following: [ 731.368601] mmc0: Timeout waiting for hardware interrupt. [ 731.374644] mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== [ 731.381828] mmc0: sdhci: Sys addr: 0x00000020 | Version: 0x00000002 [ 731.389012] mmc0: sdhci: Blk size: 0x00007200 | Blk cnt: 0x00000020 [ 731.396194] mmc0: sdhci: Argument: 0x00462a18 | Trn mode: 0x0000002b [ 731.403377] mmc0: sdhci: Present: 0x01f70106 | Host ctl: 0x00000017 [ 731.410559] mmc0: sdhci: Power: 0x0000000f | Blk gap: 0x00000000 [ 731.417733] mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x00000107 [ 731.424915] mmc0: sdhci: Timeout: 0x0000000e | Int stat: 0x00000000 [ 731.432098] mmc0: sdhci: Int enab: 0x03ff008b | Sig enab: 0x03ff008b [ 731.439282] mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000 [ 731.446464] mmc0: sdhci: Caps: 0x01f80080 | Caps_1: 0x00000007 [ 731.453647] mmc0: sdhci: Cmd: 0x0000193a | Max curr: 0x001f0f08 [ 731.460829] mmc0: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0xffffffff [ 731.468013] mmc0: sdhci: Resp[2]: 0x320f5913 | Resp[3]: 0x00000900 [ 731.475195] mmc0: sdhci: Host ctl2: 0x0000008b [ 731.480139] mmc0: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0xbe040200 [ 731.487321] mmc0: sdhci: ============================================ Signed-off-by: Andrew Jeffery Acked-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 5f4ee67ac787..94ec301ceb73 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -179,6 +179,8 @@ &emmc_controller { &emmc { status = "okay"; + aspeed,input-phase = <0x7>; + aspeed,output-phase = <0x1f>; }; &fsim0 {