From patchwork Tue Sep 15 11:45:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 11776271 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1AA9859D for ; Tue, 15 Sep 2020 11:49:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F373E218AC for ; Tue, 15 Sep 2020 11:49:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="x2xy0ly1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726325AbgIOLrz (ORCPT ); Tue, 15 Sep 2020 07:47:55 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:49622 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726452AbgIOLqr (ORCPT ); Tue, 15 Sep 2020 07:46:47 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08FBjoXr127858; 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Tue, 15 Sep 2020 06:45:50 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08FBjin7091853; Tue, 15 Sep 2020 06:45:47 -0500 From: Roger Quadros To: CC: , , , , , , , , Roger Quadros Subject: [PATCH v3 1/3] dt-bindings: usb: Convert cdns-usb3.txt to YAML schema Date: Tue, 15 Sep 2020 14:45:41 +0300 Message-ID: <20200915114543.2599-2-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200915114543.2599-1-rogerq@ti.com> References: <20200915114543.2599-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Converts cdns-usb3.txt to YAML schema cdns,usb3.yaml Signed-off-by: Roger Quadros Reviewed-by: Rob Herring --- .../devicetree/bindings/usb/cdns,usb3.yaml | 92 +++++++++++++++++++ .../devicetree/bindings/usb/cdns-usb3.txt | 45 --------- 2 files changed, 92 insertions(+), 45 deletions(-) create mode 100644 Documentation/devicetree/bindings/usb/cdns,usb3.yaml delete mode 100644 Documentation/devicetree/bindings/usb/cdns-usb3.txt diff --git a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml new file mode 100644 index 000000000000..9b14c8443d39 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/cdns,usb3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence USBSS-DRD controller bindings + +maintainers: + - Pawel Laszczak + +properties: + compatible: + const: cdns,usb3 + + reg: + items: + - description: OTG controller registers + - description: XHCI Host controller registers + - description: DEVICE controller registers + + reg-names: + items: + - const: otg + - const: xhci + - const: dev + + interrupts: + items: + - description: OTG/DRD controller interrupt + - description: XHCI host controller interrupt + - description: Device controller interrupt + + interrupt-names: + items: + - const: host + - const: peripheral + - const: otg + + dr_mode: + enum: [host, otg, peripheral] + + maximum-speed: + enum: [super-speed, high-speed, full-speed] + + phys: + minItems: 1 + maxItems: 2 + + phy-names: + minItems: 1 + maxItems: 2 + items: + anyOf: + - const: cdns3,usb2-phy + - const: cdns3,usb3-phy + + cdns,on-chip-buff-size: + description: + size of memory intended as internal memory for endpoints + buffers expressed in KB + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + bus { + #address-cells = <2>; + #size-cells = <2>; + + usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x6000000 0x00 0x10000>, + <0x00 0x6010000 0x00 0x10000>, + <0x00 0x6020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = , + , + ; + interrupt-names = "host", "peripheral", "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/cdns-usb3.txt b/Documentation/devicetree/bindings/usb/cdns-usb3.txt deleted file mode 100644 index b7dc606d37b5..000000000000 --- a/Documentation/devicetree/bindings/usb/cdns-usb3.txt +++ /dev/null @@ -1,45 +0,0 @@ -Binding for the Cadence USBSS-DRD controller - -Required properties: - - reg: Physical base address and size of the controller's register areas. - Controller has 3 different regions: - - HOST registers area - - DEVICE registers area - - OTG/DRD registers area - - reg-names - register memory area names: - "xhci" - for HOST registers space - "dev" - for DEVICE registers space - "otg" - for OTG/DRD registers space - - compatible: Should contain: "cdns,usb3" - - interrupts: Interrupts used by cdns3 controller: - "host" - interrupt used by XHCI driver. - "peripheral" - interrupt used by device driver - "otg" - interrupt used by DRD/OTG part of driver - -Optional properties: - - maximum-speed : valid arguments are "super-speed", "high-speed" and - "full-speed"; refer to usb/generic.txt - - dr_mode: Should be one of "host", "peripheral" or "otg". - - phys: reference to the USB PHY - - phy-names: from the *Generic PHY* bindings; - Supported names are: - - cdns3,usb2-phy - - cdns3,usb3-phy - - - cdns,on-chip-buff-size : size of memory intended as internal memory for endpoints - buffers expressed in KB - -Example: - usb@f3000000 { - compatible = "cdns,usb3"; - interrupts = , - , - ; - interrupt-names = "host", "peripheral", "otg"; - reg = <0xf3000000 0x10000>, /* memory area for HOST registers */ - <0xf3010000 0x10000>, /* memory area for DEVICE registers */ - <0xf3020000 0x10000>; /* memory area for OTG/DRD registers */ - reg-names = "xhci", "dev", "otg"; - phys = <&usb2_phy>, <&usb3_phy>; - phy-names = "cdns3,usb2-phy", "cnds3,usb3-phy"; - }; From patchwork Tue Sep 15 11:45:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 11776273 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E98AF92C for ; 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Tue, 15 Sep 2020 06:45:50 -0500 From: Roger Quadros To: CC: , , , , , , , , Roger Quadros Subject: [PATCH v3 2/3] dt-bindings: usb: cdns,usb3: Add cdns,phyrst-a-enable property Date: Tue, 15 Sep 2020 14:45:42 +0300 Message-ID: <20200915114543.2599-3-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200915114543.2599-1-rogerq@ti.com> References: <20200915114543.2599-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Controller version 0x0002450D has USB2 PHY RX sensitivity issues that needs to be worked around by enabling phyrst-a-enable bit in PHYRST_CFG register. There is no way to know controller version before device controller is started and the workaround needs to be applied for both host and device modes, so we add this DT property. Signed-off-by: Roger Quadros Acked-by: Rob Herring --- Documentation/devicetree/bindings/usb/cdns,usb3.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml index 9b14c8443d39..ac20b98e9910 100644 --- a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml +++ b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml @@ -61,6 +61,10 @@ properties: buffers expressed in KB $ref: /schemas/types.yaml#/definitions/uint32 + cdns,phyrst-a-enable: + description: Enable resetting of PHY if Rx fail is detected + type: boolean + required: - compatible - reg From patchwork Tue Sep 15 11:45:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 11776267 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C043F92C for ; Tue, 15 Sep 2020 11:48:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A176520732 for ; Tue, 15 Sep 2020 11:48:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="qdfqgzoL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726135AbgIOLsM (ORCPT ); Tue, 15 Sep 2020 07:48:12 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:45588 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726471AbgIOLqq (ORCPT ); Tue, 15 Sep 2020 07:46:46 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08FBjtqr009346; Tue, 15 Sep 2020 06:45:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1600170355; bh=3APtkbHYrt+xP2S/hKgF189ShFm5BX6uKlppIWy5V58=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qdfqgzoLlIfknsIFP6Wbhr9fPKk3BkikrD9cAjjTkpORW1njh7m2s/kSpv6gzCfPe h9vVgHeFSikbCPvROXjraDy3vm5ld2vM6J/Njh1Q+hFzUYcI+l4PgoxeeZDnQdI5kj x5B/Ls84qLCjlZv3V8zs90+M2URbKHknZTBOk2eA= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 08FBjt7f055540 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 15 Sep 2020 06:45:55 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 15 Sep 2020 06:45:55 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 15 Sep 2020 06:45:55 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08FBjin9091853; Tue, 15 Sep 2020 06:45:53 -0500 From: Roger Quadros To: CC: , , , , , , , , Roger Quadros Subject: [PATCH v3 3/3] usb: cdns3: Enable workaround for USB2.0 PHY Rx compliance test PHY lockup Date: Tue, 15 Sep 2020 14:45:43 +0300 Message-ID: <20200915114543.2599-4-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200915114543.2599-1-rogerq@ti.com> References: <20200915114543.2599-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Pawel Laszczak USB2.0 PHY hangs in Rx Compliance test when the incoming packet amplitude is varied below and above the Squelch Level of Receiver during the active packet multiple times. Version 1 of the controller allows PHY to be reset when RX fail condition is detected to work around the above issue. This feature is disabled by default and needs to be enabled using a bit from the newly added PHYRST_CFG register. This patch enables the workaround. There is no way to know controller version before device controller is started and the workaround needs to be applied for both host and device modes, so we rely on a DT property do decide when to apply the workaround. Signed-off-by: Pawel Laszczak Signed-off-by: Roger Quadros --- drivers/usb/cdns3/core.c | 2 ++ drivers/usb/cdns3/core.h | 1 + drivers/usb/cdns3/drd.c | 12 ++++++++++++ drivers/usb/cdns3/drd.h | 5 ++++- 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c index 5c1586ec7824..34b36487682b 100644 --- a/drivers/usb/cdns3/core.c +++ b/drivers/usb/cdns3/core.c @@ -443,6 +443,8 @@ static int cdns3_probe(struct platform_device *pdev) return -ENXIO; } + cdns->phyrst_a_enable = device_property_read_bool(dev, "cdns,phyrst-a-enable"); + cdns->otg_res = *res; mutex_init(&cdns->mutex); diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h index 1ad1f1fe61e9..24cf0f1b5726 100644 --- a/drivers/usb/cdns3/core.h +++ b/drivers/usb/cdns3/core.h @@ -76,6 +76,7 @@ struct cdns3 { #define CDNS3_CONTROLLER_V0 0 #define CDNS3_CONTROLLER_V1 1 u32 version; + bool phyrst_a_enable; int otg_irq; int dev_irq; diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c index 6234bcd6158a..b74803e9703d 100644 --- a/drivers/usb/cdns3/drd.c +++ b/drivers/usb/cdns3/drd.c @@ -42,6 +42,18 @@ int cdns3_set_mode(struct cdns3 *cdns, enum usb_dr_mode mode) reg = readl(&cdns->otg_v1_regs->override); reg |= OVERRIDE_IDPULLUP; writel(reg, &cdns->otg_v1_regs->override); + + /* + * Enable work around feature built into the + * controller to address issue with RX Sensitivity + * est (EL_17) for USB2 PHY. The issue only occures + * for 0x0002450D controller version. + */ + if (cdns->phyrst_a_enable) { + reg = readl(&cdns->otg_v1_regs->phyrst_cfg); + reg |= PHYRST_CFG_PHYRST_A_ENABLE; + writel(reg, &cdns->otg_v1_regs->phyrst_cfg); + } } else { reg = readl(&cdns->otg_v0_regs->ctrl1); reg |= OVERRIDE_IDPULLUP_V0; diff --git a/drivers/usb/cdns3/drd.h b/drivers/usb/cdns3/drd.h index 7e7cf7fa2dd3..f1ccae285a16 100644 --- a/drivers/usb/cdns3/drd.h +++ b/drivers/usb/cdns3/drd.h @@ -31,7 +31,7 @@ struct cdns3_otg_regs { __le32 simulate; __le32 override; __le32 susp_ctrl; - __le32 reserved4; + __le32 phyrst_cfg; __le32 anasts; __le32 adp_ramp_time; __le32 ctrl1; @@ -153,6 +153,9 @@ struct cdns3_otg_common_regs { /* Only for CDNS3_CONTROLLER_V0 version */ #define OVERRIDE_IDPULLUP_V0 BIT(24) +/* PHYRST_CFG - bitmasks */ +#define PHYRST_CFG_PHYRST_A_ENABLE BIT(0) + #define CDNS3_ID_PERIPHERAL 1 #define CDNS3_ID_HOST 0